CN117614427B - Switch module, switch switching method and radio frequency switch device - Google Patents

Abstract

The present disclosure provides a switch module, a switch switching method, and a radio frequency switch device, where the switch module includes a switch control node, a radio frequency input node, a radio frequency output node, a plurality of first resistors, a plurality of main switches, and a bias unit; each main switch comprises a first end, a second end and a control end, wherein the control end is configured to selectively conduct the first end and the second end; the first ends and the second ends of the main switches are connected in series between the radio frequency input node and the radio frequency output node, and the control end of each main switch is connected to the switch control node; the first resistor is connected in parallel between the first end and the second end of the main switch; the biasing unit is connected with the first end or the second end of the at least one main switch; and the bias unit is configured to provide bias voltage for the first end and the second end of the main switch, so that weak on and weak off phenomena can be improved, and the switching performance of the switch can be improved.

Description

A switch module, a switch switching method and a radio frequency switch device

Technical Field

The present disclosure relates to the field of integrated circuits, and in particular to a switch module, a switch switching method, and a radio frequency switch device.

Background technique

In a multi-channel transceiver system, channel switching needs to be achieved using an RF switch. With the improvement of the quality requirements for communication signals, higher requirements are placed on the power handling, switching speed, insertion loss and other performance of the RF switch. However, there is a trade-off relationship between these performance indicators. Therefore, how to design an RF switch with high power handling, low insertion loss and fast switching has become a design difficulty for the transceiver system.

Summary of the invention

The present disclosure provides a switch module, a switch switching method and a radio frequency switch device.

The technical solution of the present disclosure is achieved as follows:

In a first aspect, an embodiment of the present disclosure provides a switch module, wherein the switch module includes a switch control node, an RF input node, an RF output node, a plurality of first resistors, a plurality of main switches and a bias unit; each of the main switches includes a first end, a second end and a control end, and the control end is configured to selectively turn on the first end and the second end; the first end and the second end of the plurality of main switches are connected in series between the RF input node and the RF output node, and the control end of each main switch is connected to the switch control node; the first resistor is connected in parallel between the first end and the second end of the main switch; the bias unit is connected to the first end or the second end of at least one of the main switches; and the bias unit is configured to provide a bias voltage to the first end and the second end of the main switch.

In a second aspect, an embodiment of the present disclosure provides a switch switching method, which is applied to the switch module as described in the first aspect, and the method includes: receiving an external instruction, wherein the external instruction indicates an action mode of a main switch, a first switch, a second switch, and a third switch, wherein the action mode includes turning the switch on or off; generating a main control signal, a first control signal, and a second control signal according to the external instruction, wherein the main control signal controls turning the main switch on or off, the first control signal controls turning the first switch on or off, and the second control signal controls turning the second switch and the third switch on or off; when the external instruction indicates that the main switch is on: sending the main control signal to the main switch to control the main switch to switch on; sending the first control signal to the first switch to control the first switch to switch on; sending the second control signal to the second switch and the third switch to control the second switch and the third switch to switch on or off. The main switch and the third switch are switched on; after a first time period: the first switch sends the first control signal to control the first switch to switch off; the second control signal is sent to the second switch and the third switch to control the second switch and the third switch to switch off; when the external instruction indicates that the main switch is off: the main control signal is sent to the main switch to control the main switch to switch off; the first control signal is sent to the first switch to control the first switch to switch on; the second control signal is sent to the second switch and the third switch to control the second switch and the third switch to switch on; after a second time period: the first control signal is sent to the first switch to control the first switch to switch off; the second control signal is sent to the second switch and the third switch to control the second switch and the third switch to switch off.

In a third aspect, an embodiment of the present disclosure provides a radio frequency switching device, the radio frequency switching device comprising a plurality of selection branches, each selection branch comprising at least one switch module connected in series and at least one switch module connected in parallel, the switch module being the switch module as described in the first aspect.

The present disclosure provides a switch module, a switch switching method and a radio frequency switch device, wherein a plurality of first resistors are connected in parallel to a main switch in a switch main path, so that a bias unit provides a bias voltage to a first end and a second end of the main switch in the switch main path via the first resistor, and the impedance of the first end and the second end of the main switch is reduced, so that the absolute value of the turn-off voltage of the main switch is lower, thereby improving the floating effect, thereby improving the weak turn-on and weak turn-off phenomena, so that the main switch can be turned on or off quickly, thereby improving the switching speed of the entire switch unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the application structure of a radio frequency switch device in a radio frequency front end;

FIG2 is a schematic diagram of the structure of a single-pole double-throw radio frequency switch device;

FIG3 is a schematic diagram of the structure of a switch module;

FIG4 is a schematic structural diagram of a switch module provided in an embodiment of the present disclosure;

FIG5 is a schematic structural diagram of another switch module provided in an embodiment of the present disclosure;

FIG6 is a schematic structural diagram of another switch module provided in an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a structure of a bias unit provided in an embodiment of the present disclosure.

FIG8 is a schematic structural diagram of another switch module provided in an embodiment of the present disclosure;

FIG9 is a schematic diagram of switch switching performance provided by an embodiment of the present disclosure;

FIG10 is a schematic diagram of a switch switching method provided by an embodiment of the present disclosure;

FIG11 is a schematic diagram of another switch switching method provided by an embodiment of the present disclosure;

FIG12 is a schematic diagram of the structure of a radio frequency switch device provided in an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of the structure of another radio frequency switch device provided in an embodiment of the present disclosure.

Detailed ways

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

NMOS: N-type doped metal-oxide semiconductor field effect transistor;

PMOS: P-type doped metal-oxide semiconductor field effect transistor;

CMOS (Complementary Metal Oxide Semiconductor): Complementary Metal Oxide Semiconductor;

BJT (Bipolar Junction Transistor): Bipolar junction transistor;

HBT (Hetero Junction Bipolar Transistor): heterojunction bipolar transistor;

dB (decibel): decibel;

dBm (decibel relative to one milliwatt): decibel milliwatt;

DC（Direct Current）：direct current;

Ω (ohm): Ohm;

kΩ: kiloohm;

SH/SR (Series Connection/Series Parallel): series connection/parallel connection.

Please refer to Figure 1, which provides a schematic diagram of the application structure of an RF switch device in the RF front end. As shown in Figure 1, the multi-channel transceiver system includes an antenna, an RF switch device, a low noise amplifier LNA and a power amplifier PA. In one working scenario, the RF switch device and the low noise amplifier LNA form an electrical path. At this time, the antenna receives an external RF signal, and the external RF signal is transmitted to the low noise amplifier LNA via the RF switch device and enters the subsequent circuit (such as RF integrated circuit and/or baseband) for processing; in another working scenario, the RF switch device and the power amplifier PA form an electrical path, and the internal RF signal generated by other circuits is amplified by the power amplifier PA, and then transmitted to the antenna via the RF switch device, and continues to be sent out.

Please refer to Figure 2, which provides a schematic diagram of the structure of a single pole double throw (SP2T) RF switch device. As shown in Figure 2, the RF switch device includes two selection branches, the first selection branch is used to conduct the first signal node RFC and the first second signal node RF1, and the second selection branch is used to conduct the first signal node RFC and the second second signal node RF2. Each selection branch includes a switch module (also called SR/SH structure) formed by stacking multiple transistors in series. The specific structure of each switch module is shown in Figure 3.

As shown in FIG3 , each switch module includes a switch main circuit formed by a plurality of main switches connected in series. The main switch can be a transistor. The gate of each main switch is connected to a switch control node (the signal of the node is called a switch control signal VC) via a gate resistor Rg. At the same time, a source-drain resistor is connected in parallel between the source and drain of each main switch. For high-power RF switch devices, the more main switches are stacked in the switch module, the better the power resistance performance of the RF switch device. Specifically, on the one hand, in the small signal state, the main switch is turned on to pass the RF signal. Due to the coupling effect of the parasitic capacitance of the transistor, the RF signal will be coupled to the gate of the transistor and leak through the gate resistance of the transistor, worsening the insertion loss. Increasing the gate resistance Rg can reduce the leakage. On the other hand, in the large signal state (generally >40dBm), assuming that node 1 passes a large swing signal, the signal will be coupled to node 2 through the parasitic capacitance. If the gate resistance Rg is small, the coupled signal of node 2 leaks through the gate resistance Rg, and the voltage swing of node 2 is relatively small, resulting in the swing difference between node 1 and node 2 being too large and exceeding the breakdown voltage of the transistor, affecting the power resistance performance of the switch. If the gate resistance Rg is large, the signal coupled to node 2 is blocked by the gate resistance Rg at node 2 and is difficult to leak through the gate resistance Rg. At this time, the signal swing of node 2 is large, and the swing difference between node 1 and node 2 is within the breakdown voltage of the MOS tube. Therefore, increasing the gate resistance Rg can improve the power resistance performance of the switch.

However, the gate resistance Rg also affects the switching speed of the RF switch device. Assuming that the gate parasitic capacitance of the transistor is Cgate, the switching time of the RF switch device is generally in the order of (5×Rg×Cgate). The larger the gate resistance Rg, the longer the switching time. Considering the above insertion loss and power resistance performance, the gate resistance Rg may be in the order of 500kΩ. If Cgate~10pF at this time, the switching time reaches the order of 25us. However, in practical applications, the switching time is often required to be <1us. Here, the switching time refers to the switching time from the start of the switch control signal VC switching to the switching of node 2 to the 90% DC value of the required on/off voltage.

From the above, it can be seen that the switch structure of RF switching devices faces a serious compromise problem between insertion loss, power handling and switching speed.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In a specific embodiment, please refer to FIG4, which is a schematic diagram of the structure of a switch module 10 provided in an embodiment of the present disclosure. As shown in FIG4, the switch module 10 includes a gate resistance unit (including a common resistance chain 21 and a gate resistance array 22), a first bypass unit (including a first bypass subunit 61 and a second bypass subunit 62), and a switch main circuit 30. Specifically, during the switching period of the switch module 10, multiple switches of the first bypass subunit 61 and the second bypass subunit 62 are turned on, thereby short-circuiting the common resistance chain 21 and the gate resistance array 22, so that the switch control signal of the switch control node can quickly reach each main switch in the switch main circuit 30, greatly improving the switching speed; during the steady state period of the switch module 10, the switches in the first bypass subunit 61 and the second bypass subunit 62 are turned off, and the resistors stacked in series by the common resistance chain 21 and the gate resistance array 22 provide the gate resistance of each transistor in the switch main circuit 30, ensuring the signal insertion loss and large signal power resistance performance.

In a specific embodiment, the bypass switch in FIG. 4 is generally composed of a transistor (MOS). To meet the power handling requirement, the number of switches in the first bypass subunit 61 is at least the same as the number of main switches in the switch main path 30 .

At the same time, the switch module 10 shown in FIG. 4 uses a common bypass COM bypass (i.e., a common resistor chain 21 + a first bypass subunit 61) to provide a switch control voltage VC for each MOS supervisor, without providing multiple stacked COM bypass branches for the gate resistor Rg corresponding to each supervisor (refer to FIG. 3), so the circuit structure is relatively simple.

Assume that the source and drain of the main switch are constantly biased at +2.5V. When the main switch switches from the off steady state to the on steady state, the gate voltage of the main switch switches from 0V to +5V. When the main switch is about to be turned on, the source and drain of the middle main switch connected to the upper and lower adjacent main switches are not turned on. At this time, the impedance seen by the source and drain of the middle main switch is large, which will produce a floating effect (float) similar to the gate resistor Rg, causing the source and drain voltage of the middle main switch to follow the gate voltage to make the same switch, and ultimately causing the gate voltage to be cut to +5V (ideal state V _GS = +2.5V), and the actual gate voltage V _GS of the main switch is still at around 0V. The actual main switch is not turned on (or the turn-on voltage is small, weak turn-on), which seriously slows down the switching speed; the same problem also exists during the period when the main switch switches from the on state to the off state, which can be called "weak turn-on" and "weak turn-off" phenomena.

In another embodiment of the present disclosure, please refer to Fig. 5, which is a schematic diagram of the structure of another switch module 10 provided in an embodiment of the present disclosure. Referring to Fig. 5, the switch module 10 includes a switch control node, an RF input node, an RF output node, a plurality of main switches 31, a plurality of first resistors 41 and a bias unit 50.

Each main switch 31 includes a first end, a second end and a control end, and the control end is configured to selectively conduct the first end and the second end; as shown in FIG5 , the first end and the second end of the plurality of main switches 31 are connected in series between the RF input node and the RF output node, and the control end of each main switch 31 is connected to the switch control node;

A first resistor 41 is connected in parallel between the first end and the second end of the main switch 31, and a plurality of first resistors 41 are connected in series;

The bias unit 50 is connected to the first end or the second end of at least one first resistor 41 ; the bias unit 50 is configured to provide a bias voltage to the first end and the second end of the main switch 31 .

Taking the transistor as a MOS tube as an example, its control end is specifically a gate, its first end is one of a source and a drain, and its second end is the other of the source and the drain.

It should be noted that, taking the main switch 31 as N-type doping, i.e., NMOS, as an example, the bias unit 50 provides a positive bias voltage. Specifically, considering the power resistance and harmonic performance of the switch module 10, the turn-off voltage (turn-off voltage = gate voltage - source/drain DC voltage) of the N-type doped main switch 31 is a negative voltage. Since the bias unit 50 can provide a positive bias voltage for the source/drain of the main switch 31, the turn-off voltage does not need to be particularly small (or particularly negative), so that the turn-off voltage of the main switch 31 is desired, the circuit is less difficult to implement, and the circuit performance is more stable.

In some embodiments, please refer to Figure 6, the switch module 10 also includes a plurality of first switches 71, and a first switch 71 is connected in parallel between the first end and the second end of the main switch 31; the first switch 71 is configured to selectively short-circuit the first end and the second end of the corresponding main switch 31 in response to the first control signal VG2.

In this way, in the switching state of the switch module 10, the multiple first switches 71 can bypass the multiple first resistors 41, which is equivalent to directly short-circuiting the first end and the second end of the main switch 31. Therefore, the bias voltage provided by the bias unit 50 can be quickly given to the first end and the second end of each main switch 31 through the multiple first switches 71, and the impedance between the source and the drain is small, which improves the floating effect of the source and the drain (float will cause the source and drain voltages to change with the gate voltage), avoids weak turn-on and weak turn-off phenomena, and improves the switching speed; during the steady state of the switch module 10, the multiple first switches 71 are in the disconnected state, which will not affect the normal operation of the main switch 31; in addition, the bias unit 50 provides a constant bias voltage, which can raise the source-drain voltage domain of the main switch, thereby raising the turn-off negative voltage of the main switch, and the turn-off negative voltage of the main switch is easier to achieve.

In some embodiments, please refer to Figure 2. In the RF switch device, the switch module 10 can be divided into two types: one type has an RF output node connected to the second signal nodes RF1 and RF2, which can be regarded as the RF output node being connected in series with the next-level RF device (and/or the previous-level RF device), and the other type has an RF output node connected in series with the ground signal.

When the RF output node of the switch module 10 is connected to the ground terminal, the internal resistance of the bias unit 50 is a first value to provide a first bias voltage, and the output terminal of the bias unit 50 is connected to the end of the main switch 31 closest to the ground terminal.

When the RF output node of the switch module 10 is connected to the next-stage RF device/previous-stage RF device (i.e., the second signal nodes RF1 and RF2), the internal resistance of the bias unit 50 is a second value to provide a second bias voltage, and at this time, the output end of the bias unit 50 is preferably connected to the end of the main switch 31 closest to the next-stage RF device/previous-stage RF device, but the bias unit 50 may also be connected to the first end or the second end of the other main switch 31.

It should be noted that the first bias voltage and the second bias voltage have the same voltage value, the first value is smaller than the second value, 10Ω≤first value≤200Ω, for example, 50Ω, 100Ω or 150Ω, and the second value≥100kΩ, for example, 200kΩ, 300kΩ or 400kΩ, that is, the first value is approximately on the order of 100 ohms, and the second value is approximately on the order of 100,000 ohms.

That is to say, if the RF output node of the switch module 10 is connected to the node RF1, or the node RF2, etc., the internal resistance of the bias unit 50 therein is relatively large (on the order of hundreds of kΩ), which can be provided by a circuit structure such as a resistor divider. The main function here is to stabilize the bias voltage and will not affect the performance such as small signal insertion loss; if the RF output node of the switch module 10 is connected to the ground terminal, the bias source internal resistance of the bias unit 50 therein is small (on the order of hundreds of Ω), which is used to provide a smaller impedance to the source and drain of the main switch during the switching process, thereby reducing the disturbance caused by the coupling phenomenon on the source and drain DC bias of the main switch 31 during the switching process, and improving the switching speed.

Exemplarily, FIG7 shows a schematic diagram of the structure of a bias unit 50. As shown in FIG7, the bias unit includes a plurality of voltage divider units, a plurality of transistors and an operational amplifier (AMP), and the specific connection relationship thereof is shown in the figure. FIG7 takes the voltage divider unit as a resistor as an example for explanation. At the same time, the bias unit works based on the power supply voltage VDD and the bias auxiliary signal Vbis, and generates an output signal Vout (i.e., the bias voltage of the switch module 10) in a feedback manner. Specifically, the first voltage divider unit RC and the second voltage divider unit RD are connected in series between the power supply voltage VDD and the ground, the first end of the first voltage divider unit RC is connected to the power supply voltage VDD, the second end of the first voltage divider unit RC is connected to the first end of the second voltage divider unit RD, and the second end of the second voltage divider unit RD is grounded. The connection node between the first voltage divider unit RC and the second voltage divider unit RD is connected to the first input end of the operational amplifier AMP. The output end of the operational amplifier AMP is connected to the gate (control end) of the first transistor _ML1 , the source (first end) of the first transistor _ML1 is connected to the power supply voltage VDD, the drain (second end) of the first transistor _ML1 is connected to the drain (first end) of the second transistor _ML2 , the gate (control end) of the second transistor _ML2 is connected to the bias auxiliary signal Vbis, and the source (second end) of the second transistor _ML2 is grounded. The source of the third transistor _ML3 is connected to the power supply voltage VDD, the gate (control end) of the third transistor _ML3 is connected to the drain of the first transistor _ML1 , and the source of the third transistor _ML3 outputs the output signal Vout. The drain of the third transistor _ML3 is connected to one end of the third voltage dividing unit RA, the other end of the third voltage dividing unit RA is connected to one end of the fourth voltage dividing unit RB, the other end of the fourth voltage dividing unit RB is grounded, and the second end of the third voltage dividing unit RA is connected to the second input end of the operational amplifier AMP, for inputting the feedback signal Vtak to the second input end of the operational amplifier AMP.

The reference signal Vref has a proportional relationship with the working power signal VDD (the first voltage divider unit RC and the second voltage divider unit RD are connected in series for voltage division). At the same time, after the entire bias unit is balanced, the voltages of the two input signals of the operational amplifier (reference signal Vref and feedback signal Vtak) are the same, and the output signal Vout has a proportional relationship with the feedback signal Vtak (the third voltage divider unit RA and the fourth voltage divider unit RB are connected in series for voltage division). Therefore, the output signal Vout has a functional relationship with the working power signal VDD. In this way, through the bias unit shown in FIG. 7, an output signal with a relatively stable voltage value can be output, which is used as the bias voltage of the switch module 10.

Here, looking from the output end of the bias unit, the equivalent resistance of the bias unit is regarded as the resistance or internal resistance of the bias unit 50 .

The bias unit 50 shown in FIG7 can provide a stable bias voltage to avoid affecting the RF signal. The bias unit 50 can conveniently adjust the internal resistance of the bias unit 50 by adjusting the resistance values of the third voltage divider unit RA, the fourth voltage divider unit RB, the first voltage divider unit RC, and the second voltage divider unit RD to conveniently provide the first value and the second value of the internal resistance, ensuring that the small signal insertion loss is not affected and avoiding disturbances during the switching process.

In some embodiments, the bias unit 50 further includes a first capacitor C _L1 and a second capacitor C _L2 . The first capacitor C _L1 is connected in parallel to both ends of the second voltage divider unit RD, and the second capacitor C _L2 is connected in parallel between the second end of the third transistor M _L3 and the ground. The first capacitor C _L1 and the second capacitor C _L2 can filter to further improve the stability of the bias voltage.

In some other embodiments, the bias unit 50 may also be a linear regulator, which may be a positive adjustable regulator, a negative adjustable regulator, a fixed output regulator, a tracking regulator or a floating regulator, etc. The linear regulator may also provide a bias voltage.

In some embodiments, referring to FIG. 6 , the switch module 10 further includes a plurality of second resistors 221 and a plurality of second switches 621 ; a second resistor 221 is connected in parallel between the control ends of two adjacent main switches 31 ; both ends of the second switch 621 are connected in parallel with the second resistor 221 , and the second switch 621 is configured to selectively short-circuit the second resistor 221 in response to the second control signal VG1 .

In some embodiments, please refer to Figure 6, the switch module 10 also includes a common resistor chain 21 and a plurality of third switches 611, the control end of at least one main switch 31 is provided with a common resistor chain 21, and the switch control node reaches the control end of the corresponding main switch 31 via the common resistor chain 21; the common resistor chain 21 includes a plurality of third resistors 211, in each common resistor chain 21, the first third resistor 211 is connected to the switch control node, and the last third resistor 211 is connected to one of the second resistors 221; both ends of the third switch 611 are connected in parallel with the third resistor 211, and the third switch 611 is configured to selectively short-circuit the third resistor 211 in response to the second control signal VG1.

In this way, when the switch module 10 switches its state (from on to off, and from off to on), the second switch 621 and the third switch 611 are turned on, and the plurality of third resistors 211 and the plurality of second resistors 221 are bypassed. At this time, the resistance between the control end of the main switch 31 and the switch control node is very small, so that the switch control signal VC of the switch control node can be quickly transmitted to the gate of each main switch 31, greatly improving the switching speed; during the steady state period of the switch main path 30, the second switch 621 and the third switch 611 are turned off, so the third resistor 211/second resistor 221 with a larger resistance value can prevent the gate leakage problem.

In addition, when the switch module 10 is in the open steady state or the closed steady state, the bias unit 50 provides a positive voltage bias for the source and drain of each main switch 31 through the first resistor 41. During the switching process, the bias unit 50 serves to weaken the coupling effect on the source and drain of the main switch 31 and improve the weak opening and weak closing phenomena.

In order to prevent the area of the switch module 10 from being too large, the number of the shared resistor chains is generally less than or equal to three.

It should be noted that in FIG. 6 , the second resistor 221 is not provided between the gates of the two main switches 31 in the middle, so the gates of the two main switches 31 in the middle are only coupled to the switch control node (which transmits the switch control signal VC) through the common resistor chain 21; that is, taking FIG. 6 as an example, in the switch main path 30, the main switch 31 located in the middle position is coupled to the switch control node via the common resistor chain 21 without passing through the second resistor 221, and the main switch 31 located in the non-middle position is coupled to the switch control node via at least part of the second resistor 221 and the common resistor chain 21. However, this is only an example, and in other embodiments, the second resistor 221 may also be provided between the gates of the two main switches 31 in the middle.

It should be noted that different shared resistor chains 21 may include the same number of third resistors 211, or different shared resistor chains 21 may include different numbers of third resistors. In particular, in order to better share the voltage and protect the transistor from breakdown, the total number of the third resistors 211 in each shared resistor chain 21 is greater than or equal to the number of the main switches 31.

In this way, the switch main circuit 30 can reuse the shared resistor chain 21, so there is no need to provide multiple stacked resistors for each main switch 31, reducing circuit costs; at the same time, there can be multiple shared resistor chains 21, thereby further improving the speed of signal switching.

Exemplarily, as shown in FIG6 , when the number of shared resistor chains 21 is 1, the main switch 31 at the middle position is provided with the shared resistor chain 21; that is, the third resistor 211 at the end of the shared resistor chain is electrically connected to the second resistor at the middle position; the second resistor at the middle position means that the number of resistors between the second resistor and the first second resistor is half or approximately half of the total number of second resistors, or it can be understood that the number of main switches between the main switch 31 at the middle position and the RF input node is equal to or substantially equal to the number of main switches between the main switch 31 at the middle position and the RF output node.

When the number of shared resistor chains 21 is 2, the main switch 31 at the 1/3 position is provided with the first shared resistor chain; for the second shared resistor chain 21, the main switch 31 at the 2/3 position is provided with the second shared resistor chain 21; that is: for the first shared resistor chain 21, the third resistor 21 at the end is electrically connected to the second resistor 221 at the 1/3 position; as shown in FIG8, for the second shared resistor chain 21, the third resistor 211 at the end is electrically connected to the second resistor 221 at the 2/3 position. The second resistor at the 1/3 position means that the number of resistors between the second resistor and the first second resistor is 1/3 or approximately 1/3 of the total number of second resistors. Or it can be understood that the number of main switches between the main switch 31 at the 1/3 position and the RF input node is equal to or substantially equal to the number of main switches between the main switch 31 at the 2/3 position and the RF output node, and is equal to or substantially equal to the number of main switches between the main switch 31 at the 1/3 position and the main switch 31 at the 2/3 position.

It should be noted that the resistance of the third resistor 211 is smaller than the resistance of the second resistor 221. Exemplarily, 100Ω≤the resistance of the third resistor 211 is less than≤10kΩ, the overall resistance of each common resistor chain is ≥10kΩ, and 10kΩ≤the resistance of the second resistor 221 is ≤200kΩ. The above are only examples, and the specific values can be adjusted according to the actual application scenario.

When the signal path between the switch control node and the gate of each main switch 31 does not short-circuit the gate resistance, the equivalent impedance between the switch control node and the gate of each main switch 31 is greater than 100,000 ohms (i.e., 100 kΩ), so that the gate leakage problem is relatively small when the switch main circuit 30 is in the on steady state.

In addition, the resistance values of the multiple third resistors 211 in each shared resistor chain 21 are not completely the same, so as to balance the voltage division of the first switch 611. Specifically, in a steady state, when the first switch tube 31 passes a high-power signal, it will be coupled to the shared resistor chain 21. At this time, the first switch 611 will share the voltage swing, but different switch devices generally have various non-ideal parasitic parameters, resulting in unbalanced secondary voltage division. The resistance values of different third resistors 211 in the present application are not completely the same, so the first switch 611 can be designed for balanced voltage division; for example, in FIG6, along the left direction, the resistance value of the third resistor 211 in the shared resistor chain 21 can be gradually reduced, or other resistance fluctuation methods can be used. For the second gate resistor array 22, the resistance values of different second resistors 221 can be completely the same or not completely the same.

In some embodiments, referring to FIG. 6 or FIG. 8 , the switch module 10 further includes a plurality of fourth resistors 612 / 622 , the control end of the third switch 611 receives the second control signal VG1 via a fourth resistor 612 , and the control end of the second switch 621 receives the second control signal VG1 via a fourth resistor 622 .

The switch module 10 further includes a plurality of fifth resistors 72 . The control end of each first switch 71 receives the first control signal VG2 via a fifth resistor 72 .

Here, the resistance values of the fourth resistor 621 / 622 and the fifth resistor 72 are both greater than 100 kΩ, thereby reducing the gate leakage problem of the first switch 71 , the second switch 621 and the third switch 611 when they are turned on.

It should be noted that, on the one hand, when the switch module 10 is in the on steady state/off steady state, it is necessary to pay attention to its insertion loss and power resistance performance. The first resistor 41, the second resistor 221, and the third resistor 211 are not short-circuited, thereby forming the gate resistance or source-drain resistance of the main switch 31. In order not to short-circuit the first resistor 41, the second resistor 221, and the third resistor 211, the first switch 71, the second switch 621, and the third switch 611 are in the off state. However, due to the parasitic capacitance coupling therein, the signal may leak through the gate. Therefore, a high-resistance fourth resistor 621/622 and a fifth resistor 72 are required to prevent signal leakage; on the other hand, when the switch module 10 is in the switching state, it is necessary to pay attention to its switching speed. At this time, the first switch 71, the second switch 621, and the third switch 611 are in the on state, thereby short-circuiting the parallel resistors and improving the switching speed.

In particular, the bias unit 50 can also reduce the turn-off voltage of the second switch 621 and the third switch 611. Exemplarily, assuming that when the main switch 31 is turned off, the voltage between the gate and the drain is V _GS =-2.5V. Generally, the source-drain voltage of the main switch 31 is 0V. Therefore, the switch control signal V _C ≤-2.5V can enable the main switch to achieve a good turn-off effect; and at this time, the second control signal VG1≤-5V can turn off the second switch 621 and the third switch 611 well, but the second control signal VG≤-5V is difficult to achieve in the CMOS process. In order to solve this problem, the bias unit 50 provides a bias voltage between the gate and the drain of the main switch, and the specific voltage value is +2.5V. At this time, the switch control signal V _C ≤0V can turn off the main switch 31, and the second control signal VG≤-2.5V can turn off the second switch 621 and the third switch 611 well, and the circuit performance is more stable and the cost is lower.

It should be noted that the switches mentioned above may be various types of transistors with switch functions, such as MOS, BJT, and HBT. The embodiments of the present disclosure will be described below using only N-type MOS transistors as an example.

In summary, the embodiments of the present disclosure provide a switch module 10 with fast switching speed and small gate leakage, and provide specific embodiments of various structures.

In the first specific embodiment, please refer to FIG. 6 , which has the following specific features:

(1) Three types of bypass switches are introduced into the switch module 10: a plurality of first switches 71, a plurality of second switches 621, and a plurality of third switches 611; the on/off of each second switch 621 and each third switch 611 is controlled by the second control signal VG1, the on/off of each first switch 71 is controlled by the first control signal VG2, and the switch control signal VC is the gate control voltage of the main switch 31, which controls the on/off of the switch module 10;

(2) When the main tube in the switch module 10 is in the switching state, all the first switches 71, all the second switches 621, and all the third switches 611 are turned on, and the switch control signal VC is quickly transmitted to the gate of the main tube. When the transmission of the switch control signal VC is completed, all the first switches 71, all the second switches 621, and all the third switches 611 are turned off;

(3) All bypass switches are equipped with higher gate resistance (>100kOhm) to reduce signal leakage introduced by the bypass switch and ensure power handling capability;

(4) The source-drain voltage of the main switch is a constant bias positive voltage provided by the bias unit 50, which is used to raise the source-drain voltage domain of the main switch, thereby raising the turn-off voltage of the main switch, causing the source-drain voltage domain of the second switch 621 and the third switch 611 to be raised, and further raising the turn-off voltage of the second switch 621 and the third switch 611. Therefore, the second control signal VG1 does not need to be reduced to -5V to turn off the second switch 621 and the third switch 611, so that the minimum negative voltage required is -3.3~-2.5V.

(6) Comparing FIG6 with FIG4, it can be seen that the switch module 10 additionally introduces a third type of bypass switch: the first switch 71, and during the switching of the switch module 10, all the first switches 71 are turned on, thereby short-circuiting the source and drain of all the main pipes. The benefits of this are as follows: by introducing the bias unit 50 and the first switch 71, when the switch module 10 is switched, since the first switch 71 is turned on, the source and drain of each level of the main pipe are connected to the +2.5V bias point through the first switch 71, which is a +2.5V strong bias. At this time, the impedance seen by the source and drain voltage of the main pipe is reduced, the float effect is weakened, and the switching speed of the main switch V _GS is improved; in short, the introduction of the first switch 71 makes the source and drain voltage of each level of the main pipe in a strong bias state during switching, thereby improving the switching speed.

Please refer to FIG9, which shows a schematic diagram of the switch switching performance provided by an embodiment of the present disclosure. As shown in FIG9, curve 1 describes the voltage change of the switch control signal VC, curve 2 describes the change of the gate voltage of the main switch 31 introduced with the fast switching circuit (see the switch module of FIG6), and curve 3 describes the change of the gate voltage of the main switch 31 without the fast switching circuit (see the switch module of FIG3); at this time, after the fast switching circuit is introduced, the gate voltage switching time of the main switch 31 is reduced from the original 6us to 220ns (90% of the DC stable value).

In summary, the embodiments of the present disclosure provide a switch module, which provides a bias voltage for each transistor in the switch main circuit through a bias unit. When the state is switched, the second control signal only needs to reach a relatively low negative voltage to close the bypass switch in the first bypass unit, and the circuit implementation is simple; a shared resistor chain can provide gate resistance for multiple main switches at the same time, and there is no need to provide multiple stacked gate resistors for each main switch separately, and the circuit area is small; when the state is switched, the gate resistance of the main switch is bypassed, thereby improving the switching speed.

In another embodiment of the present disclosure, referring to FIG. 10 or FIG. 11, a schematic diagram of a switch switching method provided by an embodiment of the present disclosure is shown. The method is applied to the aforementioned switch module 10, and the switch control node of the switch module 10 receives the switch control signal VC, and the switch module 10 also works in response to the second control signal VG1 and the first control signal VG2.

In some embodiments, the switch control signal VC may be generated by a level shift circuit.

In some embodiments, a signal control module receives an external instruction, the external instruction indicates the action mode of the main switch 31, the action mode of the first switch 71, the action mode of the third switch 611, and the action mode of the second switch 621, the action mode including the on (i.e., turned on) or off (i.e., turned off) of these switches;

According to external instructions, a main control signal VC, a first control signal VG2, and a second control signal VG1 are generated. The main control signal VC controls the opening or closing of the main switch, the first control signal VG2 controls the opening or closing of the first switch 71, and the second control signal VG1 controls the opening or closing of the second switch 621 and the third switch 611.

When the external command instructs the main switch 31 to turn on:

A main control signal VC is sent to the main switch 31 to control the main switch 31 to switch on; a first control signal VG2 is sent to the first switch 71 to control the first switch 71 to switch on; a second control signal VG1 is sent to the second switch 621 and the third switch 611 to control the second switch 621 and the third switch 611 to switch on; at this time, the state of the previous switching period in FIG. 10 may be referred to;

After the first time period: a first control signal VG2 is sent to the first switch 71 to control the first switch 71 to switch off; a second control signal VG1 is sent to the second switch 621 and the third switch 611 to control the second switch 621 and the third switch 611 to switch off. At this time, reference can be made to the state of turning on the steady state in FIG. 11; in some embodiments, the first time period is very short, the first time period can be from a few milliseconds to several hundred milliseconds, and the first time period is the time period of the previous switching period in FIG. 10.

When the external command instructs the main switch 31 to be turned off:

A main control signal VC is sent to the main switch 31 to control the main switch 31 to switch off; a first control signal VG2 is sent to the first switch 71 to control the first switch 71 to switch on; a second control signal VG1 is sent to the second switch 621 and the third switch 611 to control the second switch 621 and the third switch 611 to switch on; at this time, the state of the latter switching period in FIG. 10 may be referred to;

After the second time period: a first control signal VG2 is sent to the first switch 71 to control the first switch 71 to switch off; a second control signal VG1 is sent to the second switch 621 and the third switch 611 to control the second switch 621 and the third switch 611 to switch off. At this time, reference can be made to the state of the closed steady state in FIG. 11; in some embodiments, the second time period is very short, the second time period can be from a few milliseconds to several hundred milliseconds, and the second time period is the time period of the latter switching period in FIG. 11.

Referring to FIG. 10 or FIG. 11 , the switch switching method includes:

(1) When the switch module 10 is in the off steady state (ie, the main switch is turned off), the switch control signal VC is the first voltage value VN, the second control signal VG1 is the third voltage value VN2, and the first control signal VG2 is the first voltage value VN.

(2) When the switch module 10 switches from the off steady state to the on steady state, the switch control signal VC is the second voltage value VP, the second control signal VG1 is the fourth voltage value VP2, and the first control signal VG2 is the second voltage value VP;

(3) When the switch module 10 is in the on steady state, the switch control signal VC is the second voltage value VP, the second control signal VG1 is the fifth voltage value V0, and the first control signal VG2 is the first voltage value VN ( FIG. 10 ) or the second voltage value VP ( FIG. 11 );

(4) When the switch module 10 switches from the switch steady state to the switching steady state, the switch control signal VC is the first voltage value VN, the second control signal VG1 is the fourth voltage value VP2, and the first control signal VG2 is the second voltage value VP.

It should be noted that the fifth voltage value V0 is also the bias voltage provided by the bias unit 50 .

In some embodiments, when the transistors in the switch module 10 are all N-type doped, the first voltage value VN and the third voltage value VN2 are both negative voltages, and the second voltage value VP, the fourth voltage value VP2 and the fifth voltage value V0 are all positive voltages. In other embodiments, the first voltage value VN may also be 0.

That is, the third voltage value VN2<the first voltage value VN≤0<the fifth voltage value V0<the second voltage value VP<the fourth voltage value VP2.

In some embodiments, the third voltage value VN2 is greater than or equal to -3.3V, and the fourth voltage value VP2 is less than or equal to 6V.

In a specific embodiment, VN=-0.8V, VN2=-3.3V, VP=+5V, VP2=+6V, V0=+1.7V.

Please refer to FIG. 6 or FIG. 8 , during the shutdown steady state, all the main switches 31 are in the closed state, so that the RF input node and the RF output node are electrically isolated, and all the second switches 621, all the third switches 611 and all the first switches 71 are in the closed state;

During the switching from the closed steady state to the open steady state, all the main switches 31 gradually change to the open state, so that the RF input node and the RF output node gradually change to be electrically connected, and at the same time, all the second switches 621 and all the third switches 611 are in the open state, and the corresponding resistors are bypassed, so that the switch control signal VC is transmitted to the gate of each main switch 31, and the opening speed is accelerated; at the same time, all the first switches 71 are in the open state, and the bias unit 50 provides a positive bias voltage (for example, V0=+2.5V) between the source and drain of each main switch 31 to improve the float effect;

During the on-state period, all main switches 31 are in the on state, so that the RF input node and the RF output node are electrically connected, and all second switches 621 and all third switches 611 are in the off state; since all main switches 31 are in the on state at this time, all first switches 71 can be on or off;

During the switching from the closed steady state to the open steady state, all the main switches 31 gradually change to the closed state, so that the RF input node and the RF output node gradually change to be electrically isolated. At the same time, all the second switches 621, all the third switches 611 and all the first switches 71 are in the open state, which speeds up the switching speed and improves the float effect.

In another embodiment of the present disclosure, a radio frequency switch device 80 is provided. The radio frequency switch device 80 includes a plurality of selection branches. Each selection branch includes at least one switch module connected in series and at least one switch module connected in parallel. The switch module is the aforementioned switch module 10.

In some embodiments, the RF switching device further includes a plurality of DC blocking capacitors, which are connected in series with the plurality of switch modules; and the capacitance value of the DC blocking capacitors is greater than 20 pF.

In some embodiments, at least some of the switch modules connected in series share the same bias unit 50, and the bias unit 50 provides a second bias voltage (weak bias); the switch modules connected in parallel have their own bias units 50, and the bias unit 50 provides a first bias voltage (strong bias).

In a specific embodiment, referring to FIG12, a schematic diagram of the structure of a radio frequency switch device 80 is shown. As shown in FIG12, the radio frequency switch device 80 includes N selection branches (FIG12 shows N=2), each of which includes a switch module 10 connected in series and a switch module 10 connected in parallel; it should be understood that 10x in FIG12 represents the circuit structure of the switch module 10 except the bias unit 50;

The RF input nodes of the first switch modules (equivalent to the parallel structure SR) in all the selection branches are coupled to the same first signal node RFC, and the RF output nodes of the first switch modules in the nth selection branch are coupled to the nth second signal node (e.g., RF1 and RF2 in FIG. 12 ); n and N are both positive integers, n≤N;

The RF input node of the second switch module (equivalent to the series structure SH) in the nth selection branch is coupled to the RF output node of the first switch module in the corresponding selection branch, and the RF output node of the second switch module in each selection branch is coupled to the ground terminal.

In FIG12 , the second signal nodes RF1 and RF2 are respectively connected to different next-stage RF devices/previous-stage RF devices, VC_RF1 refers to the switch control signal of the first switch module in the first selection branch, VG1_RF1 refers to the second control signal of the first switch module in the first selection branch, and VG2_RF1 refers to the first control signal of the first switch module in the first selection branch; VC_H refers to the switch control signal of the second switch module in the first selection branch, VG1_H refers to the second control signal of the second switch module in the first selection branch, and VG2_H refers to the first control signal of the first switch module in the first selection branch. ; VC_RF2 refers to the switch control signal of the first switch module in the second selection branch, VG1_RF2 refers to the second control signal of the first switch module in the second selection branch, and VG2_RF2 refers to the first control signal of the first switch module in the second selection branch; VC_H_RF2 refers to the switch control signal of the second switch module in the second selection branch, VG1_H_RF2 refers to the second control signal of the second switch module in the second selection branch, and VG2_H_RF2 refers to the first control signal of the second switch module in the second selection branch.

It should also be noted that, although the two switch modules in the selection branch have similar structures, the device parameters in the two switch modules may be different, and the device parameters at least include the size of the transistor and the size of the resistor.

It should be noted that the RF output port of the first switch module in each selection branch is connected to the next-stage RF device, and the first switch modules in all selection branches share a bias unit 50, and the bias unit 50 provides a second bias voltage.

The RF output port of the second switch module in each selection branch is connected to the ground terminal, and the second switch module in each selection branch has a respective bias unit 50 , and the bias unit 50 provides a first bias voltage.

That is, the internal resistance of the bias unit of the first switch module in each selection branch is relatively large, that is, node 1 adopts weak bias, and the internal resistance of the bias unit of the second switch module in each selection branch is relatively small, that is, node 2 adopts strong bias.

Specifically, (1) in the RF switch device, the main source and drain bias includes two constant positive voltage biases (the bias voltage is consistent). The bias 1 of the series switch module 10 is a weak bias (the bias source has a large internal resistance, in the order of hundreds of kΩ), which can be provided by a circuit structure such as a resistor divider. The main function here is to stabilize the bias voltage. If only node 2 is used for biasing, leakage current may exist due to the influence of the bias source impedance, resulting in the actual bias voltage at node 1 being lower than expected; at the same time, the bias source internal resistance of node 1 is large, which will not affect the performance such as small signal insertion loss; (2) bias 2 is a strong bias (the bias source has a small internal resistance, within the order of hundreds of Ω), which is used to provide a smaller impedance to the main source and drain during the switching process to increase the switching speed; bias point 2 can be provided by an internal bias unit or direct power supply from outside the chip.

During the switching period, for the switch modules connected in series and in parallel, the first switch 71 is in the on state, so regardless of the switch modules connected in series or in parallel, the source and drain of the main switch are connected to the parallel strong bias 2 through their respective first switches 71. In addition, for the strong bias 2, its voltage is not easily affected by voltage fluctuations (small internal resistance), so during the switching period, the source and drain voltages of the main switches connected in series and in parallel are relatively stable on the bias voltage, with small fluctuations, and only the gate voltage of the main switch is switched, at which time the gate-source voltage Vgs of the main switch switches faster, thereby improving the switching speed.

It should also be noted that, since the switch module 10 provides a constant positive voltage bias to the source and drain of each transistor in the main circuit, it is necessary to introduce a capacitor to the RF input/output port for DC isolation. The disclosed embodiment uses a series capacitor for DC isolation. The DC isolation capacitor often uses a matching electrostatic protection structure, such as an electrostatic protection structure made of a transistor, which will have leakage current. In this solution, node 1 uses a weak bias with a larger impedance, which can adjust the size of the leakage current and improve the leakage current.

Specifically, as shown in FIG12 , the RF switch device 80 further includes a first DC blocking capacitor 81 , N second DC blocking capacitors 82 , and N third DC blocking capacitors 83 ;

The RF input node of the first switch module 10 in all the selection branches is coupled to the first signal node via the first DC blocking capacitor 81;

The RF output node of the first switch module 10 in the nth selection branch is coupled to the nth second signal node via the nth second DC blocking capacitor 82;

The RF output node of the second switch module 10 in the nth selection branch is coupled to the ground via the nth third DC blocking capacitor 83 .

It should be noted that, considering the impact on insertion loss and matching performance, the capacitance values of the first DC blocking capacitor, any second DC blocking capacitor and any third DC blocking capacitor are greater than 20 pF.

It should also be noted that FIG. 12 is only a specific example of the RF switch device 80 , and the RF switch device 80 may include more branches.

Figure 13 provides an RF device formed by combining multiple RF switch devices 80. In particular, there is no need to set a DC blocking capacitor 81 in Figure 13 because the left and right sides of node 1 are both biased with a constant positive voltage. Similarly, in Figure 13, VC_RF3/VG1_RF3/VG2_RF3, VC_H_RF3/VG1_H_RF3/VG2_H_RF/3, VC_RF4/VG1_RF4/VG2_RF4, VC_H_RF4/VG1_H_RF4/VG2_H_RF/4 refer to the switch control signal/second control signal/first control signal of the corresponding switch module 10.

The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims (15)

1. A switch module, characterized in that the switch module comprises a switch control node, a radio frequency input node, a radio frequency output node, a plurality of first resistors, a plurality of main switches and a bias unit;

each of the main switches includes a first terminal, a second terminal, and a control terminal configured to selectively turn on the first terminal and the second terminal; the first ends and the second ends of the main switches are connected in series between the radio frequency input node and the radio frequency output node, and the control end of each main switch is connected to the switch control node;

The first resistor is connected in parallel between the first end and the second end of the main switch;

The bias unit is connected with a first end or a second end of at least one main switch; the bias unit is configured to provide a constant bias voltage to the first end and the second end of the main switch;

When the radio frequency output node of the switch module is connected with a grounding end, the internal resistance of the bias unit is a first value, and when the radio frequency output node of the switch module is connected with a previous-stage radio frequency device or a next-stage radio frequency device, the internal resistance of the bias unit is a second value; the first value is less than the second value; the first value is less than or equal to 10 omega and less than or equal to 200 omega, and the second value is more than or equal to 100k omega.

2. The switch module of claim 1, wherein the biasing unit comprises:

The first end of the first voltage dividing unit is connected with the power supply voltage, the second end of the first voltage dividing unit is connected with the first end of the second voltage dividing unit, and the second end of the second voltage dividing unit is grounded;

The first input end of the operational amplifier is connected with the second end of the first voltage dividing unit, and the second input end of the operational amplifier receives a feedback signal;

The first end of the first transistor is connected with the power supply voltage, the second end of the first transistor is connected with the first end of the second transistor, the second end of the second transistor is grounded, the control end of the first transistor is connected with the output end of the operational amplifier, and the control end of the second transistor receives a bias auxiliary signal;

A third transistor, a control terminal of which is connected to the second terminal of the first transistor, a first terminal of which is connected to the power supply voltage, and a second terminal of which outputs the bias voltage;

The first end of the third voltage division unit is connected with the second end of the third transistor, the second end of the third voltage division unit is connected with the first end of the fourth voltage division unit, the second end of the fourth voltage division unit is grounded, and the second end of the third voltage division unit outputs the feedback signal.

3. The switch module of claim 2, wherein the biasing unit further comprises:

The first capacitor is connected with the second voltage division unit in parallel;

And the second capacitor is connected in parallel between the second end of the third transistor and ground.

4. The switch module of claim 1, wherein the biasing unit is a linear regulator.

5. The switch module as claimed in claim 1, wherein,

When the radio frequency output node of the switch module is connected with the grounding end, the bias unit provides a first bias voltage, and the output end of the bias unit is connected to one end, closest to the grounding end, of the main switch, closest to the grounding end;

when the radio frequency output node of the switch module is connected with a previous stage radio frequency device or a next stage radio frequency device, the bias unit provides a second bias voltage;

Wherein the first bias voltage and the second bias voltage have the same voltage value.

6. The switch module of claim 1 wherein the bias voltage is a positive voltage if the main switch is N-doped.

7. The switch module of any one of claims 1-6, further comprising a plurality of first switches, the first resistors being connected in parallel with the first switches;

the first switch is configured to selectively short the first resistor in response to a first control signal.

8. The switch module of any of claims 1-6, further comprising a plurality of second resistors and a plurality of second switches;

The second resistors are connected in parallel between the control ends of the adjacent 2 main switches;

the two ends of the second switch are connected with the second resistor in parallel, and the second switch is configured to respond to a second control signal to selectively short-circuit the second resistor.

9. The switch module of claim 8, further comprising at least one common resistor chain and a plurality of third switches, wherein a control terminal of at least one of the main switches is provided with the common resistor chain, and the switch control node reaches the control terminal of the corresponding main switch after passing through the common resistor chain;

the common resistor chains each include a plurality of third resistors, in each of the common resistor chains, a first one of the third resistors is connected to the switch control node, and a last one of the third resistors is connected to one of the second resistors;

two ends of the third switch are connected with the third resistor in parallel, and the third switch is configured to respond to a second control signal to selectively short the third resistor;

when the number of the common resistor chains is1, the main switch at the middle position is provided with the common resistor chains;

When the number of the common resistor chains is 2, the 1 st common resistor chain is arranged on the main switch at the 1/3 position; for the 2 nd common resistor chain, the main switch at the 2/3 position is provided with the 2 nd common resistor chain.

10. The switch module as claimed in claim 9, wherein,

The total number of the third resistors is larger than or equal to the total number of the main switches, and the resistance value of the second resistor is smaller than or equal to 200kΩ and is smaller than or equal to 10 k Ω;

the resistance value of the third resistor is less than or equal to 100 omega and less than or equal to 10k omega;

In the same common resistor chain, the resistances of the plurality of third resistors are not identical.

11. A switching method applied to a switching module according to any one of claims 8-10, the method comprising:

receiving an external instruction, wherein the external instruction indicates action modes of the main switch, the first switch, the second switch and the third switch, and the action modes comprise on or off of the switches;

Generating a main control signal, a first control signal and a second control signal according to the external instruction, wherein the main control signal controls the on or off of the main switch, the first control signal controls the on or off of the first switch, and the second control signal controls the on or off of the second switch and the third switch;

When the external instruction instructs the main switch to be on:

Sending the main control signal to the main switch to control the main switch to be switched on; transmitting the first control signal to the first switch to control the first switch to be on; transmitting the second control signal to the second switch and the third switch to control the second switch and the third switch to on;

After a first period of time:

Transmitting the first control signal to the first switch to control the first switch to off; transmitting the second control signal to the second switch and the third switch to control the second switch and the third switch to off;

When the external instruction instructs the main switch to be off:

transmitting the main control signal to the main switch to control the main switch to be off; transmitting the first control signal to the first switch to control the first switch to be on; transmitting the second control signal to the second switch and the third switch to control the second switch and the third switch to on;

after a second period of time:

Transmitting the first control signal to the first switch to control the first switch to off; and sending the second control signal to the second switch and the third switch to control the second switch and the third switch to be switched to be closed.

12. The method of claim 11, wherein the step of determining the position of the probe is performed,

When the external instruction instructs the main switch to be on: the switch control signal is changed from a first voltage value to a second voltage value, the first control signal is changed from the first voltage value to the second voltage value, and the second control signal is changed from a third voltage value to a fourth voltage value;

After the first period of time:

The switch control signal is the second voltage value, the first control signal is the first voltage value or the second voltage value, and the second control signal is changed into a fifth voltage value;

When the external instruction instructs the main switch to be off:

The switch control signal is the first voltage value, the first control signal is the second voltage value, and the second control signal is the fourth voltage value;

After the second period of time:

The switch control signal is a first voltage value, the first control signal is a first voltage value, and the second control signal is a third voltage value;

Under the condition that transistors or switches in the switch module are doped with N types, the third voltage value is less than or equal to 0 and less than or equal to the fifth voltage value is less than or equal to 0 and the second voltage value is less than or equal to the fourth voltage value, and the bias voltage provided by a bias unit in the switch module is the fifth voltage value.

13. A radio frequency switching device, characterized in that it comprises a plurality of selection branches, each selection branch comprising at least one switching module in series and at least one switching module in parallel, said switching modules being the switching modules according to any of claims 1-10.

14. The device of claim 13, wherein the radio frequency switching device further comprises a plurality of blocking capacitors, a plurality of the blocking capacitors being connected in series with a plurality of the switching modules;

the capacitance value of the blocking capacitor is larger than 20 picofarads.

15. The device of claim 14, wherein the device further comprises a semiconductor die,

The switch modules which are at least partially connected in series share the same bias unit, and the bias unit provides a second bias voltage; the switch modules in parallel have respective bias units, and the bias units provide a first bias voltage.