CN117640270A

CN117640270A - An FPGA-based method for sending large packets of data via Gigabit multicast

Info

Publication number: CN117640270A
Application number: CN202311492507.9A
Authority: CN
Inventors: 张远安; 袁子乔; 杨刚; 陈颖哲; 王岩; 赵博; 魏鹏伟
Original assignee: Xian Electronic Engineering Research Institute
Current assignee: Xian Electronic Engineering Research Institute
Priority date: 2023-11-09
Filing date: 2023-11-09
Publication date: 2024-03-01
Anticipated expiration: 2043-11-09
Also published as: CN117640270B

Abstract

The invention relates to a method for sending large packet data by gigabit network multicast based on FPGA, belonging to the field of data transmission of the gigabit network of a radar system. The method is used for solving the problem that occasional packet loss exists when part of projects adopt domestic chips such as DSP, CPU and the like to adapt to a domestic operating system to carry out network transmission of large packet data. The FPGA network multicasts and transmits the big packet data without operating an operating system, a user firstly splits the big packet data into a plurality of small packets, and adds UDP header, IP header and Ethernet header layer by layer to each small packet application layer data to form a transmission layer, a network layer and a data link layer of the network, so that layer by layer controllability is realized, meanwhile, the transmission time of each packet data can be flexibly controlled, and finally, the final network data is transmitted to a physical layer by means of the hard core TEMAC in the FPGA. And the FPGA multicast is adopted to send large-packet data, so that the reliability and the effectiveness of network transmission are ensured.

Description

FPGA-based gigabit network multicast large packet data sending method

Technical Field

The invention belongs to the field of data transmission of a kilomega network of a radar system, and mainly relates to a method for sending large packet data by network multicast based on an FPGA.

Background

In a radar system, data are often transmitted by using a network, for a radar signal processing system, control instructions of a terminal or a central control machine are often required to be received through the network, then signal processing trace information, original video information, state information and the like are transmitted to other subsystems through the network, for network data transmission among the subsystems, a common network transmission mode is a multicast mode, trace information and original video information of the signal processing subsystems are often more than 1472 bytes, even up to 64K bytes, so that the signal processing subsystems are required to be transmitted according to a format of network big packet data, and network transmission efficiency is improved.

The existing radar signal processing system mainly adopts a DSP, FPGA, CPU processor and the like, and provides application requirements for domestic chips and domestic operation systems, when the DSP and the CPU processor use a network to transmit data, the operation systems almost need to be operated, in the process of adapting the domestic operation systems, certain unstable factors are found when part of projects are debugged, the phenomenon of packet loss exists mainly when the network group broadcasts and transmits large packet data, the DSP and the CPU network transmit packets at the bottom layer, a user cannot see a control mechanism in the DSP and the CPU network transmit the large packet data, the FPGA group broadcasts and transmits the large packet data, the operation systems are not needed, the user can clearly know the transmission information of each layer of the network, the design concept is convenient to grasp, and meanwhile, the transmission moment of each packet of data is flexible and controllable. Therefore, for the signal processing system, if the DSP network exists to send the large packet data, the FPGA can be considered to be used as a transfer station for data forwarding, the FPGA receives the DSP data through the SRIO and multicasts the large packet data through the network, so that the DSP is prevented from directly transmitting network data, and the reliability of network data transmission of the system is improved. In addition, the large packet data is transmitted through network multicast, and compared with a plurality of independent small packets, the transmission efficiency can be improved.

Disclosure of Invention

The technical problems to be solved by the invention are as follows:

in order to avoid the problem that a DSP and a CPU send network big packet data by multicast to lose the packet occasionally, the invention provides a method for sending the big packet data by gigabit network multicast based on FPGA, which adopts the FPGA as a transfer station and sends the big packet data by network multicast, thereby improving the stability and efficiency of network packet sending.

In order to solve the technical problems, the invention adopts the following technical scheme:

a method for sending big packet data by gigabit network multicast based on FPGA is characterized by comprising the following steps:

step1: determining a target MAC and an IP when the FPGA network multicasts data, wherein IANA prescribes that the high 24 bits of the IPv4 multicast MAC address are 0x01005E, the 25 th bit is 0, and the low 23 bits are the low 23 bits of the IPv4 multicast IP address; simultaneously determining a destination port; the source MAC address, the source IP address and the source port can be set in the FPGA;

step2: dividing the big packet data into a plurality of small packets according to the byte number of the big packet data to be sent by an application layer, wherein the 1 st packet 1472 bytes, the 2 nd to M-1 th packets, 1480 bytes and the last 1 packet N-1472- (M-2) 1480 bytes; wherein N is the byte number of big packet data, M is the number of small packets;

step3: for the split data packet, only adding UDP header before the 1 st packet data to construct transport layer data; the UDP header contains 8 bytes, respectively: source port 2 bytes, destination port 2 bytes, packet length 2 bytes, checksum 2 bytes; the calculation of the UDP checksum comprises three parts, namely a UDP pseudo-header, a UDP header and a data part;

step 4: adding an IP header, wherein the IP header is required to be added before each packet of data, and constructing network layer data; the IP header contains 20 bytes;

step 5: adding an Ethernet header, wherein the Ethernet header is required to be added before each packet of data, and the data link layer data is built, and the Ethernet header comprises 14 bytes;

step6: and sending out each packet of data through a physical layer by using the FPGA hard core TEMAC.

The invention further adopts the technical scheme that: the unpacking method for the big packet data in the step2 is that the total number of unpacked small packets and the byte number of each small packet are strictly determined according to the maximum transmission byte number of the network.

The invention further adopts the technical scheme that: when the IP header is added before each packet data in step 4, special attention is required to be paid to the setting of the 7 th byte and the 8 th byte, the correct setting of the flag and the slice offset, so that each packet data can be restored to the large packet data at the network receiving end.

The invention further adopts the technical scheme that: the IP header 20 bytes information is added, specifically:

bytes 1, 2 are fixed at 16' h4500;

bytes 3 and 4 are the sum of the length of the IP header and the data part, the header is fixed to 20 bytes, the data part 1 to 44 packets are 1480 bytes, the 45 th packet is 395 bytes, so the 2 bytes of the 1 st to 44 th packets are 16'h05dc, and the 2 bytes of the 45 th packet are 16' h019F;

the 5 th and 6 th byte counter values, the initial value 0 is given after the system is powered on, and 1 big packet data is sent every time, the counter value is increased by 1, and the counter values of all small packets in the big packets are the same;

the 7 th and 8 th bytes are marks bit [15:13] and slice offset bit [12:0], bit [13] is MF, MF=1 indicates the last slice, MF=0 indicates the last slice, bit [14] is DF, and only when DF=0, the slice is allowed, and bit [15] is not used; bit [12:0] is a slice offset, which refers to the relative position of a slice in the original packet after slicing of a longer packet. The slice offset takes 8 bytes as offset units; the tile offset per packet is 1480/8 x (n-1), n is 1 to 45.

Byte 9 is the generation time, here fixed at 8' h80;

byte 10 is a protocol type, here UDP protocol, type 17;

the 11 th and 12 th are IP header checksums, which are calculated here by taking the 45 th packet as an example.

A computer system, comprising: one or more processors, a computer-readable storage medium storing one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods described above.

A computer readable storage medium, characterized by storing computer executable instructions that when executed are configured to implement the method described above.

The invention has the beneficial effects that:

the method for sending the big packet data by the gigabit network multicast based on the FPGA can replace partial projects and adopts the scheme of carrying out network multicast to send the big packet data by adopting processors such as DSP, CPU and the like, the FPGA sends packets by the network, the application layer, the transmission layer, the network layer and the data link layer can be controlled by the user layer by layer, the moment of sending the data packets is flexibly controlled, and the method has certain instability when the DSP, the CPU and the like send the network big packet data in the initial stage of adapting domestic chips and domestic operation systems, the FPGA does not have the risks, and the transmission efficiency of sending the big packet data to the network is also improved.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, like reference numerals being used to refer to like parts throughout the several views.

Fig. 1 shows the mapping relationship between an IPv4 multicast IP address and an IPv4 multicast MAC address.

Fig. 2 is a schematic diagram of a packet data flow for multicast transmission by the FPGA.

Fig. 3UDP header checksum calculation component.

Fig. 4IP header composition.

Fig. 5 illustrates the UDP header checksum calculation component of an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

In a radar system, network transmission data are frequently used, FPGA gigabit network multicasting is adopted to send large packet data, the problem that occasional packet loss exists when a part of projects adopt domestic chips such as DSPs (digital signal processors) and CPUs (central processing units) to adapt to domestic operation systems for network transmission of the large packet data can be solved, the FPGA network multicasting is used for sending the large packet data, the operation systems do not need to be operated, a user firstly splits the large packet data into a plurality of small packets, UDP (user datagram protocol) headers, IP (Internet protocol) headers and Ethernet headers are added to each small packet application layer data layer by layer to form the transmission layer, network layer and data link layer data of a network, the layer by layer are controllable, meanwhile, flexible control can be achieved on the sending moment of each packet data, and finally, the final network data is sent to a physical layer by virtue of hard core TEMAC (Internet protocol) in the FPGA. And the FPGA multicast is adopted to send large-packet data, so that the reliability and the effectiveness of network transmission are ensured.

The embodiment of the invention provides a method for sending big packet data by gigabit network multicast based on FPGA, which comprises the following steps:

step2: dividing the big packet data into a plurality of small packets (M) according to the byte number (N) of the big packet data to be sent by an application layer, wherein the 1 st packet 1472 bytes, the 2 nd to M-1 th packets, 1480 bytes and finally 1 packet N-1472- (M-2) x 1480 bytes;

step3: and for the split data packet, only adding UDP header before the 1 st packet data to construct the transport layer data. The UDP header contains 8 bytes, respectively: source port 2 bytes, destination port 2 bytes, packet length 2 bytes, checksum 2 bytes; the calculation of the UDP checksum comprises three parts, namely a UDP pseudo-header, a UDP header and a data part;

step 4: and adding an IP header, wherein the IP header is required to be added before each packet of data, and constructing network layer data. The IP header contains 20 bytes, and for the packets after splitting the data of the sent big packets, special attention needs to be paid to 7 th and 8 th byte marks and slice offset information, and just because of the association of the information, a plurality of small packet data can be combined into the big packets;

The steps are as follows:

step one: setting a destination MAC, a destination IP, a source MAC, a source IP, a destination port and a source port which are sent by FPGA multicast. The destination MAC is set as: 01-00-5E-05-06-1A, the objective IP is: E6-05-06-1A, the source MAC is set to: 00-11-22-33-44-55, the source IP is: 10-00-02-01, destination port: 16'd6026, source port: 16'd49607.

Step two: the transmitted big packet data is set to 65507 bytes, the 1 st byte is set to 8'h50, and the remaining 65504 bytes are set to 8' h33. The data is split into 45 packets, packet 1 1472 bytes, packets 2 through 44 1480 bytes, and packet 45 395 bytes.

Step three: the UDP header 8 bytes information is added. The method sequentially comprises the following steps: source port, destination port, data length, checksum. The data length is 65515, which is the total bytes of data to be sent (65507) plus the number of UDP header bytes (8); the checksum specific calculation is shown in fig. 5:

step1: calculating pseudo header 0x1000+0x0201+0xe605+0x061a+0x0011+0xffeb=0x1fe1c;

step2: the header 0xc1c7+0x178a+0xffeb+0x0000=0x1d93 c is calculated;

step3: the calculated data portion 0x5033+0x3333 x 0x7ff0+0x3300=0x1996d003;

step4：0x0001+0xfe1c+0x0001+0xd93c+0x1996+0xd003＝0x2c0f3；

step5：0x0002+0xc0f3＝0xc0f5；

step6: the inversion results in a checksum 0x3f0a.

Finally, 8 bytes of information of the UDP header are obtained as follows: c1c7 178a ff eb 3f0a.

Step four: the IP header 20 bytes of information is added.

Bytes 1, 2 are fixed at 16' h4500;

Byte 9 is the generation time, here fixed at 8' h80;

byte 10 is a protocol type, here UDP protocol, type 17;

the 11 th and 12 th are IP header checksums, which are calculated by taking the 45 th packet as an example, and assuming that the counter values of the 5 th and 6 th bytes at this time are 0x02d0, the checksum is calculated as follows:

step1：

0x4500+0x019f+0x02d0+0x1fcc+0x8011+0x0000+0x1000+0x0201+0xe605+0x061a＝0x1e76c；

step2：0x0001+0xe76c＝0xe76d；

step3: the inversion yields a checksum of 0x1892.

Bytes 13 to 16 are the source IP address, 32' h10_00_02_01;

the 17 th to 20 th bytes are the destination IP address, 32' he6_05_06_1a.

Therefore, the IP header of the 45 th packet is: 4500 019f 02d0 1f cc 80 11 1892 1000 02 01e6 05 061a.

Step five: the ethernet header 14 bytes are added, the destination MAC, the source MAC, the type, and the 14 bytes of information are: 01005e 05 061a 0011 22 33 44 55 08 00.

Step six: and sending the combined data link layer packet data to a physical layer by using a hard core TEMAC in the FPGA.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made without departing from the spirit and scope of the invention.

Claims

1. An FPGA-based Gigabit network multicast method for sending large packet data, which is characterized by the following steps:

Step 1: Determine the destination MAC and IP when the FPGA network multicasts data. IANA stipulates that the high 24 bits of the IPv4 multicast MAC address are 0x01005E, the 25th bit is 0, and the low 23 bits are the low 23 bits of the IPv4 multicast IP address. ; Determine the destination port at the same time; the source MAC address, source IP address, and source port can be set in the FPGA;

Step 2: According to the number of bytes of the large packet data to be sent at the application layer, split the large packet data into multiple small packets. The first packet is 1472 bytes, the second to M-1 packets are 1480 bytes, and the last packet is N. -1472-(M-2)*1480 bytes; among which

N is the number of bytes of large packet data, M is the number of small packets;

Step 3: For the split data packet, only add the UDP header before the first packet data to form the transport layer data; the UDP header contains 8 bytes, which are: 2 bytes for the source port and 2 words for the destination port. Section, data packet length is 2 bytes, checksum is 2 bytes; UDP checksum calculation consists of three parts, UDP pseudo-header, UDP header, and data part;

Step 4: Add an IP header. An IP header needs to be added before each packet of data to form network layer data; the IP header contains 20 bytes;

Step 5: Add an Ethernet header. An Ethernet header needs to be added before each packet of data to form data link layer data. The Ethernet header contains 14 bytes;

Step 6: Send each packet of data through the physical layer through the FPGA hard core TEMAC.

2. A method for sending large packet data by Gigabit network multicast based on FPGA according to claim 1, characterized in that: the unpacking method of large packet data in step 2, the total number of small packets after unpacking , and the number of bytes of each packet are strictly determined according to the maximum number of bytes transmitted by the network.

3. A method for sending large packet data via FPGA-based Gigabit network multicast according to claim 1, characterized in that: when adding an IP header before each small packet data in step 4, special attention needs to be paid to steps 7 and 7. The 8-byte setting, correct setting flag and slice offset enable each small packet data to be restored to large packet data at the network receiving end.

4. A method for sending large packet data via FPGA-based Gigabit network multicast according to claim 3, characterized by: adding 20 bytes of information in the IP header, specifically:

The 1st and 2nd bytes are fixed to 16'h4500;

The 3rd and 4th bytes are the sum of the lengths of the IP header and the data part. The header is fixed at 20 bytes. The 1st to 44th packets of the data part are all 1480 bytes. The 45th packet is 395 bytes, so the 1st to 44th The 2 bytes of the package are 16'h05dc, and the 2 bytes of the 45th package are 16'h019F;

The counter value of the 5th and 6th bytes is assigned an initial value of 0 after the system is powered on. Every time a large packet of data is sent, the counter value is incremented by 1. The counter value of each small packet in the large packet is the same;

The 7th and 8th bytes are the flag bit[15:13] and the fragment offset bit[12:0]. The bit[13] is MF. MF=1 means there are still fragments later. MF=0 means the last one. Fragmentation, bit[14] is DF, fragmentation is allowed only when DF=0, bit[15] is not used; bit[12:0] is the fragment offset, which means that a certain fragment of a longer packet is in the original position after fragmentation Relative position within the group. The slice offset is in 8 bytes as the offset unit; the slice offset of each packet is 1480/8*(n-1), and n ranges from 1 to 45.

The 9th byte is the generation time, which is fixed at 8'h80 here;

The 10th byte is the protocol type, here it is the UDP protocol, the type is 17;

Numbers 11 and 12 are the IP header checksum. Here we take the 45th packet as an example to calculate the IP header checksum.

5. A computer system, characterized by comprising: one or more processors, a computer-readable storage medium for storing one or more programs, wherein when the one or more programs are executed by the one or more When executed by one processor, the one or more processors implement the method of claim 1.

6. A computer-readable storage medium, characterized by storing computer-executable instructions, which when executed are used to implement the method of claim 1.