CN117690968B - MOS tube and preparation method thereof - Google Patents

Abstract

The present application provides a MOS tube and a preparation method thereof. The MOS tube comprises a drift layer, a plurality of first doping regions, a plurality of second doping regions, a gate, a source and a drain. A boss is formed on one side of the drift layer. The plurality of first doping regions are arranged around the boss at intervals, and a first interval is formed between two adjacent first doping regions. Each of the plurality of second doping regions is correspondingly arranged in a first interval. The doping type of the second doping region is different from the doping type of the first doping region. In the present application, on the one hand, the first doping region and the second doping region are formed around the boss, so that a lateral horizontal electric field is formed in the first doping region and the second doping region. Before the gate causes the source and the drain to be turned on, the lateral horizontal electric field needs to be overcome first so that the region can be broken down, which is beneficial to improving the breakdown voltage of the MOS tube. On the other hand, each second doping region can form a conductive channel, and the provision of a plurality of conductive channels is beneficial to reducing the on-resistance.

Description

MOS tube and preparation method thereof

Technical Field

The present application belongs to the technical field of MOS tube structures, and in particular, relates to a MOS tube and a preparation method thereof.

Background technique

With the continuous development of electronic technology, MOS tubes (Metal Oxide Semiconductor, Metal Oxide Semiconductor transistors) as an important part of semiconductor devices have been widely used in various circuits. The breakdown voltage (BV) and on-resistance (Ron, sp) of MOS tubes are important parameters to measure their performance.

In the related art, the on-resistance is usually reduced by increasing the doping concentration of the drift region; however, at the same time, the breakdown voltage of the MOS tube will also become smaller.

Therefore, how to reduce the on-resistance of the MOS tube while ensuring the breakdown voltage is a problem that those skilled in the art need to solve at present.

Summary of the invention

The purpose of the present application is to provide a MOS tube and a method for manufacturing the same, in order to solve the problem in the conventional technology that the breakdown voltage of the MOS tube is reduced due to the reduction of the on-resistance thereof.

A first aspect of an embodiment of the present application provides a MOS transistor, the MOS transistor comprising:

A drift layer, wherein a boss is formed on one side of the drift layer;

A plurality of first doping regions, wherein the plurality of first doping regions are arranged around the boss at intervals, and a first interval is formed between two adjacent first doping regions;

A plurality of second doping regions, wherein the plurality of second doping regions are arranged around the boss at intervals, and each second doping region is correspondingly arranged in one of the first intervals; wherein the doping type of the second doping region is different from the doping type of the first doping region;

A gate is disposed on the boss, and the gate extends to the first doping region and the second doping region;

a source electrode, disposed on the second doping region and electrically connected to the second doping region;

The drain is arranged on a side of the drift layer away from the boss.

In some embodiments of the present application, a plurality of the first doping regions are evenly spaced around the boss.

In some embodiments of the present application, the number of the first doping regions is four, and four first intervals are defined between the four first doping regions.

In some embodiments of the present application, the number of the second doping regions is four, and the four second doping regions are arranged in a one-to-one correspondence with the four first intervals.

In some embodiments of the present application, the first doped region is made of a P-type semiconductor material; and/or the second doped region is made of an N-type semiconductor material.

In some embodiments of the present application, the MOS transistor further includes a P body layer, and the P body layer is disposed between the drift layer and the second doping region.

In some embodiments of the present application, a first insulating layer is disposed on a side of the gate close to the boss, and the first insulating layer is connected to the boss, the first doping region, and the second doping region.

In some embodiments of the present application, the MOS transistor further includes a base layer, and the base layer is arranged between the drain and the drift layer.

In a second aspect, the present application further provides a method for preparing a MOS tube, which is applied to the above-mentioned MOS tube. The method for preparing the MOS tube comprises:

Providing a drift layer, and forming a boss on one side of the drift layer;

A plurality of the first doping regions and a plurality of pre-doping regions are alternately arranged around the boss;

A gate is arranged on the boss, and the gate extends to the first doping region and the pre-doping region;

Implanting ions into at least a portion of the pre-doped region to form the second doped region;

The source is arranged on the second doping region, and the drain is arranged on a side of the drift region away from the boss.

In some embodiments of the present application, the step of implanting ions into at least a portion of the pre-doped region to form the second doped region includes:

forming a P body region on the pre-doped region by using a self-aligned double diffusion process;

Ions are implanted into a first portion of the P body region to form the second doping region, and the remaining second portion forms a P body layer.

Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned MOS tube and its preparation method, the MOS tube comprises a drift layer, a plurality of first doping regions, a plurality of second doping regions, a gate, a source and a drain, a boss is formed on one side of the drift layer; a plurality of first doping regions are arranged around the boss at intervals, and a first interval is formed between two adjacent first doping regions; a plurality of second doping regions are arranged around the boss at intervals, and each second doping region is correspondingly arranged in a first interval; wherein the doping type of the second doping region is different from the doping type of the first doping region; in the present application, on the one hand, by forming the first doping region and the second doping region around the boss, the first doping region and the second doping region form a lateral horizontal electric field; before the gate causes the source and the drain to conduct, the lateral horizontal electric field needs to be overcome first to break down the region, thereby facilitating the improvement of the breakdown voltage of the MOS tube; on the other hand, each second doping region can form a conductive channel, and by providing a plurality of conductive channels, it is beneficial to reduce the on-resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a MOS tube provided in an embodiment of the present application;

FIG2 is a schematic diagram of a cross-sectional structure taken along the line A-A of FIG1 provided by an embodiment of the present application;

FIG3 is a schematic diagram of a cross-sectional structure taken along line B-B of FIG1 provided by an embodiment of the present application;

FIG. 4 is a flowchart of the steps of a method for preparing a MOS tube provided in an embodiment of the present application.

Specific element symbol description: 100-drain, 200-base layer, 300-drift layer, 310-boss, 400-second doping region, 410-P body layer, 500-source, 600-gate, 610-first insulating layer, 700-first doping region, a-first direction.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "up", "down", "inside" and "outside" are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

It should be noted that, with the continuous development of electronic technology, MOS tubes, as an important part of semiconductor devices, have been widely used in various circuits. The breakdown voltage and on-resistance of MOS tubes are important parameters to measure their performance.

In the related art, in semiconductor devices, the drift region is a key area that affects the on-resistance and breakdown voltage. The on-resistance refers to the resistance when current passes through a semiconductor material, while the breakdown voltage is the maximum voltage that the device can withstand. In order to reduce the on-resistance, measures are usually taken to increase the doping concentration of the drift region. This is because a high concentration of doping substances can provide more carriers, thereby reducing the scattering and resistance of electrons or holes during transmission, making it easier for current to pass.

However, increasing the doping concentration in the drift region will also have a negative impact on the breakdown voltage of the device. As the doping concentration increases, the electric field distribution will change, causing the electric field concentration area to become more sensitive. When the applied voltage exceeds a certain threshold, the electric field strength in the drift region will exceed the material's tolerance, resulting in a sudden increase in current and even avalanche breakdown. Therefore, although increasing the doping concentration can reduce the on-resistance, it is also necessary to pay attention to the impact on the breakdown voltage to avoid damage to the device during normal operation. In short, the on-resistance is usually reduced by increasing the doping concentration in the drift region; but at the same time, the breakdown voltage of the MOS tube will also become smaller.

Therefore, the present application improves the relevant MOS tube and its preparation method based on this.

Please refer to Figures 1 to 3 in combination, Figure 1 shows a schematic diagram of the top structure of the MOS tube provided in this embodiment; Figure 2 shows a schematic diagram of the A-A cross-sectional structure of Figure 1 provided in this embodiment; Figure 3 shows a schematic diagram of the B-B cross-sectional structure of Figure 1 provided in this embodiment. A MOS transistor of the present embodiment includes a drift layer 300, a plurality of first doping regions 700, a plurality of second doping regions 400, a gate 600, a source 500 and a drain 100; a boss 310 is formed on one side of the drift layer 300; a plurality of first doping regions 700 are arranged around the boss 310 at intervals, and a first interval is formed between two adjacent first doping regions 700; a plurality of second doping regions 400 are arranged around the boss 310 at intervals, and each second doping region 400 is correspondingly arranged in a first interval; wherein the doping type of the second doping region 400 is different from the doping type of the first doping region 700; the gate 600 is arranged on the boss 310, and the gate 600 extends to the first doping region 700 and the second doping region 400; the source 500 is arranged on the second doping region 400 and is electrically connected to the second doping region 400; and the drain 100 is arranged on the side of the drift layer 300 away from the boss 310.

It should be explained that when the power MOSFET is in the on state, the carriers drift in the drift layer 300. The drift layer 300 is usually located between the second doping region 400 and the P-body region; illustratively, when a voltage is applied between the drain 100 and the source 500, the P region has a high doping concentration, the depletion layer mainly expands in the drift layer 300, and the blocking voltage of the drain 100 and the source 500 is almost completely dependent on the width and doping concentration of the drift layer 300. The doping region refers to a region whose conductive properties are changed by doping impurities. For example, in a MOSFET, two shoulder regions are N-doped, and the remaining other regions are P-doped. These P-doped regions are the so-called substrates, and the N-doped regions are called N channels. It can be understood that the MOS tube has a source 500, a gate 600 and a drain 100, and the function of the gate 600 is to promote conduction between the source 500 and the drain 100 so that the MOS tube is turned on.

It is also necessary to explain that the multiple first doping regions 700 are arranged around the boss 310 at intervals, which means that the multiple first doping regions 700 and the boss 310 are arranged at the same level. The multiple second doping regions 400 are arranged around the boss 310 at intervals, which means that the multiple second doping regions 400 and the boss 310 are also arranged at the same level. And the first doping regions 700 and the second doping regions 400 are arranged alternately at intervals. The first doping regions 700 and the second doping regions 400 can form a lateral horizontal electric field in the horizontal direction. The gate 600 extends to the first doping region 700 and the second doping region 400, which means that the projection of the gate 600 in the first direction a at least partially covers the projection of the first doping region 700 and the second doping region 400 in the first direction a. The first direction a refers to the direction from one side of the drift layer 300 forming the boss 310 to the other side away from it.

In the current MOS tube, the on-resistance is improved by adjusting the doping concentration, but the breakdown voltage of the MOS tube is reduced. However, in the present application, on the one hand, by forming the first doping region 700 and the second doping region 400 around the boss 310 of the drift layer 300, the first doping region 700 and the second doping region 400 form a lateral horizontal electric field; before the gate 600 causes the source 500 and the drain 100 to conduct, it is necessary to overcome the lateral horizontal electric field before the region can be broken down, so it is beneficial to improve the breakdown voltage of the MOS tube; on the other hand, each second doping region 400 can form a conductive channel, so multiple conductive channels can be formed, which is beneficial to reduce the on-resistance.

In an exemplary embodiment, for an N-channel MOS transistor, the first doping region 700 is made of a P-type semiconductor material; the second doping region 400 is made of an N-type semiconductor material. When the MOS transistor is in the off state, the voltage of the gate 600 is 0, the first doping region 700 and the second doping region 400 form a PN junction reverse bias, the first doping region 700 and the drift layer 300 form a PN junction reverse bias, the PN junction depletion layer increases, and a lateral horizontal electric field is established. When the appropriate doping concentration and width of the drift layer 300 are selected, the N+ of the drift layer 300 can be completely depleted, so that the drift layer 300 has no free electrons and is equivalent to an intrinsic semiconductor. Since the lateral electric field near the drift layer 300 is extremely high, only when the external voltage is greater than the internal lateral horizontal electric field voltage can this region be broken down, so the withstand voltage of this region is extremely high, and is much greater than the withstand voltage of the epitaxial layer. Therefore, the MOS transistor in this embodiment has a very large breakdown voltage.

In some embodiments of the present application, please continue to refer to FIG. 1 , a plurality of first doping regions 700 are evenly spaced around the boss 310. It is understandable that the plurality of first doping regions 700 are evenly arrayed around the boss 310. This is conducive to ensuring the uniformity of the breakdown voltage at different conductive channels. If the spacing between the plurality of first doping regions 700 is different, different second doping regions 400 may form different degrees of withstand voltage structures, and then a second doping region 400 may be turned on in advance.

In some embodiments of the present application, please continue to refer to FIG. 1. In this embodiment, the number of the first doping regions 700 is four, and four first intervals are defined between the four first doping regions 700. In other words, four second doping regions 400 can be placed in the four first intervals. More second doping regions 400 will also increase the flow conducting cross-sectional area when the MOS tube is turned on, which is conducive to increasing the on-resistance of the MOS tube.

In some embodiments of the present application, please continue to refer to FIG. 1 . In this embodiment, the number of the second doping regions 400 is four, and the four second doping regions 400 are arranged in a one-to-one correspondence with the four first intervals.

In some embodiments of the present application, the first doped region 700 is made of a P-type semiconductor material; and/or the second doped region 400 is made of an N-type semiconductor material. In other words, the first doped region 700 is a P column, and the second doped region 400 is an N column.

In some embodiments, the MOS transistor is an N-channel MOS transistor; in another embodiment, the MOS transistor is a P-channel MOS transistor.

In some embodiments of the present application, please continue to refer to FIG. 1 to FIG. 3 . The MOS tube of this embodiment further includes a P-body layer 410 (P-body). The P-body layer 410 is disposed between the drift layer 300 and the second doping region 400 .

In some embodiments of the present application, please continue to refer to Figures 2 and 3. A first insulating layer 610 is provided on the side of the gate 600 of this embodiment close to the boss 310. The first insulating layer 610 is connected to the boss 310, the first doping region 700 and the second doping region 400.

It should be explained that the function of the first insulating layer 610 is mainly to prevent current from flowing from the gate 600 to the source 500. It is usually called a gate oxide layer or a gate dielectric layer, and is made of an insulating material (such as silicon dioxide). This insulating layer effectively isolates the gate 600 and the substrate, preventing the flow of current from the gate 600 to the source. Under normal operating conditions, when the MOS tube is in the cut-off state, this insulating layer ensures effective isolation between the substrate and the source, thereby preventing current from flowing. When an appropriate positive voltage is applied to the gate 600, this forms a conductive channel between the source 500 and the drain 100, so that current can flow from the source to the drain instead of flowing to the substrate.

In some embodiments of the present application, the MOS transistor of the present embodiment further includes a base layer 200 , and the base layer 200 is disposed between the drain 100 and the drift layer 300 .

It should be explained that the base layer 200 can be understood as a substrate (Sub), which is a structure in a semiconductor device. The substrate usually refers to the semiconductor material layer located at the bottom of the semiconductor crystal structure, and is also the basis of the entire device. The conductivity type and doping concentration of the substrate have an important influence on the performance of the device. In a MOS tube, the substrate is usually connected to the source 500 (source) to form a common potential reference point. The function of the substrate is mainly to provide a transport channel for electrons and holes, so that electrons can flow from the source 500 through the channel (channel) to the drain 100 (drain), thereby realizing the conduction of current. At the same time, the substrate also plays the role of supporting and fixing the device to ensure the stability and reliability of the device structure.

Further, in order to better implement the MOS tube in any of the above embodiments, based on the MOS tube structure, please refer to FIG. 4, which shows a flow chart of the steps of the method for preparing the MOS tube provided in this embodiment. The present application also provides a method for preparing a MOS tube, which is applied to the MOS tube in any of the above embodiments, and the method for preparing the MOS tube includes:

S100: providing a drift layer 300, and forming a boss 310 on one side of the drift layer 300. Specifically, the boss 310 is a structure of the drift layer 300 itself, and has all the characteristics of the drift layer 300. Exemplarily, the boss 310 can be formed by etching the area around the boss 310.

S200: Alternately arrange a plurality of first doping regions 700 and a plurality of pre-doping regions around the boss 310. Specifically, the structure in which the first doping regions 700 and the pre-doping regions are alternately arranged may be formed by stepwise epitaxy and push-in junction.

S300: a gate 600 is disposed on the boss 310 , and the gate 600 extends to the first doping region 700 and the pre-doping region. Specifically, an oxidation process may be used to form a gate oxide layer (first insulating layer 610 ), and then polysilicon is deposited to form the gate 600 .

S400: Ions are implanted into at least a portion of the pre-doped region to form a second doped region 400. Specifically, for an N-channel MOS transistor, ions of an N+ source region are implanted into the pre-doped region to form the second doped region 400.

S500: a source electrode 500 is disposed on the second doping region 400, and a drain electrode 100 is disposed on a side of the drift region away from the protrusion 310. Specifically, a complete MOS tube structure is formed after the source electrode 500 and the drain electrode 100 are formed.

In some embodiments of the present application, step S400 includes:

S410: forming a P body region on the pre-doped region by using a self-aligned double diffusion process.

S420 : implanting ions into a first portion of the P body region to form a second doping region 400 , and the remaining second portion forms a P body layer 410 .

In some embodiments, the MOS transistor in any of the above embodiments is a SJ-MOS transistor (Super Junction Metal Oxide Semiconductor).

In some technologies, super junction MOSFET adopts a structure in which P columns and N columns are arranged alternately. The higher the doping concentration in the drift region, the smaller the on-resistance and the smaller the breakdown voltage, and vice versa. However, the present application reasonably designs the cell structure of the device to achieve a significant improvement in on-resistance with little impact on the breakdown voltage. Specifically, the present application adds an N column to the middle area of the P column to change the depletion region and increase the breakdown voltage of the device. At the same time, the number of channels in the on state is increased, reducing the on-resistance of the device.

More specifically, in the current MOSFET under pressure, its depletion region only exists in one direction, and the electric field also points in one direction. However, after adding the N column in this application, the depletion region extends in two directions, and the electric field is also distributed in two cross directions. This distribution pattern can increase the pressure-bearing capacity during the period. In addition, the N column in this application uses a conventional channel formation method to form a channel under the planar gate, and the increase in the number of channels is conducive to reducing the on-resistance of the device.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and/or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims (5)

1. A MOS tube, characterized in that the MOS tube comprises: A drift layer, wherein a boss is formed on one side of the drift layer; A plurality of first doping regions, wherein the plurality of first doping regions are arranged around the boss at intervals, and a first interval is formed between two adjacent first doping regions; A plurality of second doping regions, wherein the plurality of second doping regions are arranged around the boss at intervals, and each second doping region is correspondingly arranged in one of the first intervals; wherein the doping type of the second doping region is different from the doping type of the first doping region; A gate is disposed on the boss, and the gate extends to the first doping region and the second doping region; a source electrode, disposed on the second doping region and electrically connected to the second doping region; A drain electrode is arranged on a side of the drift layer away from the boss; A plurality of the first doping regions are evenly spaced around the boss, and the first doping regions and the second doping regions are alternately spaced; The number of the first doping regions is four, and four first intervals are defined between the four first doping regions; the number of the second doping regions is four, and the four second doping regions are arranged in one-to-one correspondence with the four first intervals; The first doped region is made of a P-type semiconductor material, and the second doped region is made of an N-type semiconductor material; The MOS tube further includes a P body layer, which is disposed between the drift layer and the second doping region, and the P body layer extends between the first doping region and the second doping region. 2 . The MOS transistor according to claim 1 , wherein a first insulating layer is disposed on a side of the gate close to the boss, and the first insulating layer is connected to the boss, the first doping region, and the second doping region. 3 . The MOS transistor according to claim 1 , further comprising a base layer, wherein the base layer is disposed between the drain and the drift layer. 4. A method for preparing a MOS tube, characterized in that it is applied to the MOS tube according to any one of claims 1 to 3, and the method for preparing the MOS tube comprises: Providing a drift layer, and forming a boss on one side of the drift layer; A plurality of the first doping regions and a plurality of pre-doping regions are alternately arranged around the boss; A gate is arranged on the boss, and the gate extends to the first doping region and the pre-doping region; Implanting ions into at least a portion of the pre-doped region to form the second doped region; The source is arranged on the second doping region, and the drain is arranged on a side of the drift layer away from the boss. 5. The method for preparing a MOS transistor according to claim 4, wherein the step of implanting ions into at least a portion of the pre-doped region to form the second doped region comprises: forming a P body region on the pre-doped region by using a self-aligned double diffusion process; Ions are implanted into a first portion of the P body region to form the second doping region, and the remaining second portion forms a P body layer.