CN117724569B - A bias voltage enhancement circuit and radio frequency power amplifier - Google Patents
A bias voltage enhancement circuit and radio frequency power amplifier Download PDFInfo
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- CN117724569B CN117724569B CN202410164073.8A CN202410164073A CN117724569B CN 117724569 B CN117724569 B CN 117724569B CN 202410164073 A CN202410164073 A CN 202410164073A CN 117724569 B CN117724569 B CN 117724569B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
- H03F1/14—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of neutralising means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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Abstract
本发明适用于无线通讯技术领域，尤其涉及一种偏置电压增强电路及射频功率放大器。所述偏置电压增强电路包括依次电连接的信号输入端、电流源产生电路、过充产生电路、线性稳压器电路以及信号输出端；所述过充产生电路包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第一电阻、第二电阻以及第一电容。与现有技术相比，通过本发明提出的偏置电压增强电路，在偏置电压建立瞬间，产生可控的电压过充，在偏置电压建立瞬间这一阶段，提升射频功率放大器的偏置电压，进一步提升其开启阶段线性度，有效提高射频功率放大器的性能。
The present invention is applicable to the field of wireless communication technology, and in particular, relates to a bias voltage enhancement circuit and a radio frequency power amplifier. The bias voltage enhancement circuit includes a signal input terminal, a current source generation circuit, an overcharge generation circuit, a linear voltage regulator circuit and a signal output terminal which are electrically connected in sequence; the overcharge generation circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor and a first capacitor. Compared with the prior art, the bias voltage enhancement circuit proposed in the present invention generates a controllable voltage overcharge at the moment when the bias voltage is established, and at the stage when the bias voltage is established, the bias voltage of the radio frequency power amplifier is increased, and its linearity in the start-up stage is further improved, thereby effectively improving the performance of the radio frequency power amplifier.
Description
Technical Field
The invention is applicable to the technical field of wireless communication, and particularly relates to a bias voltage enhancement circuit and a radio frequency power amplifier.
Background
In a wireless radio frequency communication system, a radio frequency power amplifier is mainly used for amplifying radio frequency signals with as little distortion as possible, the linearity of the radio frequency power amplifier is influenced by a bias voltage, the bias voltage of the existing method is a stable voltage value generated by a linear voltage stabilizer, but for a time division communication system, the linearity is limited in the starting stage of the radio frequency power amplifier, and the performance of the radio frequency power amplifier is influenced. In order to solve this problem, it is necessary to generate a voltage-enhancing overcharge during the bias voltage establishment stage to effectively improve the linearity of the rf power amplifier.
Therefore, a new bias voltage boosting circuit and a radio frequency power amplifier are needed to solve the above problems.
Disclosure of Invention
The invention provides a bias voltage enhancement circuit and a radio frequency power amplifier, and aims to solve the problem that the linearity of bias voltage is limited in the starting stage of the radio frequency power amplifier.
In a first aspect, the present invention provides the bias voltage enhancing circuit comprising a signal input terminal, a current source generating circuit, an overcharge generating circuit, a linear voltage stabilizer circuit and a signal output terminal electrically connected in sequence;
the current source generating circuit is used for generating current; the overcharge generating circuit is used for generating an overcharge voltage; the linear voltage stabilizer circuit is used for outputting a voltage stabilizing signal; the signal output end is used for outputting reference voltage;
the overcharging generating circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor and a first capacitor;
the first end of the first capacitor is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the first PMOS tube and the gate electrode of the fourth PMOS tube, the second end of the first capacitor is respectively connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube and grounded, the gate electrode of the first NMOS tube is connected to an external logic control circuit, the drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube, the gate electrode of the second NMOS tube is used as the first output end of the overcharge generating circuit, the gate electrode of the third NMOS tube is used as the second output end of the overcharge generating circuit, the drain electrode of the third NMOS tube is respectively connected with the first end of the first resistor and the gate electrode of the second NMOS tube, the second end of the first resistor is respectively connected with the drain electrode of the fourth NMOS tube and the gate electrode of the third NMOS tube, the source electrode of the fourth NMOS tube is connected with the first end of the second resistor, the second PMOS tube is connected with the drain electrode of the second PMOS tube is used as the second output end of the overcharge generating circuit, the drain electrode of the PMOS tube is connected with the second PMOS tube is connected with the drain electrode of the second PMOS tube is used as the second output end of the second PMOS tube.
Preferably, the current source generating circuit comprises a first filtering voltage stabilizing circuit, a first operational amplifier, a first miller compensating circuit, a third resistor, a fifth PMOS tube and a sixth PMOS tube; the first end of the first filtering voltage stabilizing circuit is used as the input end of the current source generating circuit to be connected with the signal input end, the second end of the first filtering voltage stabilizing circuit is grounded, the third end of the first filtering voltage stabilizing circuit is connected with the negative input end of the first operational amplifier, the output end of the first operational amplifier is respectively connected with the first end of the first miller compensating circuit and the grid electrode of the sixth PMOS tube, the positive input end of the first operational amplifier is respectively connected with the second end of the first miller compensating circuit, the drain electrode of the fifth PMOS tube and the first end of the third resistor, the second end of the third resistor is connected with the second end of the first capacitor, the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube is used as the first output end of the current source generating circuit to be connected with the first input end of the overcharging generating circuit, the source electrode of the sixth PMOS tube is connected with the second end of the second charge generating circuit.
Preferably, the first filtering voltage stabilizing circuit includes a second capacitor and a fourth resistor, a first end of the fourth resistor is used as a first end of the first filtering voltage stabilizing circuit, a second end of the fourth resistor is connected with a first end of the second capacitor, a second end of the fourth resistor is used as a third end of the filtering voltage stabilizing circuit, and a second end of the second capacitor is used as a second end of the filtering voltage stabilizing circuit.
Preferably, the first miller compensation circuit includes a third capacitor and a fifth resistor, a first end of the fifth resistor is used as a first end of the first miller compensation circuit, a second end of the fifth resistor is connected with a first end of the third capacitor, and a second end of the third capacitor is used as a second end of the first miller compensation circuit.
Preferably, the linear voltage regulator circuit includes a second filter voltage regulator circuit, a second operational amplifier, a second miller compensation circuit, a fourth NMOS tube, a fifth NMOS tube, a seventh PMOS tube, a sixth resistor, and a seventh resistor, wherein a first end of the second filter voltage regulator circuit is connected to the signal input terminal, a second end of the second filter voltage regulator circuit is grounded, a third end of the second filter voltage regulator circuit is connected to a negative input terminal of the second operational amplifier, an output terminal of the second operational amplifier is connected to a first end of the second miller compensation circuit and a gate of the seventh PMOS tube, a first end of the sixth resistor is connected to a second end of the second miller compensation circuit and a drain of the seventh PMOS tube, a positive input terminal of the second operational amplifier is connected to a drain of the fifth NMOS tube, a second end of the sixth resistor, and a first end of the seventh resistor, a source of the seventh PMOS tube is connected to a power supply voltage, a source of the seventh NMOS is connected to the fourth NMOS is connected to a drain of the fourth NMOS compensation circuit, a source of the seventh NMOS is connected to a fourth NMOS output terminal of the fourth PMOS tube, and a source of the fourth NMOS compensation circuit is connected to a drain of the fourth NMOS compensation circuit.
Preferably, the second filtering voltage stabilizing circuit includes an eighth resistor and a fourth capacitor, a first end of the eighth resistor is used as a first end of the second filtering voltage stabilizing circuit, a second end of the eighth resistor is connected with a first end of the fourth capacitor, a second end of the fourth capacitor is used as a second end of the second filtering voltage stabilizing circuit, and a second end of the eighth resistor is used as a third end of the second filtering voltage stabilizing circuit.
Preferably, the second miller compensation circuit includes a ninth resistor and a fifth capacitor, wherein a first end of the ninth resistor is used as a first end of the second miller compensation circuit, a second end of the ninth resistor is connected with a first end of the fifth capacitor, and a second end of the fifth capacitor is used as a second end of the second miller compensation circuit.
In a second aspect, the present invention also provides a radio frequency power amplifier comprising a bias voltage enhancing circuit as in any one of the embodiments above.
Compared with the prior art, the bias voltage enhancing circuit provided by the invention generates controllable voltage overcharge at the moment of bias voltage establishment, and improves the bias voltage of the radio frequency power amplifier at the moment of bias voltage establishment, further improves the linearity of the starting stage of the radio frequency power amplifier, and effectively improves the performance of the radio frequency power amplifier.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:
FIG. 1 is a schematic diagram of a bias voltage enhancement circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating controllable voltage overcharge of the bias voltage boost circuit according to an embodiment of the present invention.
In the figure, 100 parts of bias voltage enhancing circuit, 1 part of signal input end, 2 parts of current source generating circuit, 3 parts of overcharge generating circuit, 4 parts of linear voltage stabilizer circuit, 5 parts of signal output end.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
Referring to fig. 1-2, the present invention provides a bias voltage enhancing circuit 100, wherein the bias voltage enhancing circuit 100 includes a signal input terminal 1, a current source generating circuit 2, an overcharge generating circuit 3, a linear voltage regulator circuit 4 and a signal output terminal 5 electrically connected in sequence; the signal input terminal 1 generates VBG voltage and inputs the VBG voltage to the current source generating circuit 2, and the signal output terminal 5 outputs reference voltage Vreg.
The signal input end 1 is used for inputting a voltage VBG, and the current source 2 generating circuit is used for generating current; the overcharge generation circuit 3 is used for generating an overcharge voltage; the linear voltage stabilizer circuit 4 is used for outputting a voltage stabilizing signal; the signal output terminal 5 is used for outputting a reference voltage Vreg;
the overcharge generating circuit 3 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first resistor R1, a second resistor R2, and a first capacitor C1;
the first end of the first capacitor C1 is respectively connected with the drain of the first NMOS transistor MN1, the drain of the first PMOS transistor MP1 and the gate of the fourth PMOS transistor MP4, the second end of the first capacitor C1 is respectively connected with the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 and grounded, the gate of the first NMOS transistor MN1 is connected to the external logic control circuit ENB, the drain of the second NMOS transistor MN2 is connected with the source of the third NMOS transistor MN3, the gate of the second NMOS transistor MN2 is used as the first output end of the overcharge generating circuit 3, the gate of the third NMOS transistor MN3 is used as the second output end of the overcharge generating circuit 3, the drain of the third NMOS transistor MN3 is respectively connected with the first end of the first resistor R1 and the gate of the second NMOS transistor MN2, the second end of the first resistor R1 is respectively connected with the drain of the fourth NMOS transistor MP4 and the gate of the second NMOS transistor MP2, the gate of the second NMOS transistor MP2 is connected with the second end of the second PMOS transistor MP2 and the gate of the second PMOS transistor MP2, the gate of the second NMOS transistor MP2 is connected with the second end of the second PMOS transistor MP2, the gate of the third NMOS transistor MP2 is connected with the second gate of the second PMOS transistor MP2, the second resistor MP2 is connected with the second gate of the second output end of the second transistor MP2 is connected with the second output end of the second transistor MP 2.
In this embodiment, the current source generating circuit 2 includes a first filtering voltage stabilizing circuit 21, a first operational amplifier OP1, a first miller compensation circuit 22, a third resistor R3, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6; the first end of the first filter voltage stabilizing circuit 21 is connected to the signal input end 1 as the input end of the current source generating circuit 2, the second end of the first filter voltage stabilizing circuit 21 is grounded, the third end of the first filter voltage stabilizing circuit 21 is connected to the negative input end of the first operational amplifier OP1, the output end of the first operational amplifier OP1 is connected to the first end of the first miller compensating circuit 22 and the gate of the sixth PMOS transistor MP6, the positive input end of the first operational amplifier OP1 is connected to the second end of the first miller compensating circuit 22, the drain of the fifth PMOS transistor MP5 and the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second end of the first capacitor C1, the source of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6, the gate of the fifth PMOS transistor MP5 is connected to the first output end of the current source generating circuit 2 and the first end of the sixth PMOS transistor MP3 as the first output end of the current source generating circuit 2, and the second end of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP 6.
In this embodiment, the first filter voltage stabilizing circuit 21 includes a second capacitor C2 and a fourth resistor R4, wherein a first end of the fourth resistor R4 is used as a first end of the first filter voltage stabilizing circuit 21, a second end of the fourth resistor R4 is connected to a first end of the second capacitor C2, a second end of the fourth resistor R4 is used as a third end of the filter voltage stabilizing circuit 21, and a second end of the second capacitor C2 is used as a second end of the filter voltage stabilizing circuit 21.
In this embodiment, the first miller compensation circuit 22 includes a third capacitor C3 and a fifth resistor R5, wherein a first end of the fifth resistor R5 is used as a first end of the first miller compensation circuit 22, a second end of the fifth resistor R5 is connected to the first end of the third capacitor C3, and a second end of the third capacitor C3 is used as a second end of the first miller compensation circuit 22.
In the present embodiment, the linear regulator circuit 4 includes a second filter regulator circuit 41, a second operational amplifier OP2, a second miller compensation circuit 42, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a seventh PMOS transistor MP7, a sixth resistor R6, and a seventh resistor R7, a first end of the second filtering voltage stabilizing circuit 41 is connected with the signal input end 1, a second end of the second filtering voltage stabilizing circuit 41 is grounded, a third terminal of the second filter voltage stabilizing circuit 41 is connected to the negative input terminal of the second operational amplifier OP2, the output end of the second operational amplifier OP2 is connected to the first end of the second miller compensation circuit 42 and the gate of the seventh PMOS MP7, the first end of the sixth resistor R6 is connected to the second end of the second miller compensation circuit 42 and the drain of the seventh PMOS MP7 respectively, the positive input end of the second operational amplifier OP2 is connected to the drain electrode of the fifth NMOS transistor MN5, the second end of the sixth resistor R6, and the first end of the seventh resistor R7, the source electrode of the seventh PMOS tube MP7 is connected with the power supply voltage VDD, the drain electrode of the seventh PMOS tube MP7 is used as the output end of the linear voltage stabilizer circuit 4 to be connected with the signal output end 1, the source electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the fourth NMOS tube MN4, the source electrode of the fourth NMOS tube MN4 is connected with the second end of the seventh resistor R7 and the source electrode of the second NMOS tube MN2, the gate of the fourth NMOS transistor MN4 is connected to the first output terminal of the overcharge generator circuit 3 as the first input terminal of the linear voltage regulator circuit 4, the gate of the fifth NMOS transistor MN5 is connected to the second output terminal of the overcharge generator circuit 3 as the second input terminal of the linear voltage regulator circuit 4.
In this embodiment, the second filter voltage stabilizing circuit 41 includes an eighth resistor R8 and a fourth capacitor C4, wherein a first end of the eighth resistor R8 is used as the first end of the second filter voltage stabilizing circuit 41, a second end of the eighth resistor R8 is connected to a first end of the fourth capacitor C4, a second end of the fourth capacitor C4 is used as the second end of the second filter voltage stabilizing circuit 41, and a second end of the eighth resistor R8 is used as the third end of the second filter voltage stabilizing circuit 41.
In this embodiment, the second miller compensation circuit 42 includes a ninth resistor R9 and a fifth capacitor C5, wherein a first end of the ninth resistor R9 is used as the first end of the second miller compensation circuit 42, a second end of the ninth resistor R9 is connected to the first end of the fifth capacitor C5, and a second end of the fifth capacitor C5 is used as the second end of the second miller compensation circuit 42.
As shown in fig. 2, fig. 2 is a schematic diagram illustrating controllable voltage overcharge of the bias voltage enhancement circuit according to an embodiment of the present invention. In fig. 2 a, a waveform diagram of the bias voltage Vreg is shown when no voltage overcharge occurs at the moment of establishing the bias voltage Vreg; fig. 2B shows waveforms of the bias voltage Vreg when the voltage is overcharged at the moment of establishing the bias voltage Vreg. The bias voltage enhancing circuit provided by the invention realizes that the voltage overcharge with the delta V amplitude with the controllable time delta T length is generated at the moment of establishing the bias voltage Vreg, and at the stage, the bias voltage of the radio frequency power amplifier is improved, and the linearity of the starting stage of the radio frequency power amplifier is further improved.
Specifically, the current source generating circuit 2 includes a first operational amplifier OP1 and a PMOS current mirror circuit formed by a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, which form a negative feedback, and the VBG voltage input from the signal input terminal 1 generates a fixed current source on the resistor R3. The fourth resistor R4 and the second capacitor C2 form a low-pass circuit for filtering and voltage stabilization. The fifth resistor R5 and the third capacitor C3 are used for miller compensation, stability of a feedback loop is guaranteed, the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a common-source common-gate configuration, channel modulation effect is reduced, and current accuracy is improved. The first PMOS transistor MP1 and the second PMOS transistor MP2 in the overcharge generating circuit 3 mirror the current and flow into the first capacitor C1, the first NMOS transistor MN1 and the third PMOS transistor MP3 perform a switching function, and the external logic control circuit ENB starts to operate from high to low. In the initial stage of enabling, the first end point position of the first capacitor C1 starts to climb from 0V, and finally reaches the power supply voltage VDD after being charged by the current source, and the charging time of the capacitor and the current magnitude of the current source are linearly related, namely the time delta T of the overcharging voltage is finally generated. In this stage, the fourth PMOS transistor MP4 is turned on to off, the output current of the fourth PMOS transistor MP4 is from large to small, and finally, 0, and the second resistor R2 plays a role in current regulation. The second NMOS tube MN2, the third NMOS tube MN3, the fourth NMOS tube MN4 and the fifth NMOS tube MN5 form an NMOS current mirror circuit, and the first resistor R1 plays a role in biasing. The fifth NMOS transistor MN5 and the fourth NMOS transistor MN4 inject a controlled current into the feedback node of the linear regulator circuit 4, thereby generating a controlled voltage overcharge voltage. In the linear voltage stabilizer circuit 4, an eighth resistor R8 and a fourth capacitor C4 are used for low-pass filtering, a second operational amplifier OP2, a seventh PMOS tube MP7, a sixth resistor R6 and a seventh resistor R7 form a linear voltage stabilizing circuit of a negative feedback loop, and a ninth resistor R9 and a fifth capacitor C5 play a role of Miller compensation to ensure the stability of the loop. Finally, the reference voltage Vreg is generated, and the overcharge amplitude and time of the reference voltage Vreg are controllable.
Compared with the prior art, the bias voltage enhancing circuit provided by the invention generates controllable voltage overcharge at the moment of bias voltage establishment, and improves the bias voltage of the radio frequency power amplifier at the moment of bias voltage establishment, further improves the linearity of the starting stage of the radio frequency power amplifier, and effectively improves the performance of the radio frequency power amplifier.
Example two
The embodiment of the present invention further provides a radio frequency power amplifier, which includes the bias voltage enhancing circuit 100 described in the above embodiment, and can achieve the same technical effects, and the description in the above embodiment is omitted herein.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (8)
1. The bias voltage enhancing circuit is characterized by comprising a signal input end, a current source generating circuit, an overcharge generating circuit, a linear voltage stabilizer circuit and a signal output end which are electrically connected in sequence;
the current source generating circuit is used for generating current; the overcharge generating circuit is used for generating an overcharge voltage; the linear voltage stabilizer circuit is used for outputting a voltage stabilizing signal; the signal output end is used for outputting reference voltage;
the overcharging generation circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first resistor, a second resistor and a first capacitor;
the first end of the first capacitor is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the first PMOS tube and the grid electrode of the fourth PMOS tube, the second end of the first capacitor is respectively connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube and is grounded, and the grid electrode of the first NMOS tube is connected to an external logic control circuit;
the drain electrode of the second NMOS tube is connected with the source electrode of the third NMOS tube, and the grid electrode of the second NMOS tube is used as the first output end of the overcharge generating circuit and is connected to the first input end of the linear voltage stabilizer circuit;
the grid electrode of the third NMOS tube is used as a second output end of the overcharge generating circuit and is connected to a second input end of the linear voltage stabilizer circuit, the drain electrode of the third NMOS tube is respectively connected with the first end of the first resistor and the grid electrode of the second NMOS tube, and the second end of the first resistor is respectively connected with the drain electrode of the fourth PMOS tube and the grid electrode of the third NMOS tube;
the source electrode of the fourth PMOS tube is connected with the first end of the second resistor, the second end of the second resistor is connected with the drain electrode of the third PMOS tube, the grid electrode of the third PMOS tube is connected with an external logic control circuit, and the source electrode of the third PMOS tube and the source electrode of the second PMOS tube are respectively connected with a power supply voltage;
the drain electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, and the grid electrode of the first PMOS tube is used as the first input end of the overcharge generating circuit and is connected to the first output end of the current source generating circuit; and the grid electrode of the second PMOS tube is used as a second input end of the overcharge generating circuit and is connected to a second output end of the current source generating circuit.
2. The bias voltage enhancement circuit of claim 1, wherein the current source generating circuit comprises a first filter voltage stabilizing circuit, a first operational amplifier, a first miller compensation circuit, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor; the first end of the first filtering voltage stabilizing circuit is used as an input end of the current source generating circuit to be connected with the signal input end, the second end of the first filtering voltage stabilizing circuit is grounded, and the third end of the first filtering voltage stabilizing circuit is connected with the negative input end of the first operational amplifier; the output end of the first operational amplifier is respectively connected with the first end of the first miller compensation circuit and the grid electrode of the sixth PMOS tube, the positive input end of the first operational amplifier is respectively connected with the second end of the first miller compensation circuit, the drain electrode of the fifth PMOS tube and the first end of the third resistor, and the second end of the third resistor is connected with the second end of the first capacitor; the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube, the grid electrode of the fifth PMOS tube is used as the first output end of the current source generating circuit, the source electrode of the sixth PMOS tube is connected with the power supply voltage, and the grid electrode of the sixth PMOS tube is used as the second output end of the current source generating circuit.
3. The bias voltage boosting circuit of claim 2, wherein the first filter voltage stabilizing circuit comprises a second capacitor and a fourth resistor, a first end of the fourth resistor being a first end of the first filter voltage stabilizing circuit, a second end of the fourth resistor being connected to a first end of the second capacitor, a second end of the fourth resistor being a third end of the filter voltage stabilizing circuit, a second end of the second capacitor being a second end of the filter voltage stabilizing circuit.
4. The bias voltage enhancing circuit of claim 2, wherein the first miller compensation circuit comprises a third capacitor and a fifth resistor, a first end of the fifth resistor being a first end of the first miller compensation circuit, a second end of the fifth resistor being connected to a first end of the third capacitor, a second end of the third capacitor being a second end of the first miller compensation circuit.
5. The bias voltage enhancement circuit of claim 1, wherein the linear regulator circuit comprises a second filter regulator circuit, a second operational amplifier, a second miller compensation circuit, a fourth NMOS transistor, a fifth NMOS transistor, a seventh PMOS transistor, a sixth resistor, and a seventh resistor; the first end of the second filtering voltage stabilizing circuit is connected with the signal input end, the second end of the second filtering voltage stabilizing circuit is grounded, and the third end of the second filtering voltage stabilizing circuit is connected with the negative input end of the second operational amplifier; the output end of the second operational amplifier is respectively connected with the first end of the second miller compensation circuit and the grid electrode of the seventh PMOS tube, the first end of the sixth resistor is respectively connected with the second end of the second miller compensation circuit and the drain electrode of the seventh PMOS tube, and the positive input end of the second operational amplifier is respectively connected with the drain electrode of the fifth NMOS tube, the second end of the sixth resistor and the first end of the seventh resistor; the source electrode of the seventh PMOS tube is connected with the power supply voltage, and the drain electrode of the seventh PMOS tube is used as the output end of the linear voltage stabilizer circuit to be connected with the signal output end; the source electrode of the fifth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the second end of the seventh resistor and the source electrode of the second NMOS tube, the grid electrode of the fourth NMOS tube is used as the first input end of the linear voltage stabilizer circuit, and the grid electrode of the fifth NMOS tube is used as the second input end of the linear voltage stabilizer circuit.
6. The bias voltage boosting circuit according to claim 5, wherein said second filter voltage stabilizing circuit comprises an eighth resistor and a fourth capacitor, a first end of said eighth resistor being a first end of said second filter voltage stabilizing circuit, a second end of said eighth resistor being connected to a first end of said fourth capacitor, a second end of said fourth capacitor being a second end of said second filter voltage stabilizing circuit, a second end of said eighth resistor being a third end of said second filter voltage stabilizing circuit.
7. The bias voltage boosting circuit of claim 5 wherein said second miller compensation circuit comprises a ninth resistor and a fifth capacitor, a first end of said ninth resistor being a first end of said second miller compensation circuit, a second end of said ninth resistor being connected to a first end of said fifth capacitor, a second end of said fifth capacitor being a second end of said second miller compensation circuit.
8. A radio frequency power amplifier comprising a bias voltage enhancing circuit as claimed in any one of claims 1 to 7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410164073.8A CN117724569B (en) | 2024-02-05 | 2024-02-05 | A bias voltage enhancement circuit and radio frequency power amplifier |
| PCT/CN2025/073168 WO2025167535A1 (en) | 2024-02-05 | 2025-01-19 | Bias voltage enhancement circuit and radio frequency power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410164073.8A CN117724569B (en) | 2024-02-05 | 2024-02-05 | A bias voltage enhancement circuit and radio frequency power amplifier |
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| CN117724569A CN117724569A (en) | 2024-03-19 |
| CN117724569B true CN117724569B (en) | 2024-04-12 |
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| CN202410164073.8A Active CN117724569B (en) | 2024-02-05 | 2024-02-05 | A bias voltage enhancement circuit and radio frequency power amplifier |
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| WO (1) | WO2025167535A1 (en) |
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| CN117724569B (en) * | 2024-02-05 | 2024-04-12 | 深圳飞骧科技股份有限公司 | A bias voltage enhancement circuit and radio frequency power amplifier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200404544Y1 (en) * | 2005-07-23 | 2005-12-26 | 알에프아이씨 테크놀로지 코퍼레이션 | Bias circuit for improving stability of a radio frequency power amplifier |
| CN109976424A (en) * | 2019-04-18 | 2019-07-05 | 电子科技大学 | A kind of non-capacitive low-dropout linear voltage regulator |
| CN115756057A (en) * | 2022-11-23 | 2023-03-07 | 西安电子科技大学 | Transient response enhancement type LDO linear voltage regulator |
| CN116736922A (en) * | 2023-06-14 | 2023-09-12 | 圣邦微电子（北京）股份有限公司 | Low-dropout linear voltage regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7911279B2 (en) * | 2008-11-26 | 2011-03-22 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Amplifier with bias circuit providing improved linearity |
| CN107508563B (en) * | 2017-08-09 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | Self-adaptive linearity enhanced low noise amplifier |
| CN110808720B (en) * | 2018-08-06 | 2023-07-14 | 锐迪科创微电子（北京）有限公司 | Anti-saturation radio frequency power amplifier |
| CN115913136A (en) * | 2022-11-17 | 2023-04-04 | 深圳芯佰特微电子有限公司 | Power amplifier DEVM optimizing circuit |
| CN117724569B (en) * | 2024-02-05 | 2024-04-12 | 深圳飞骧科技股份有限公司 | A bias voltage enhancement circuit and radio frequency power amplifier |
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- 2024-02-05 CN CN202410164073.8A patent/CN117724569B/en active Active
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR200404544Y1 (en) * | 2005-07-23 | 2005-12-26 | 알에프아이씨 테크놀로지 코퍼레이션 | Bias circuit for improving stability of a radio frequency power amplifier |
| CN109976424A (en) * | 2019-04-18 | 2019-07-05 | 电子科技大学 | A kind of non-capacitive low-dropout linear voltage regulator |
| CN115756057A (en) * | 2022-11-23 | 2023-03-07 | 西安电子科技大学 | Transient response enhancement type LDO linear voltage regulator |
| CN116736922A (en) * | 2023-06-14 | 2023-09-12 | 圣邦微电子（北京）股份有限公司 | Low-dropout linear voltage regulator |
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| CN117724569A (en) | 2024-03-19 |
| WO2025167535A1 (en) | 2025-08-14 |
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