CN117728820B - Level shifter and integrated circuit system - Google Patents

Abstract

The application discloses a level shifter and an integrated circuit system, which relate to the technical field of integrated circuits, wherein the level shifter comprises: a high level control circuit; a conversion circuit including a first switch and a second switch; a conversion control circuit; when the input control signal is changed from a low level signal to a high level signal, the high level control circuit outputs the high level signal to the input end of the first switch, the conversion control circuit controls the first switch to be opened and the second switch to be closed, and the first switch outputs the high level output signal. When the input control signal is changed from the high level signal to the low level signal, the high level control circuit stops outputting the high level signal to the input end of the first switch so as to prevent leakage caused by incomplete closing of the first switch, and the conversion control circuit controls the second switch to be opened and the first switch to be closed, and the second switch outputs the low level output signal. The application has no current contention problem of pull-up and pull-down in the traditional power-on reset circuit, and effectively reduces the power consumption of the circuit.

Description

A level converter and integrated circuit system

Technical Field

The present invention relates to the technical field of integrated circuits, and in particular to a level converter and an integrated circuit system.

Background Art

With the development of integrated circuits, power consumption has gradually become a key issue that limits the application of integrated circuits. In order to solve the power consumption problem of integrated circuits, low-voltage technology has gradually attracted attention in recent years. Low-voltage technology can effectively reduce circuit power consumption by reducing the power supply voltage, but there are usually multiple different power supply voltages in the system. When the signal is transmitted from the low-voltage domain to the high-voltage domain, a level converter needs to be inserted to ensure the function of the circuit. However, the conversion range of traditional level converters is narrow, and it is difficult to correctly convert signals at extremely low power supply voltages into signals at higher power supply voltages, which greatly limits the development of low-voltage technology.

Summary of the invention

The object of the present invention is to provide a level converter and an integrated circuit system. The present application does not have the current contention problem between the pull-up network and the pull-down network in the traditional power-on reset circuit, and effectively reduces the power consumption of the circuit.

In order to solve the above technical problems, the present invention adopts the following technical solutions:

An aspect of an embodiment of the present invention provides a level converter, the level converter comprising: a high-level control circuit, the input end of the high-level control circuit is used to connect to an external power supply, the control end of the high-level control circuit is used to receive an input control signal, and the output end of the high-level control circuit is used to output a high-level signal; a conversion circuit, the conversion circuit comprising a first switch and a second switch, the input end of the first switch is connected to the output end of the high-level control circuit, the input end of the second switch is grounded, the output end of the first switch is connected to the output end of the second switch, the output end of the first switch is used to output a high-level output signal, and the output end of the second switch is used to output a low-level output signal; a conversion control circuit, the input end of the conversion control circuit is used to connect to the external power supply, and the output end of the conversion control circuit is connected to the conversion circuit The control end of the conversion control circuit is used to receive the input control signal; the output end of the high-level control circuit is used to output a high-level signal to the input end of the first switch when the input control signal changes from a low-level signal to a high-level signal; the conversion control circuit is used to control the first switch to be turned on and the second switch to be turned off when the input control signal changes from a low-level signal to a high-level signal, so as to output a high-level output signal; the conversion control circuit is used to control the second switch to be turned on and the first switch to be turned off when the input control signal changes from a high-level signal to a low-level signal, so as to output a low-level output signal; the high-level control circuit is used to stop outputting a high-level signal to the input end of the first switch when the input control signal changes from a high-level signal to a low-level signal.

In some embodiments, the first switch adopts a first PMOS tube, and the second switch adopts a first NMOS tube, the source of the first PMOS tube is connected to the output end of the high-level control circuit, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and the output end of the conversion control circuit, the source of the first NMOS tube is grounded, and the drain of the first PMOS tube is connected to the drain of the first NMOS tube, so as to output high-level and low-level output signals respectively.

In some embodiments, the high-level control circuit includes a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is connected to the external power supply, the gate of the second PMOS tube is connected to the drain of the second NMOS tube, the source of the second NMOS tube is grounded, the gate of the second NMOS tube is used to receive the input control signal, and the drain of the second PMOS tube is connected to the input end of the first switch.

In some embodiments, the high-level control circuit also includes a third PMOS tube, the source of the third PMOS tube is connected to the external power supply, and the gate of the third PMOS tube is connected to the gate of the second PMOS tube, the drain of the second NMOS tube and the drain of the third PMOS tube.

In some embodiments, the high-level control circuit also includes a fourth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, the drain of the fourth PMOS tube is connected to the gate of the second PMOS tube, the gate of the third PMOS tube and the drain of the second NMOS tube, and the gate of the fourth PMOS tube is used to receive the output signal.

In some embodiments, the conversion control circuit includes a first control circuit and a second control circuit, the first control circuit includes a fifth PMOS tube and a third NMOS tube, the source of the fifth PMOS tube is connected to a power supply, the drain of the fifth PMOS tube is connected to the drain of the third NMOS tube, the gate of the first PMOS tube and the gate of the first NMOS tube, the source of the third NMOS tube is grounded, the gate of the third NMOS tube is used to receive the input control signal, and the second control circuit is respectively connected to the gate of the fifth PMOS tube, the power supply and the gate of the third NMOS tube.

In some embodiments, the second control circuit includes a fourth NMOS tube, a source of the fourth NMOS tube is connected to a gate of the third NMOS tube, a drain of the fourth NMOS tube is connected to a gate of the fifth PMOS tube, and the gate of the fourth NMOS tube is used to receive an on signal.

In some embodiments, the second control circuit further includes a fifth NMOS tube, the source of the fifth NMOS tube is connected to the drain of the fourth NMOS tube, the drain of the fifth NMOS tube is connected to the gate of the fifth PMOS tube, and the gate of the fifth NMOS tube is used to receive the output signal.

In some embodiments, the second control circuit further includes a sixth PMOS tube, a source of the sixth PMOS tube being connected to a power supply, and a gate of the sixth PMOS tube being connected to a gate of the fifth PMOS tube, a drain of the sixth PMOS tube, and a drain of the fifth NMOS tube.

An aspect of an embodiment of the present invention provides an integrated circuit system, wherein the integrated circuit system includes the level converter as described above.

A level converter and an integrated circuit system according to an embodiment of the present invention have at least the following beneficial effects: the conventional level converter has a narrow conversion range and is difficult to be applied to a low voltage system. However, the level converter of the present application does not have the current contention problem between the pull-up network and the pull-down network in the conventional power-on reset circuit, and can quickly cut off the DC path after the output is flipped, effectively reducing the power consumption of the circuit.

It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG. 1 is a circuit diagram of a level converter according to an embodiment.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

The terms "first", "second", and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", and "third" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected", "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that the description of the present disclosure will be more comprehensive and complete and the concepts of the example embodiments will be fully conveyed to those skilled in the art. The accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

The technical solution of the embodiment of the present application is briefly described below:

According to some embodiments, as shown in FIG. 1 , the present application provides a level converter, the level converter comprising:

A high-level control circuit, wherein the input end of the high-level control circuit is used to connect to an external power supply VDDH, the control end of the high-level control circuit is used to receive an input control signal IN, and the output end of the high-level control circuit is used to output a high-level signal;

A conversion circuit, the conversion circuit comprising a first switch and a second switch, the input end of the first switch is connected to the output end of the high-level control circuit, the input end of the second switch is grounded VSS, the output end of the first switch is connected to the output end of the second switch, the output end of the first switch is used to output a high-level output signal OUT, and the output end of the second switch is used to output a low-level output signal OUT;

A conversion control circuit, wherein the input end of the conversion control circuit is used to connect to the external power supply VDDH, the output end of the conversion control circuit is connected to the control end of the conversion circuit, and the control end of the conversion control circuit is used to receive the input control signal IN;

The output end of the high level control circuit is used to output a high level signal to the input end of the first switch when the input control signal IN changes from a low level signal to a high level signal;

The conversion control circuit is used for controlling the first switch to be turned on and the second switch to be turned off when the input control signal IN changes from a low level signal to a high level signal, so as to output a high level output signal OUT;

The conversion control circuit is used for controlling the second switch to be turned on and the first switch to be turned off when the input control signal IN changes from a high level signal to a low level signal, so as to output a low level output signal OUT;

The high level control circuit is used for stopping outputting the high level signal to the input end of the first switch when the input control signal IN changes from a high level signal to a low level signal.

Based on the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the high level control circuit outputs a high level signal to the input end of the first switch. At the same time, the conversion control circuit controls the first switch to turn on and controls the second switch to turn off. At this time, the first switch outputs a high level output signal OUT.

When the input control signal IN changes from a high level signal to a low level signal, the high level control circuit stops outputting the high level signal to the input end of the first switch, and at the same time the conversion control circuit controls the second switch to turn on, and controls the first switch to turn off. At this time, the second switch outputs a low level output signal OUT. The high level control circuit stops outputting the high level signal to the input end of the first switch to prevent leakage caused by the first switch not being completely closed.

When the first switch is turned on, the second switch is turned off; when the second switch is turned on, the first switch is turned off, thereby solving the current contention problem between the pull-up network and the pull-down network in the traditional power-on reset circuit.

When the second switch is controlled to output a low-level output signal OUT, the high-level control circuit stops outputting a high-level signal to the input end of the first switch to prevent leakage caused by the first switch not being completely closed, thereby effectively reducing the power consumption of the circuit.

The preferred embodiment of the present disclosure is further described in detail below in conjunction with FIG1 of the present specification.

According to some embodiments, as shown in FIG. 1 , the first switch adopts a first PMOS transistor P1, and the second switch adopts a first NMOS transistor N1, the source of the first PMOS transistor P1 is connected to the output end of the high-level control circuit, the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1 and the output end of the conversion control circuit, the source of the first NMOS transistor N1 is grounded to VSS, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, so as to output high-level and low-level output signals OUT respectively.

Based on the working principle of the above embodiment, when the gate of the first PMOS tube P1 and the gate of the first NMOS tube N1 both receive a high level, the first PMOS tube P1 is turned off and the first NMOS tube N1 is turned on. When the gate of the first PMOS tube P1 and the gate of the first NMOS tube N1 both receive a low level, the first PMOS tube P1 is turned on and the first NMOS tube N1 is turned off.

When the input control signal IN changes from a low level signal to a high level signal, the high level control circuit outputs a high level signal to the source of the first PMOS transistor P1. At the same time, the conversion control circuit controls the first PMOS transistor P1 to turn on and controls the first NMOS transistor N1 to turn off. At this time, the first PMOS transistor P1 outputs a high level output signal OUT.

When the input control signal IN changes from a high-level signal to a low-level signal, the high-level control circuit stops outputting the high-level signal to the source of the first PMOS tube P1, and at the same time, the conversion control circuit controls the first NMOS tube N1 to turn on, and controls the first PMOS tube P1 to turn off. At this time, the first NMOS tube N1 outputs a low-level output signal OUT. The high-level control circuit stops outputting the high-level signal to the source of the first PMOS tube P1 to prevent leakage caused by the first PMOS tube P1 not being completely turned off.

According to some embodiments, as shown in FIG. 1 , the high-level control circuit includes a second PMOS tube P2 and a second NMOS tube N2, the source of the second PMOS tube P2 is connected to the external power supply VDDH, the gate of the second PMOS tube P2 is connected to the drain of the second NMOS tube N2, the source of the second NMOS tube N2 is grounded VSS, the gate of the second NMOS tube N2 is used to receive the input control signal IN, and the drain of the second PMOS tube P2 is connected to the input end of the first switch.

According to the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the second NMOS transistor N2 is turned on, and the second PMOS transistor P2 is turned on.

When the input control signal IN changes from a high level signal to a low level signal, the second NMOS transistor N2 is turned off, and the second PMOS transistor P2 is turned off.

In order to better turn off the second PMOS tube P2, in other embodiments, the gate of the second PMOS is connected to the power supply VDDH (not shown) through a resistor, and when the second NMOS tube N2 is turned on, the voltage of the gate of the second PMOS tube P2 is pulled down to turn on the second PMOS tube P2; when the second NMOS tube N2 is turned off, the voltage of the gate of the second PMOS tube P2 is pulled up to turn off the second PMOS tube P2.

Further, according to some embodiments, as shown in FIG1 , the high-level control circuit also includes a third PMOS tube P3, a source of the third PMOS tube P3 is connected to the external power supply VDDH, and a gate of the third PMOS tube P3 is connected to the gate of the second PMOS tube P2, the drain of the second NMOS tube N2 and the drain of the third PMOS tube P3.

Based on the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the second NMOS transistor N2 is turned on, and the second PMOS transistor P2 and the third PMOS transistor P3 are turned on.

When the input control signal IN changes from a high level signal to a low level signal, the second NMOS tube N2 is turned off, and then the high level output by the third PMOS tube P3 turns off both the second PMOS tube P2 and the third PMOS tube P3.

Further, according to some embodiments, as shown in FIG. 1 , the high-level control circuit also includes a fourth PMOS tube P4, a source of the fourth PMOS tube P4 is connected to a drain of the third PMOS tube P3, a drain of the fourth PMOS tube P4 is connected to a gate of the second PMOS tube P2, a gate of the third PMOS tube P3 and a drain of the second NMOS tube N2, and a gate of the fourth PMOS tube P4 is used to receive the output signal OUT.

Based on the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the second NMOS tube N2 is turned on, and the second PMOS tube P2 and the third PMOS tube P3 are turned on. At the same time, the conversion control circuit controls the first PMOS tube P1 to turn on, and controls the first NMOS tube N1 to turn off. The output signal OUT changes from a low level to a high level, and the fourth PMOS tube P4 changes from on to off.

When the input control signal IN changes from a high level signal to a low level signal, the second NMOS tube N2 is turned off, and at the same time, the conversion control circuit controls the first PMOS tube P1 to be turned off, and controls the first NMOS tube N1 to be turned on, which further causes the fourth PMOS tube P4 to turn from off to on, and then the high level output by the third PMOS tube P3 turns off the second PMOS tube P2 and the third PMOS tube P3.

The fourth PMOS tube P4 is provided for the purpose that when the input control signal IN changes from a low level signal to a high level signal, the second NMOS tube N2 is turned on, causing both the second PMOS tube P2 and the third PMOS tube P3 to be turned on, but the fourth PMOS tube P4 is turned from on to off, preventing the third PMOS tube P3 from leaking too much electricity when the second NMOS tube N2 is turned on, thereby effectively reducing the power consumption of the circuit.

According to some embodiments, as shown in FIG. 1 , the conversion control circuit includes a first control circuit and a second control circuit, the first control circuit includes a fifth PMOS tube P5 and a third NMOS tube N3, the source of the fifth PMOS tube P5 is connected to a power supply VDDH, the drain of the fifth PMOS tube P5 is connected to a drain of the third NMOS tube N3, a gate of the first PMOS tube P1 and a gate of the first NMOS tube N1, the source of the third NMOS tube N3 is grounded VSS, the gate of the third NMOS tube N3 is used to receive the input control signal IN, and the second control circuit is respectively connected to the gate of the fifth PMOS tube P5, the power supply VDDH and the gate of the third NMOS tube N3.

When the input control signal IN changes from a low level signal to a high level signal, the second control circuit controls the third NMOS transistor N3 to be turned on (opened), and controls the fifth PMOS transistor P5 to be turned off (closed).

When the input control signal IN changes from a high level signal to a low level signal, the second control circuit controls the third NMOS transistor N3 to be turned off, and controls the fifth PMOS transistor P5 to be turned on.

Further, according to some embodiments, as shown in FIG1 , the second control circuit includes a fourth NMOS tube N4, a source of the fourth NMOS tube N4 is connected to a gate of the third NMOS tube N3, a drain of the fourth NMOS tube N4 is connected to a gate of the fifth PMOS tube P5, and the gate of the fourth NMOS tube N4 is used to receive a start signal VDDL.

The gate of the fourth NMOS transistor N4 receives a high-level start-up signal VDDL.

Based on the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the source of the fourth NMOS tube N4 is at a high level, so the drain of the fourth NMOS tube N4 does not output, the third NMOS tube N3 is turned on, and the fifth PMOS tube P5 is turned off.

In order to better turn off the fifth PMOS tube P5, in other embodiments, the gate of the fifth PMOS is connected to the power supply VDDH (not shown) through a resistor, and when the fourth NMOS tube N4 outputs a low level, the voltage of the gate of the fifth PMOS tube P5 is pulled down, so that the fifth PMOS tube P5 is turned on; when the fourth NMOS tube N4 is turned off, the voltage of the gate of the fifth PMOS tube P5 is pulled up, so that the fifth PMOS tube P5 is turned off.

The third NMOS transistor N3 outputs a low level so that the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off.

When the input control signal IN changes from a high level signal to a low level signal, the source of the fourth NMOS tube N4 is at a low level, so the drain of the fourth NMOS tube N4 outputs a low level, the third NMOS tube N3 is turned off, and the fifth PMOS tube P5 is turned on. The fifth PMOS tube P5 outputs a high level to turn off the first PMOS tube P1 and turn on the first NMOS tube N1.

According to some embodiments, as shown in FIG. 1 , the second control circuit further includes a fifth NMOS tube N5, a source of the fifth NMOS tube N5 being connected to a drain of the fourth NMOS tube N4, a drain of the fifth NMOS tube N5 being connected to a gate of the fifth PMOS tube P5, and a gate of the fifth NMOS tube N5 being used to receive the output signal OUT.

According to some embodiments, as shown in FIG. 1 , the second control circuit further includes a sixth PMOS tube P6, a source of the sixth PMOS tube P6 is connected to a power supply VDDH, and a gate of the sixth PMOS tube P6 is connected to a gate of the fifth PMOS tube P5, a drain of the sixth PMOS tube P6, and a drain of the fifth NMOS tube N5.

Based on the working principle of the above embodiment, when the input control signal IN changes from a low level signal to a high level signal, the source of the fourth NMOS tube N4 is at a high level, so the drain of the fourth NMOS tube N4 does not output, the third NMOS tube N3 is turned on, and the fifth PMOS tube P5 and the sixth PMOS tube P6 are turned off. The third NMOS tube N3 outputs a low level to turn on the first PMOS tube P1 and turn off the first NMOS tube N1. The output signal OUT is at a high level, and the fifth NMOS tube N5 is turned on.

When the input control signal IN changes from a high level signal to a low level signal, the source of the fourth NMOS tube N4 is at a low level, so the drain of the fourth NMOS tube N4 outputs a low level, the third NMOS tube N3 is turned off, and the fifth NMOS tube N5 is still in an on state in the initial stage, causing the fifth PMOS tube P5 and the sixth PMOS tube P6 to be turned on, and the voltage point V2 of the gate of the first PMOS tube P1 and the first NMOS tube N1 is charged to a high level. V2 is charged to a high level, causing the first PMOS tube P1 to be turned off and the first NMOS tube N1 to be turned on. The output signal OUT changes from a high level to a low level, and the fifth NMOS tube N5 changes from the on state in the initial stage to the subsequent off state. Because there is a parasitic capacitance between the first PMOS tube P1 and the first NMOS tube N1, the voltage point V2 is kept at a high level voltage, which further causes the output signal OUT to maintain an output low level. Since the fifth NMOS transistor N5 is subsequently turned off, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are also turned off, which reduces the leakage current of the sixth PMOS transistor P6 and effectively reduces the power consumption of the circuit.

According to some embodiments, the present application provides an integrated circuit system, wherein the integrated circuit system includes the level converter as described above.

In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

Although the present disclosure has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present disclosure can be implemented in a variety of forms without departing from the spirit or essence of the present application, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be widely interpreted within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims (9)

1.A level shifter, the level shifter comprising:

the high-level control circuit is characterized by comprising a high-level control circuit, a high-voltage circuit and a high-voltage circuit, wherein the input end of the high-level control circuit is used for being connected with an external power supply, the control end of the high-level control circuit is used for receiving an input control signal, and the output end of the high-level control circuit is used for outputting a high-level signal;

The switching circuit comprises a first switch and a second switch, wherein the input end of the first switch is connected with the output end of the high-level control circuit, the input end of the second switch is grounded, the output end of the first switch is connected with the output end of the second switch, the output end of the first switch is used for outputting a high-level output signal, and the output end of the second switch is used for outputting a low-level output signal;

The input end of the conversion control circuit is used for being connected with the external power supply, the output end of the conversion control circuit is connected with the control end of the conversion circuit, and the control end of the conversion control circuit is used for receiving the input control signal;

The output end of the high-level control circuit is used for outputting a high-level signal to the input end of the first switch when the input control signal changes from a low-level signal to a high-level signal;

The switching control circuit is used for controlling the first switch to be opened and controlling the second switch to be closed when the input control signal changes from a low level signal to a high level signal so as to output a high level output signal;

The switching control circuit is used for controlling the second switch to be opened and controlling the first switch to be closed when the input control signal changes from a high level signal to a low level signal so as to output a low level output signal;

the high-level control circuit is used for stopping outputting the high-level signal to the input end of the first switch when the input control signal changes from the high-level signal to the low-level signal;

The first switch adopts a first PMOS tube, the second switch adopts a first NMOS tube, the source electrode of the first PMOS tube is connected with the output end of the high-level control circuit, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and the output end of the conversion control circuit, the source electrode of the first NMOS tube is grounded, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube so as to be used for respectively outputting output signals of high level and low level.

2. The level shifter of claim 1, wherein the high level control circuit comprises a second PMOS and a second NMOS, wherein a source of the second PMOS is connected to the external power supply, a gate of the second PMOS is connected to a drain of the second NMOS, a source of the second NMOS is grounded, a gate of the second NMOS is configured to receive the input control signal, and a drain of the second PMOS is connected to an input of the first switch.

3. The level shifter of claim 2, wherein the high level control circuit further comprises a third PMOS transistor, a source of the third PMOS transistor is connected to the external power supply, and a gate of the third PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the second NMOS transistor, and the drain of the third PMOS transistor.

4. The level shifter of claim 3, wherein the high level control circuit further comprises a fourth PMOS transistor, a source of the fourth PMOS transistor is connected to a drain of the third PMOS transistor, a drain of the fourth PMOS transistor is connected to a gate of the second PMOS transistor, a gate of the third PMOS transistor, and a drain of the second NMOS transistor, and a gate of the fourth PMOS transistor is configured to receive the output signal.

5. The level shifter of claim 1, wherein the shift control circuit comprises a first control circuit and a second control circuit, the first control circuit comprises a fifth PMOS transistor and a third NMOS transistor, a source of the fifth PMOS transistor is connected to a power supply, a drain of the fifth PMOS transistor is connected to a drain of the third NMOS transistor, a gate of the first PMOS transistor and a gate of the first NMOS transistor, a source of the third NMOS transistor is grounded, a gate of the third NMOS transistor is configured to receive the input control signal, and the second control circuit is connected to the gate of the fifth PMOS transistor, the power supply, and the gate of the third NMOS transistor, respectively.

6. The level shifter of claim 5, wherein the second control circuit comprises a fourth NMOS transistor having a source connected to the gate of the third NMOS transistor, a drain connected to the gate of the fifth PMOS transistor, and a gate for receiving an on signal.

7. The level shifter of claim 6, wherein the second control circuit further comprises a fifth NMOS transistor, a source of the fifth NMOS transistor being connected to a drain of the fourth NMOS transistor, a drain of the fifth NMOS transistor being connected to a gate of the fifth PMOS transistor, the gate of the fifth NMOS transistor being configured to receive the output signal.

8. The level shifter of claim 7, wherein the second control circuit further comprises a sixth PMOS transistor, a source of the sixth PMOS transistor being connected to a power supply, a gate of the sixth PMOS transistor being connected to the gate of the fifth PMOS transistor, a drain of the sixth PMOS transistor, and a drain of the fifth NMOS transistor.

9. An integrated circuit system comprising a level shifter as claimed in any one of claims 1 to 8.