CN117849598A - Synchronous test signal generating system and synchronous test signal generating method - Google Patents
Synchronous test signal generating system and synchronous test signal generating method Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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Abstract
The system comprises a main control board and a plurality of test boards, wherein the test boards comprise a first control unit and a second control unit, and the main control board sends synchronous clock signals to the plurality of test boards; based on the synchronous clock signal, the main control board issues a test instruction to a first control unit of the plurality of test boards; the first control unit sends a test instruction to the second control unit, the second control unit converts the test instruction into a corresponding test vector and sends the corresponding test vector to the first control unit, the first control unit converts the test vector into a corresponding synchronous test signal to be output, and the system respectively bears the functions of generating the test vector and generating the test signal through the two control units, so that the problems that the FPGA chip resources of the digital board card of the tester are tense and the signal time sequence is difficult to converge due to mutual influence are solved.
Description
Technical Field
The present disclosure relates to the field of device testing technologies, and in particular, to a synchronous test signal generating system and a synchronous test signal generating method.
Background
In a digital board card of a common tester, a monolithic FPGA includes a plurality of functional modules such as PG (Pattern Generater, test vector generation module), TG (Timing generator, timing generation module), result processing, and peripheral management. The functional modules are connected with each other to realize real-time communication of data, and the generated data and signals have strict time synchronization requirements. However, since these functional modules are integrated in one FPGA, the resource consumption of the FPGA is excessive, and the signal timings of the functional modules are difficult to converge due to each other, increasing the debugging time and labor cost.
Aiming at the problems that the FPGA chip resources of the digital board card of the tester are tense and the signal time sequence mutual influence is difficult to converge in the related technology, no effective solution is proposed at present.
Disclosure of Invention
The embodiment provides a synchronous test signal generation system and a synchronous test signal generation method, which are used for solving the problems that FPGA chip resources of a digital board card of a tester are tense and signal time sequences are difficult to converge due to mutual influence in the related technology.
In a first aspect, in this embodiment, there is provided a synchronous test signal generating system, the system including a main control board and a plurality of test boards, the test boards including a first control unit and a second control unit,
The main control board sends synchronous clock signals to the plurality of test boards;
based on the synchronous clock signal, the main control board issues a test instruction to a first control unit of the plurality of test boards;
based on the synchronous clock signal, the first control unit sends the test instruction to the second control unit, the second control unit converts the test instruction into a corresponding test vector and sends the corresponding test vector to the first control unit, and the first control unit converts the test vector into a corresponding synchronous test signal to be output; and the synchronous test signals output by the test boards are used for executing parallel test of the tested device.
In some of these embodiments, the test board determines the output time of the synchronous test signal based on a time of issue of the test instruction, a first time of transmission of the test instruction from the first control unit to the second control unit, a second time of transmission of the test vector inside the second control unit, and a third time of transmission of the test vector from the second control unit to the first control unit.
In some of these embodiments, the first control unit includes a memory module, the second control unit includes a test vector generation module,
the test board determines the starting time of the test vector generation module based on the issuing time of the test instruction and the first transmission time of the test instruction transmitted from the memory module to the test vector generation module;
and after the test vector generation module is started, converting the test instruction into a corresponding test vector.
In some embodiments, the second control unit further includes a buffer module, and the first control unit further includes a test signal generation module;
the buffer module is used for buffering the test vectors generated by the test vector generation module and sequentially sending the test vectors to the test signal generation module according to a storage sequence;
the test board determines the starting time of the test signal generating module based on the issuing time of the test instruction, the first transmission time, the second transmission time of the test vector from the test vector generating module to the buffer module, and the third transmission time of the test vector from the buffer module to the test signal generating module;
And after the test signal generating module is started, the test vector is converted into a corresponding synchronous test signal to be output.
In some embodiments, the cache module is further configured to:
and under the condition that the number of the cached test vectors reaches a preset number threshold value, starting the sending of the test vectors.
In some embodiments, when the test vector generation module pauses operation, continuously sending invalid data to the cache module until the test vector generation module resumes operation, wherein the invalid data comprises an invalid identifier;
the caching module caches the invalid data and sequentially sends the invalid data to the test signal generating module;
the test signal generation module discards the invalid data based on the invalid identification.
In some of these embodiments, the first control unit and the second control unit comprise a synchronous counting module,
the synchronous counting module obtains a synchronous counting value based on the synchronous clock signal;
the second control unit determines a synchronous count value corresponding to the output time of the test vector based on the synchronous count value corresponding to the issuing time of the test instruction and a first transmission count value corresponding to the first transmission time;
The first control unit determines a synchronous count value corresponding to the output time of the synchronous test signal based on the synchronous count value corresponding to the issuing time of the test instruction, the first transmission count value corresponding to the first transmission time, the second transmission count value corresponding to the second transmission time, and the third transmission count value corresponding to the third transmission time.
In some embodiments, the first control unit further includes a memory module and a test signal generating module connected to the corresponding synchronous counting module, and the second control unit further includes a test vector generating module and a buffer module connected to the corresponding synchronous counting module;
the memory module obtains a reference count value based on the synchronous count value when a test instruction is received;
the test vector generation module acquires a first judgment value based on the reference count value and a first transmission count value acquired in advance; starting the test vector output under the condition that the synchronous count value reaches the first judgment value;
the test signal generation module acquires a second judgment value based on the reference count value and a first transmission count value, a second transmission count value and a third transmission count value which are acquired in advance; and under the condition that the synchronous count value reaches the second determination value, starting the synchronous test signal output.
In some of these embodiments, the test board includes a plurality of first control units,
based on the synchronous clock signals, the plurality of first control units send corresponding test instructions to the second control units, wherein the test instructions comprise unit identifications;
the second control unit converts the test instruction into a corresponding test vector and sends the test vector to the corresponding first control unit based on the unit identifier.
In a second aspect, in this embodiment, there is provided a synchronous test signal generating method, which is applied to a test board including a first control unit and a second control unit, the method including:
based on the received synchronous clock signal, sending the test instruction received by the first control unit to the second control unit, wherein the synchronous clock signal and the test instruction are issued by a main control board;
based on the synchronous clock signal, a test vector correspondingly generated by the second control unit based on the test instruction is sent to the first control unit;
based on the synchronous clock signal, outputting a synchronous test signal correspondingly generated by the first control unit based on the test vector; and the synchronous test signals output by the test boards are used for executing parallel test of the tested device.
In some embodiments, outputting, by the first control unit, based on the synchronous clock signal, synchronous test signals correspondingly generated by the first control unit based on the test vectors includes:
based on the synchronous clock signal, determining a synchronous count value corresponding to the issuing time of the test instruction, a first transmission count value corresponding to a first transmission time of the test instruction transmitted from the first control unit to the second control unit, a second transmission count value corresponding to a second transmission time of the test vector transmitted inside the second control unit, and a third transmission count value corresponding to a third transmission time of the test vector transmitted from the second control unit to the first control unit;
and determining the output time of the synchronous test signal based on the synchronous count value, the first transmission count value, the second transmission count value and the third transmission count value.
In some embodiments, the sending, based on the synchronous clock signal, the test vector correspondingly generated by the second control unit based on the test instruction to the first control unit includes:
based on the synchronous clock signal, determining a synchronous count value corresponding to the issuing time of the test instruction and a first transmission count value corresponding to the first transmission time of the test instruction from the first control unit to the second control unit;
And determining the starting time of the second control unit for correspondingly generating the test vector based on the test instruction based on the synchronous count value and the first transmission count value.
Compared with the related art, the synchronous test signal generating system provided in the embodiment sends synchronous clock signals to a plurality of test boards through the main control board, and provides reference signals for action synchronization for the plurality of test boards; issuing test instructions to a first control unit of a plurality of test boards based on synchronous clock signals through a main control board so as to ensure that the test instructions received by the test boards are synchronous; the first control unit and the second control unit respectively bear the functions of generating the test vector and the test signal, so that the resource requirement on a single control unit is reduced, the mutual influence of signal time sequences is reduced, and the problems that the FPGA chip resources of the digital board card of the tester are tense and the mutual influence of the signal time sequences is difficult to converge in the related technology are solved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the other features, objects, and advantages of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a block diagram of a synchronous test signal generation system according to some embodiments of the present application;
FIG. 2 is a block diagram of the structure of a test board according to some embodiments of the present application;
FIG. 3 is a block diagram of a test board according to further embodiments of the present application;
FIG. 4 is a block diagram of a test board according to further embodiments of the present application;
FIG. 5 is a flow chart of a synchronous test signal generation method of some embodiments of the present application;
FIG. 6 is a flow chart of outputting a synchronous test signal from a first control unit based on a synchronous clock signal in accordance with some embodiments of the present application;
fig. 7 is a flow chart of transmitting test vectors from a second control unit based on synchronous clock signals in accordance with some embodiments of the present application.
Detailed Description
For a clearer understanding of the objects, technical solutions and advantages of the present application, the present application is described and illustrated below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
Unless defined otherwise, technical or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and the like in this application are not intended to be limiting in number, but rather are singular or plural. The terms "comprising," "including," "having," and any variations thereof, as used in the present application, are intended to cover a non-exclusive inclusion; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (units) is not limited to the list of steps or modules (units), but may include other steps or modules (units) not listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference to "a plurality" in this application means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. Typically, the character "/" indicates that the associated object is an "or" relationship. The terms "first," "second," "third," and the like, as referred to in this application, merely distinguish similar objects and do not represent a particular ordering of objects.
Fig. 1 is a block diagram of a synchronous test signal generation system according to some embodiments of the present application. As shown in fig. 1, the synchronous test signal generating system provided in the embodiment of the present application includes a main control board 10 and a plurality of test boards 20 (2 are shown in fig. 1), where the test boards 20 include a first control unit 21 and a second control unit 22. The first control unit 21 and the second control unit 22 may be integrated circuits having programmable logic functions, such as field programmable gate array chips (Field Programmable Gate Array, FPGA) and the like. The synchronous test signal generating system is used for generating a plurality of synchronous test signals so as to execute parallel test of the tested device. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the synchronous test signal generating system described above. For example, the synchronous test signal generation system may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The main control board 10 sends a synchronous clock signal clk_dom to the plurality of test boards 20; based on the synchronous clock signal clk_dom, the main control board 10 issues a test instruction Tcom to the first control unit 21 of the plurality of test boards 20; based on the synchronous clock signal, the first control unit 21 sends the test command Tcom to the second control unit 22, the second control unit 22 converts the test command Tcom into a corresponding test vector Tpat and sends the corresponding test vector Tpat to the first control unit 21, and the first control unit 21 converts the test vector Tpat into a corresponding synchronous test signal Tsig to output; the plurality of synchronous test signals Tsig output from the plurality of test boards are used to perform parallel testing of the device under test.
In a specific embodiment, the main control board 10 sends the synchronous clock signal clk_dom to the first control unit 21 and the second control unit 22 of the plurality of test boards 20, for controlling the timing variation of the circuit signals of each test board. clk_dom may be a differential synchronous clock signal.
In a specific embodiment, the first control unit 21 and the second control unit 22 include a synchronous counting module, and the synchronous counting module synchronously counts the first control unit 21 and the second control unit 22 based on the synchronous clock signal clk_dom to obtain a synchronous count value. The first control unit 21 and the second control unit 22 can start the related modules to start working based on the synchronous count value, so that synchronous output of signals is realized.
The synchronous counting module comprises a phase-locked loop and a counter, and the principle that the plurality of test boards 20 execute synchronous actions based on the synchronous counting module is as follows:
a. firstly, disconnecting the synchronous clock signal clk_dom;
b. after the phase-locked loop detects that the synchronous clock signal clk_dom stops, pulling up the clk_stop signal;
c. asynchronously resetting the counter using the rising edge of the signal;
d. restoring the supply of the synchronous clock signal clk_dom;
e. the counter starts counting from 0, and receives each synchronizing clock signal clk_dom plus 1, so as to obtain the synchronizing count value among the test boards 20.
The first control unit 21 and the second control unit 22 have an inter-board synchronous counting function, and synchronous starting and signal synchronous output of the same functional module between different test boards 20 can be realized by presetting synchronous count values corresponding to the functional modules in the first control unit 21 and the second control unit 22 on each test board 20.
In this embodiment, the test instruction Tcom may be a test vector Pattern loading information, the test vector Tpat may be a test vector Pattern with a timing characteristic, and the synchronous test signal Tsig may be a test signal input to each pin of the device under test.
According to the synchronous test signal generation system, synchronous clock signals are sent to a plurality of test boards through a main control board, and reference signals for action synchronization are provided for the plurality of test boards; issuing test instructions to a first control unit of a plurality of test boards based on synchronous clock signals through a main control board so as to ensure that the test instructions received by the test boards are synchronous; the first control unit and the second control unit respectively bear the functions of generating the test vector and the test signal, so that the resource requirement on a single control unit is reduced, the mutual influence of signal time sequences is reduced, and the problems that the FPGA chip resources of the digital board card of the tester are tense and the mutual influence of the signal time sequences is difficult to converge in the related technology are solved.
In some embodiments, the test board determines the output time of the synchronous test signal based on the issue time of the test instruction, the first transmission time of the test instruction from the first control unit to the second control unit, the second transmission time of the test vector internally transmitted in the second control unit, and the third transmission time of the test vector from the second control unit to the first control unit.
When the master control board issues a test instruction to the first control units of the plurality of test boards based on the synchronous clock signal, the time at which each test board receives the test instruction is synchronous, and the issue time may be set as an initial time. According to the process from issuing the test command to outputting the synchronous test signal by each test board shown in fig. 1, the output time of the synchronous test signal is determined by the issuing time of the test command, the first transmission time of the test command from the first control unit to the second control unit, the second transmission time of the test vector in the second control unit, the third transmission time of the test vector from the second control unit to the first control unit, and the conversion time of the test command to the test vector and the test vector to the synchronous test signal.
Because the first control unit and the second control unit of each test board are designed identically, the time for converting the test instruction into the test vector and the time for converting the test vector into the synchronous test signal are identical under the condition that the starting time of the functional modules is identical, and in the embodiment, the conversion time is negligible. Therefore, the output time of the synchronous test signal is determined based on the sum of the issuing time, the first transmission time, the second transmission time and the third transmission time of the test instruction. And the first transmission time, the second transmission time, and the third transmission time may be acquired based on a pre-completed test.
Specifically, the first control unit and the second control unit comprise a synchronous counting module, and the synchronous counting module acquires a synchronous counting value based on a synchronous clock signal; the second control unit determines a synchronous count value corresponding to the output time of the test vector based on the synchronous count value corresponding to the issuing time of the test instruction and the first transmission count value corresponding to the first transmission time; the first control unit determines a synchronous count value corresponding to the output time of the synchronous test signal based on the synchronous count value corresponding to the issuing time of the test instruction, the first transmission count value corresponding to the first transmission time, the second transmission count value corresponding to the second transmission time, and the third transmission count value corresponding to the third transmission time.
The synchronization count value refers to an accumulated value obtained by accumulating the number of the synchronization clock signals by the synchronization count module. The first transmission count value refers to the accumulated number of synchronous clock signals during the first transmission time. A second transmission count value, a third transmission count value, and so on. The first transmission count value, the second transmission count value and the third transmission count value can be obtained by calculating the difference value of the synchronous count values respectively corresponding to the start and the completion of the test instruction or the test vector transmission action.
In one embodiment, when the synchronization count value is 10, a test instruction is issued to the first module of the first control unit; when the synchronous count value is 20, the test instruction is transmitted from the first module of the first control unit to the second module of the second control unit; when the synchronization count value is 40, the test vector is transmitted from the second module of the second control unit to the third module of the second control unit; when the synchronization count value is 70, the test vector is transmitted from the third module of the second control unit to the fourth module of the first control unit. Then the first transmission count value may be determined to be 10; the second transmission count value is 20; the third transmission count value is 30.
In an embodiment, the sum of the synchronization count value corresponding to the issuing time of the test instruction and the first transmission count value is used as the synchronization count value corresponding to the output time of the test vector, and the second control unit starts the output of the test vector according to the synchronization count value.
In another embodiment, a sum of a synchronization count value corresponding to the issuing time of the test instruction, a first transmission count value, and a preset first margin threshold is used as the synchronization count value corresponding to the output time of the test vector, and the first margin threshold is used for reserving a certain margin time for transmission of the test instruction.
In an embodiment, the sum of the synchronous count value corresponding to the issuing time of the test instruction, the first transmission count value, the second transmission count value and the third transmission count value is used as the synchronous count value corresponding to the output time of the synchronous test signal, and the first control unit starts the output of the synchronous test signal according to the synchronous count value.
In another embodiment, the sum of the synchronous count value corresponding to the issuing time of the test instruction, the first transmission count value, the second transmission count value, the third transmission count value and the preset second margin threshold is used as the synchronous count value corresponding to the output time of the synchronous test signal. The second margin threshold is used for reserving certain margin time for transmission of the test instruction and the test vector, and ensuring accuracy of transmission of the test instruction and the test vector.
According to the synchronous test signal generation system, based on the issuing time of the test instruction, the first transmission time of the test instruction transmitted from the first control unit to the second control unit, the second transmission time of the test vector transmitted inside the second control unit and the third transmission time of the test vector transmitted from the second control unit to the first control unit, the output time of the synchronous test signal is determined, a feasible control mode for guaranteeing the output synchronization of the test signals of all the test boards is provided, the quantification of the transmission time is realized through the counting of the synchronous counting module, and the synchronicity of the test instruction, the test vector and the test signal transmission is improved.
In some embodiments, fig. 2 is a block diagram of the structure of a test board according to some embodiments of the present application, and as shown in fig. 2, the first control unit 21 includes a memory module 211, and the second control unit 22 includes a test vector generation module 222. The first control unit 21 and the second control unit 22 each comprise a synchronous counting module 23. As shown in fig. 2, one end of the synchronous counting module 23 in the first control unit 21 is connected with the main control board 10, and the other end is connected with the memory module 211; one end of the synchronous counting module 23 in the second control unit 22 is connected with the main control board 10, and the other end is connected with the test vector generating module 222. The synchronous counting module 23 receives the synchronous clock signal clk_dom, and counts based on the synchronous clock signal clk_dom to obtain a corresponding synchronous count value syn_c. The synchronous counting module 23 of the first control unit 21 sends a synchronous clock signal clk_dom and a synchronous count value syn_c to the memory module 211; the synchronous counting module 23 of the second control unit 22 transmits the synchronous clock signal clk_dom and the synchronous count value syn_c to the test vector generating module 222.
The test board 20 determines the start time of the test vector generation module 222 based on the issue time of the test instruction Tcom, the first transfer time of the test instruction Tcom from the memory module 211 to the test vector generation module 222. After the test vector generation module 222 is started, the test command Tcom is converted into a corresponding test vector Tpat based on the synchronous clock signal clk_dom and output immediately.
The memory module 211 may be a volatile memory such as DDR or a nonvolatile memory. The test vector generation module 222 may be a test vector generator (PatternGenerater, PG). The main control board issues a test instruction Tcom to the memory module 211, and the time corresponding to the time when the memory module 211 receives the test instruction Tcom is the issuing time; the memory module 211 is configured to send the test instruction Tcom to the test vector generation module 222 of the second control unit 22, where the transmission process corresponds to the first transmission time.
In one embodiment, the start time of the test vector generation module 222 is equal to the sum of the test instruction issue time and the first transmission time; the synchronous count value syn_c_p corresponding to the start time of the test vector generation module 222 is equal to the sum of the synchronous count value syn_c0 corresponding to the test instruction issue time and the first transmission count value syn_t1 corresponding to the first transmission time.
In another embodiment, the start time of the test vector generation module 222 is equal to the sum of the test instruction issue time, the first transmission time, and the preset first margin time. The synchronous count value syn_c_p corresponding to the start time of the test vector generation module 222 is equal to the sum of the synchronous count value syn_c0 corresponding to the test instruction issuing time, the first transmission count value syn_t1 corresponding to the first transmission time and the first margin threshold corresponding to the first margin time.
The test vector generation module 222 starts the operation according to the synchronization count value syn_c_p acquired in the above embodiment, and converts the received test instruction Tcom into the corresponding test vector Tpat. There are a plurality of the number of test vectors Tpat, and the test vector generation module 222 may sequentially transmit the test vectors Tpat based on the synchronous clock signal clk_dom.
The synchronous test signal generating system of the embodiment determines the starting time of the test vector generating module based on the issuing time of the test instruction and the first transmission time of the test instruction transmitted from the memory module to the test vector generating module, controls the synchronous starting of the test vector generating modules on each test board, and realizes the synchronization of the generation and the output of the test vectors.
In a further embodiment, fig. 3 is a block diagram of the structure of a test board according to other embodiments of the present application, and as shown in fig. 3, the second control unit 22 further includes a buffer module 224, and the first control unit 21 further includes a test signal generating module 213. As shown in fig. 3, the test signal generation module 213 is connected to the synchronous counting module 23 of the first control unit 21; the buffer module 224 is connected to the synchronous counting module 23 of the second control unit 22. Wherein, the synchronous clock signal clk_dom and the synchronous count value syn_c output by the synchronous counting module 23 of the first control unit 21 are sent to the test signal generating module 213; the synchronous clock signal clk_dom and the synchronous count value syn_c output from the synchronous count module 23 of the second control unit 22 are sent to the buffer module 224.
The buffer module 224 is configured to buffer the test vector Tpat generated by the test vector generating module 222, and sequentially send the test vector Tpat to the test signal generating module 213 according to a storage order; test board 20 determines a start-up time of test signal generation module 213 based on a launch time of test instruction Tcom, a first transfer time, a second transfer time of test vector Tpat from test vector generation module 222 to buffer module 224, and a third transfer time of test vector Tpat from buffer module 224 to test signal generation module 213.
After the test signal generating module 213 is started, the test vector Tpat is converted into a corresponding synchronous test signal Tsig based on the synchronous clock signal clk_dom and output immediately.
The buffer module 224 may be a volatile memory such as a FIFO. The test signal generation module 213 may be a timing generator (TimingGenerater, TG). The test signal generating module 213 obtains a corresponding synchronous count value syn_c3 when the test vector Tpat is transmitted from the buffer module 224 to the test signal generating module 213 according to the synchronous count value syn_c sent by the corresponding synchronous count module 23; the buffer module 224 obtains the corresponding synchronous count value syn_c2 when the test vector Tpat is transferred from the test vector generating module 222 to the buffer module 224 according to the synchronous count value syn_c sent by the corresponding synchronous count module 23. It can be seen that the third transmission count value syn_t3 corresponding to the third transmission time is equal to the difference between syn_c3 and syn_c2; the second transmission count value syn_t2 corresponding to the second transmission time is equal to the difference between syn_c2 and syn_c1, where syn_c1 is the synchronization count value corresponding to the memory module 211 when transmitting to the test vector generation module 222.
In an embodiment, the start time of the test signal generating module 213 is equal to the sum of the test instruction issuing time, the first transmission time, the second transmission time, and the third transmission time; the synchronous count value syn_c_s corresponding to the start time of the test signal generating module 213 is equal to the sum of the synchronous count value syn_c0, the first transmission count value syn_t1, the second transmission count value syn_t2 and the third transmission count value syn_t3 corresponding to the test instruction issuing time.
In another embodiment, the start time of the test signal generating module 213 is equal to the sum of the test instruction issue time, the first transmission time, the second transmission time, the third transmission time, and the preset second margin time. The synchronous count value syn_c_s corresponding to the start time of the test signal generating module 213 is equal to the sum of the synchronous count value syn_c0 corresponding to the test instruction issuing time, the first transmission count value syn_t1, the second transmission count value syn_t2, the third transmission count value syn_t3, and the second margin threshold corresponding to the second margin time.
The test signal generating module 213 starts operation according to the synchronization count value syn_c_s acquired in the above embodiment, and converts the received test vector Tpat into the corresponding synchronization test signal Tsig. There are a plurality of the synchronous test signals Tsig, and the test signal generation module 213 may sequentially transmit the synchronous test signals Tsig based on the synchronous clock signal clk_dom.
In a further embodiment, as shown in fig. 3, the first control unit includes a synchronous counting module 23, and a memory module 211 and a test signal generating module 213 connected to the corresponding synchronous counting module 23, and the second control unit includes a synchronous counting module 23, and a test vector generating module 222 and a buffer module 224 connected to the corresponding synchronous counting module 23.
The memory module 211 acquires a reference count value based on the synchronization count value syn_c0 when the test instruction Tcom is received; the test vector generation module 222 acquires a first determination value based on the reference count value and a first transmission count value syn_t1 acquired in advance; when the synchronization count value syn_c reaches a first determination value, the test vector Tpat output is started.
The test signal generating module 213 acquires a second determination value based on the reference count value and the first transmission count value syn_t1, the second transmission count value syn_t2, and the third transmission count value syn_t3 acquired in advance; in the case where the synchronization count value syn_c reaches the second determination value, the synchronization test signal Tsig is started to be output.
The first transmission count value syn_t1, the second transmission count value syn_t2, and the third transmission count value syn_t3 may be obtained through a correlation test performed in advance.
The reference count value is reference data for calculating the first determination value and the second determination value. The reference count value may be equal to the sync count value syn_c0 when the memory module 211 receives the test instruction Tcom. The first control unit transmits the reference count value to the test signal generation module 213 and the test vector generation module 222 of the second control unit.
In one embodiment, the first determination value is equal to the sum of the reference count value and the first transmission count value syn_t1.
In another embodiment, the first decision value is equal to a sum of the reference count value, the first transmission count value syn_t1, and the first margin threshold.
In an embodiment, the second determination value is equal to a sum of the reference count value, the first transmission count value syn_t1, the second transmission count value syn_t2, and the third transmission count value syn_t3.
In another embodiment, the first decision value is equal to a sum of the reference count value, the first transmission count value syn_t1, the second transmission count value syn_t2, the third transmission count value syn_t3, and the second margin threshold.
The synchronous test signal generating system of the embodiment determines the starting time of the test signal generating module based on the issuing time of the test instruction, the first transmission time, the second transmission time of the test vector transmitted from the test vector generating module to the buffer module and the third transmission time of the test vector transmitted from the buffer module to the test signal generating module, controls the synchronous starting of the test signal generating modules on each test board, and realizes the synchronization of the generation and the output of the test signals.
In a further embodiment, the buffer module is further configured to initiate sending of the test vectors if the number of buffered test vectors reaches a preset number threshold.
After receiving the test vectors, the buffer module in this embodiment does not forward the test vectors immediately, but starts the test vectors to be sent after the number of the buffered test vectors reaches a preset number threshold. The start-up time of the test signal generation module may be determined based on the test instruction issue time, the first transmission time, the second transmission time, the third transmission time, and the buffer delay time of the test vector.
According to the synchronous test signal generation system, under the condition that the number of the test vectors cached by the cache module reaches the preset number threshold value, the transmission of the test vectors is started, a certain number of test vectors are always present in the cache module in the test vector transmission process, data interruption caused by the abnormality of other modules in the transmission process is avoided, and the stability of test operation is improved.
In some embodiments, when the test vector generation module pauses operation, continuously sending invalid data to the cache module until the test vector generation module resumes operation, wherein the invalid data comprises an invalid identifier; the caching module caches invalid data and sequentially sends the invalid data to the test signal generating module; the test signal generation module discards invalid data based on the invalid identification.
In practical application, the test vector generation module may suspend sending the test vector due to environmental factors or abnormal states. After all the test vectors stored in the buffer memory module are sent to the test signal generating module, if the test vector generating module still cannot recover the normal state, the sending of the test vectors is interrupted, so that the interruption of the synchronous test signals is caused. In order to avoid the situation, the test vector generation module can continuously send invalid data to the cache module until the test vector generation module resumes operation under the condition that the test vector cannot be normally sent. Wherein the invalid data contains an invalid identifier, and the invalid identifier can be a specific character or a character string. The buffer module buffers the invalid data and sequentially sends the buffered invalid data to the test signal generating module, and the test signal generating module identifies and discards the invalid data based on the invalid identifier.
According to the synchronous test signal generation system, invalid data is sent through the test vector generation module, the invalid data is received, identified and discarded through the test signal generation module, the interruption of synchronous test signal output caused by the interruption of the test vector data flow is avoided, and the stability of test operation is improved.
In some embodiments, fig. 4 is a block diagram of a test board according to still other embodiments of the present application, as shown in fig. 4, where the test board includes a plurality of first control units 21 (2 are shown in the figure), based on the synchronous clock signal clk_dom, the plurality of first control units 21 send corresponding test instructions Tcom1, tcom2 to the second control unit 22, and the test instructions Tcom1, tcom2 include a unit identifier; the second control unit 22 converts the test instructions Tcom1, tcom2 into corresponding test vectors Tpat1, tpat2 and sends the test vectors Tpat1, tpat2 to the corresponding first control unit 21 based on the unit identifications.
Specifically, the memory module 211 of the plurality of first control units 21 may send a test instruction to the test vector generation module 222 of the same second control unit 22, where the test instruction includes a unit identifier for identifying each first control unit 21, and after the test vector generation module 222 obtains the test instruction, the test instruction is converted into a corresponding test vector and sequentially sent to the buffer module 224, where the test vector also includes a unit identifier for identifying each first control unit 21. The buffer module 224 sends the test vectors to the test signal generating modules 213 of the corresponding first control units 21 according to the unit identifications in the test vectors, respectively. The test signal generation module 213 converts the test vector into a corresponding test signal output. The test signals output by the test signal generating modules 213 with the same serial numbers in the plurality of test boards are synchronously output between the boards.
According to the synchronous test signal generation system, the corresponding test instructions are respectively sent to the second control units through the plurality of first control units, so that the test instruction loading and the function separation based on the plurality of control units are realized, the resource requirement on a single control unit is reduced, and the mutual influence of signal time sequences is reduced; the second control unit is used for converting the test instruction into the corresponding test vector, and the test vector is sent to the corresponding first control unit based on the unit identification, so that the test vectors of different test instructions are uniformly generated and respectively output, hardware resources required by the generation of the test vector are reduced, and the test cost is reduced.
In some embodiments, the present application further provides a synchronous test signal generating method. The synchronous test signal generating method is applied to a test board in a synchronous test signal generating system, the test board comprises a first control unit and a second control unit, fig. 5 is a flowchart of the synchronous test signal generating method according to some embodiments of the present application, and as shown in fig. 5, the flowchart comprises the following steps:
step S501, based on the received synchronous clock signal, a test instruction received by the first control unit is sent to the second control unit, and the synchronous clock signal and the test instruction are issued by the main control board;
Step S502, based on the synchronous clock signal, a test vector correspondingly generated by the second control unit based on the test instruction is sent to the first control unit;
step S503, based on the synchronous clock signal, outputting a synchronous test signal correspondingly generated by the first control unit based on the test vector; the plurality of synchronous test signals output by the plurality of test boards are used for executing parallel test of the tested device.
Through the steps S501 to S503, the test instructions received by the first control unit are sent to the second control unit based on the synchronous clock signal, so as to ensure synchronous receiving and synchronous transmission of the test instructions of each test board; the second control unit sends the test vectors generated by the second control unit based on the test instructions to the first control unit based on the synchronous clock signals, so that synchronous generation and synchronous transmission of the test vectors of all the test boards are ensured; the synchronous test signals generated by the first control unit based on the test vectors are output based on the synchronous clock signals, so that synchronous generation and synchronous transmission of the test signals of each test board are ensured, under the condition that two control units respectively bear the functions of generating the test vectors and generating the test signals on the test boards, the inter-board synchronization of the test signals is realized, the resource requirement on a single control unit is reduced, the mutual influence of signal time sequences is reduced, and the problems that FPGA (field programmable gate array) chip resources of a digital board card of a testing machine are tense and the mutual influence of the signal time sequences is difficult to converge in the related art are solved.
In some embodiments, fig. 6 is a flowchart of outputting a synchronous test signal from a first control unit based on a synchronous clock signal according to some embodiments of the present application, as shown in fig. 6, the flowchart including the steps of:
step S601, based on the synchronous clock signal, determining a synchronous count value corresponding to the issuing time of the test instruction, a first transmission count value corresponding to the first transmission time of the test instruction from the first control unit to the second control unit, a second transmission count value corresponding to the second transmission time of the test vector transmitted inside the second control unit, and a third transmission count value corresponding to the third transmission time of the test vector transmitted from the second control unit to the first control unit;
step S602, determining an output time of the synchronous test signal based on the synchronous count value, the first transmission count value, the second transmission count value, and the third transmission count value.
Through the steps S601 to S602, the synchronization count value corresponding to the issuing time of the test instruction, the first transmission count value corresponding to the first transmission time, the second transmission count value corresponding to the second transmission time, and the third transmission count value corresponding to the third transmission time are determined based on the synchronization clock signal, so as to realize the quantification of the transmission time based on the synchronization count mode; the output time of the synchronous test signals is determined based on the synchronous count value, the first transmission count value, the second transmission count value and the third transmission count value, so that a feasible control mode for guaranteeing the output synchronization of the test signals of all the test boards is provided.
In some embodiments, fig. 7 is a flowchart of transmitting test vectors from the second control unit based on the synchronous clock signal according to some embodiments of the present application, as shown in fig. 7, the flowchart including the steps of:
step S701, determining a synchronous count value corresponding to a issuing time of a test instruction and a first transmission count value corresponding to a first transmission time of the test instruction from the first control unit to the second control unit based on the synchronous clock signal;
step S702, determining a start time of the second control unit for generating the test vector based on the test instruction correspondence based on the synchronization count value and the first transmission count value.
Through the steps S701 to S702, the synchronization count value corresponding to the issuing time of the test instruction and the first transmission count value corresponding to the first transmission time are determined based on the synchronization clock signal, and the quantification of the transmission time of the test instruction is realized based on the synchronization count mode; and determining the starting time of the second control unit for generating the test vector based on the corresponding test instruction based on the synchronous count value and the first transmission count value, and controlling the synchronous starting of the test vector generation modules on each test board to realize the synchronization of the generation and the output of the test vector.
It should be noted that the steps illustrated in the above-described flow or flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
In addition, in combination with the failure data acquisition method provided in the above embodiment, a readable storage medium may be provided in the present embodiment. The readable storage medium has a program stored thereon; the program, when executed by a processor, implements any of the failure data acquisition methods of the above embodiments.
It should be noted that, specific examples in this embodiment may refer to examples described in the foregoing embodiments and alternative implementations, and are not described in detail in this embodiment.
It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present application, are within the scope of the present application in light of the embodiments provided herein.
It is evident that the drawings are only examples or embodiments of the present application, from which the present application can also be adapted to other similar situations by a person skilled in the art without the inventive effort. In addition, it should be appreciated that while the development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as an admission of insufficient detail.
The term "embodiment" in this application means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive. It will be clear or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the patent. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application shall be subject to the appended claims.
Claims (10)
1. A synchronous test signal generating system is characterized in that the system comprises a main control board and a plurality of test boards, the test boards comprise a first control unit and a second control unit,
the main control board sends synchronous clock signals to the plurality of test boards;
based on the synchronous clock signal, the main control board issues a test instruction to a first control unit of the plurality of test boards;
based on the synchronous clock signal, the first control unit sends the test instruction to the second control unit, the second control unit converts the test instruction into a corresponding test vector and sends the corresponding test vector to the first control unit, and the first control unit converts the test vector into a corresponding synchronous test signal to be output; and the synchronous test signals output by the test boards are used for executing parallel test of the tested device.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the test board determines an output time of the synchronous test signal based on a issuing time of the test instruction, a first transmission time of the test instruction from the first control unit to the second control unit, a second transmission time of the test vector transmitted inside the second control unit, and a third transmission time of the test vector transmitted from the second control unit to the first control unit.
3. The system of claim 2, wherein the first control unit comprises a memory module and the second control unit comprises a test vector generation module,
the test board determines the starting time of the test vector generation module based on the issuing time of the test instruction and the first transmission time of the test instruction transmitted from the memory module to the test vector generation module;
and after the test vector generation module is started, converting the test instruction into a corresponding test vector.
4. The system of claim 3, wherein the second control unit further comprises a buffer module and the first control unit further comprises a test signal generation module;
the buffer module is used for buffering the test vectors generated by the test vector generation module and sequentially sending the test vectors to the test signal generation module according to a storage sequence;
the test board determines the starting time of the test signal generating module based on the issuing time of the test instruction, the first transmission time, the second transmission time of the test vector from the test vector generating module to the buffer module, and the third transmission time of the test vector from the buffer module to the test signal generating module;
And after the test signal generating module is started, the test vector is converted into a corresponding synchronous test signal to be output.
5. The system of claim 4, wherein the caching module is further configured to:
and under the condition that the number of the cached test vectors reaches a preset number threshold value, starting the sending of the test vectors.
6. The system of claim 4, wherein the system further comprises a controller configured to control the controller,
when the test vector generation module is in a temporary operation state, invalid data is continuously sent to the cache module until the test vector generation module resumes operation, wherein the invalid data comprises an invalid identifier;
the caching module caches the invalid data and sequentially sends the invalid data to the test signal generating module;
the test signal generation module discards the invalid data based on the invalid identification.
7. The system of claim 2, wherein the first control unit and the second control unit comprise a synchronous counting module,
the synchronous counting module obtains a synchronous counting value based on the synchronous clock signal;
the second control unit determines a synchronous count value corresponding to the output time of the test vector based on the synchronous count value corresponding to the issuing time of the test instruction and a first transmission count value corresponding to the first transmission time;
The first control unit determines a synchronous count value corresponding to the output time of the synchronous test signal based on the synchronous count value corresponding to the issuing time of the test instruction, the first transmission count value corresponding to the first transmission time, the second transmission count value corresponding to the second transmission time, and the third transmission count value corresponding to the third transmission time.
8. The system of claim 7, wherein the first control unit further comprises a memory module and a test signal generation module connected to the corresponding synchronous counting module, and the second control unit further comprises a test vector generation module and a cache module connected to the corresponding synchronous counting module;
the memory module obtains a reference count value based on the synchronous count value when a test instruction is received;
the test vector generation module acquires a first judgment value based on the reference count value and a first transmission count value acquired in advance; starting the test vector output under the condition that the synchronous count value reaches the first judgment value;
the test signal generation module acquires a second judgment value based on the reference count value and a first transmission count value, a second transmission count value and a third transmission count value which are acquired in advance; and under the condition that the synchronous count value reaches the second determination value, starting the synchronous test signal output.
9. The system of claim 1, wherein the test board comprises a plurality of first control units,
based on the synchronous clock signals, the plurality of first control units send corresponding test instructions to the second control units, wherein the test instructions comprise unit identifications;
the second control unit converts the test instruction into a corresponding test vector and sends the test vector to the corresponding first control unit based on the unit identifier.
10. A synchronous test signal generation method, characterized in that the method is applied to a test board comprising a first control unit and a second control unit, the method comprising:
based on the received synchronous clock signal, sending the test instruction received by the first control unit to the second control unit, wherein the synchronous clock signal and the test instruction are issued by a main control board;
based on the synchronous clock signal, a test vector correspondingly generated by the second control unit based on the test instruction is sent to the first control unit;
based on the synchronous clock signal, outputting a synchronous test signal correspondingly generated by the first control unit based on the test vector; and the synchronous test signals output by the test boards are used for executing parallel test of the tested device.
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| CN119356731B (en) * | 2024-12-25 | 2025-07-01 | 杭州长川科技股份有限公司 | Inter-board synchronous triggering method of micro-instructions and micro-instruction control test system |
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