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CN117855159A - Stacked package structure and method for manufacturing the same - Google Patents

Stacked package structure and method for manufacturing the same Download PDF

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Publication number
CN117855159A
CN117855159A CN202211216247.8A CN202211216247A CN117855159A CN 117855159 A CN117855159 A CN 117855159A CN 202211216247 A CN202211216247 A CN 202211216247A CN 117855159 A CN117855159 A CN 117855159A
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CN
China
Prior art keywords
substrate
chip
conductive
package
package structure
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CN202211216247.8A
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Chinese (zh)
Inventor
李森阳
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Shunsin Technology Zhongshan Ltd
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Shunsin Technology Zhongshan Ltd
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Priority to CN202211216247.8A priority Critical patent/CN117855159A/en
Publication of CN117855159A publication Critical patent/CN117855159A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A stacked package structure, comprising: a lower package including a lower thermally conductive substrate and a first chip mounted on the lower thermally conductive substrate; the upper packaging body comprises an upper substrate and a second chip arranged on the upper substrate, wherein the lower heat conducting substrate is directly connected to the upper substrate through a plurality of conductive columns, so that multi-path heat dissipation is realized, heat dissipation efficiency is improved, and damage to a device due to the fact that the total amount of heat generated by the chips in the stacked packaging structure is increased due to the increase of power density and chip density is reduced.

Description

Stacked package structure and method for manufacturing the same
Technical Field
The invention relates to the technical field of packaging, in particular to a stacked packaging structure and a method for manufacturing the stacked packaging structure.
Background
With the development of the electronics industry, such as the 3C (computer, communication, and consumer electronics) related industry, the demand for multi-functional, more convenient, and smaller-sized devices has rapidly increased, further forcing an increase in Integrated Circuit (IC) density. Increasing integrated circuit density has led to the development of multiple chip packages such as in-package packages (package in package, piP) and package-on-package (package on package, poP). Stacked packages allow integration of chips (e.g., microprocessors, memories, logic or optical integrated circuits, etc.) having different functions. However, stacked packages require higher power densities than individual single chip packages. Therefore, thermal management is becoming increasingly important as power densities increase and semiconductor device sizes within a chip shrink (i.e., chip densities increase). The increase in power density and chip density increases the amount of heat generated by the chips in the stacked package structure, and excessive heat typically reduces device performance and may damage the device.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a stacked package structure that improves heat dissipation efficiency and reduces the damage to the device caused by the increase in the total amount of heat generated by the chips in the stacked package structure due to the increase in power density and IC density.
An embodiment of the present invention provides a stacked package structure, including:
a lower package including a lower thermally conductive substrate and a first chip mounted on the lower thermally conductive substrate;
the upper packaging body comprises an upper substrate and a second chip arranged on the upper substrate, wherein the lower heat conducting substrate is directly connected to the upper substrate through a plurality of electric conduction columns.
Preferably, the top of the lower heat conducting substrate comprises a plurality of opening structures, each opening structure is provided with a bare metal bonding pad, and the plurality of conductive posts are respectively implanted into the opening structures.
Preferably, the bottom of the lower heat conductive substrate includes a plurality of solder balls, and the plurality of solder balls are in contact with the metal pads.
Preferably, the conductive posts on two sides of the top of the lower heat conducting substrate are higher than the conductive posts in the middle;
and forming a slotted hole area after the conductive posts are injected with glue, wherein the first chip is arranged in the slotted hole area.
Preferably, the first chip comprises a contact pad, and the contact pad is electrically connected with the middle conductive post;
and the first chip is encapsulated by glue injection.
Preferably, the upper substrate is disposed above the first chip, the bottom of the upper substrate is connected to the conductive columns on two sides of the top of the lower heat conducting substrate, and the second chip is disposed on the top of the upper substrate.
An embodiment of the present invention provides a method for manufacturing a stacked package structure, including the steps of:
arranging a first chip on the lower heat conducting substrate to form a lower package;
disposing a second chip on the upper substrate to form an upper package;
the lower thermally conductive substrate is directly connected to the upper substrate by a plurality of electrically conductive posts.
Preferably, the disposing the first chip on the lower heat conductive substrate forms a lower package, and specifically includes the following steps:
forming a plurality of opening structures by opening holes on the lower heat conducting substrate;
providing a metal pad on each opening structure;
placing the plurality of conductive posts in the plurality of opening structures respectively;
injecting glue to the plurality of conductive columns to form a slotted hole area, wherein the conductive columns on two sides of the top of the lower heat conducting substrate are higher than the conductive columns in the middle;
the first chip is arranged in the slotted hole area.
Preferably, the method further comprises the following steps:
planting a plurality of solder balls at the bottom of the lower heat conduction substrate, wherein the plurality of solder balls are in contact with the metal bonding pads;
encapsulating the first chip by injecting glue, wherein the first chip comprises a contact pad, and the contact pad is electrically connected with the middle conductive column;
and the conductive posts on two sides of the top of the lower heat conducting substrate are exposed.
Preferably, the disposing the second chip on the upper substrate forms an upper package, specifically including:
placing the upper substrate over the first chip;
connecting the bottom of the upper substrate with the conductive columns on two sides of the top of the lower heat conducting substrate;
the second chip is disposed on top of the upper substrate.
Compared with the prior art, the stacked package structure provided by the embodiment of the invention comprises a lower package body and an upper package body, wherein the lower package body comprises a lower heat conduction substrate and a first chip arranged on the lower heat conduction substrate; the upper packaging body comprises an upper substrate and a second chip arranged on the upper substrate, wherein the lower heat conducting substrate is directly connected to the upper substrate through a plurality of electric conduction columns. Since the lower heat conducting substrate is directly connected to the upper substrate through the plurality of conductive posts, the stacked package structure has 3 heat dissipation paths: the radiation heat dissipation path, the convection heat dissipation path and the thermal conduction heat dissipation path improve the heat dissipation efficiency and reduce the damage to the device caused by the increase of the total heat generated by chips in the stacked package structure due to the increase of the power density and the IC density.
Drawings
FIG. 1 is a schematic block diagram of a stacked package structure according to an embodiment of the present invention;
FIG. 2 is a schematic view illustrating an opening of a lower thermally conductive substrate of the stacked package structure according to the present invention;
FIG. 3 is a schematic view of a stacked package structure of the present invention with conductive pillars implanted in an opening structure;
FIG. 4 is a schematic diagram of the stacked package structure of the present invention for injecting glue into the conductive pillars;
FIG. 5 is a schematic diagram of a stacked package structure of the present invention for grooving a glue injection region of a conductive post to form a slot region;
FIG. 6 is a schematic diagram of a first chip package of the stacked package structure of the present invention;
FIG. 7 is a schematic illustration of the glue injection of a first chip of the stacked package structure of the present invention;
FIG. 8 is a schematic diagram illustrating the polishing of the first chip after the glue injection of the stacked package structure according to the present invention;
FIG. 9 is a schematic view of a bottom ball mounting of a lower thermally conductive substrate of a stacked package structure according to the present invention;
fig. 10 is a flow chart of an embodiment of a method for fabricating a stacked package structure according to the present invention.
Description of the main reference signs
1: stacked package structure
11: lower package
12: upper package
13: conductive column
15: slot hole area
14. 16: sealing adhesive layer
110: lower heat conducting substrate
111: first chip
120: upper base plate
121: second chip
1101: opening structure
1102: metal bonding pad
1110: contact pad
A: radiation heat dissipation path
B: convection heat dissipation path
C: heat conduction and dissipation path
S100, S102, S104: step (a)
The following detailed description will further illustrate the application in conjunction with the above-described figures.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic block diagram of an embodiment of a stacked package structure 1 according to the present invention. As shown in fig. 1, the stacked package structure 1 includes a lower package 11, an upper package 12, and a plurality of conductive pillars 13. The lower package 11 includes a lower heat conductive substrate 110 and a first chip 111 mounted on the lower heat conductive substrate 110. The lower heat conductive substrate 110 may be an ultra-high heat conductive aluminum substrate. The upper package 12 includes an upper substrate 120 and a second chip 121 mounted on the upper substrate 120, wherein the lower thermally conductive substrate 110 is directly connected to the upper substrate 120 through a plurality of conductive posts 13. The upper substrate 120 may be a Printed Circuit Board (PCB) or a laminate substrate. The substrate may be formed by a lamination method (laminated) and a Build-up method (Build-up), which are prior art, so specific implementation details will not be described in detail for brevity. The material of the dielectric structure inside the substrate may include epoxy, phenolic, glass epoxy, polyimide, polyester, epoxy molding compound, ceramic, or the like. Since the lower thermally conductive substrate 110 is directly connected to the upper substrate 120 through the plurality of conductive pillars 13, the stacked package structure 1 has 3 heat dissipation paths: a radiation heat dissipation path A, a convection heat dissipation path B and a thermal conduction heat dissipation path C. The radiation heat dissipation path a radiates a part of heat of the upper package 11 to the periphery. The heat conduction and dissipation path C transfers a part of heat of the upper package 11 to the lower heat conduction substrate 110 through the plurality of conductive columns, and the lower heat conduction substrate 110 has a heat conduction effect, so that the heat is dissipated to the periphery rapidly. The convective heat dissipation path B convectively dissipates heat through the upper and lower surfaces of the lower heat conductive substrate 110. The stacked package structure 1 improves heat dissipation efficiency through various heat dissipation paths, and reduces damage to devices due to an increase in the total amount of heat generated by chips in the stacked package structure caused by an increase in power density and chip density.
In this embodiment, the top of the lower heat conductive substrate 110 includes a plurality of opening structures 1101, and each opening structure 1101 is provided with a bare metal pad 1102, as shown in fig. 2, and fig. 2 is a schematic view of the opening of the lower heat conductive substrate 110. The plurality of conductive pillars 13 are respectively implanted into the opening structure 1101 and connected to the metal pads 1102, and the conductive pillars on both sides of the top of the lower thermally conductive substrate 110 are higher than the conductive pillars in the middle, as shown in fig. 3, and fig. 3 is a schematic diagram of implanting conductive pillars in the opening structure. The plurality of conductive posts 13 may be made of copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold, or metal materials capable of achieving a conductive function, and the implantation may be electrolytic plating or chemical deposition. In the present embodiment, 5 opening structures 1101 and 5 conductive pillars 13 are exemplified, but not limited thereto. And injecting glue into the plurality of conductive posts 13, and sealing the plurality of conductive posts to form a sealing layer 14. The injection molding material can be epoxy resin (Expoxyresin), cyanate Ester, bismaleimide triazine, glass fiber, and polybenzoOxazole (polybenzoxazole), polyimide (polyimide), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or similar insulating materials, or a mixture of epoxy and glass fiber or other insulating organic or ceramic materials. As shown in fig. 4, fig. 4 is a schematic illustration of the injection of the conductive pillars 13. As shown in fig. 5, fig. 5 is a schematic diagram of slotting the sealing adhesive layer 14 of the conductive post 13 to form a slot area 15. The first chip 111 is disposed in the slot region 15. The first chip 111 includes a contact pad 1110, and is electrically connected to the intermediate conductive pillar through the contact pad 1110, as shown in fig. 6, and fig. 6 is a schematic view of the first chip set. Injecting glue to the first chip 111, and molding the first chip 111 to form a sealing glue layer16. The injection molding material can be epoxy resin (Expoxyresin), cyanate Ester, bismaleimide triazine, glass fiber, and polybenzo->Oxazole (polybenzoxazole), polyimide (polyimide), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or similar insulating materials, or a mixture of epoxy and glass fiber or other insulating organic or ceramic materials. As shown in fig. 7, fig. 7 is a schematic illustration of the injection of the first chip 111. After the first chip 111 is injected with the glue, the first chip 111 is polished to expose the conductive pillars on both sides of the lower thermally conductive substrate 110 and the top of the first chip, as shown in fig. 8, and fig. 8 is a schematic diagram of polishing the first chip 111 after the glue injection. In this embodiment, the planarization process may be used to polish the sealing layer until the conductive pillars on both sides of the lower thermally conductive substrate 110 and the top of the first chip 111 are exposed. The planarization process may include a mechanical polishing process, a chemical mechanical polishing (chemical mechanical polishing, CMP) process, or other suitable processes, and combinations thereof.
In this embodiment, the portion of the lower thermally conductive substrate 110 includes a plurality of solder balls 1103, the plurality of solder balls 1103 are in contact with the metal pads 1102, the solder balls 1103 can be implanted at the bottom of the lower thermally conductive substrate 110 by a ball implantation operation (Ball Implantation), and the stacked package structure 1 can be electrically connected to an external device (such as a printed circuit board) by using the solder balls 1103, as shown in fig. 9, and fig. 9 is a schematic diagram of ball implantation at the bottom of the lower thermally conductive substrate 110. After the ball is planted at the bottom of the lower heat conducting substrate 110, stacking the lower package 11 and the upper package 12 to form a stacking structure. Specifically, the upper substrate 120 is disposed above the first chip 111, the bottom of the upper substrate 120 is connected to the conductive pillars on both sides of the top of the lower heat conductive substrate 110, and the second chip 121 is disposed on the top of the upper substrate 120 and connected to the upper substrate 120 through the contact pads 1210, as shown in fig. 1.
Referring to fig. 10, fig. 10 is a schematic flow chart of an embodiment of a method for manufacturing a stacked package structure 1 according to the present invention. As shown in fig. 10, the method of manufacturing a stacked package structure of the present invention includes the steps of:
step S100: the first chip 111 is disposed on the lower heat conductive substrate 110 to form the lower package 11.
Specifically, holes are formed on the lower heat conductive substrate 110 to form a plurality of opening structures 1101; a metal pad 1102 is provided over each open structure 1101, as shown in particular in fig. 2. The plurality of conductive pillars 13 are respectively disposed in the plurality of opening structures 1101 and connected to the metal pads 1102, as shown in fig. 3, the plurality of conductive pillars 13 may be made of copper, aluminum, nickel, silver, gold, copper silver, nickel gold, nickel palladium gold or a metal material capable of achieving a conductive function, and the implantation method may be electrolytic plating or chemical deposition. The plurality of conductive pillars 13 are injected with glue to form a sealing layer 14, as shown in fig. 4. The injection molding material can be epoxy resin (Expoxyresin), cyanate Ester, bismaleimide triazine, glass fiber, and polybenzoOxazole (polybenzoxazole), polyimide (polyimide), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or similar insulating materials, or a mixture of epoxy and glass fiber or other insulating organic or ceramic materials. The conductive columns on both sides of the top of the lower heat conducting substrate 110 are higher than the conductive columns in the middle, and the sealing glue layer 14 formed by injecting glue into the conductive columns 13 is grooved to form a slot area 15 and expose the conductive columns in the middle of the top of the lower heat conducting substrate, so that the first chip 111 is disposed in the slot area 15, as shown in fig. 5.
In this embodiment, the method further includes: a plurality of solder balls 1103 are planted on the bottom of the lower heat conductive substrate 110, and the plurality of solder balls 1103 are in contact with the metal pads 1102, as shown in fig. 9; encapsulating the first chip 111 by injecting glue, wherein the first chip 111 comprises a contact pad 1110, and the contact pad 1110 is electrically connected with the middle conductive column; the conductive pillars on both sides of the top of the lower thermally conductive substrate 110 are exposed. Specifically, the first chip 111 is injected with a glue, and the first chip 111 is molded to form a sealing glue layer 16, and the glue injection material may be an epoxy treeFats (Expoxyresin), cyanate Ester, bismaleimide triazine, glass fiber, and polybenzoOxazole (polybenzoxazole), polyimide (polyimide), nitride (e.g., silicon nitride), oxide (e.g., silicon oxide), silicon oxynitride, or similar insulating materials, or a mixture of epoxy and glass fiber or other insulating organic or ceramic materials. As shown in fig. 7. After the first chip 111 is completely filled with the adhesive, the conductive pillars and the first chip 111 on both sides of the top of the lower thermally conductive substrate 110 are exposed by grinding, as shown in fig. 8. In this embodiment, the planarization process may be used to polish the sealing layer until the conductive pillars on both sides of the lower thermally conductive substrate 110 and the top of the first chip 111 are exposed. The planarization process may include a mechanical polishing process, a chemical mechanical polishing (chemical mechanical polishing, CMP) process, or other suitable processes, and combinations thereof. .
In step S102, the second chip 121 is disposed on the upper substrate 120 to form an upper package.
Specifically, the upper substrate 120 is placed above the first chip 111; connecting the bottom of the upper substrate 120 with the conductive pillars on both sides of the top of the lower thermally conductive substrate 110; the second chip 121 is disposed on top of the upper substrate 120, as shown in fig. 1. The upper substrate 120 may be a Printed Circuit Board (PCB) or a laminate substrate. The substrate may be formed by a lamination method (laminated) and a Build-up method (Build-up), which are prior art, so specific implementation details will not be described in detail for brevity. The material of the dielectric structure inside the substrate may include epoxy, phenolic, glass epoxy, polyimide, polyester, epoxy molding compound, ceramic, or the like.
In step S104, the lower thermally conductive substrate 110 is directly connected to the upper substrate 120 through the plurality of conductive posts 13.
Since the lower thermally conductive substrate 110 is directly connected to the upper substrate 120 through the plurality of conductive pillars 13, the stacked package structure 1 has 3 heat dissipation paths: a radiation heat dissipation path A, a convection heat dissipation path B and a thermal conduction heat dissipation path C. The radiation heat dissipation path a radiates a part of heat of the upper package 11 to the periphery. The heat conduction and dissipation path C transfers a part of heat of the upper package 11 to the lower heat conduction substrate 110 through the plurality of conductive columns, and the lower heat conduction substrate 110 has a heat conduction effect, so that the heat is dissipated to the periphery rapidly. The convective heat dissipation path B convectively dissipates heat through the upper and lower surfaces of the lower heat conductive substrate 110. The stacked package structure 1 improves heat dissipation efficiency through various heat dissipation paths, and reduces damage to devices due to an increase in the total amount of heat generated by chips in the stacked package structure caused by an increase in power density and IC density.
Compared with the prior art, the stacked package structure provided by the embodiment of the invention comprises a lower package body and an upper package body, wherein the lower package body comprises a lower heat conduction substrate and a first chip arranged on the lower heat conduction substrate; the upper packaging body comprises an upper substrate and a second chip arranged on the upper substrate, wherein the lower heat conducting substrate is directly connected to the upper substrate through a plurality of electric conduction columns. Since the lower heat conducting substrate is directly connected to the upper substrate through the plurality of conductive posts, the stacked package structure has 3 heat dissipation paths: the radiation heat dissipation path, the convection heat dissipation path and the thermal conduction heat dissipation path improve the heat dissipation efficiency and reduce the damage to the device caused by the increase of the total heat generated by chips in the stacked package structure due to the increase of the power density and the IC density.
It will be appreciated by persons skilled in the art that the above embodiments have been provided for the purpose of illustrating the invention and are not to be construed as limiting the invention, and that suitable modifications and variations of the above embodiments are within the scope of the invention as claimed.

Claims (10)

1. A stacked package structure, comprising:
a lower package including a lower thermally conductive substrate and a first chip mounted on the lower thermally conductive substrate;
the upper packaging body comprises an upper substrate and a second chip arranged on the upper substrate, wherein the lower heat conducting substrate is directly connected to the upper substrate through a plurality of electric conduction columns.
2. The package on package structure of claim 1, wherein the top of the lower thermally conductive substrate includes a plurality of opening structures, each opening structure being provided with exposed metal pads, the plurality of conductive pillars being respectively implanted into the opening structures.
3. The package on package structure of claim 2, wherein the bottom of the lower thermally conductive substrate includes a plurality of solder balls in contact with the metal pads.
4. The package on package structure of claim 1, wherein:
the conductive columns on the two sides of the top of the lower heat conduction substrate are higher than the conductive columns in the middle;
and forming a slotted hole area after the conductive posts are injected with glue, wherein the first chip is arranged in the slotted hole area.
5. The package on package structure of claim 4, wherein:
the first chip comprises a contact pad, and is electrically connected with the middle conductive column through the contact pad;
and the first chip is encapsulated by glue injection.
6. The package on package structure of claim 4, wherein the upper substrate is disposed above the first die, the bottom of the upper substrate is connected to the conductive pillars on both sides of the top of the lower thermally conductive substrate, and the second die is disposed on top of the upper substrate.
7. A method of manufacturing a stacked package structure, the method comprising the steps of:
arranging a first chip on the lower heat conducting substrate to form a lower package;
disposing a second chip on the upper substrate to form an upper package;
the lower thermally conductive substrate is directly connected to the upper substrate by a plurality of electrically conductive posts.
8. The method of manufacturing a stacked package structure of claim 7, wherein the disposing the first chip on the lower thermally conductive substrate forms a lower package, comprising:
forming a plurality of opening structures by opening holes on the lower heat conducting substrate;
providing a metal pad on each opening structure;
placing the plurality of conductive posts in the plurality of opening structures respectively;
injecting glue to the plurality of conductive columns to form a slotted hole area, wherein the conductive columns on two sides of the top of the lower heat conducting substrate are higher than the conductive columns in the middle;
the first chip is arranged in the slotted hole area.
9. The method of manufacturing a stacked package structure of claim 8, further comprising the steps of:
planting a plurality of solder balls at the bottom of the lower heat conduction substrate, wherein the plurality of solder balls are in contact with the metal bonding pads;
encapsulating the first chip by injecting glue, wherein the first chip comprises a contact pad, and the contact pad is electrically connected with the middle conductive column;
and the conductive posts on two sides of the top of the lower heat conducting substrate are exposed.
10. The method of manufacturing a stacked package structure of claim 9, wherein disposing the second chip on the upper substrate forms an upper package, in particular comprising:
placing the upper substrate over the first chip;
connecting the bottom of the upper substrate with the conductive columns on two sides of the top of the lower heat conducting substrate;
the second chip is disposed on top of the upper substrate.
CN202211216247.8A 2022-09-30 2022-09-30 Stacked package structure and method for manufacturing the same Pending CN117855159A (en)

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