CN117851312B - Data reading system, electronic component, electronic device and data reading method - Google Patents

Abstract

The present disclosure provides a data reading system, an electronic component, an electronic device, and a data reading method, the method including: after receiving an AXI read request sent by any DMA channel, storing request related information into a first storage unit corresponding to the DMA channel, wherein the request related information is used for representing that the AXI read request is not processed; sending an AXI read request to a slave; storing the request result returned by the slave into a second FIFO; according to the target request ID of the target request result, clearing or reading request related information corresponding to the target request ID from a first storage unit corresponding to the target request ID, reading the target request result from a second FIFO, and sending the target request result to a downstream module of a corresponding DMA channel; the target request result is the earliest request result received by the DMA in the unread request results. The present disclosure effectively combines AXI bus protocol with DMA so that DMA has both out-of-order and in-order transfer capabilities.

Description

Data reading system, electronic component, electronic device and data reading method

Technical Field

The present disclosure relates to the field of data processing technology, and in particular to a data reading system, an electronic component, an electronic device, and a data reading method.

Background technique

The existing AXI (Advanced eXtensible Interface) bus protocol supports out-of-order transmission. The so-called out-of-order transmission means that the slave can return the request result of each read request to the host in a non-sequential order for multiple read requests carrying different request IDs (i.e., arid). For example, the slave receives read request a and read request b in sequence, and the arid carried by read request a is different from the arid carried by read request b. If the slave prepares the request result corresponding to read request b first, the slave can first return the request result of read request b to the host, and then return the request result of read request a to the host after preparing the request result corresponding to read request a.

The existing AXI bus protocol is not effectively combined with DMA (Direct Memory Access), resulting in a single DMA function.

Summary of the invention

The purpose of the present disclosure is to provide a data reading system, an electronic component, an electronic device and a data reading method, which effectively combine the AXI bus protocol with DMA to solve the problem of single DMA function.

According to one aspect of the present disclosure, there is provided a data reading system, the system comprising a DMA, the DMA comprising: a plurality of first storage units, a second FIFO and a control circuit;

The control circuit is configured to, after receiving an AXI read request sent by any DMA channel, store request related information in the first storage unit corresponding to the DMA channel, wherein the request related information is used to indicate that the AXI read request has not been processed, and AXI read requests sent by different DMA channels have different request IDs; send the AXI read request to the slave; and store the request result returned by the slave in the second FIFO;

The control circuit is also configured to clear or read out request-related information corresponding to the target request ID from the first storage unit corresponding to the target request ID according to the target request ID of the target request result, read out the target request result from the second FIFO, and send the target request result to the downstream module of the corresponding DMA channel; wherein the target request result is the earliest received request result among the unread request results.

In a feasible implementation of the present disclosure, the request related information includes a request ID of the AXI request, and when the control circuit clears or reads the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID, it is specifically configured as follows:

Determine whether the request related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID;

The request related information including the target request ID is cleared or read out from the first storage unit corresponding to the target request ID.

In a feasible implementation of the present disclosure, the DMA further includes a third FIFO, and the third FIFO is used to store a request ID corresponding to the request result; when the control circuit determines whether the request related information first stored in each first storage unit includes the target request ID, the control circuit is specifically configured as follows:

The request ID stored in the entry currently pointed to by the read pointer of the third FIFO is read, and the read pointer of the third FIFO is updated; and it is determined whether the request related information first stored in each first storage unit includes the request ID.

In a feasible implementation of the present disclosure, the control circuit is further configured as follows:

For the request result currently being received, after receiving the transmission completion signal last corresponding to the request result, the request ID corresponding to the request result is stored in the third FIFO.

In a feasible implementation of the present disclosure, the request related information also includes a beat number arlen, and when the control circuit reads the target request result from the second FIFO, it is specifically configured as follows:

According to the beat number arlen, the first stored request results of the beat number arlen are read out from the second FIFO.

In a feasible implementation of the present disclosure, a preset data bit of the request ID of each AXI read request is used to indicate a DMA channel that sends the AXI read request.

In a feasible implementation of the present disclosure, when the control circuit sends the target request result to the downstream module of the corresponding DMA channel, it is specifically configured as follows:

According to the preset data bit of the target request ID, the target request result is sent to a downstream module of the DMA channel represented by the preset data bit.

In a feasible implementation of the present disclosure, the DMA further includes a fourth FIFO, and the fourth FIFO is used to store request related information of the AXI read request of each DMA channel; the control circuit is further used to: after receiving the AXI read request sent by any DMA channel, store the request related information into the fourth FIFO; the request related information includes the request ID and the beat number arlen of the AXI read request;

When the control circuit stores the request related information into the first storage unit corresponding to the DMA channel, the control circuit is specifically configured as follows:

The request related information first stored in the fourth FIFO is read out, and according to the preset data bit of the request ID contained in the read request related information, the request related information is stored in the first storage unit corresponding to the DMA channel represented by the preset data bit.

In a feasible implementation of the present disclosure, the depth of each first storage unit is equal to 1.

According to another aspect of the present disclosure, an electronic component is also provided, which includes the data reading system described in any of the above embodiments. In some usage scenarios, the product form of the electronic component is embodied as a graphics card; in other usage scenarios, the product form of the electronic component is embodied as a CPU motherboard.

According to another aspect of the present disclosure, an electronic device is also provided, the electronic device comprising the above-mentioned electronic component. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

According to another aspect of the present disclosure, a data reading method is further provided, the method comprising:

After receiving an AXI read request sent by any DMA channel, storing request related information in a first storage unit corresponding to the DMA channel, wherein the request related information is used to indicate that the AXI read request has not been processed, and AXI read requests sent by different DMA channels have different request IDs;

Sending the AXI read request to the slave;

Store the request result returned by the slave into the second FIFO;

According to the target request ID of the target request result, the request related information corresponding to the target request ID is cleared or read from the first storage unit corresponding to the target request ID, and the target request result is read from the second FIFO, and the target request result is sent to the downstream module of the corresponding DMA channel; wherein, the target request result is the earliest request result received by the DMA among the unread request results.

In a feasible implementation of the present disclosure, the request related information includes a request ID of the AXI request, and clearing or reading the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID includes:

Determine whether the request related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID;

The request related information including the target request ID is cleared or read out from the first storage unit corresponding to the target request ID.

In a feasible implementation of the present disclosure, the determining whether the request related information first stored in each first storage unit contains the target request ID includes:

Read the request ID stored in the table entry currently pointed to by the read pointer of the third FIFO, and update the read pointer of the third FIFO; determine whether the request related information first stored in each first storage unit contains the request ID; wherein the third FIFO is used to store the request ID corresponding to the request result.

In a feasible implementation of the present disclosure, the method further includes:

For the request result currently being received, after receiving the transmission completion signal last corresponding to the request result, the request ID corresponding to the request result is stored in the third FIFO.

In a feasible implementation of the present disclosure, the request related information also includes a beat number arlen, and reading the target request result from the second FIFO includes:

According to the beat number arlen, the first stored request results of the beat number arlen are read out from the second FIFO.

In a feasible implementation of the present disclosure, a preset data bit of the request ID of each AXI read request is used to indicate a DMA channel that sends the AXI read request.

In a feasible implementation of the present disclosure, sending the target request result to a downstream module of the corresponding DMA channel includes:

According to the preset data bit of the target request ID, the target request result is sent to a downstream module of the DMA channel represented by the preset data bit.

In a feasible implementation of the present disclosure, storing the request related information of the AXI read request into the first storage unit corresponding to the DMA channel includes:

Read out the request related information first stored in the fourth FIFO; wherein the fourth FIFO is used to store the request related information of the AXI read request of each DMA channel;

According to the preset data bit of the request ID included in the read request related information, the request related information is stored in a first storage unit corresponding to the DMA channel represented by the preset data bit.

In a feasible implementation of the present disclosure, the depth of each first storage unit is equal to 1.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a data reading system proposed in an embodiment of the present disclosure;

FIG2 is a schematic diagram of the structure of a data reading system proposed in another embodiment of the present disclosure;

FIG3 is a schematic diagram of the structure of a data reading system proposed in another embodiment of the present disclosure;

FIG. 4 is a schematic flow chart of a data reading method provided in an embodiment of the present disclosure.

Detailed ways

Before introducing the embodiments of the present disclosure, it should be noted that:

Some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be given sequential step numbers, the operation steps therein may be implemented in parallel, concurrently or simultaneously.

In the embodiments of the present disclosure, the terms "first", "second", etc. may be used to describe various features, but these features should not be limited by these terms. These terms are used only to distinguish one feature from another.

The term “and/or” may be used in embodiments of the present disclosure. “And/or” includes any and all combinations of one or more of the associated features listed.

It should be understood that when describing the connection or communication relationship between two components, unless it is explicitly stated that the two components are directly connected or directly communicating, the connection or communication between the two components can be understood as direct connection or communication, or as indirect connection or communication through an intermediate component.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the exemplary embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present disclosure can be combined with each other without conflict.

Considering that the AXI bus protocol and DMA are not effectively combined in the prior art, resulting in the problem of single function of DMA, the present disclosure provides a data reading system. Referring to FIG1 , FIG1 is a structural schematic diagram of a data reading system proposed in an embodiment of the present disclosure. As shown in FIG1 , the data reading system includes DMA, the DMA includes multiple first storage units, and the DMA also includes a second FIFO (First Input First Output) and a control circuit (the control circuit is not shown in FIG1 ).

In the present disclosure, each first storage unit corresponds to a DMA channel, and each first storage unit is used to store request-related information of an AXI read request of a corresponding DMA channel, and the request-related information is used to characterize that the AXI read request has not been processed. Among them, an AXI read request refers to a read data request based on the AXI protocol, which is used to read data from the slave side. The depth of each first storage unit is equal to 1. For example, each first storage unit can be a FIFO with a depth of 1, and each first storage unit can only store request-related information of at most one AXI read request. Specifically, when the request-related information of an AXI read request is cleared or read out from the first storage unit, the control circuit can store the request-related information of the next AXI read request into the first storage unit, and send the next AXI read request to the slave.

In the present disclosure, the second FIFO is used to store the request result of each AXI read request.

In the present disclosure, the control circuit is configured to: after receiving an AXI read request sent by any DMA channel, store the request related information in a first storage unit corresponding to the DMA channel, the request related information is used to indicate that the AXI read request has not been processed, and the AXI read requests sent by different DMA channels have different request IDs; send the AXI read request to the slave; store the request result returned by the slave in the second FIFO;

The control circuit is also configured to clear or read request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID according to the target request ID of the target request result, read the target request result from the second FIFO, and send the target request result to the downstream module of the corresponding DMA channel; wherein the target request result is the earliest received request result among the unread request results.

It should be noted that the control circuit in the present disclosure may be a circuit generated by synthesizing and placing and routing the code written in the hardware description language HDL in sequence. Specifically, according to the functions to be implemented by the control circuit in the present disclosure, codes that can implement the corresponding functions may be written based on the hardware description language (such as the Verilog language), and then the written codes may be synthesized and placed and routed in sequence to obtain the control circuit in the present disclosure.

Alternatively, the control circuit in the present disclosure may also be a general-purpose processor, which stores codes or instructions for implementing corresponding functions. The general-purpose processor implements the functions that the control circuit in the present disclosure needs to implement by executing the codes or instructions stored therein.

During the implementation of the present disclosure, when the DMA control circuit receives an AXI read request sent by a DMA channel, on the one hand, the control circuit extracts request-related information from the AXI read request and stores the request-related information in a first storage unit corresponding to the DMA channel. After the DMA channel stores the request-related information, it indicates that an AXI read request of the DMA channel is being processed; on the other hand, the control circuit acts as an AXI protocol host and sends the AXI read request to the corresponding slave (for example, the slave may be a memory).

When the DMA control circuit receives a request result returned by a slave, the control circuit stores the request result in the second FIFO.

In addition, the DMA control circuit also reads the first stored request result (i.e., the target request result) from the second FIFO on the one hand, and determines the first storage unit corresponding to the request ID according to the request ID of the request result on the other hand, and clears or reads the request related information corresponding to the request ID from the first storage unit; the DMA control circuit also sends the read request result to the downstream module of the corresponding DMA channel. Among them, the corresponding DMA channel refers to the DMA channel corresponding to the first storage unit corresponding to the request ID, and the downstream module of the corresponding DMA channel refers to: a module that has a use demand for the request result of the DMA channel. It should also be noted that the second FIFO is a first-in-first-out queue, and the remaining request results in the second FIFO are all unread request results. The request result first stored in the second FIFO is the earliest received request result among the unread request results (i.e., the target request result).

In the present disclosure, the AXI read requests sent by different DMA channels have different request IDs, and the slave can return the request results of the AXI read requests sent by different DMA channels to the DMA in a disorderly manner based on the disorderly transmission characteristics of the AXI protocol. Furthermore, in the present disclosure, different DMA channels correspond to different first storage units respectively, instead of storing the request-related information of multiple DMA channels in the same first storage unit, so the DMA will not be limited by the first-in-first-out mechanism of the first storage unit, and can also return the request results of the AXI read requests sent by different DMA channels to the downstream module in a disorderly manner.

For the same DMA channel (such as channel CH0), since the depth of the first storage unit is equal to 1, after the request-related information of an AXI read request of the DMA channel is read out from the first storage unit (accompanied by sending the request result of the AXI read request to the downstream module of the DMA channel), the control circuit can store the request-related information of the next AXI read request of the DMA channel into the first storage unit and send the next AXI read request to the slave. Therefore, for each AXI read request of the same DMA channel, DMA will return the request results of each AXI read request in sequence.

In short, the DMA disclosed in the present invention has both out-of-order transmission capabilities and in-order transmission capabilities, and has stronger adaptability. When the application has order-preserving requirements for the request results, the same DMA channel can be called to send multiple AXI read requests to the DMA in sequence; when the application has no order-preserving requirements for the request results, multiple DMA channels can be called to send multiple AXI read requests to the DMA, so that multiple request results can be obtained more quickly.

For ease of understanding, illustratively, as shown in Figure 1, the DMA includes four first storage units, namely the first storage unit-0, the first storage unit-1, the first storage unit-2 and the first storage unit-3, and the DMA channels corresponding to these four first storage units are CH0, CH1, CH2 and CH3, respectively. The DMA also includes a second FIFO.

Assume that at the first moment, the DMA control circuit receives an AXI read request a through CH0, the control circuit stores the request related information a' of the AXI read request a into the first storage unit -0, and sends the AXI read request a to the slave; the request related information a' includes a request ID, which is arid-a.

Assume that at a second moment (the second moment is later than the first moment), the DMA control circuit receives an AXI read request b through CH2, the control circuit stores the request related information b' of the AXI read request b into the first storage unit -2, and sends the AXI read request b to the slave; the request related information b' includes a request ID, which is arid-b.

Assume that at the third moment (the third moment is later than the second moment), the DMA control circuit receives the request result b'', and the control circuit stores the request result b'' in the second FIFO (assuming that the second FIFO is empty at this time). The request result b'' carries the request ID, which is rid-b (in the AXI protocol, the rid carried by the request result and the arid carried by the corresponding AXI read request are the same string or binary string).

Assume that at the fourth moment (the fourth moment is later than the third moment), the DMA control circuit receives the request result a'', and the control circuit stores the request result a'' in the second FIFO. The request result a'' carries the request ID, which is rid-a.

It should be noted that after the third moment, the DMA control circuit will read the first stored request result (i.e., request result b'') from the second FIFO, and read the request related information b including rid-b from the first storage unit-2 according to the request ID (i.e., rid-b) of the request result b'', and the control circuit will also send the request result b'' to the downstream module of CH2. In the present disclosure, since the relevant request information b' of the AXI read request b of CH2 and the relevant request information a' of the AXI read request a of CH0 are respectively stored in different first storage units, although the relevant request information a' is first stored in the first storage unit-0 and the relevant request information b' is later stored in the first storage unit-2, it does not affect the relevant request information b' being read out from the first storage unit-2 first. It can be seen that the DMA in the present disclosure has the ability of out-of-order transmission.

It should also be noted that the DMA control circuit can indicate through a certain signal (such as a pointer, the present disclosure does not limit the specific selection of the signal) that the first storage unit-2 has been filled, thereby restricting CH2 from sending AXI read requests to the DMA.

Assume that at the fifth moment (the fifth moment is later than the third moment), the DMA control circuit receives an AXI read request c through CH2, the control circuit stores the request related information c of the AXI read request c into the first storage unit -2, and sends the AXI read request c to the slave; the request related information c includes a request ID, which is arid-c.

Assume that at the sixth moment (the sixth moment is later than the fifth moment and later than the fourth moment), the DMA control circuit receives the request result c, and the control circuit stores the request result c into the second FIFO. The request result c carries a request ID, which is rid-c.

After the sixth moment, assuming that the second FIFO also includes request result a and request result c at this time, the control circuit of the DMA first reads the request result a from the second FIFO, and reads the request related information a containing rid-a from the first storage unit-0 according to the request ID of the request result a (i.e., rid-a), and the control circuit also sends the request result a to the downstream module of CH0; then the control circuit reads the request result c from the second FIFO, and reads the request related information c containing rid-c from the first storage unit-2 according to the request ID of the request result c (i.e., rid-c), and the control circuit also sends the request result c to the downstream module of CH2. It can be seen that for the AXI read request b and AXI read request c of CH2, the DMA returns the request results of the two AXI read requests in sequence. In summary, the DMA in the present disclosure has the ability to transmit in sequence for multiple AXI read requests of the same DMA channel.

In some specific embodiments, the request-related information includes the request ID of the AXI request. When the control circuit clears or reads the request-related information corresponding to the target request ID from the first storage unit corresponding to the target request ID, it is specifically configured to: determine whether the request-related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID; clear or read the request-related information containing the target request ID from the first storage unit corresponding to the target request ID.

Specifically, for the case where the depth of the first storage unit is greater than 1, that is, the first storage unit can store multiple request-related information at the same time, the control circuit uses the target request ID as the query basis to query whether the request-related information first stored in each first storage unit contains the target request ID, and then reads out the request-related information first stored in the first storage unit for the queried first storage unit.

For the case where the depth of the first storage unit is equal to 1, that is, each first storage unit can only store one copy of request-related information at a time, the control circuit uses the target request ID as the query basis to query whether the request-related information stored in each first storage unit contains the target request ID, and then reads out the request-related information stored in the queried first storage unit.

Referring to FIG. 2 , FIG. 2 is a schematic diagram of the structure of a data reading system proposed in another embodiment of the present disclosure. As shown in FIG. 2 , in some specific implementations, the DMA further includes a third FIFO, and the third FIFO is used to store a request ID corresponding to a request result. The control circuit is also used to: for a request result currently being received, after receiving a transmission completion signal last corresponding to the request result, store the request ID corresponding to the request result into the third FIFO.

When the control circuit determines whether the request-related information first stored in each first storage unit contains the target request ID, the control circuit is specifically configured to: read the request ID stored in the table entry currently pointed to by the read pointer of the third FIFO, and update the read pointer of the third FIFO; determine whether the request-related information first stored in each first storage unit contains the request ID.

In the present disclosure, the order in which the request IDs are stored in the third FIFO is consistent with the order in which the corresponding request results are stored in the second FIFO. The request ID first stored in the third FIFO (i.e., the request ID stored in the table entry currently pointed to by the read pointer) is the target request ID. Specifically, the DMA control circuit stores the request result in the second FIFO for each beat received by the DMA control circuit, and stores the request result in the third FIFO after receiving the transmission completion signal last corresponding to the request result.

For ease of understanding, exemplarily, as shown in FIG2 , the first request ID stored in the third FIFO is rid-c; the second is rid-d; the last request ID stored is rid-e. The first request result stored in the second FIFO is the multi-beat request result c, and each request result c occupies a depth of the second FIFO (i.e., an entry of the second FIFO); the second is the multi-beat request result d, and each request result d occupies a depth of the second FIFO; the third is the multi-beat request result e, and each request result e occupies a depth of the second FIFO; the last request result stored is the multi-beat request result f, and each request result f occupies a depth of the second FIFO. Since the DMA control circuit has not yet received the transmission completion signal last corresponding to the request result f, the control circuit has not yet stored the request ID (i.e., rid-f) corresponding to the request result f in the third FIFO.

The current control circuit needs to read the request ID stored in the table entry currently pointed to by the read pointer from the third FIFO (i.e., the first stored request ID (i.e., rid-c)), and then use rid-c as the query basis to determine whether the first stored request related information in each first storage unit contains rid-c. Assuming that the first stored request related information c in the first storage unit-2 contains rid-c, the request related information c containing rid-c is read from the first storage unit-2, and each request result c is read from the second FIFO, and then each request result c is sent to the downstream module of CH2. It should be noted that after rid-c is read out from the third FIFO, according to the inherent characteristics of FIFO first-in first-out, the first stored request ID in the third FIFO becomes rid-d.

In some specific implementations, when receiving each request result, the DMA control circuit stores the request result and the corresponding rid in an entry of the second FIFO. When the request result needs to be read from the second FIFO, the rid in each entry is determined to be consistent with the target request ID in the order in which the request results are stored in the second FIFO. If they are consistent, the request result and rid in the entry are read out.

Alternatively, in some other specific implementations, the request-related information further includes a beat number arlen, and the beat number arlen is used to indicate the beat number of the request result of the corresponding AXI read request. For ease of understanding, illustratively, assuming that the beat number arlen of the AXI read request c is equal to 32, it means that the request result of the AXI read request has a total of 32 beats.

When the control circuit reads the target request result from the second FIFO, it is specifically used to: read out the first stored request results of number arlen from the second FIFO according to the number arlen.

Specifically, the DMA control circuit queries the first request related information stored in each first storage unit according to the target request ID to see whether the target request ID is included, reads the request related information including the target request ID from the queried first storage unit, and then reads the request results with the number of beats arlen from the third FIFO according to the number of beats arlen information included in the request related information. For example, if the number of beats arlen included in the request related information is 32, the first 32 request results stored are read from the third FIFO.

In the present disclosure, by recording the beat number arlen information in the request related information, when reading the request result from the second FIFO, the first stored arlen beat request result can be directly read from the second FIFO according to arlen. In this way, there is no need to store rid in each entry of the second FIFO, so that the bit width of each entry of the second FIFO can be reduced, thereby reducing the area and hardware cost of the second FIFO.

In some specific embodiments, the DMA control circuit reads the first stored request ID (i.e., the target request ID) from the third FIFO, queries the first storage unit storing the target request ID according to the target request ID, reads the request information including the target request ID from the first storage unit, and reads the target request result from the second FIFO, and then, according to the correspondence between the first storage unit and the DMA channel, sends the target request result to the downstream module of the DMA channel corresponding to the first storage unit.

Alternatively, in some other specific implementations, the preset data bits of the request ID of each AXI read request are used to indicate the DMA channel that sends the AXI read request. For ease of understanding, illustratively, assuming that the request ID of each AXI read request is a 4-bit binary number, when the lower two bits arid[1:0] of the request ID are equal to 00, it indicates that the AXI read request comes from channel CH0; when the lower two bits arid[1:0] of the request ID are equal to 01, it indicates that the AXI read request comes from channel CH1; when the lower two bits arid[1:0] of the request ID are equal to 10, it indicates that the AXI read request comes from channel CH2; when the lower two bits arid[1:0] of the request ID are equal to 11, it indicates that the AXI read request comes from channel CH3.

When the control circuit sends the target request result to the downstream module of the corresponding DMA channel, it is specifically used to: according to the preset data bit of the target request ID, send the target request result to the downstream module of the DMA channel represented by the preset data bit.

Specifically, the DMA control circuit reads the first stored request ID (i.e., the target request ID) from the third FIFO, reads the request information including the target request ID from the corresponding first storage unit according to the target request ID, and reads the target request result from the second FIFO, then determines the corresponding DMA channel according to the lower two bits of the target request ID, and then sends the target request result to the downstream module of the DMA channel.

In some specific implementations, as shown in FIG2 , the DMA further includes a fourth FIFO, and the fourth FIFO is used to store request-related information of the AXI read request of each DMA channel. The control circuit is also used to: after receiving the AXI read request sent by any DMA channel, store the request-related information into the fourth FIFO; the request-related information includes the request ID and the beat number arlen of the AXI read request.

When the control circuit stores the request related information into the first storage unit corresponding to the DMA channel, it is specifically used to: read out the request related information first stored in the fourth FIFO, and according to the preset data bits of the request ID contained in the read request related information, store the request related information into the first storage unit corresponding to the DMA channel represented by the preset data bits.

Specifically, on the one hand, when the DMA control circuit receives an AXI read request, it reads out the request related information of the AXI read request and stores the request related information in the fourth FIFO. On the other hand, the DMA control circuit reads out the request related information first stored in the fourth FIFO, and determines the DMA channel from which the corresponding AXI read request comes according to the preset data bits (such as arid[1:0]) of the request ID in the read request related information, thereby storing the read request related information in the first storage unit corresponding to the DMA channel.

In some specific embodiments, as shown in FIG3 , the data reading system includes a DMA, and the DMA includes four first storage units, namely, first storage unit-0, first storage unit-1, first storage unit-2, and first storage unit-3, each of which has a depth of 1 and a bit width of 15. The lower four bits of each first storage unit are used to store arid, and the remaining bits are used to store arlen. The DMA channels corresponding to the four first storage units are CH0, CH1, CH2, and CH3, respectively.

DMA also includes the second FIFO, the third FIFO and the fourth FIFO. The bit width of the second FIFO is equal to 256, which is equal to the bit width of each request result in the AXI bus protocol. The depth of the second FIFO should be deep enough to store at least the request results of the AXI read requests of the four DMA channels at the same time.

The bit width of the third FIFO is equal to 3, and the depth is equal to 4. The lower two bits of each entry of the third FIFO are used to store the lower two bits of rid (i.e., rid[1:0]), and the highest bit of each entry is used to indicate whether the entry stores rid[1:0]. If rid[1:0] is stored, the highest bit of the entry is set to 1, otherwise the highest bit of the entry is set to 0. Only when the highest bit of the entry is set to 1, the DMA control circuit will read rid from the entry. In this embodiment, by using the highest bit of each entry to indicate whether each entry stores rid, the control circuit can be prevented from being confused by the two situations where rid is equal to 00 and the entry is empty. For example, if an entry in the third FIFO is 100, it means that rid equal to 00 has been filled into the entry. For example, if an entry in the FIFO is 000, it means that the entry is empty.

The bit width of the fourth FIFO is 16 and the depth is 4. The lower four bits of each entry of the fourth FIFO are used to store arid, the highest bit of each entry is used to indicate whether the entry stores request related information, and the remaining bits of each entry are used to store arlen. Only when the highest bit of the entry is set to 1, the DMA control circuit will read the request related information, that is, arlen and arid, from the entry.

In addition, the DMA also includes a control circuit. FIG3 shows only a part of the control circuit. Specifically, the connecting lines between the FIFOs in FIG3, i.e., the arrows, can be understood as the control circuit. The control circuit has the following functions:

1. After receiving an AXI read request sent by any DMA channel, the control circuit, on the one hand, reads arlen and arid from the AXI read request, stores arlen and arid into an entry of the fourth FIFO, and sets the highest bit of the entry to 1; on the other hand, sends the AXI read request to the slave;

2. The control circuit reads the first stored arlen and arid from the fourth FIFO, sets the highest position of the entry where the arlen and arid are located to 0, and stores the arlen and arid into the corresponding first storage unit according to the lower two bits of the arid, arid[1:0];

3. The control circuit receives each request result and the related information corresponding to the request result returned by the slave, and stores each request result received into an entry of the second FIFO; the related information corresponding to each request result includes rid. If the related information corresponding to a request result also includes last information, the lower two bits rid[1:0] of rid in the related information are stored into an entry of the third FIFO, and the highest bit of the entry is set to 1;

4. The control circuit reads the rid[1:0] stored first from the third FIFO, and sets the highest position of the entry where the rid[1:0] is located to 0, and then uses the rid[1:0] as a query basis to query whether the lower two bits of each first storage unit are equal to rid[1:0]. If the lower two bits of a first storage unit are equal to rid[1:0], arlen and arid are read from the first storage unit, and based on the read arlen, the request result stored first by arlen is read from the second FIFO, and then the read request result is sent to the downstream module of the DMA channel corresponding to the first storage unit.

The disclosed embodiment also provides an electronic component, which includes the data reading system described in any of the above embodiments. In some usage scenarios, the product form of the electronic component is a graphics card; in other usage scenarios, the product form of the electronic component is a CPU motherboard.

The disclosed embodiments also provide an electronic device, which includes the above-mentioned electronic components. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, a workstation, a server, etc.

The disclosed embodiment also provides a data reading method. The data reading method and the aforementioned data reading system are based on the same inventive concept. To avoid repetition, the data reading method is only briefly introduced below, and the relevant parts may refer to the aforementioned data reading system.

Referring to FIG4 , FIG4 is a flow chart of a data reading method provided by an embodiment of the present disclosure. As shown in FIG4 , the data reading method includes the following steps:

S410: after receiving an AXI read request sent by any DMA channel, storing request related information in a first storage unit corresponding to the DMA channel, the request related information is used to indicate that the AXI read request has not been processed, and the AXI read requests sent by different DMA channels have different request IDs;

S420: Send the AXI read request to the slave;

S430: storing the request result returned by the slave into the second FIFO;

S440: According to the target request ID of the target request result, clear or read the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID, read the target request result from the second FIFO, and send the target request result to the downstream module of the corresponding DMA channel; wherein, the target request result is the earliest request result received by DMA among the unread request results.

It should be noted that the present disclosure does not limit the execution order of the above steps S410 to S440.

In some specific implementations, the request related information includes a request ID of the AXI request, and clearing or reading the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID includes:

Determine whether the request related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID;

The request related information including the target request ID is cleared or read from the first storage unit corresponding to the target request ID.

In some specific implementations, determining whether the request related information first stored in each first storage unit includes the target request ID includes:

Read the request ID stored in the table entry currently pointed to by the read pointer of the third FIFO, and update the read pointer of the third FIFO; determine whether the request related information first stored in each first storage unit contains the request ID; wherein the third FIFO is used to store the request ID corresponding to the request result.

In some embodiments, the method further comprises:

For the request result currently being received, after receiving the transmission completion signal last corresponding to the request result, the request ID corresponding to the request result is stored in the third FIFO.

In some specific implementations, the request related information also includes the beat number arlen, and the target request result is read from the second FIFO, including:

According to the beat number arlen, the first stored request results of the beat number arlen are read out from the second FIFO.

In some specific implementations, a preset data bit of the request ID of each AXI read request is used to indicate a DMA channel that sends the AXI read request.

In some specific implementations, sending the target request result to a downstream module of the corresponding DMA channel includes:

According to the preset data bit of the target request ID, the target request result is sent to the downstream module of the DMA channel represented by the preset data bit.

In some specific implementations, storing request related information of the AXI read request in a first storage unit corresponding to the DMA channel includes:

Read out the request related information first stored in the fourth FIFO; wherein the fourth FIFO is used to store the request related information of the AXI read request of each DMA channel;

According to the preset data bit of the request ID included in the read request related information, the request related information is stored in a first storage unit corresponding to the DMA channel represented by the preset data bit.

In some specific implementations, the depth of each first storage unit is equal to 1.

Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims (16)

1. A data reading system, the system comprising a DMA, the DMA comprising: a plurality of first storage units, a second FIFO and a control circuit; The control circuit is configured to, after receiving an AXI read request sent by any DMA channel, store request related information in the first storage unit corresponding to the DMA channel, wherein the request related information is used to indicate that the AXI read request has not been processed, and the AXI read requests sent by different DMA channels have different request IDs, and the preset data bit of the request ID of each AXI read request is used to indicate the DMA channel that sent the AXI read request; send the AXI read request to the slave; and store the request result returned by the slave in the second FIFO; The control circuit is also configured to, according to the target request ID of the target request result, clear or read out the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID, and read out the target request result from the second FIFO, and according to the preset data bit of the target request ID, send the target request result to the downstream module of the DMA channel represented by the preset data bit; wherein the target request result is the earliest received request result among the unread request results; the downstream module of the corresponding DMA channel refers to: a module that has a use demand for the request result of the DMA channel. 2. The system according to claim 1, wherein the request related information includes a request ID of the AXI request, and when the control circuit clears or reads the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID, the control circuit is specifically configured as follows: Determine whether the request related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID; The request related information including the target request ID is cleared or read out from the first storage unit corresponding to the target request ID. 3. The system according to claim 2, wherein the DMA further comprises a third FIFO, wherein the third FIFO is used to store a request ID corresponding to the request result; when the control circuit determines whether the request related information first stored in each first storage unit contains the target request ID, the control circuit is specifically configured as follows: The request ID stored in the entry currently pointed to by the read pointer of the third FIFO is read, and the read pointer of the third FIFO is updated; and it is determined whether the request related information first stored in each first storage unit includes the request ID. 4. The system according to claim 3, wherein the control circuit is further configured to: For the request result currently being received, after receiving the transmission completion signal last corresponding to the request result, the request ID corresponding to the request result is stored in the third FIFO. 5. The system according to claim 2, wherein the request related information further includes a beat number arlen, and when the control circuit reads the target request result from the second FIFO, the control circuit is specifically configured as follows: According to the beat number arlen, the first stored request results of the beat number arlen are read out from the second FIFO. 6. The system according to claim 1, wherein the DMA further comprises a fourth FIFO, wherein the fourth FIFO is used to store request related information of the AXI read request of each DMA channel; the control circuit is further used to: after receiving the AXI read request sent by any DMA channel, store the request related information into the fourth FIFO; the request related information comprises the request ID and the beat number arlen of the AXI read request; When the control circuit stores the request related information into the first storage unit corresponding to the DMA channel, the control circuit is specifically configured as follows: The request related information first stored in the fourth FIFO is read out, and according to the preset data bit of the request ID contained in the read request related information, the request related information is stored in the first storage unit corresponding to the DMA channel represented by the preset data bit. 7. The system according to any one of claims 1 to 6, wherein the depth of each first storage unit is equal to 1. 8. An electronic assembly comprising the system according to any one of claims 1 to 7. 9. An electronic device comprising the electronic component according to claim 8. 10. A data reading method, the method comprising: After receiving an AXI read request sent by any DMA channel, storing request related information in a first storage unit corresponding to the DMA channel, wherein the request related information is used to indicate that the AXI read request has not been processed, and AXI read requests sent by different DMA channels have different request IDs, and a preset data bit of the request ID of each AXI read request is used to indicate the DMA channel that sent the AXI read request; Sending the AXI read request to the slave; Store the request result returned by the slave into the second FIFO; According to the target request ID of the target request result, the request related information corresponding to the target request ID is cleared or read from the first storage unit corresponding to the target request ID, and the target request result is read from the second FIFO, and according to the preset data bit of the target request ID, the target request result is sent to the downstream module of the DMA channel represented by the preset data bit; wherein the target request result is the earliest request result received by the DMA among the unread request results; the downstream module of the corresponding DMA channel refers to: a module that has a use demand for the request result of the DMA channel. 11. The method according to claim 10, wherein the request related information includes a request ID of the AXI request, and the clearing or reading out the request related information corresponding to the target request ID from the first storage unit corresponding to the target request ID comprises: Determine whether the request related information first stored in each first storage unit contains the target request ID, thereby querying the first storage unit corresponding to the target request ID; The request related information including the target request ID is cleared or read out from the first storage unit corresponding to the target request ID. 12. The method according to claim 11, wherein determining whether the request related information first stored in each first storage unit contains the target request ID comprises: Read the request ID stored in the table entry currently pointed to by the read pointer of the third FIFO, and update the read pointer of the third FIFO; determine whether the request related information first stored in each first storage unit contains the request ID; wherein the third FIFO is used to store the request ID corresponding to the request result. 13. The method according to claim 12, further comprising: For the request result currently being received, after receiving the transmission completion signal last corresponding to the request result, the request ID corresponding to the request result is stored in the third FIFO. 14. The method according to claim 11, wherein the request related information further includes a beat number arlen, and the step of reading the target request result from the second FIFO comprises: According to the beat number arlen, the first stored request results of the beat number arlen are read out from the second FIFO. 15. The method according to claim 10, wherein storing the request related information of the AXI read request into the first storage unit corresponding to the DMA channel comprises: Read out the request related information first stored in the fourth FIFO; wherein the fourth FIFO is used to store the request related information of the AXI read request of each DMA channel; According to the preset data bit of the request ID included in the read request related information, the request related information is stored in a first storage unit corresponding to the DMA channel represented by the preset data bit. 16 . The method according to claim 10 , wherein the depth of each first storage unit is equal to 1.