CN117895449B - Low-clamp voltage type bidirectional electrostatic protection circuit and bidirectional electrostatic protection device - Google Patents
Low-clamp voltage type bidirectional electrostatic protection circuit and bidirectional electrostatic protection device Download PDFInfo
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 131
- 230000003068 static effect Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 5
- 235000012773 waffles Nutrition 0.000 claims description 4
- 238000006880 cross-coupling reaction Methods 0.000 claims description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000740 bleeding effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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Abstract
The invention provides a low-clamp voltage type bidirectional static protection circuit and a bidirectional static protection device. On the premise of maintaining the layout area of the chip, the on-resistance and clamping voltage of the electrostatic protection network are obviously reduced, and the electrostatic tolerance level of the chip is effectively improved.
Description
Technical Field
The invention relates to an electrostatic protection circuit, in particular to a low-clamping voltage type bidirectional electrostatic protection circuit, and also relates to a bidirectional electrostatic protection device for realizing the low-clamping voltage type bidirectional electrostatic protection circuit.
Background
Electrostatic discharge (Electrostatic Discharge, ESD) refers to the phenomenon of rapid transfer of charge between objects through conductive channels, which can have a significant impact on the reliability of integrated circuit products. Integrated circuit (INTEGRATED CIRCUIT, IC) products may accumulate electrical charge internally during production, packaging, testing, shipping, assembly, use, and the like. The increasing specific gravity of chip failure caused by ESD problems has become one of the major reliability problems for IC products. As semiconductor processing is scaled down, the failure voltage of the transistor is reduced, which results in a scaled design window for electrostatic protection of the integrated circuit chip. At this time, the electrostatic protection energy level of the ESD protection network is increasingly limited by its parasitic resistance. Therefore, constructing an ESD protection architecture with low on-resistance and low clamp voltage is not trivial.
The diode string is a very simple and efficient ESD protection device, and is widely used in ESD protection engineering of various chip ports. In advanced low voltage ports, diode strings may be used directly for local ESD protection between an Input/Output (I/O) port and ground. For silicon process diodes, typically one diode may contribute a blocking voltage of about 0.3-0.4 v for low power consumption. Thus, for a typical 0.8V/1V/1.2V low voltage I/O port, the number of diodes in series (n) is typically 3; whereas for a 1.8V I/O port the number of diodes in series typically needs to be increased to 6.
In practical application, a designer can meet the working voltage of the I/O port by adjusting the serial number of the diode strings, and meanwhile, lower leakage current can be realized. For some I/O ports that have bi-directional voltage swings (i.e., I/O signals have both positive and negative voltages), the same number of diodes in opposite directions need to be placed in the I/O-GND and GND-I/O directions. As shown in fig. 1, a typical design scheme is that two diode strings with opposite directions are respectively arranged in the I/O-GND direction and the GND-I/O direction, and 3 diodes are connected in series on each diode string, so that bidirectional electrostatic discharge between I/o→gnd and gnd→i/O is realized. The number of diode strings used is also different according to the different operating voltages of the chip ports. However, as the number of diode strings increases, the on-resistance of the diode strings also increases proportionally, so that the clamp voltage thereof is significantly deteriorated, which generally drastically reduces the final static withstand level of the chip. At this point, the degradation of on-resistance can naturally be mitigated by properly increasing the device size, but this in turn sacrifices a significant amount of chip area, which is intolerable for advanced integrated circuit processes that are on-die.
Disclosure of Invention
In order to solve the problems that the on-resistance is required to be relieved by increasing the size of a device and a large amount of chip area is sacrificed in the prior art, the invention provides the low-clamp voltage type bidirectional electrostatic protection circuit and the bidirectional electrostatic protection device for realizing the low-clamp voltage type bidirectional electrostatic protection circuit, which can obviously reduce the on-resistance and the clamp voltage of an electrostatic protection network under the original layout area and effectively improve the electrostatic tolerance level of the chip.
The invention discloses a low-clamping voltage type bidirectional static protection circuit which is arranged between a first port and a second port and comprises a PNP bidirectional triode, an NPN bidirectional triode and a plurality of static protection elements, wherein one P pin of the PNP bidirectional triode and one N pin of the NPN bidirectional triode are respectively connected with the first port, the other P pin of the PNP bidirectional triode and the other N pin of the NPN bidirectional triode are respectively connected with the second port, and after the plurality of static protection elements are connected in series, one end of each static protection element is connected with the N pin of the PNP bidirectional triode, and the other end of each static protection element is connected with the P pin of the NPN bidirectional triode.
And three electrostatic discharge passages are formed between the first port and the second port, and are respectively a PNP passage flowing through the PNP bidirectional triode, an NPN passage flowing through the NPN bidirectional triode, and a third passage flowing through the PNP bidirectional triode, the NPN bidirectional triode and a plurality of electrostatic protection elements.
Further, the PNP bidirectional triode and the NPN bidirectional triode are cross-coupled, wherein an N pin of the PNP bidirectional triode is connected to an emitter of the NPN bidirectional triode, and a P pin of the NPN bidirectional triode is connected to the emitter of the PNP bidirectional triode.
Further, the electrostatic protection element includes a diode, a metal-oxide-semiconductor field effect transistor, a bipolar junction transistor, or a zener diode.
Further, the combination of the first port and the second port includes an I/O port-ground port, a power port-I/O port, a power port-ground port, an I/O port-I/O port.
The invention also provides a bidirectional electrostatic protection device provided with the low clamping voltage type bidirectional electrostatic protection circuit, which comprises a substrate and a plurality of well regions arranged on the substrate, wherein the number of the well regions is consistent with the total number of PNP bidirectional triode, NPN bidirectional triode and electrostatic protection elements, and the PNP bidirectional triode, NPN bidirectional triode and electrostatic protection elements are respectively arranged in the corresponding well regions.
Further, the substrate is a P-type substrate, a first N well, a plurality of second N wells and a first P well are arranged on the P-type substrate, wherein the PNP bidirectional triode is arranged in the first N well, the NPN bidirectional triode is arranged in the first P well, and a plurality of static protection elements are respectively arranged in the second N wells in a one-to-one correspondence manner.
Further, two P active regions and one N active region are disposed on the first N well, two N active regions and one P active region are disposed in the first P well respectively, the second N well includes one N active region and one P active region respectively, after the N active regions and the P active regions in the plurality of second N wells are connected in series one by one respectively, the N active regions at the end are connected with the P active regions of the first P well, and the P active regions at the end are connected with the N active regions of the first N well.
As an improvement of the invention, the first N well and the first P well are arranged in parallel, two P active areas in the first N well are respectively a first P active area and a second P active area, wherein the second P active area is arranged close to the first P well, two N active areas in the first N well are respectively a first N active area and a second N active area, wherein the first N active area is arranged close to the first N well, the first P active area and the first N active area are respectively connected with a first port, and the second P active area and the second N active area are respectively connected with a second port.
As another improvement of the present invention, the first N-well and the first P-well are arranged in parallel, two P-active regions in the first N-well are a first P-active region and a second P-active region, respectively, wherein the second P-active region is arranged close to the first P-well, two N-active regions in the first N-well are a first N-active region and a second N-active region, respectively, wherein the first N-active region is arranged close to the first N-well, the first P-active region and the second N-active region are connected with the first port, respectively, and the second P-active region and the first N-active region are connected with the second port, respectively.
Further, the layout shape of the low clamping voltage type bidirectional electrostatic protection device comprises a strip layout, a ring layout or a waffle layout.
Compared with the prior art, the invention has the beneficial effects that: the invention is based on the improvement of the traditional diode string type electrostatic protection circuit and is used for realizing the bidirectional electrostatic discharge between two ports. According to the invention, through optimizing the circuit topology structure and layout, on the premise of maintaining the layout area of the chip and the current discharge capacity of the intrinsic bidirectional diode string unchanged, two bipolar junction transistors (bipolar junction transistor, BJT for short) can be additionally parasitic, namely NPN and PNP transistors, and the parasitic elements can obviously reduce the on-resistance and clamp voltage of the electrostatic protection network by increasing the number of discharge channels of ESD current under the original layout area, so that the electrostatic tolerance level of the chip is effectively improved.
Through adjusting the connection mode of NPN and PNP pipes and two ports, a Silicon-Controlled Rectifier (SCR) can be additionally generated, and then an SCR discharging passage is additionally increased, so that the on-resistance and the clamping voltage of the electrostatic protection network are further greatly reduced.
Drawings
In order to more clearly illustrate the invention or the solutions of the prior art, a brief description will be given below of the drawings used in the description of the embodiments or the prior art, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a circuit equivalent diagram of a prior art bi-directional electrostatic protection scheme;
Fig. 2 (a) is an equivalent circuit diagram of a low clamp voltage type bidirectional electrostatic protection circuit and a schematic diagram of an I/o→gnd electrostatic discharge path according to a first embodiment of the present invention;
Fig. 2 (b) is a circuit equivalent diagram of a low clamp voltage type bidirectional electrostatic protection circuit according to a first embodiment of the present invention, and a schematic diagram of a gnd→i/O electrostatic discharge path;
Fig. 2 (c) is a schematic structural diagram of an embodiment of a bidirectional electrostatic protection device according to the first embodiment of the present invention;
FIG. 2 (d) is a cross-sectional view A-A of FIG. 2 (c);
Fig. 3 (a) is an equivalent circuit diagram of a low clamp voltage type bidirectional electrostatic protection circuit and a schematic diagram of an I/o→gnd electrostatic discharge path according to a second embodiment of the present invention;
Fig. 3 (b) is a circuit equivalent diagram of a low clamp voltage type bidirectional electrostatic protection circuit and a schematic diagram of a gnd→i/O electrostatic discharge path according to a second embodiment of the present invention;
Fig. 3 (c) is a schematic structural diagram of an embodiment of a bidirectional electrostatic protection device according to a second embodiment of the present invention;
Fig. 4 (a) is a circuit equivalent diagram of a low clamp voltage type bidirectional electrostatic protection circuit and a schematic diagram of an I/o→gnd electrostatic discharge path according to a third embodiment of the present invention;
Fig. 4 (b) is a circuit equivalent diagram of a low clamp voltage type bidirectional electrostatic protection circuit according to a third embodiment of the present invention, and a schematic diagram of a gnd→i/O electrostatic discharge path;
Fig. 4 (c) is a schematic structural diagram of an embodiment of a bidirectional electrostatic protection device according to a third embodiment of the present invention;
FIG. 4 (d) is a cross-sectional view A-A of FIG. 4 (c) and a schematic diagram of the I/O→GND electrostatic bleed path;
FIG. 4 (e) is a schematic diagram of the section A-A and GND→I/O electrostatic discharge path of FIG. 4 (c).
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention; the terms "comprising" and "having" and any variations thereof in the description of the invention and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the described embodiments of the invention may be combined with other embodiments.
In order to enable those skilled in the art to better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
As shown in fig. 2 (a) -2 (d), fig. 3 (a) -3 (c) and fig. 4 (a) -4 (e), the invention is improved based on a traditional diode string type electrostatic protection circuit and is used for realizing bidirectional electrostatic discharge between I/o→gnd and gnd→i/O. The invention discloses a low-clamping voltage type bidirectional static protection circuit which is arranged between a first port and a second port and comprises a PNP bidirectional triode, an NPN bidirectional triode and a plurality of static protection elements, wherein one P pin of the PNP bidirectional triode and one N pin of the NPN bidirectional triode are respectively connected with the first port, the other P pin of the PNP bidirectional triode and the other N pin of the NPN bidirectional triode are respectively connected with the second port, and after the plurality of static protection elements are connected in series, one end of each static protection element is connected with the N pin of the PNP bidirectional triode, and the other end of each static protection element is connected with the P pin of the NPN bidirectional triode.
At least three static discharge paths are formed between the first port and the second port, and each static discharge path comprises a PNP path flowing through a PNP bidirectional triode, an NPN path flowing through an NPN bidirectional triode, and a third path flowing through the PNP bidirectional triode, the NPN bidirectional triode and a plurality of static protection elements.
The topology of the electrostatic protection device is not only suitable for the serial connection structure of diodes, but also suitable for the serial connection structure of other Semiconductor devices, such as the serial connection structure of Metal-Oxide-Semiconductor field effect transistors (MOSFETs), the serial connection structure of bipolar junction transistors (bipolar junction Transistor, BJTs), the serial connection structure of zener diodes, etc. The following description will take a diode as an example.
As shown in fig. 2 (a) and 2 (b), as a first embodiment of the present invention, the present embodiment applies bidirectional electrostatic protection between an I/O port and a GND port. The invention is provided with a PNP bidirectional triode, an NPN bidirectional triode and a diode, wherein the diode is connected in series between the bases of the PNP bidirectional triode and the NPN bidirectional triode. Compared with the technical scheme shown in fig. 1 (three diodes are connected in series to form a discharging path from I/O to GND; three other diodes are connected in series to form a discharging path from GND to I/O), the bidirectional electrostatic protection circuit is formed by 6 diodes, in the first embodiment of the present invention, the bidirectional electrostatic discharging function can be realized by only 5 diodes, and three bidirectional electrostatic discharging paths from I/O ↔ GND are provided: PNP via, NPN via, and intrinsic bidirectional DIODE string via (DIODE via).
The optimization idea of the embodiment is as follows: on the bidirectional bleeding path of the I/O ↔ GND, the number of diodes is reduced by using 1 common diode, and the layout area is saved. Meanwhile, the number of discharge channels of ESD current is increased by hosting PNP paths and NPN paths, the on-resistance and clamping voltage of the electrostatic protection network are reduced, and the purpose of bidirectional electrostatic protection of I/O ↔ GND is achieved.
Of course, the present invention is not limited to application to bidirectional electrostatic protection between an I/O port and a ground port (GND), but may also be applied to other port combinations, such as a power port-I/O port, a power port-ground port, an I/O port-I/O port, and so forth.
The working principle of the embodiment is as follows:
Taking fig. 2 (a) as an example, the DIODE channel is taken as an intrinsic DIODE string channel, and when the applied electrostatic voltage exceeds the sum of the turn-on voltages of all the series DIODEs, the DIODE string channel is turned on to start discharging electrostatic charges. Meanwhile, since the first diode in the diode string is also the emitter of the parasitic PNP transistor, the last diode is also the emitter of the parasitic NPN transistor. Therefore, when the DIODE channel is turned on, the emitters of the two triodes are synchronously turned on, which further promotes the two triodes to trigger and turn on to participate in the static charge discharging operation. Thus, the intrinsic diode string path, the parasitic PNP path and the parasitic NPN path simultaneously discharge ESD charges, and compared with the existing diode string protection network, the equivalent resistance of a current channel can be obviously reduced, so that the voltage clamping capability is improved, and the static tolerance level of a chip is improved.
As shown in fig. 2 (c), in order to implement the I/O ↔ GND low-clamp voltage type bidirectional electrostatic protection circuit according to the first embodiment of the present invention, the present invention proposes a bidirectional electrostatic protection device, which includes a substrate, three well regions disposed on the substrate, and the PNP bidirectional triode, NPN bidirectional triode and diode are respectively disposed in the corresponding well regions.
The substrate of this example is the P type substrate, be equipped with first N well, second N well and first P well on the P type substrate, wherein, PNP bidirectional triode sets up in first N well, NPN bidirectional triode sets up in first P well, the diode sets up in the second N well.
The first N well is provided with two P active areas and one N active area, the first P well is respectively provided with two N active areas and one P active area, the second N well respectively comprises one N active area and one P active area, the N active area in the second N well is connected with the P active area of the first P well, and the P active area in the second N well is connected with the N active area of the first N well.
The first N well and the first P well are arranged in parallel, two P active areas in the first N well are respectively a first P active area and a second P active area, wherein the second P active area is close to the first P well, two N active areas in the first N well are respectively a first N active area and a second N active area, the first N active area is close to the first N well, the first P active area and the first N active area are respectively connected with an I/O port, and the second P active area and the second N active area are respectively connected with a GND port.
Of course, this example may also employ an N-type substrate, and three well regions are respectively disposed on the N-type substrate.
The layout of the embodiment is a classical strip-shaped layout, namely, the shape of each heavily doped active region is strip-shaped and is distributed in the well region to which each heavily doped active region belongs in parallel, the strip-shaped layout has the advantages of simple design, the structural cross section of the strip-shaped layout is shown as a figure 2 (d), and a figure 2 (d) shows PNP paths and NPN paths parasitic by I/O ↔ GND. The design scheme of the embodiment has the advantages that the number of the discharging channels of ESD current can be increased by the parasitic PNP channel and NPN channel, and the on-resistance and the clamping voltage of the electrostatic protection network are reduced.
The layout of the invention is not only suitable for strip layout, but also suitable for common layout shapes such as annular layout, waffle layout and the like.
The invention is suitable for various common integrated circuit manufacturing processes, such as a nanoscale complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, a three-dimensional fin field effect transistor (FinField-EffectTransistor, finFET) and a full-surrounding Gate transistor (Gate-All-Around FET, GAA) process, a Silicon-On-Insulator (SOI) process On an insulating substrate, and the like.
As shown in fig. 3 (a) and 3 (b), as a second embodiment of the present invention, the number of diodes is further optimized on the basis of the first embodiment, and the optimization concept of this embodiment is as follows: on the bidirectional discharging path of the I/O ↔ GND, the total diode use number is reduced by using n-2 common diodes, meanwhile, the discharging channel number of ESD current is increased by hosting a PNP path and an NPN path, under the condition of reducing the on-resistance and the clamping voltage of an electrostatic protection network, compact layout can be realized, the layout area is greatly saved, and meanwhile, the bidirectional electrostatic protection purpose of the I/O ↔ GND is achieved. Compared with the traditional scheme, the placement of 2n diodes is needed, and the design scheme of the embodiment can realize the bidirectional electrostatic protection of the I/O ↔ GND by using n+2 diodes, and further obtain a more excellent voltage clamping effect and a higher chip electrostatic tolerance level.
As shown in fig. 3 (c), in order to implement the I/O ↔ GND low-clamp voltage type bidirectional electrostatic protection circuit according to the second embodiment of the present invention, the bidirectional electrostatic protection device of the present invention includes a substrate, n well regions disposed on the substrate, and the PNP bidirectional triode, NPN bidirectional triode and n-2 diodes are respectively disposed in the corresponding well regions in one-to-one correspondence.
The substrate of this example is the P type substrate, be equipped with first N well, N-2 second N wells and first P well on the P type substrate, wherein, PNP triac sets up in first N well, NPN triac sets up in first P well, and N-2 diodes set up respectively in N-2 second N wells.
The first N well is provided with two P active areas and one N active area, the first P well is respectively provided with two N active areas and one P active area, the second N well respectively comprises one N active area and one P active area, the N active areas and the P active areas in the N-2 second N wells are respectively connected in series one by one, the N active areas at the end are connected with the P active areas of the first P well, and the P active areas at the end are connected with the N active areas of the first N well.
The first N well and the first P well are arranged in parallel, two P active areas in the first N well are respectively a first P active area and a second P active area, wherein the second P active area is close to the first P well, two N active areas in the first N well are respectively a first N active area and a second N active area, the first N active area is close to the first N well, the first P active area and the first N active area are respectively connected with an I/O port, and the second P active area and the second N active area are respectively connected with a GND port.
The layout of this example is a classical "stripe" layout, i.e. each heavily doped active region has a shape of "stripe", and is distributed in parallel in the well region to which each heavily doped active region belongs, and the advantage of the "stripe" layout is that the design is simple, and its structural cross-sectional view is identical to that of fig. 2 (d). The design scheme of the embodiment has the advantages that the number of the discharging channels of ESD current can be increased by the parasitic PNP channel and NPN channel, and the on-resistance and the clamping voltage of the electrostatic protection network are reduced.
The layout of the invention is not only suitable for strip layout, but also suitable for common layout shapes such as annular layout, waffle layout and the like.
The invention is suitable for various common integrated circuit manufacturing processes, such as a nanoscale complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process, a three-dimensional fin field effect transistor (FinField-EffectTransistor, finFET) and a full-surrounding Gate transistor (Gate-All-Around FET, GAA) process, a Silicon-On-Insulator (SOI) process On an insulating substrate, and the like.
The layout schematic diagram of the low-clamp voltage type bidirectional electrostatic protection circuit provided by the embodiment 2 of the invention.
As shown in fig. 4 (a) and 4 (b), as a third embodiment of the present invention, the present example can realize the bidirectional electrostatic discharge function by using only n+2 diodes, and has four paths from the I/O ↔ GND: PNP via, NPN via, intrinsic bidirectional diode string via, and parasitic SCR via.
On the basis of the first embodiment, the invention further optimizes the layout to couple four layers of P-N-P-N current channels, namely SCR paths (pink paths), between the first N WELL (also known as N-WELL) and the first P WELL (also known as P-WELL) where the parasitic PNP and NPN are respectively located. The SCR path is formed by cross coupling of a PNP bidirectional triode and an NPN bidirectional triode, and the emitter junction of the SCR path corresponds to the first diode and the last diode in the intrinsic diode string path respectively.
In summary, when the intrinsic diode string is conducted, not only the parasitic PNP and parasitic NPN paths are conducted and opened, but also the SCR paths are conducted and opened, and the parasitic PNP and parasitic NPN paths participate in the static charge discharging work together. Because of the strong current conduction efficiency of the SCR device, the embodiment is expected to greatly optimize the voltage clamping capability and greatly improve the ESD protection level of the chip.
As shown in fig. 4 (c) -4 (e), the bidirectional electrostatic protection device of the present embodiment has the same structure as the second embodiment, but is different from the connection of ports in that: the first P active region and the second N active region are respectively connected with the I/O port, and the second P active region and the first N active region are respectively connected with the GND port.
Through optimizing the mode of connection, between I/O ↔ GND, in addition to parasitic PNP route, NPN route, DIODE string formed DIODE route, also formed PNPN route through SCR (Silicon-Controlled-Rectifier) route. The design scheme of the embodiment has the advantages that PNPN channels formed by the parasitic PNP channels, NPN channels and SCR channels can increase the number of discharge channels of ESD current, and further greatly reduce the on-resistance and clamping voltage of the electrostatic protection network.
Of course, the first embodiment of the present invention may also adopt the coupling mode of the present embodiment to additionally form the SCR path.
According to the embodiment, compared with the existing diode string design scheme, the low-clamping voltage type bidirectional electrostatic protection circuit can additionally generate two bipolar junction transistors (bipolar junction transistor, BJT for short), namely NPN and PNP transistors and a silicon controlled rectifier on the premise of maintaining the current discharging capability of the chip layout area and the intrinsic bidirectional diode string unchanged by optimizing the circuit topology structure and layout. The parasitic elements can obviously reduce the on-resistance and the clamping voltage of the electrostatic protection network by increasing the number of discharge channels of ESD current under the original layout area, and effectively improve the electrostatic tolerance level of the chip.
The invention is especially suitable for chip protection application on advanced integrated circuit process platform, and provides a good electrostatic protection solution for high electrostatic/surge robustness and small-size requirement of products.
The above embodiments are preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, which includes but is not limited to the embodiments, and equivalent modifications according to the present invention are within the scope of the present invention.
Claims (10)
1. The utility model provides a two-way static protection circuit of low clamp voltage type, sets up between first port and second port, its characterized in that: comprises a PNP bidirectional triode, an NPN bidirectional triode and a plurality of static protection elements, wherein one P pin of the PNP bidirectional triode and one N pin of the NPN bidirectional triode are respectively connected with a first port, the other P pin of the PNP bidirectional triode and the other N pin of the NPN bidirectional triode are respectively connected with a second port, one end of the static protection elements are connected with the N pin of the PNP bidirectional triode after being connected in series, the other end of the static protection elements are connected with the P pin of the NPN bidirectional triode,
And three bidirectional static discharge passages are formed between the first port and the second port, and are respectively a PNP passage flowing through the PNP bidirectional triode, an NPN passage flowing through the NPN bidirectional triode, and a third passage flowing through the PNP bidirectional triode, the NPN bidirectional triode and a plurality of static protection elements.
2. The low clamp voltage type bidirectional electrostatic protection circuit of claim 1, wherein: the PNP bidirectional triode and the NPN bidirectional triode are in cross coupling, wherein an N pin of the PNP bidirectional triode is connected with an emitter of the NPN bidirectional triode, and a P pin of the NPN bidirectional triode is connected with the emitter of the PNP bidirectional triode.
3. The low clamp voltage type bidirectional electrostatic protection circuit according to claim 1 or 2, wherein: the electrostatic protection element comprises a diode, a metal-oxide-semiconductor field effect transistor or a bipolar junction transistor.
4. The low clamp voltage type bidirectional electrostatic protection circuit of claim 1, wherein: the combination of the first port and the second port includes an I/O port-ground port, a power port-I/O port, a power port-ground port, or an I/O port-I/O port.
5. A bidirectional electrostatic protection device for implementing the low clamping voltage type bidirectional electrostatic protection circuit of any one of claims 1-4, characterized in that: the PNP bidirectional triode trigger comprises a substrate and a plurality of trap areas arranged on the substrate, wherein the number of the trap areas is consistent with the total number of the PNP bidirectional triode trigger, the NPN bidirectional triode trigger and the static protection element, and the PNP bidirectional triode trigger, the NPN bidirectional triode trigger and the static protection element are respectively arranged in the corresponding trap areas.
6. The bi-directional electrostatic protection device of claim 5, wherein: the substrate is a P-type substrate, a first N well, a plurality of second N wells and a first P well are arranged on the P-type substrate, wherein the PNP bidirectional triode is arranged in the first N well, the NPN bidirectional triode is arranged in the first P well, and a plurality of static protection elements are respectively arranged in the second N wells in a one-to-one correspondence manner.
7. The bi-directional electrostatic protection device of claim 6, wherein: the first N well is provided with two P active areas and one N active area, the first P well is respectively provided with two N active areas and one P active area, the second N well respectively comprises one N active area and one P active area, the N active areas and the P active areas in the second N wells are respectively connected in series one by one, the N active areas at the end parts are connected with the P active areas of the first P well, and the P active areas at the end parts are connected with the N active areas of the first N well.
8. The bi-directional electrostatic protection device of claim 7, wherein: the first N well and the first P well are arranged in parallel, two P active areas in the first N well are respectively a first P active area and a second P active area, wherein the second P active area is close to the first P well, two N active areas in the first N well are respectively a first N active area and a second N active area, the first N active area is close to the first N well, the first P active area and the first N active area are respectively connected with a first port, and the second P active area and the second N active area are respectively connected with a second port.
9. The bi-directional electrostatic protection device of claim 7, wherein: the first N well and the first P well are arranged in parallel, two P active areas in the first N well are respectively a first P active area and a second P active area, wherein the second P active area is close to the first P well, two N active areas in the first N well are respectively a first N active area and a second N active area, the first N active area is close to the first N well, the first P active area and the second N active area are respectively connected with a first port, and the second P active area and the first N active area are respectively connected with a second port.
10. The bi-directional electrostatic protection device of any of claims 5-9, wherein: the layout shape of the low clamping voltage type bidirectional electrostatic protection device comprises a strip layout, a ring layout or a waffle layout.
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| CN105810679A (en) * | 2014-12-31 | 2016-07-27 | 湘潭大学 | NPNPN-typetype bidirectional silicon controlled rectifier electrostatic protection device and layout thereof |
| US9502399B1 (en) * | 2015-06-26 | 2016-11-22 | Silicon Laboratories Inc. | Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction during electrostatic discharge (ESD) events |
| CN205582938U (en) * | 2016-03-10 | 2016-09-14 | 湖南静芯微电子技术有限公司 | Two -way SCR devices who triggers by reverse biased diode |
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| US12136622B2 (en) * | 2022-01-03 | 2024-11-05 | Amazing Microelectronic Corp. | Bidirectional electrostatic discharge (ESD) protection device |
| CN114743967A (en) * | 2022-04-07 | 2022-07-12 | 长鑫存储技术有限公司 | Electrostatic protection structure, electrostatic protection circuit and chip |
| CN114709210B (en) * | 2022-06-07 | 2022-09-02 | 深圳市晶扬电子有限公司 | Low clamping voltage ESD protection device for nanoscale FinFET process |
| CN115864348A (en) * | 2022-12-20 | 2023-03-28 | 钳芯半导体科技(无锡)有限公司 | Multi-channel bidirectional electrostatic surge protection circuit suitable for communication chip |
| CN117334692A (en) * | 2023-10-12 | 2024-01-02 | 江南大学 | Bidirectional static and surge protection circuit suitable for ultra-low noise power supply voltage stabilizing chip |
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