CN117954479B - Planar grid power device and manufacturing method thereof - Google Patents

Abstract

The present invention proposes a planar gate power device and a manufacturing method thereof, the method comprising providing a substrate, and making an epitaxial layer on the upper side of the substrate; forming a JFET region on the epitaxial layer; growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer; injecting a first conductive type element into the polysilicon, and performing a well-pushing operation, and then forming a polysilicon gate through an etching process; etching the middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer on the lower side thereof to form a separation groove, the lower end of the separation groove being arranged in the JFET region; and depositing a dielectric layer in the separation groove and on the upper side of the polysilicon gate and the exposed epitaxial layer. The present invention optimizes the oxide layer thickness of the JFET region and the gate edge, avoids high electric field concentration in the region, improves the withstand voltage, reduces the gate charge Qg and the gate Cgs, and greatly reduces the on-resistance.

Description

A planar gate power device and a manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a planar gate power device and a manufacturing method thereof.

Background technique

In a planar metal oxide semiconductor (MOS) field effect transistor, in the off state, the voltage is blocked between the drain and source of the device by the reverse biased p-type body region/n-epitaxial junction. In the on state, current is conducted between the n+ source and the n-epitaxial through the n-type channel. During switching, the n-epitaxial under the gate is charged or discharged through the gate capacitance. Therefore, the switching speed depends largely on the gate-n-epitaxial overlap area.

Devices with different structures in the prior art all have certain defects, as follows:

Conventional planar gate devices have a large gate-n-epitaxial overlap area, which can reduce the distance between two adjacent p-type body regions and reduce gate capacitance and gate charge Qg. However, if they are too close to each other, high resistance will be caused in the upper part of the n-epitaxial between the two adjacent p-type body regions, which will cause high on-resistance of the device.

The split-gate device has a higher switching speed than the conventional planar gate device. At the same time, the space between adjacent p-type body regions is not reduced to maintain approximately the same on-resistance. However, in the off state, the electric field is concentrated at the edge of the split-gate-n-epitaxial overlap region, causing the device to break down prematurely.

The device with an additional dummy gate connects the additional dummy gate to the source electrode. The dummy gate has the function of a field plate, which can optimize the electric field at the edge of the gate electrode in the off state. The problem of premature breakdown is solved. However, the dummy gate will generate additional capacitance at the sidewall of the split gate, which will cause a degradation in switching speed compared to the switching speed of the device with a general split gate structure.

A planar power MOSFET with a split gate and a semi-insulating field plate connected to the source electrode at the sidewall. When the device is in the off state, the semi-insulating field plate can play a role similar to a virtual gate, and can also suppress the high electric field near the gate electrode and thus prevent premature breakdown. However, the on-resistance of the JFET region is still large, affecting the switching speed and switching losses.

Summary of the invention

In view of the above problems, the present invention provides a planar gate power device and a method for manufacturing the same.

To solve the above technical problems, in a first aspect, the present invention provides a method for manufacturing a planar gate power device, comprising:

Providing a substrate of a first conductivity type, and forming an epitaxial layer on an upper side of the substrate;

Forming a JFET region on the epitaxial layer by JFET implantation and JFET well-pushing operations;

growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer;

Implanting the first conductivity type element into the polysilicon, performing a well-pushing operation, and then forming a polysilicon gate through an etching process;

Implanting an element of a second conductivity type into the epitaxial layer without the polysilicon gate and the gate oxide layer to form a body region;

Implanting an element of the first conductivity type into a side of the body region close to the polysilicon gate, and forming a source region through a well-driving operation;

Etching the middle of the polysilicon gate and the gate oxide layer and the epitaxial layer at the lower side thereof to form a separation trench, wherein the lower end of the separation trench is arranged in the JFET region;

Depositing a dielectric layer in the separation trench and on the upper side of the polysilicon gate and the exposed epitaxial layer, and etching a connection hole on the dielectric layer;

Implanting an element of the second conductivity type into the epitaxial layer below the connection hole to form a deep source region;

A metal layer is formed on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a source metal and a gate metal.

Furthermore, a gap is provided in the middle of the dielectric layer in the separation trench so that the source metal can be filled into the gap, and the lower end of the gap is arranged to penetrate into the JFET region.

Furthermore, the dielectric layer includes a filling oxide layer and a dielectric oxide layer which are formed in sequence.

Furthermore, a silicon nitride or silicon oxynitride interlayer is provided between the filling oxide layer and the dielectric oxide layer.

Furthermore, the first conductivity type is N-type, and the second conductivity type is P-type.

In a second aspect, the present invention provides a planar gate power device, comprising a substrate of a first conductivity type, an epitaxial layer is provided on the upper side of the substrate, a JFET region is formed on the epitaxial layer through JFET injection and JFET well-pushing operations, a gate oxide layer is provided on the upper side of the epitaxial layer, a polysilicon gate of the first conductivity type is provided on the upper side of the gate oxide layer, a body region of the second conductivity type is provided in the epitaxial layer, a source region of the first conductivity type is provided on the side of the body region close to the polysilicon gate, a middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer on the lower side thereof are etched to form a separation trench, the lower end of the separation trench is arranged in the JFET region, a dielectric layer is deposited in the separation trench and on the upper side of the polysilicon gate and the exposed epitaxial layer, a connection hole is etched on the dielectric layer, a deep source region of the second conductivity type is provided in the body region outside the source region, a metal layer is made on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a source metal and a gate metal.

Furthermore, a gap is provided in the middle of the dielectric layer in the separation trench so that the source metal can be filled into the gap, and the lower end of the gap is arranged to penetrate into the JFET region.

Furthermore, the dielectric layer includes a filling oxide layer and a dielectric oxide layer which are formed in sequence.

Furthermore, a silicon nitride or silicon oxynitride interlayer is provided between the filling oxide layer and the dielectric oxide layer.

Furthermore, the first conductivity type is N type, and the second conductivity type is P type

Compared with the prior art, the beneficial effects of the present invention include: the present invention forms a separation trench by etching, the lower end of the separation trench penetrates into the JFET region, and the dielectric layer and the source metal are filled between the separated polysilicon gates, which can play the role of a field plate and shield the gate and the drain, optimize the oxide layer thickness of the JFET region and the gate edge, avoid high electric field concentration in this area, improve the withstand voltage, reduce the gate charge Qg and the gate Cgs, and greatly reduce the on-resistance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a gate oxide layer after polysilicon is deposited;

FIG2 is a schematic diagram of etching polysilicon to form a polysilicon gate;

FIG3 is a schematic diagram showing the body region and the source region after being fabricated in the epitaxial layer;

FIG4 is a schematic diagram after the separation grooves are etched;

FIG5 is a schematic structural diagram of a planar gate power device according to an embodiment of the present invention;

6 is a schematic diagram of the structure of a planar gate power device with a dielectric layer as a filling oxide layer and a dielectric oxide layer;

FIG7 is a schematic diagram of the structure of a planar gate power device with an interlayer between a filling oxide layer and a dielectric oxide layer;

Explanation of the accompanying drawings: 1. substrate; 2. epitaxial layer; 3. JFET region; 4. gate oxide layer; 5. polysilicon; 6. polysilicon gate; 7. body region; 8. source region; 9. separation trench; 10. dielectric layer; 101. filling oxide layer; 102. dielectric oxide layer; 103. interlayer; 11. deep source region; 12. source metal.

Detailed ways

The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. The present embodiments are implemented based on the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

An embodiment of the present invention provides a method for manufacturing a planar gate power device, comprising:

Referring to FIG. 1 , a substrate 1 of a first conductivity type is provided, and an epitaxial layer 2 is formed on the upper side of the substrate 1. The following is a specific description taking the first conductivity type as N type and the second conductivity type as N type as an example. The substrate 1 generally adopts an N type (100) crystal orientation, is doped with arsenic or antimony, and has a resistivity generally less than 0.1Ω.cm. The resistivity and thickness of the epitaxial layer 2 are determined by the withstand voltage of different devices.

The JFET region 3 is formed on the epitaxial layer 2 by JFET implantation and JFET well-pushing operation. Specifically, the element implanted by the JFET implantation operation is preferably phosphorus, the implantation dose is preferably 1E12-1E13atom/cm ³ , and the implantation energy is preferably 60-150Kev. The temperature of the JFET well-pushing operation is 1050-1200° C., and the time is 50-150 minutes. The formed JFET region 3 can reduce the on-resistance of the device.

A gate oxide layer 4 is grown on the upper side of the epitaxial layer 2, and polysilicon 5 is deposited on the upper side of the gate oxide layer 4. The thickness of the gate oxide layer 4 is preferably 700-1500 angstroms, and the thickness of the polysilicon 5 is preferably 6000-9000 angstroms.

N-type elements are injected into the polysilicon 5, and a well-pushing operation is performed, and then a polysilicon gate 6 is formed through an etching process. The element injected into the polysilicon 5 is preferably phosphorus, the injection dose is preferably 1E15-3E15atom/cm ³ , and the injection energy is preferably 40-60Kev. The temperature of the well-pushing operation is preferably 800-1150° C., and the time is 10-20 seconds. It should also be noted that when etching to form the polysilicon gate 6, the gate oxide layer 4 on the lower side of the etched polysilicon 5 will also be etched away, and the structure after etching is shown in FIG2 .

3, a P-type element is implanted into the epitaxial layer 2 without the polysilicon gate 6 and the gate oxide layer 4 to form a body region 7. Specifically, the implanted element is preferably boron, the implantation energy is preferably 60-120 KeV, and the implantation dose can be adjusted according to the requirements of the VTH parameter, usually about 1E13-8E13 atom/ ^cm3 .

N-type elements are implanted on the side of the body region 7 close to the polysilicon gate 6, and a well-driving operation is performed to form a source region 8. Specifically, the implanted element is preferably phosphorus, the implanted dose is preferably 1E15-1E16atom/cm ³ , and the implanted energy is preferably 50Kev-100Kev. The well-driving temperature is preferably 900-950° C., and the time is preferably 25-50 minutes.

4 , the middle of the polysilicon gate 6 and the gate oxide layer 4 and the epitaxial layer 2 at the lower side thereof are etched to form a separation trench 9 . The lower end of the separation trench 9 is disposed in the JFET region 3 .

A dielectric layer 10 is deposited in the separation trench 9 and on the upper side of the polysilicon gate 6 and the exposed epitaxial layer 2 , and a connection hole is etched on the dielectric layer 10 .

P-type elements are implanted into the epitaxial layer 2 below the contact hole to form a deep source region 11. Specifically, the implanted element may be boron, the implantation dose is preferably 1E15-3E15atom/ ^cm3 , and the implantation energy is preferably 120-160Kev.

5 to 7 , a metal layer is formed on the upper side of the dielectric layer 10 and in the connection hole, and the metal layer is etched to form a source metal 12 and a gate metal (not shown in the figure), and the gate metal is connected to the polysilicon gate 6 .

In addition, a passivation layer may be deposited on the upper side of the metal layer. The passivation layer is preferably 7000-12000 angstroms thick silicon nitride, and then etched to form the opening areas of the Gate and Source, which can reduce device leakage caused by mobile ions on the chip surface.

The substrate 1 may be thinned from the bottom to a remaining thickness of about 200-300 um, and then a back gold layer may be formed by evaporation on the bottom of the substrate 1. The back gold layer is preferably a Ti-Ni-Ag (titanium-nickel-silver) layer.

6 and 7 , the dielectric layer 10 can fill the interior of the separation trench 9, and the portion of the dielectric layer 10 that penetrates into the JFET region 3 can serve as a field plate. Referring to FIG5 , it is more preferred that a gap is provided in the middle of the dielectric layer 10 in the separation trench 9, so that the source metal 12 can be filled into the gap, and the lower end of the gap is set to penetrate into the JFET region 3, so that the source metal 12 can penetrate into the JFET region 3, and the source metal 12 that penetrates can not only serve as a field plate, but also assist depletion and reduce the surface electric field.

Referring to FIG6 , in order to improve reliability, the dielectric layer 10 includes a filling oxide layer 101 and a dielectric oxide layer 102 formed in sequence. The filling oxide layer 101 and the dielectric oxide layer 102 are preferably both made of silicon dioxide. Referring to FIG7 , a silicon nitride or silicon oxynitride interlayer 103 is preferably provided between the filling oxide layer 101 and the dielectric oxide layer 102.

In conjunction with Figures 1 to 7, those skilled in the art can easily understand that the present invention also provides a planar gate power device, including a substrate 1 of a first conductivity type, and an epitaxial layer 2 is provided on the upper side of the substrate 1. The following is a specific description taking the first conductivity type as N type and the second conductivity type as N type as an example. The substrate 1 generally adopts an N-type (100) crystal orientation, is doped with arsenic or antimony, and has a resistivity generally less than 0.1Ω.cm. The resistivity and thickness of the epitaxial layer 2 are determined by different device withstand voltages.

The JFET region 3 is formed on the epitaxial layer 2 by JFET implantation and JFET well-pushing operation. Specifically, the element implanted by the JFET implantation operation is preferably phosphorus, the implantation dose is preferably 1E12-1E13atom/cm ³ , and the implantation energy is preferably 60-150Kev. The temperature of the JFET well-pushing operation is 1050-1200° C., and the time is 50-150 minutes. The formed JFET region 3 can reduce the on-resistance of the device.

A gate oxide layer 4 is provided on the upper side of the epitaxial layer 2, and the thickness of the gate oxide layer 4 is preferably 700-1500 angstroms. An N-type polysilicon gate 6 is provided on the upper side of the gate oxide layer 4. The polysilicon gate 6 is formed by depositing polysilicon 5 on the upper side of the gate oxide layer 4, injecting N-type elements into the polysilicon 5, and then performing a well-pushing operation and an etching process. The thickness of the polysilicon 5 is preferably 6000-9000 angstroms, and the element injected into the polysilicon 5 is preferably phosphorus. The injection dose is preferably 1E15-3E15atom/cm ³ , and the injection energy is preferably 40-60Kev. The temperature of the well-pushing operation is preferably 800-1150°C, and the time is 10-20 seconds. It should also be noted that when etching to form the polysilicon gate 6, the gate oxide layer 4 on the lower side of the etched polysilicon 5 will also be etched away together, and the structure after etching is shown in FIG2 .

A P-type body region 7 is provided in the epitaxial layer 2. Specifically, the body region 7 is formed by injecting a P-type element into the epitaxial layer 2 covered with no polysilicon gate 6 and gate oxide layer 4. The element injected here is preferably boron, and the injection energy is preferably 60-120Kev. The injection dose can be adjusted according to the requirements of the VTH parameter, usually about 1E13-8E13atom/ ^cm3 .

A source region 8 of the first conductivity type is provided on one side of the body region 7 close to the polysilicon gate 6. Specifically, the source region 8 is formed by implanting an N-type element and performing a well-driving operation. The implanted element is preferably phosphorus, the implanted dose is preferably 1E15-1E16atom/cm ³ , and the implanted energy is preferably 50Kev-100Kev. The well-driving temperature is preferably 900-950° C., and the time is preferably 25-50 minutes.

The middle of the polysilicon gate 6 and the gate oxide layer 4 and the epitaxial layer 2 below it are etched to form a separation trench 9. The lower end of the separation trench 9 is arranged in the JFET region 3. A dielectric layer 10 is deposited in the separation trench 9 and on the upper side of the polysilicon gate 6 and the exposed epitaxial layer 2. A connection hole is etched on the dielectric layer 10. A P-type deep source region 11 is arranged in the body region 7 outside the source region 8. Specifically, the deep source region 11 is formed by implanting a P-type element into the epitaxial layer 2 below the connection hole. The implanted element may be boron. The implanted dose is preferably 1E15-3E15atom/cm ³ , and the implanted energy is preferably 120-160Kev.

A metal layer is formed on the upper side of the dielectric layer 10 and in the connection hole. The metal layer is etched to form a source metal 12 and a gate metal (not shown in the figure). The gate metal is connected to the polysilicon gate 6 .

In addition, a passivation layer may be deposited on the upper side of the metal layer. The passivation layer is preferably 7000-12000 angstroms thick silicon nitride, and then etched to form the opening areas of the Gate and Source, which can reduce device leakage caused by mobile ions on the chip surface.

The substrate 1 may be thinned from the bottom to a remaining thickness of about 200-300 um, and then a back gold layer may be formed by evaporation on the bottom of the substrate 1. The back gold layer is preferably a Ti-Ni-Ag (titanium-nickel-silver) layer.

6 and 7 , the dielectric layer 10 can fill the interior of the separation trench 9, and the portion of the dielectric layer 10 that penetrates into the JFET region 3 can serve as a field plate. Referring to FIG5 , it is more preferred that a gap is provided in the middle of the dielectric layer 10 in the separation trench 9, so that the source metal 12 can be filled into the gap, and the lower end of the gap is set to penetrate into the JFET region 3, so that the source metal 12 can penetrate into the JFET region 3, and the source metal 12 that penetrates can not only serve as a field plate, but also assist depletion and reduce the surface electric field.

Referring to FIG6 , in order to improve reliability, the dielectric layer 10 includes a filling oxide layer 101 and a dielectric oxide layer 102 formed in sequence. The filling oxide layer 101 and the dielectric oxide layer 102 are preferably both made of silicon dioxide. Referring to FIG7 , a silicon nitride or silicon oxynitride interlayer 103 is preferably provided between the filling oxide layer 101 and the dielectric oxide layer 102.

The above is only a preferred embodiment of the present invention. It should be noted that for ordinary technicians in this technical field, other parts not specifically described belong to the prior art or common knowledge. Several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims (10)

1. A method for manufacturing a planar gate power device, comprising: Providing a substrate of a first conductivity type, and forming an epitaxial layer on an upper side of the substrate; Forming a JFET region on the epitaxial layer by JFET implantation and JFET well-pushing operations; growing a gate oxide layer on the upper side of the epitaxial layer, and depositing polysilicon on the upper side of the gate oxide layer; Implanting the first conductivity type element into the polysilicon, performing a well-pushing operation, and then forming a polysilicon gate through an etching process; Implanting an element of a second conductivity type into the epitaxial layer without the polysilicon gate and the gate oxide layer to form a body region; Implanting an element of the first conductivity type into a side of the body region close to the polysilicon gate, and forming a source region through a well-driving operation; Etching the middle of the polysilicon gate and the gate oxide layer and the epitaxial layer at the lower side thereof to form a separation trench, wherein the lower end of the separation trench is arranged in the JFET region; Depositing a dielectric layer in the separation trench and on the upper side of the polysilicon gate and the exposed epitaxial layer, and etching a connection hole on the dielectric layer; Implanting an element of the second conductivity type into the epitaxial layer below the connection hole to form a deep source region; A metal layer is formed on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a source metal and a gate metal. 2. The method for manufacturing a planar gate power device according to claim 1 is characterized in that a gap is provided in the middle of the dielectric layer in the separation trench so that the source metal can be filled into the gap, and the lower end of the gap is set deep into the JFET region. 3 . The method for manufacturing a planar gate power device according to claim 1 , wherein the dielectric layer comprises a filling oxide layer and a dielectric oxide layer formed in sequence. 4 . The method for manufacturing a planar gate power device according to claim 3 , wherein a silicon nitride or silicon oxynitride interlayer is provided between the filling oxide layer and the dielectric oxide layer. 5 . The method for manufacturing a planar gate power device according to claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type. 6. A planar gate power device, characterized in that it includes a substrate of a first conductivity type, an epitaxial layer is provided on the upper side of the substrate, a JFET region is formed on the epitaxial layer through JFET injection and JFET well-pushing operation, a gate oxide layer is provided on the upper side of the epitaxial layer, a polysilicon gate of the first conductivity type is provided on the upper side of the gate oxide layer, a body region of the second conductivity type is provided in the epitaxial layer, a source region of the first conductivity type is provided on the side of the body region close to the polysilicon gate, a middle part of the polysilicon gate and the gate oxide layer and the epitaxial layer on the lower side thereof are etched to form a separation trench, the lower end of the separation trench is arranged in the JFET region, a dielectric layer is deposited in the separation trench and on the upper side of the polysilicon gate and the exposed epitaxial layer, a connection hole is etched on the dielectric layer, a deep source region of the second conductivity type is provided in the body region outside the source region, a metal layer is made on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a source metal and a gate metal. 7. The planar gate power device according to claim 6, characterized in that a gap is provided in the middle of the dielectric layer in the separation trench so that the source metal can be filled into the gap, and the lower end of the gap is set deep into the JFET region. 8 . The planar gate power device according to claim 6 , wherein the dielectric layer comprises a filling oxide layer and a dielectric oxide layer formed in sequence. 9 . The planar gate power device according to claim 8 , wherein a silicon nitride or silicon oxynitride interlayer is provided between the filling oxide layer and the dielectric oxide layer. 10 . The planar gate power device according to claim 6 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.