CN117976554A - Method for forming package structure - Google Patents
Method for forming package structure Download PDFInfo
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- CN117976554A CN117976554A CN202410017845.5A CN202410017845A CN117976554A CN 117976554 A CN117976554 A CN 117976554A CN 202410017845 A CN202410017845 A CN 202410017845A CN 117976554 A CN117976554 A CN 117976554A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
A method for forming a package structure comprises providing a substrate; providing a bottom chip, wherein the functional surface of the bottom chip is provided with a first welding bulge and a first non-conductive film covering the first welding bulge; attaching the functional surface of the bottom chip on the upper surface of the substrate; providing a top chip, wherein the functional surface of the top chip is provided with a second welding bulge and a second non-conductive film covering the second welding bulge; providing a pseudo substrate, wherein the lower surface of the pseudo substrate is provided with an adhesion layer; adhering the lower surface of the dummy substrate on the back surface of the top chip; adsorbing the upper surface of the pseudo substrate through a welding suction nozzle, and attaching the functional surface of the top chip on the back surface of the bottom chip; and performing a welding process, heating and pressurizing through a welding suction nozzle to enable the second welding bulge on the top chip to be welded to the back surface of the bottom chip, and enabling the first welding bulge on the bottom chip to be welded to the substrate. The second non-conductive film is prevented from contaminating the surface of the solder nozzle and the back surface of the top chip.
Description
Technical Field
The present disclosure relates to semiconductor devices, and particularly to a method for forming a package structure.
Background
At present, the stacking welding of chips mainly adopts a hot-press bonding process (Thermal Compression Bonding, TCB), and the welding is carried out in situ under the synchronous action of pressure and temperature. Currently, the mainstream stacking process adopts a Thermal Compression Bonding (TCB) +non-conductive Film (NCF) method, the non-conductive Film is attached to the surface of the chip in advance, and covers the welding protrusions on the surface of the chip, in the welding process, pressure is applied to the back surface of the chip and the non-conductive Film is heated, the non-conductive Film is filled between the chip and the substrate in a flowing manner, the influence of the stress on the chip is buffered, and the welding protrusions are protected, and meanwhile, the welding protrusions of the chip are welded together with the welding fingers on the substrate under the combined action of the pressure and the temperature.
In the existing Thermal Compression Bonding (TCB) +non-conductive Film (NCF) process, pressure is applied to the back of the chip through the bonding nozzle, when the chip is thin or the non-conductive Film is thick, the extrusion height of the non-conductive Film at the edge of the chip is higher than the surface of the chip, so that the non-conductive Film easily pollutes the back of the chip and the surface of the bonding nozzle.
Disclosure of Invention
The application aims to solve the technical problem of how to prevent a non-conductive film from polluting the back surface of a chip and the surface of a welding suction nozzle in the packaging process.
To this end, some embodiments of the present application provide a method for forming a package structure, including:
Providing a substrate comprising opposing upper and lower surfaces;
Providing a bottom chip, wherein the bottom chip comprises a functional surface and a back surface which are opposite, and the functional surface of the bottom chip is provided with a plurality of raised first welding protrusions and a first non-conductive film covering the plurality of first welding protrusions;
Attaching the functional surface of the bottom chip to the upper surface of the substrate in a downward aligned manner;
Providing a top chip, wherein the top chip comprises a functional surface and a back surface which are opposite, and the functional surface of the top chip is provided with a plurality of raised second welding protrusions and a second non-conductive film covering the second welding protrusions;
Providing a dummy substrate comprising opposing upper and lower surfaces, the lower surface of the dummy substrate having an adhesion layer;
Adhering the lower surface of the pseudo substrate to the back surface of the top chip through an adhesive layer;
Adsorbing the upper surface of the pseudo substrate through a welding suction nozzle, and downwards aligning and mounting the functional surface of the top chip adhered on the lower surface of the pseudo substrate on the back surface of the bottom chip;
And (3) performing a welding process, wherein heating is performed during the welding process, pressurizing is performed through the welding suction nozzle, so that the second welding protrusion on the top chip is welded to the back surface of the bottom chip and is electrically connected with the bottom chip, the first welding protrusion on the bottom chip is welded to the substrate and is electrically connected with the substrate, and the first non-conductive film and the second non-conductive film are in a molten state during the welding process.
In some embodiments, further comprising: and forming a plastic sealing layer for coating the top chip, the bottom chip and the side surfaces of the pseudo substrate.
In some embodiments, the material of the pseudo substrate is silicon, glass, resin, or metal.
In some embodiments, the size of the dummy substrate is less than, equal to, or greater than the size of the top chip.
In some embodiments, when the size of the dummy substrate is greater than the size of the top chip, the thickness of the dummy substrate is less than, equal to, or greater than the thickness of the top chip; and when the size of the pseudo substrate is equal to or smaller than that of the top chip, the thickness of the pseudo substrate is larger than that of the top chip.
In some embodiments, the material of the adhesion layer is an adhesive glue.
In some embodiments, the upper surface of the substrate is provided with a plurality of first welding fingers, the first welding protrusions are welded with the corresponding first welding fingers, the lower surface of the substrate is provided with a plurality of second welding fingers, the substrate is provided with a connecting circuit, and part of the first welding fingers on the upper surface of the substrate are electrically connected with the second welding fingers on the lower surface of the substrate through the connecting circuit; further comprises: and forming an external connection protrusion on the surface of the second welding finger.
In some embodiments, the thickness of the top chip is greater than or equal to the thickness of the bottom chip; the bottom chip is one or more, the back of bottom chip has a plurality of connection pads, when bottom chip is one, the second welding lug on the top chip with one the corresponding connection pad welding in bottom chip back is in the same place, when bottom chip is a plurality of, a plurality of bottom chips pile up in proper order along the vertical direction and the electricity is connected, and be located the upper strata first welding lug on the bottom chip with be located the lower floor the connection pad welding in bottom chip back is in the same place, the second welding lug on the top chip welds with the corresponding connection pad welding in bottom chip back of the topmost layer together.
In some embodiments, the first solder bump is a solder layer protruding on the functional side of the underlying chip or the first solder bump includes a metal pillar protruding on the functional side of the underlying chip and a solder layer on a top surface of the metal pillar; the second welding bulge is a solder layer protruding on the functional surface of the top chip or comprises a metal column protruding on the functional surface of the top chip and a solder layer positioned on the top surface of the metal column; the first non-conductive film and the second non-conductive film are made of thermosetting resin materials, and the first non-conductive film and the second non-conductive film are dry films and are respectively formed on the functional surfaces of the bottom chip and the top chip through a film pasting process.
In some embodiments, the process of performing a welding process includes: the method comprises the steps of mounting the functional surface of a bottom chip on the upper surface of a substrate in a downward aligned mode, adsorbing the upper surface of a pseudo substrate through a welding suction nozzle, mounting the functional surface of a top chip adhered to the lower surface of the pseudo substrate on the back surface of the bottom chip in a downward aligned mode, applying pressure to the back surface of the top chip through the welding suction nozzle while heating, enabling a first non-conductive film and a second non-conductive film to be in a molten state, enabling a first welding protrusion on the functional surface of the bottom chip to be in contact with a corresponding first welding finger on the upper surface of the substrate, enabling a second welding protrusion on the functional surface of the top chip to be in contact with a connecting pad on the back surface of the bottom chip, and enabling a first welding protrusion on the bottom chip located on the upper layer to be in contact with a connecting pad on the back surface of the bottom chip located on the lower layer when the bottom chip is multiple in the bottom chip; and continuously applying pressure and increasing the heating temperature, wherein the first non-conductive film and the second non-conductive film are melted and extruded to flow out, simultaneously, the solder layer on the first welding bulge and the solder layer on the second welding bulge are extruded and deformed, after the melting temperature of the solder layer is reached, the first welding bulge on the functional surface of the bottom chip and the corresponding first welding finger on the upper surface of the substrate are welded together, the second welding bulge on the functional surface of the top chip and the connecting pad on the back surface of the bottom chip are welded together, and when the bottom chips are in a plurality of bottom chips, the first welding bulge on the bottom chip positioned on the upper layer and the connecting pad on the back surface of the bottom chip positioned on the lower layer are welded together.
The method for forming the package structure in the foregoing embodiments of the present application provides a substrate; providing a bottom chip, wherein the bottom chip comprises a functional surface and a back surface which are opposite, and the functional surface of the bottom chip is provided with a plurality of raised first welding protrusions and a first non-conductive film covering the plurality of first welding protrusions; attaching the functional surface of the bottom chip to the upper surface of the substrate in a downward aligned manner; providing a top chip, wherein the top chip comprises a functional surface and a back surface which are opposite, and the functional surface of the top chip is provided with a plurality of raised second welding protrusions and a second non-conductive film covering the second welding protrusions; providing a dummy substrate comprising opposing upper and lower surfaces, the lower surface of the dummy substrate having an adhesion layer; adhering the lower surface of the pseudo substrate to the back surface of the top chip through an adhesive layer; adsorbing the upper surface of the pseudo substrate through a welding suction nozzle, and downwards aligning and mounting the functional surface of the top chip adhered on the lower surface of the pseudo substrate on the back surface of the bottom chip; and (3) performing a welding process, wherein heating is performed during the welding process, pressurizing is performed through the welding suction nozzle, so that the second welding protrusion on the top chip is welded to the back surface of the bottom chip and is electrically connected with the bottom chip, the first welding protrusion on the bottom chip is welded to the substrate and is electrically connected with the substrate, and the first non-conductive film and the second non-conductive film are in a molten state during the welding process. During the soldering process, the existence of the dummy substrate can prevent the second non-conductive Film in the molten state from flowing to the surface of the soldering nozzle and the back surface of the top chip, so that the second non-conductive Film in the molten state is prevented from polluting the surface of the soldering nozzle and the back surface of the top chip, and meanwhile, the thermal compression bonding process (TCB) +non-conductive Film process (NCF) of the multi-layer chip (at least one bottom chip is used as the top chip) is realized. In addition, in some embodiments, the dummy substrate may remain as a heat-dissipating substrate after the packaging is completed, so as to release heat generated by the top chip and the bottom chip.
Drawings
Fig. 1-7 are schematic diagrams illustrating a process for forming a semiconductor structure according to some embodiments of the application.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings. In describing embodiments of the present application in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
Some embodiments of the present application provide a method for forming a package structure, which is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including opposite upper and lower surfaces; providing a bottom chip 201, wherein the bottom chip 201 comprises a functional surface and a back surface which are opposite, and the functional surface of the bottom chip 201 is provided with a plurality of first welding bulges 205 and a first non-conductive film 207 covering the plurality of first welding bulges 205; the functional surface of the base chip 201 is attached to the upper surface of the substrate 100 in a downward alignment.
The substrate 100 serves on the one hand as a carrier for subsequent processing and on the other hand as part of the package structure formed by the present application.
In some embodiments, the upper surface of the substrate 100 has a plurality of first bonding fingers 101, the lower surface of the substrate 100 has a plurality of second bonding fingers 102, the substrate 100 has a connection line 103 therein, and a portion of the first bonding fingers 101 on the upper surface of the substrate 100 are electrically connected to the second bonding fingers 102 on the lower surface of the substrate 100 through the connection line 103. The connection line 103 may include one or more of a metal line, a metal plug, a via connection structure, and a via connection structure. The melting point of the materials of the first welding finger 101, the second welding finger 102 and the connecting line 103 is greater than the melting point of the materials of the subsequent welding material layers, and in some specific embodiments, the materials of the first welding finger 101, the second welding finger 102 and the connecting line 103 are metals, and may specifically be one or several of Al, cu, ag, au, pt, ni, ti, tiN, taN, ta, taC, taSiN, W, WN, WSi. In some specific embodiments, the substrate 100 may be one of a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate, a metal substrate, a Printed Circuit Board (PCB), or a flexible circuit board (FPC). In some specific embodiments, the substrate 100 may be a single layer plate or a plurality of plates.
The first bonding fingers 101 on the upper surface of the substrate 100 are subsequently used for bonding with corresponding first bonding bumps on the functional surface of the underlying chip flipped on the upper surface of the substrate, and the positions of the first bonding fingers 101 correspond to the positions of the first bonding bumps of the underlying chip.
In some embodiments, the substrate 100 further has a first passivation layer 104 on an upper surface thereof, the first passivation layer 104 exposing a surface of the first bonding finger 101, and a second passivation layer 107 on a lower surface of the substrate 100, the second passivation layer 107 exposing a surface of the second bonding finger 102. In an embodiment, the materials of the first passivation layer 104 and the second passivation layer 107 may be high molecular polymers, such as resins. In other embodiments, the materials of the first passivation layer 104 and the second passivation layer 107 may be inorganic, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.
With continued reference to fig. 1, an underlying chip 201 is provided, the underlying chip 201 including opposing functional and backside surfaces, the functional surface of the underlying chip 201 having a raised plurality of first bonding bumps 205 thereon and a first non-conductive film 207 covering the plurality of first bonding bumps 205.
In some embodiments, the functional surface of the bottom chip 201 may further have pads, in which an integrated circuit having a specific function is formed in the bottom chip 201, the pads are electrically connected to the integrated circuit, and the first solder bumps 205 are formed on the surface of the pads. The back side of the bottom chip 201 has connection pads (not shown) that are electrically connected to the pads and/or the integrated circuit. In some embodiments, the connection pads are electrically connected to the pads and/or integrated circuit through via interconnect structures (TSVs).
In some embodiments, referring to fig. 1, the first bonding bump 205 includes a metal pillar 203 protruding above the functional surface of the underlying chip 201 and a solder layer 204 on the top surface of the metal pillar 203. In other embodiments, the first bonding bump is a solder layer protruding over the functional surface of the underlying chip. In some embodiments, the material of the metal pillar 203 is one or several of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, and tantalum, and the material of the solder layer 204 is one or several of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
The position of the first bonding bump 205 on the functional surface of the bottom chip 201 corresponds to the position of the first bonding finger 101 on the upper surface of the substrate 100.
The functional surface of the bottom chip 201 further has a first non-conductive film 207 covering the plurality of first bonding bumps 205. The material of the first nonconductive film 207 is a resin material that becomes molten (flows) when heated, and is cured by heat. In some embodiments, the material of the first non-conductive film 207 includes a thermally cured epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The first non-conductive film 207 is a dry film and is formed on the functional surface of the bottom chip 201 through a film-attaching process. The first non-conductive film 207 formed in this way can buffer the influence of stress on the underlying chip 201 and protect the first bonding bumps 205, and is more efficient than the conventional manner of forming an underfill layer by underfilling after flip-chip bonding the chip on the substrate.
In some embodiments, the bottom chip 201 is a logic chip and/or a memory chip. In some embodiments, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), a Central Processing Unit (CPU), a Micro Processing Unit (MPU), a Micro Controller Unit (MCU), a logic Integrated Circuit (IC), an Application Processor (AP), a Display Driver IC (DDI), a Radio Frequency (RF) chip, a power chip, or a Complementary Metal Oxide Semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include a volatile memory chip (such as Dynamic Random Access Memory (DRAM) or Static RAM (SRAM) or a nonvolatile memory chip (such as Flash memory (Flash), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In a particular embodiment, the memory chip may include a High Bandwidth Memory (HBM) including a DRAM chip.
The number of the bottom chips 201 is one or more. The back side of the bottom chip 201 has a plurality of connection pads. In some embodiments, when the bottom chip 201 is one, in a subsequent soldering process, one functional surface of the bottom chip 201 is aligned downward to be attached to the upper surface of the substrate 100, in a subsequent soldering process, the first soldering bump 205 on the bottom chip 201 is soldered with the corresponding first soldering finger on the upper surface of the substrate 100, and the second soldering bump on the subsequently attached top chip is soldered with the corresponding connection pad on the back surface of the bottom chip 201.
In other embodiments, when the number of the bottom chips 201 is plural, with continued reference to fig. 1, the plural bottom chips 201 are stacked in order along the vertical direction, in the subsequent soldering process, the first soldering bumps 205 on the bottom chips 201 on the bottom layer are soldered with the first soldering fingers on the upper surface of the substrate, the first soldering bumps 205 on the bottom chips 201 on the upper layer are soldered with the connection pads on the back surface of the bottom chips 201 on the lower layer, and the second soldering bumps on the top chips on the subsequent mounting are soldered with the corresponding connection pads on the back surface of the bottom chips 201 on the top layer, in this embodiment, two bottom chips 201 are taken as an example, and in other embodiments, the number of the bottom chips 201 may be three, four, five or more. The mounting of the base chip 201 on the substrate 100 and the stacking of the plurality of base chips 201 are performed in a soldering apparatus, and in the mounting and stacking process, a certain pressure is applied and heating is performed, so that a certain adhesion force exists between the base chip 201 and the substrate 100 and between the plurality of base chips 201, and the base chips 201 are prevented from moving. It should be noted that, in some embodiments, when the number of the bottom chips 201 is plural, the functions of plural bottom chips 201 may be the same or different. In some embodiments, the thickness of the plurality of the base chips 201 may be the same or different.
Referring to fig. 2, a top chip 202 is provided, the top chip 202 includes opposite functional surfaces and a back surface, and the functional surfaces of the top chip 202 have a plurality of second bonding bumps 213 thereon and a second non-conductive film 215 covering the plurality of second bonding bumps 213.
The number of the top chips 202 is one, and the top chips 202 serve as one functional chip in the package structure; on the other hand, the back surface of the top chip 202 is further required to be adhered with a dummy substrate 301 (refer to fig. 5), the upper surface of the dummy substrate 301 is then absorbed by a solder nozzle, the functional surface of the top chip 202 adhered on the lower surface of the dummy substrate 301 is aligned and attached to the back surface of the bottom chip 201, and the dummy substrate 301 is used for preventing the non-conductive film from overflowing glue to pollute the back surface of the chip and the surface of the solder nozzle when the multi-layer chip is packaged in a solder manner. The upper surface of the dummy substrate 301 may further have pads on the functional surface of the top chip 202, an integrated circuit having a specific function is formed in the top chip 202, the pads are electrically connected to the integrated circuit, and the second solder bumps 213 are formed on the surfaces of the pads.
In some embodiments, with continued reference to fig. 2, the second bonding bump 213 includes a metal pillar 211 protruding above the functional surface of the top chip 202 and a solder layer 212 on the top surface of the metal pillar 211. In other embodiments, the second bonding pad is a bonding pad protruding from the functional surface of the top chip. In some embodiments, the material of the metal pillar 211 is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, and tantalum, and the material of the solder layer 212 is one or more of tin, tin silver, tin lead, tin silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony.
The positions of the second bonding bumps 213 on the functional surface of the top chip 202 correspond to the positions of the connection pads on the back surface of the bottom chip 201, and the functional surface of the top chip 202 further has a second non-conductive film 215 covering the plurality of second bonding bumps 213. The material of the second nonconductive film 215 is a resin material that becomes molten (flows) when heated, and is cured by heat. In some embodiments, the material of the second non-conductive film 215 includes a thermally cured epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The second nonconductive film 215 is a dry film, and is formed on the functional surface of the top chip 202 through a film pasting process. The second non-conductive film 215 formed in this way can buffer the effect of stress on the top chip 202 and protect the second bonding bumps 213, and is more efficient than the conventional manner of forming an underfill layer by underfilling after flip-chip bonding on a substrate. In some embodiments, the second non-conductive film 215 and the first non-conductive film 207 are both the same material and formation process.
In some embodiments, the top chip 202 is a logic chip or a memory chip. In some embodiments, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Complex Programmable Logic Device (CPLD), a Central Processing Unit (CPU), a Micro Processing Unit (MPU), a Micro Controller Unit (MCU), a logic Integrated Circuit (IC), an Application Processor (AP), a Display Driver IC (DDI), a Radio Frequency (RF) chip, a power chip, or a Complementary Metal Oxide Semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include a volatile memory chip (such as Dynamic Random Access Memory (DRAM) or Static RAM (SRAM) or a nonvolatile memory chip (such as Flash memory (Flash), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (ReRAM)). In a particular embodiment, the memory chip may include a High Bandwidth Memory (HBM) including a DRAM chip.
In some embodiments, the top chip 202 functions the same or different than the bottom chip 201, and the thickness of the top chip 202 is greater than or equal to the thickness of the bottom chip 201.
Referring to fig. 3, a dummy substrate 301 is provided, the dummy substrate 301 including opposite upper and lower surfaces, the lower surface of the dummy substrate 301 having an adhesive layer 302.
The dummy substrate 301 is subsequently used to adhere to the back surface of the top chip 202 (refer to fig. 4 or 5), and when the functional surface of the top chip adhered to the lower surface of the dummy substrate is subsequently attached to the back surface of the bottom chip in a downward aligned manner by the bonding suction nozzle, the dummy substrate 301 can prevent the second nonconductive Film in a molten state from flowing in the direction of the surface of the bonding suction nozzle and the back surface of the top chip 202 (a part of the second nonconductive Film is adhered to the dummy substrate 301 after being melted), thereby preventing the second nonconductive Film in a molten state from contaminating the surface of the bonding suction nozzle and the back surface of the top chip 202, and simultaneously realizing a thermal compression bonding process (TCB) +nonconductive Film process (NCF) of the multi-layered chip (at least one bottom chip 201 is the top chip 202). Furthermore, in some embodiments, the dummy substrate 301 may remain as a heat-dissipating substrate after the packaging is completed to release heat generated by the top chip 202 and the bottom chip 201.
In some embodiments, the material of the dummy substrate 301 is silicon, glass, resin, or metal, and the dummy substrate 301 has flat upper and lower surfaces. In some embodiments, the dummy substrate 301 is a high thermal conductivity metallic material, including copper, aluminum, gold, nickel, steel, or stainless steel.
In some embodiments, the size of the dummy substrate 301 may be equal to, greater than, or less than the size of the top chip 202. When the size of the dummy substrate 301 is larger than the size of the top chip 202, the edge of the dummy substrate 301 protrudes outwards beyond the edge of the top chip 202, so that the second non-conductive film in a molten state can be better prevented from flowing towards the surface of the welding nozzle in the welding process by the dummy substrate 301, and the second non-conductive film in a molten state can be better prevented from polluting the surface of the welding nozzle.
In some embodiments, when the size of the dummy substrate 301 is greater than that of the top chip 202, the lower surface of the edge area of the dummy substrate 301 is further provided with a raised auxiliary heat dissipation structure, which may be a plurality of discrete auxiliary heat dissipation structures, the auxiliary heat dissipation structure and the dummy substrate may be an integral structure, and then the upper surface of the dummy substrate is absorbed by a welding nozzle, and when the functional surface of the top chip adhered on the lower surface of the dummy substrate is attached to the back surface of the bottom chip in a downward aligned manner, the auxiliary heat dissipation structure is suspended around the top chip 202 and the bottom chip 201, or part of the auxiliary heat dissipation structure surrounds the top chip 202 and abuts against the back surface of the bottom chip 201 (when the size of the bottom chip 201 is greater than that of the top chip 202), so that the heat generated by the top chip 202 and the bottom chip 201 may be transferred to the auxiliary heat dissipation structure, thereby releasing through the dummy substrate 301, and improving the heat dissipation efficiency.
In some embodiments, when the size of the dummy substrate 301 is greater than the size of the top chip 202, the thickness of the dummy substrate 301 is less than, equal to, or greater than the thickness of the top chip 202. In other embodiments, when the size of the dummy substrate 301 is equal to or smaller than the size of the top chip 202, the thickness of the dummy substrate 301 is greater than the thickness of the top chip 202, so that the dummy substrate 301 can better prevent the second non-conductive film in a molten state from flowing in a direction toward the surface of the solder nozzle and the back surface of the top chip 202 (a part of the second non-conductive film adheres to the dummy substrate 301), thereby preventing the second non-conductive film in a molten state from contaminating the surface of the solder nozzle and the back surface of the top chip 202.
In some embodiments, the lower surface of the dummy substrate 301 has an adhesive layer 302, and the material of the adhesive layer 302 is adhesive glue. In some embodiments, the adhesive may be a thermally conductive adhesive.
Referring to fig. 4, the lower surface of the dummy substrate 301 is adhered to the back surface of the top chip 202 through an adhesive layer 302.
The adhering process may be performed in a soldering apparatus, specifically, the top chip 202 is first fixed on a transfer platform (DIE TRANSFER ARM, DTA) of the soldering apparatus, and then a pick-up arm (DIE PICK ARM, DPA) of the soldering apparatus picks up and adheres the dummy substrate 301 to the back surface of the top chip on the transfer platform.
Referring to fig. 5, the functional surface of the top chip 202 adhered on the lower surface of the dummy substrate 301 is attached in downward alignment on the back surface of the bottom chip 201 by sucking the upper surface of the dummy substrate 301 through the solder bumps 401.
The soldering nozzle 401 is a soldering nozzle in a soldering apparatus, and vacuum holes are distributed in the soldering nozzle 401, so that negative pressure can be applied to suck the dummy substrate 301.
Referring to fig. 6, a soldering process is performed, in which the second soldering bump 213 on the top chip 202 is soldered to the back surface of the bottom chip 201 and electrically connected to the bottom chip 201 by heating and pressurizing the soldering nozzle 401, and the first soldering bump 205 on the bottom chip 201 is soldered to the substrate 100 and electrically connected to the substrate 100, and the first nonconductive film 207 and the second nonconductive film 215 are in a molten state during the soldering process.
The welding process is performed in a welding apparatus.
In one embodiment, the upper surface of the substrate 100 has a plurality of first bonding fingers 101, the first bonding bumps 205 are bonded to the corresponding first bonding fingers 101, the back surface of the bottom chip 201 has connection pads (not shown), and the second bonding bumps 213 are bonded to the corresponding connection pads.
In one embodiment, the welding process includes: after the functional surface of the bottom chip 201 is aligned and mounted on the upper surface of the substrate 100, and the upper surface of the dummy substrate 301 is absorbed by the bonding nozzle 401, the functional surface of the top chip 202 adhered on the lower surface of the dummy substrate 301 is aligned and mounted on the back surface of the bottom chip 201, pressure is applied to the back surface of the top chip 202 by the bonding nozzle 401, and heating is performed simultaneously, the first non-conductive film 207 and the second non-conductive film 215 are in a molten state, the first bonding bumps 205 on the functional surface of the bottom chip 201 are in contact with the corresponding first bonding fingers 101 on the upper surface of the substrate 100, the second bonding bumps 213 on the functional surface of the top chip 202 are in contact with the connection pads on the back surface of the bottom chip 201, and when the bottom chip 201 is a plurality of, the first bonding bumps 205 on the bottom chip 201 on the upper layer are in contact with the connection pads on the back surface of the bottom chip 201 on the lower layer; continuing to apply pressure and raising the heating temperature, the first nonconductive film 207 and the second nonconductive film 215 are melted and extruded to flow out, and simultaneously the solder layer 204 on the first bonding bump 205 and the solder layer 212 on the second bonding bump 213 are extruded and deformed, and after reaching the melting temperature of the solder layer 204 and the solder layer 212, the first bonding bump 205 on the functional surface of the bottom chip 201 is bonded to the corresponding first bonding finger 101 on the upper surface of the substrate 100, the second bonding bump 213 on the functional surface of the top chip 202 is bonded to the bonding pad on the back surface of the bottom chip 201, and when the bottom chip 201 is plural, the first bonding bump 205 on the bottom chip 201 on the upper layer is bonded to the bonding pad on the back surface of the bottom chip 201 on the lower layer. The existence of the dummy substrate 301 prevents the second nonconductive Film 215 in a molten state from flowing in a direction of the surface of the solder nozzle 401 and the back surface of the top chip 202 during soldering, thereby preventing the second nonconductive Film 215 in a molten state from contaminating the surface of the solder nozzle 401 and the back surface of the top chip 202, while simultaneously implementing a thermal compression bonding process (TCB) +a nonconductive Film process (NCF) of the multi-layered chip (at least one bottom chip 201 is the top chip 202).
In some embodiments, after the soldering process, a curing process is performed to cure the first and second non-conductive films 207 and 215, and the solder layer 204 and 212. In some embodiments, the curing process may be performed at a later time when the molding layer 220 is formed.
In some embodiments, referring to fig. 7, after the soldering process, the dummy substrate 301 and the adhesive layer 302 remain, forming a plastic layer 220 covering the top chip 202, the bottom chip 201, and the sides of the dummy substrate 301.
In other embodiments, after the soldering process, the dummy substrate 301 and the adhesion layer 302 are removed, forming a plastic layer that encapsulates the top chip 202 and the bottom chip 201. The removed dummy substrate 301 may be reused in the next packaging process after cleaning.
In some embodiments, the material of the plastic layer 220 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin containing a filler; or may be a filled polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. The filler may be an inorganic filler or an organic filler. The process of forming the plastic layer 220 includes an injection molding process (or a rotational molding process), and a curing process.
With continued reference to fig. 7, further comprising: an external protrusion 111 is formed on the surface of the second welding finger 102.
In some embodiments, the material of the external protrusion 111 may be one or more of tin, tin silver, tin lead, silver copper, tin silver zinc, tin bismuth indium, tin gold, tin copper, tin zinc indium, or tin silver antimony. Forming the circumscribing protrusion 111 includes screen printing or electroplating.
It should be noted that the terms "comprising" and "having," and variations thereof, as referred to in this disclosure are intended to cover non-exclusive inclusion. The terms "first," "second," and the like are used to distinguish similar objects and not necessarily to describe a particular order or sequence unless otherwise indicated by context, it should be understood that the data so used may be interchanged where appropriate. In addition, embodiments of the present disclosure and features of embodiments may be combined with each other without conflict. In addition, in the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. In the foregoing embodiments, each embodiment is mainly described for the differences from the other embodiments, and the same/similar parts between the embodiments need to be referred to (or referred to) each other.
Although the present application has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present application by using the methods and technical matters disclosed above without departing from the spirit and scope of the present application, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present application are within the scope of the technical matters of the present application.
Claims (10)
1. The method for forming the packaging structure is characterized by comprising the following steps:
Providing a substrate comprising opposing upper and lower surfaces;
Providing a bottom chip, wherein the bottom chip comprises a functional surface and a back surface which are opposite, and the functional surface of the bottom chip is provided with a plurality of raised first welding protrusions and a first non-conductive film covering the plurality of first welding protrusions;
Attaching the functional surface of the bottom chip to the upper surface of the substrate in a downward aligned manner;
Providing a top chip, wherein the top chip comprises a functional surface and a back surface which are opposite, and the functional surface of the top chip is provided with a plurality of raised second welding protrusions and a second non-conductive film covering the second welding protrusions;
Providing a dummy substrate comprising opposing upper and lower surfaces, the lower surface of the dummy substrate having an adhesion layer;
Adhering the lower surface of the pseudo substrate to the back surface of the top chip through an adhesive layer;
Adsorbing the upper surface of the pseudo substrate through a welding suction nozzle, and downwards aligning and mounting the functional surface of the top chip adhered on the lower surface of the pseudo substrate on the back surface of the bottom chip;
And (3) performing a welding process, wherein heating is performed during the welding process, pressurizing is performed through the welding suction nozzle, so that the second welding protrusion on the top chip is welded to the back surface of the bottom chip and is electrically connected with the bottom chip, the first welding protrusion on the bottom chip is welded to the substrate and is electrically connected with the substrate, and the first non-conductive film and the second non-conductive film are in a molten state during the welding process.
2. The method of forming a package structure of claim 1, further comprising: and forming a plastic sealing layer for coating the top chip, the bottom chip and the side surfaces of the pseudo substrate.
3. The method of claim 1, wherein the dummy substrate is made of silicon, glass, resin or metal.
4. The method of forming a package structure of claim 1 or 3, wherein the dummy substrate has a size smaller than, equal to, or greater than a size of the top chip.
5. The method of forming a package structure of claim 4, wherein when the size of the dummy substrate is greater than the size of the top chip, the thickness of the dummy substrate is less than, equal to, or greater than the thickness of the top chip; and when the size of the pseudo substrate is equal to or smaller than that of the top chip, the thickness of the pseudo substrate is larger than that of the top chip.
6. The method of claim 1, wherein the adhesive layer is made of an adhesive.
7. The method of forming a package structure of claim 1, wherein the upper surface of the substrate has a plurality of first bonding fingers, the first bonding bumps are bonded to the corresponding first bonding fingers, the lower surface of the substrate has a plurality of second bonding fingers, the substrate has a connection circuit therein, and a portion of the first bonding fingers on the upper surface of the substrate are electrically connected to the second bonding fingers on the lower surface of the substrate through the connection circuit; further comprises: and forming an external connection protrusion on the surface of the second welding finger.
8. The method of forming a package structure of claim 7, wherein a thickness of the top chip is greater than or equal to a thickness of the bottom chip; the bottom chip is one or more, the back of bottom chip has a plurality of connection pads, when bottom chip is one, the second welding lug on the top chip with one the corresponding connection pad welding in bottom chip back is in the same place, when bottom chip is a plurality of, a plurality of bottom chips pile up in proper order along the vertical direction and the electricity is connected, and be located the upper strata first welding lug on the bottom chip with be located the lower floor the connection pad welding in bottom chip back is in the same place, the second welding lug on the top chip welds with the corresponding connection pad welding in bottom chip back of the topmost layer together.
9. The method of forming a package structure of claim 8, wherein the first solder bump is a solder layer protruding over the functional surface of the underlying chip or the first solder bump comprises a metal pillar protruding over the functional surface of the underlying chip and a solder layer on a top surface of the metal pillar; the second welding bulge is a solder layer protruding on the functional surface of the top chip or comprises a metal column protruding on the functional surface of the top chip and a solder layer positioned on the top surface of the metal column; the first non-conductive film and the second non-conductive film are made of thermosetting resin materials, and the first non-conductive film and the second non-conductive film are dry films and are respectively formed on the functional surfaces of the bottom chip and the top chip through a film pasting process.
10. The method of forming a package structure of claim 9, wherein the performing a soldering process comprises: the method comprises the steps of mounting the functional surface of a bottom chip on the upper surface of a substrate in a downward aligned mode, adsorbing the upper surface of a pseudo substrate through a welding suction nozzle, mounting the functional surface of a top chip adhered to the lower surface of the pseudo substrate on the back surface of the bottom chip in a downward aligned mode, applying pressure to the back surface of the top chip through the welding suction nozzle while heating, enabling a first non-conductive film and a second non-conductive film to be in a molten state, enabling a first welding protrusion on the functional surface of the bottom chip to be in contact with a corresponding first welding finger on the upper surface of the substrate, enabling a second welding protrusion on the functional surface of the top chip to be in contact with a connecting pad on the back surface of the bottom chip, and enabling a first welding protrusion on the bottom chip located on the upper layer to be in contact with a connecting pad on the back surface of the bottom chip located on the lower layer when the bottom chip is multiple in the bottom chip; and continuously applying pressure and increasing the heating temperature, wherein the first non-conductive film and the second non-conductive film are melted and extruded to flow out, simultaneously, the solder layer on the first welding bulge and the solder layer on the second welding bulge are extruded and deformed, after the melting temperature of the solder layer is reached, the first welding bulge on the functional surface of the bottom chip and the corresponding first welding finger on the upper surface of the substrate are welded together, the second welding bulge on the functional surface of the top chip and the connecting pad on the back surface of the bottom chip are welded together, and when the bottom chips are in a plurality of bottom chips, the first welding bulge on the bottom chip positioned on the upper layer and the connecting pad on the back surface of the bottom chip positioned on the lower layer are welded together.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410017845.5A CN117976554A (en) | 2024-01-04 | 2024-01-04 | Method for forming package structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410017845.5A CN117976554A (en) | 2024-01-04 | 2024-01-04 | Method for forming package structure |
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