CN117976671A

CN117976671A - Semiconductor structure and preparation method thereof, memory and preparation method thereof

Info

Publication number: CN117976671A
Application number: CN202211280906.4A
Authority: CN
Inventors: 邵光速
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2024-05-03

Abstract

The embodiment of the disclosure provides a semiconductor structure, a memory, a preparation method of the semiconductor structure and a preparation method of the memory, wherein the semiconductor structure comprises the following steps: a plurality of transistor layers spaced apart along a first direction; wherein each transistor layer comprises a plurality of transistors sequentially arranged along a second direction; each of the transistors includes an active pillar and a gate; each active column comprises a source electrode, a channel and a drain electrode which are sequentially connected along a third direction, and a grid electrode in each transistor surrounds the channel of the active column in the transistor; the active pillars of the transistors in each transistor layer are offset from the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction, and the projections along the first direction are offset from each other; the first direction, the second direction and the third direction are intersected pairwise.

Description

Semiconductor structure and preparation method thereof, memory and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor structure, a memory, a method for manufacturing a semiconductor structure, and a method for manufacturing a memory.

Background

In a semiconductor integrated circuit, a transistor functions as a control circuit. For example, in a Dynamic Random Access Memory (DRAM), a transistor is connected to a capacitor, and reading or writing of data stored in the capacitor can be controlled by the transistor.

In a semiconductor product, a plurality of transistors may be arranged in an array. However, in the related art, parasitic capacitance between transistors arranged in an array is large. In very large scale integrated circuits, transistor layout density is generally low to ensure electrical performance of transistors, resulting in insufficient integration of semiconductor integrated circuits.

Disclosure of Invention

In view of this, embodiments of the present disclosure provide a semiconductor structure, a memory, a method for manufacturing a semiconductor structure, and a method for manufacturing a memory, which are at least used for improving parasitic capacitance between transistors and improving performance of transistors, thereby providing possibility for increasing arrangement density between transistors, and further supporting improvement of integration level of a semiconductor integrated circuit.

Embodiments of the present disclosure provide a semiconductor structure, comprising:

a plurality of transistor layers spaced apart along a first direction; wherein,

Each transistor layer comprises a plurality of transistors which are sequentially arranged along a second direction; each of the transistors includes an active pillar and a gate; each active column comprises a source electrode, a channel and a drain electrode which are sequentially connected along a third direction, and a grid electrode in each transistor surrounds the channel of the active column in the transistor; the active pillars of the transistors in each transistor layer are offset from the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction, and the projections along the first direction are offset from each other; the first direction, the second direction and the third direction are intersected pairwise.

The disclosed embodiments provide a memory, including:

The semiconductor structure as described in the above embodiments;

And each capacitor is correspondingly connected with the source electrode or the drain electrode of each active column in the semiconductor structure along the third direction.

The embodiment of the disclosure provides a method for forming a semiconductor structure, which comprises the following steps:

Providing a substrate;

Forming a plurality of transistor layers spaced apart along a first direction on the substrate; wherein each transistor layer comprises a plurality of transistors sequentially arranged along a second direction; each of the transistors includes an active pillar and a gate; each active column comprises a source electrode, a channel and a drain electrode which are sequentially connected along a third direction, and a grid electrode in each transistor surrounds the channel of the active column in the transistor; the active pillars of the transistors in each transistor layer are offset from the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction, and the projections along the first direction are offset from each other; the first direction, the second direction and the third direction are intersected pairwise.

The embodiment of the disclosure provides a method for forming a memory, which comprises the following steps:

Providing a substrate;

Forming a semiconductor structure and a plurality of capacitors on the surface of the substrate; each capacitor of the plurality of capacitors is correspondingly connected with the source electrode or the drain electrode of each active column of the semiconductor structure along the third direction.

In an embodiment of the present disclosure, a plurality of transistor layers are disposed at intervals along a first direction; wherein each transistor layer comprises a plurality of transistors sequentially arranged along a second direction; each of the transistors includes an active pillar and a gate; each active column comprises a source electrode, a channel and a drain electrode which are sequentially connected along a third direction, and a grid electrode in each transistor surrounds the channel of the active column in the transistor; the active pillars of the transistors in each transistor layer are offset from the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction, and the projections along the first direction are offset from each other; the first direction, the second direction and the third direction are intersected pairwise. In this way, since the projections of the active pillars of the transistors in the adjacent transistor layers along the first direction are offset from each other, the facing area between the active pillars of the adjacent transistor layers can be reduced, thereby reducing the parasitic capacitance between the active pillars in the adjacent transistor layers, and further providing a possibility for reducing the distance between the adjacent transistor layers along the first direction, so as to further reduce the distance between the adjacent transistor layers along the first direction on the premise of ensuring the electrical performance between the transistors, and further providing a support for improving the integration level of the semiconductor integrated circuit.

Drawings

In the drawings (which are not necessarily drawn to scale), like numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, various embodiments discussed herein.

Fig. 1A is a schematic structural diagram of a semiconductor structure according to an embodiment of the disclosure;

fig. 1B is a schematic diagram of a composition structure of an active pillar in a semiconductor structure according to an embodiment of the disclosure;

fig. 1C is a schematic cross-sectional view of each active pillar in a semiconductor structure along a plane perpendicular to a third direction according to an embodiment of the disclosure;

Fig. 1D is a schematic cross-sectional view of each active pillar in a semiconductor structure along a plane perpendicular to a third direction according to an embodiment of the disclosure;

FIG. 2A is a schematic diagram of a memory according to an embodiment of the disclosure;

FIG. 2B is a schematic cross-sectional view of a memory provided by an embodiment of the present disclosure;

FIG. 2C is a schematic cross-sectional view of a memory provided by an embodiment of the present disclosure;

FIG. 2D is a schematic cross-sectional view of a memory provided by an embodiment of the present disclosure;

FIG. 2E is a schematic cross-sectional view of a memory provided by an embodiment of the present disclosure;

fig. 3 is a schematic implementation flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 4A is a schematic top view and schematic cross-sectional views of a first active structure formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 4B is a schematic top view and schematic cross-sectional views of a second active structure formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 4C is a schematic top view and schematic cross-sectional views of a first support layer and a first active pillar layer formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 4D is a schematic top view and schematic cross-sectional views of a first channel formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 4E is a schematic structural diagram of a first support sub-layer and a first sacrificial structure layer formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 4F is a schematic structural diagram of forming a second support sub-layer and a second sacrificial structure layer in a method for forming a semiconductor structure according to an embodiment of the disclosure;

Fig. 4G is a schematic structural diagram of a through hole layer formed in a method for forming a semiconductor structure according to an embodiment of the disclosure;

fig. 5 is a schematic implementation flow chart of a method for forming a memory according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a word line formed in a method for forming a memory according to an embodiment of the disclosure;

Reference numerals illustrate:

100: a semiconductor structure; 10: a transistor layer; 11: a transistor; 12: an active column; 13: a gate; 14: a source electrode; 15: a channel; 16: a drain electrode; 20: a capacitor; 21: a bit line; 22: a word line; 30: a substrate; 31: a first active structure; 311: a first support layer; 101: a first transistor layer; 32: a second active structure; 321: a second support layer; 102: a first transistor layer; 301 a first active column layer; 151: a first channel; 3311: a first support sub-layer; 3312: a second support sub-layer; 331: a third support layer; 332: a first sacrificial structure layer; 3321: a sacrificial structure; 333: a second sacrificial structure layer; 334: a via layer; 17: a capacitor contact structure; 201: a first electrode; 202: a dielectric; 203: a second electrode; 410: a first fill region; 18: and a gate oxide layer.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity.

Like numbers refer to like elements throughout.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Before describing the embodiments of the present disclosure, three directions describing the three-dimensional structure that may be used in the following embodiments are defined, and may include X-axis, Y-axis, and Z-axis directions, for example, in a cartesian coordinate system. The direction in which the transistor layers are arranged may be defined as a first direction, the direction in which the plurality of transistors in the transistor layers are arranged is a second direction, and the direction in which the source, channel, and drain are arranged in the active pillars of each transistor in the transistor layers is a third direction. The first direction, the second direction and the third direction are only required to be intersected two by two, and are not limited, and at least any two directions are mutually perpendicular. In the embodiment of the disclosure, the first direction is defined as a Z-axis direction (longitudinal direction), the second direction is defined as an X-axis direction (transverse direction), and the third direction is defined as a Y-axis direction.

In the related art, parasitic capacitance exists between transistors, which affects the performance of the transistors. To ensure electrical performance of transistors, a distance is typically required between adjacent transistors, resulting in a generally not too high arrangement density between the transistors in the semiconductor product. In carrying out the embodiments of the present disclosure, the inventors have studied and found that the cause of this problem arises from: the transistors in existing semiconductor products are densely packed in a square. The transistors in square close arrangement are opposite to each other, and a large opposite area exists. The larger facing area causes parasitic capacitance between adjacent transistors, thereby causing a certain limitation in the distance between adjacent transistor layers, resulting in insufficient integration of the semiconductor integrated circuit. .

On the basis, the embodiment of the disclosure provides a semiconductor structure, by arranging that the projections of the active pillars of each transistor in the adjacent transistor layers along the first direction are staggered with each other along the first direction, the opposite area between the active pillars of the adjacent transistor layers is reduced, so that parasitic capacitance between the active pillars of the adjacent transistor layers is reduced, and further the possibility of reducing the distance between the adjacent transistor layers along the first direction is provided, and the distance between the adjacent transistor layers along the first direction is further reduced on the premise of ensuring the electrical performance between the transistors, so that the support is provided for improving the integration level of the semiconductor integrated circuit.

Fig. 1A is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure, and fig. 1B is a schematic structural diagram of an active pillar in a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 1A and 1B, the semiconductor structure 100 includes: a plurality of transistor layers 10 arranged at intervals along the first direction Z; wherein each of the transistor layers 10 includes a plurality of transistors 11 sequentially arranged in the second direction X; each of the transistors 11 comprises an active pillar 12 and a gate 13; each of the active pillars 12 comprises a source 14, a channel 15, and a drain 16 connected in sequence along a third direction Y, the gate 13 in each of the transistors 11 surrounding the channel 15 of the active pillar 12 in the transistor 11; the projection of the active pillars 12 of the transistors 11 in each of the transistor layers 10 and the projection of the active pillars 12 of the transistors 11 in the transistor layers 10 adjacent to the transistor layers in the first direction along the first direction are offset from each other; the first direction Z, the second direction X and the third direction Y are intersected in pairs.

Here, the transistor layers 10 are disposed at intervals along the first direction Z, that is, the transistor layers 10 are planes formed by the second direction X and the third direction Y, and each transistor layer 10 is parallel to each other and is disposed at intervals along the first direction Z. It will be appreciated that the plurality of transistor layers spaced apart along the first direction are insulating, for example, the transistor layers may have insulating material between them. The insulating material serves to prevent electrical conduction between the transistor layers.

In addition, the transistor layers adjacent in the first direction may refer to two transistor layers adjacent in the first direction, and may also refer to a plurality of transistor layers adjacent in the first direction. For example, in the case where the transistor layers adjacent in the first direction include two adjacent transistor layers, the transistor layers arranged in order in the first direction are the first transistor layer and the second transistor layer, respectively. For another example, in the case where the transistor layers adjacent in the first direction include adjacent three layers of transistors, the transistor layers sequentially arranged in the first direction are the first transistor layer, the second transistor layer, and the third transistor layer, respectively. The projections of the active pillars of the transistors in each of the transistor layers and the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction along the first direction are offset from each other, which may mean that the projections of the active pillars in two adjacent transistor layers along the first direction are offset from each other (e.g., the projections of the active pillars in the first transistor layer and the active pillars in the second transistor layer along the first direction are offset from each other), and which may mean that the projections of the active pillars in each of the adjacent transistor layers along the first direction are offset from each other (e.g., the projections of the active pillars in the first transistor layer, the active pillars in the second transistor layer, and the active pillars in the third transistor layer along the first direction are offset from each other). It will be appreciated that the projection of the active pillars of the transistors in the transistor layer in a first direction, i.e. the projection of the active pillars of the transistors in the transistor layer in a plane defined by the second direction and the third direction.

The plurality of transistors may be sequentially arranged in the second direction within the transistor layer, and may be a plurality of transistors arranged with only one row spacing in the second direction. I.e. the transistors are distributed in an array in a plane formed by the first direction and the second direction. In addition, the transistors are sequentially arranged in the transistor layer along the second direction, and may be a plurality of transistors arranged at intervals in a plurality of rows along the second direction, that is, a plurality of transistors arranged at intervals along the third direction, that is, the transistors are distributed in an array in a plane formed by the second direction and the third direction, so that the semiconductor structure is a stacked structure in which the transistors are distributed in a three-dimensional space.

In this embodiment, by setting the projections of the active pillars of each transistor in the adjacent transistor layers along the first direction to be offset from each other, the facing area between the active pillars of the adjacent transistor layers can be reduced, thereby reducing the parasitic capacitance between the active pillars in the adjacent transistor layers, and further providing a possibility for reducing the distance between the adjacent transistor layers along the first direction, so as to further reduce the distance between the adjacent transistor layers along the first direction on the premise of ensuring the electrical performance between the transistors, and thus providing a support for improving the integration level of the semiconductor integrated circuit.

In some embodiments, the active pillars of the transistors in each of the transistor layers are non-overlapping with the active pillars of the transistors in transistor layers adjacent to the transistor layers in the first direction, and the projections along the first direction are non-overlapping.

Here, referring to fig. 1C, fig. 1C is a schematic cross-sectional view of each active pillar in a semiconductor structure along a plane perpendicular to a third direction according to an embodiment of the disclosure. As shown in fig. 1C, projection 1 is a projection of an active pillar 12a of each transistor in a transistor layer (e.g., a first transistor layer) along the first direction, and projection "2" is a projection of an active pillar 12b of each transistor in a transistor layer (e.g., a second transistor layer adjacent to the first transistor layer) adjacent to the first transistor layer along the first direction. As can be seen from fig. 1C, projection 1 and projection 2 are non-overlapping.

The projection of the active pillars of the transistors in each of the transistor layers and the transistors in the transistor layers adjacent to the transistor layer in the first direction along the first direction is non-overlapping, that is, the dislocation degree of the active pillars of the transistors in the adjacent transistor layers along the first direction is completely dislocation. In this case, there is no direct face between the active pillars of adjacent transistor layers in the first direction. Thus, parasitic capacitance between transistors in the transistor layers adjacent in the first direction can be reduced.

In some embodiments, the active pillars of the transistors in each of the transistor layers are partially overlapping with the active pillars of the transistors in transistor layers adjacent to the transistor layer in the first direction, the projections along the first direction.

Here, referring to fig. 1D, fig. 1D is a schematic cross-sectional view of each active pillar in a semiconductor structure according to an embodiment of the disclosure along a plane perpendicular to a third direction. As shown in fig. 1D, projection 3 is a projection of an active pillar 12c of each transistor in a transistor layer (e.g., a first transistor layer) along a first direction, and projection 4 is a projection of an active pillar 12D of each transistor in a transistor layer (e.g., a second transistor layer adjacent to the first transistor layer) adjacent to the transistor layer along the first direction. As can be seen from fig. 1D, projections 3 and 4 are partially overlapping.

The projection of the active pillars of the transistors in each of the transistor layers and the transistors in the transistor layers adjacent to the transistor layer in the first direction along the first direction is partially overlapped, that is, the dislocation degree of the transistors in at least two adjacent transistor layers along the first direction is partially misplaced. In this case, the facing area between the active pillars of adjacent transistor layers in the first direction can be reduced. In one aspect, reducing the facing area between active pillars may reduce parasitic capacitance between active pillars in transistors in transistor layers adjacent in the first direction. On the other hand, reducing parasitic capacitance between active pillars in transistors in transistor layers adjacent in the first direction may provide support for reducing the distance between transistor layers adjacent in the first direction. Further, the distance between the adjacent transistor layers along the first direction is reduced to reduce the size occupied by the plurality of transistor layers in the first direction, so that the distribution density of the transistors can be increased, and the integration level of the chip can be improved.

In some embodiments, the transistor layers include a first transistor layer and a second transistor layer adjacent along the first direction, an area where a projection of an active pillar of each transistor in the first transistor layer along the first direction overlaps a projection of an active pillar of each transistor in the second transistor layer along the first direction being a first area; the projected area of the active pillars of the transistors in the first transistor layer along the first direction is a second area; the ratio of the first area to the second area is less than or equal to 1/3. Therefore, parasitic capacitance between active columns can be effectively reduced, the distribution density of the transistor can be better increased, and the integration level of the transistor can be improved.

Fig. 2A is a schematic structural diagram of a memory according to an embodiment of the present disclosure, and referring to fig. 2A, the embodiment of the present disclosure provides a memory, which includes:

a semiconductor structure 100 as described above;

a plurality of capacitors 20, each capacitor 20 of the plurality of capacitors 20 being correspondingly connected with the source 14 or the drain 16 of each active pillar in the semiconductor structure 100 along the third direction.

Here, the memory includes a plurality of capacitors 20, and the plurality of capacitors 20 correspond to a plurality of transistors 11 sequentially arranged along the second direction for each transistor layer 10 in the semiconductor structure 100. Each of the plurality of capacitors is correspondingly connected with the source electrode or the drain electrode of each active column in the semiconductor structure along the third direction. The capacitor may be connected to the source in the active column or to the drain in the active column. In fig. 2A, each capacitor 20 of the plurality of capacitors is correspondingly connected to the drain 16 of each active pillar of the semiconductor structure 100 along the third direction. It will be appreciated that the projections of the active pillars of the transistors in each transistor layer and the transistor layer adjacent to the transistor layer in the first direction along the first direction are offset from each other, and accordingly, the projections of the capacitors in the plane of each transistor layer and the capacitors in the plane of the transistor layer adjacent to the transistor layer in the first direction along the first direction are offset from each other.

In an embodiment of the disclosure, the respective capacitances in the plane of each transistor layer and the respective capacitances in the planes of transistor layers adjacent to the transistor layer in the first direction are offset from each other in the projection of the first direction. The offset capacitances can reduce the facing area between the capacitances in the plane of adjacent transistor layers. In one aspect, the area facing between the capacitances is reduced, so that parasitic capacitance between each capacitance in the plane of the transistor layer adjacent in the first direction and each capacitance in the plane of the transistor layer adjacent in the first direction can be reduced. On the other hand, parasitic capacitance between active pillars in each transistor in the transistor layers adjacent along the first direction is reduced, so that the distance between planes of the transistor layers adjacent along the first direction can be reduced, the size occupied by the transistor layers in the first direction is reduced, the distribution density of the memory can be increased, and the integration level of the memory is improved.

In addition, it should be noted that the connection manner of the capacitor and the active column may be that the capacitor wraps part of the active column, or that the capacitor is directly connected to one end face of the active column.

In some embodiments, each of the capacitors includes a first electrode, a dielectric, and a second electrode; the dielectric surrounds the first electrode, and the second electrode surrounds the dielectric;

each active column further comprises a capacitance contact structure connected with a first end face of the source electrode far away from the drain electrode or a second end face of the drain electrode far away from the source electrode in the active column, and each first electrode surrounds the capacitance contact structure in one active column respectively; or alternatively

A first end face of the source electrode far away from the drain electrode or a second end face of the drain electrode far away from the source electrode in the active column of each transistor is connected with each first electrode.

Here, referring to fig. 2B, fig. 2B is a schematic cross-sectional view of a memory according to an embodiment of the disclosure. As shown in fig. 2B, the dielectric 202 surrounds the first electrodes 201, the second electrodes 203 surround the dielectric 202, and each active pillar further includes a capacitor contact structure 17 connected to a first end surface of the source electrode far from the drain electrode or a second end surface of the drain electrode far from the source electrode in the active pillar, and each first electrode 201 surrounds the capacitor contact structure 17 in one active pillar, that is, the capacitor wraps around the connecting portion of the active pillar.

Referring to fig. 2C, fig. 2C is a schematic cross-sectional view of a memory according to an embodiment of the disclosure. As shown in fig. 2C, the dielectric 202 surrounds the first electrode 201, the second electrode 203 surrounds the dielectric 202, and a first end surface of the source electrode far from the drain electrode or a second end surface of the drain electrode far from the source electrode in the active pillars of the transistors in each transistor is connected with each first electrode 201, that is, the end surfaces of the active pillars are directly connected with the capacitor.

The material of the first electrode and the second electrode may include a metal nitride or a metal silicide, for example, titanium nitride. The material of the dielectric may include at least one of: zirconium oxide, hafnium oxide, titanium zirconium oxide, ruthenium oxide, antimony oxide, and aluminum oxide.

In some embodiments, the memory further comprises:

and a plurality of bit lines, each bit line extending along the first direction, and each bit line being connected to one of the sources or drains of at least one column of the active pillars arranged along the first direction, which is not connected to a capacitor.

Here, a column of active pillars aligned in the first direction is a plurality of active pillars whose projections in the first direction are coincident. For example, referring to fig. 2D, fig. 2D is a schematic cross-sectional view of a memory according to an embodiment of the disclosure. A column of active pillars may be R1 or R2 as in fig. 2D.

In some embodiments, the semiconductor structure includes a first transistor layer and a second transistor layer adjacent in the first direction, the capacitance connected to the active pillars in the first transistor layer being a first capacitance and the capacitance connected to the active pillars in the second transistor layer being a second capacitance; the projection of the first capacitor and the second capacitor along the first direction is non-overlapping;

each of the bit lines is connected to one of the sources or drains of a column of the active pillars arranged in the first direction that is not connected to a capacitance.

Here, the projections of the first and second capacitances along the first direction are non-overlapping, i.e. the first and second capacitances are completely offset along the first direction. Each bit line is connected to the source or drain of a column of active pillars arranged along the first direction. For example, with continued reference to FIG. 2D, as shown in FIG. 2D, each bit line 21 is connected to only one column of active pillars. In some other embodiments, the projections of the first capacitor and the second capacitor along the first direction are non-overlapping, and each bit line is connected to one of the sources or drains of the two columns of active pillars arranged along the first direction, which is not connected to a capacitor.

Here, one end of the active pillar is connected to the capacitor and the other end is connected to the word line. For example, the source at one end of the active pillar is connected to a capacitor and the drain at the other end of the active pillar is connected to a word line.

In some embodiments, the semiconductor structure includes a first transistor layer and a second transistor layer adjacent in the first direction, the capacitance connected to the active pillars in the first transistor layer being a first capacitance and the capacitance connected to the active pillars in the second transistor layer being a second capacitance; the projection of the first capacitance and the second capacitance along the first direction is partially overlapped;

each bit line is connected with one of the sources or drains of two columns of the active pillars adjacent to each other along the second direction, which are arranged along the first direction, and are not connected with a capacitor.

Here, referring to fig. 2E, fig. 2E is a schematic cross-sectional view of a memory according to an embodiment of the disclosure. In an embodiment of the disclosure, the projections of the first capacitor and the second capacitor along the first direction are partially overlapped, i.e. the first capacitor and the second capacitor are partially offset along the first direction. Each bit line is connected to the source or drain of two adjacent columns of active pillars arranged along the first direction. Referring to fig. 2E, each bit line 21 is simultaneously connected to two adjacent columns of active pillars R1 and R2. In the embodiment of the disclosure, the scheme that one bit line covers two rows of active columns is adopted, so that the number of the bit lines can be reduced, and the difficulty of the process is reduced. In some other embodiments, the projections of the first and second capacitances along the first direction are partially overlapped, and each bit line is connected to one of the sources or drains of a column of active pillars arranged along the first direction that is not connected to a capacitance, i.e., each bit line is connected to only one of the sources or drains of a column of active pillars that is not connected to a capacitance.

In some embodiments, the memory further comprises:

and a plurality of word lines, each of which extends along the second direction and is connected to a row of the gates arranged along the second direction.

Here, with continued reference to fig. 2A, one row of gates L1 arranged along the second direction is a plurality of gates arranged along the second direction in each transistor layer, and the plurality of rows of gates L1 are spaced apart from each other along the first direction.

The embodiment of the disclosure provides a method for forming a semiconductor structure, as shown in fig. 3, the method includes the following steps S310 to S320:

Step S310: providing a substrate;

Step S320: forming a plurality of transistor layers spaced apart along a first direction on the substrate; wherein each transistor layer comprises a plurality of transistors sequentially arranged along a second direction; each of the transistors includes an active pillar and a gate; each active column comprises a source electrode, a channel and a drain electrode which are sequentially connected along a third direction, and a grid electrode in each transistor surrounds the channel of the active column in the transistor; the active pillars of the transistors in each transistor layer are offset from the active pillars of the transistors in the transistor layers adjacent to the transistor layer in the first direction, and the projections along the first direction are offset from each other; the first direction, the second direction and the third direction are intersected pairwise.

In some embodiments, step S320 may include the following steps S321 to S322:

step S321: forming a first active structure on the substrate; the first active structure comprises a first supporting layer and a first transistor layer arranged in the first supporting layer;

Step S322: forming a second active structure on the first active structure; the second active structure comprises a second supporting layer and a second transistor layer arranged in the second supporting layer, and the projection of the active pillars of the transistors in the second transistor layer and the projection of the active pillars of the transistors in the first transistor layer along the first direction are staggered with each other.

Fig. 4A is a schematic top view and schematic cross-sectional views of a first active structure formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure, where a1 is a schematic top view of the first active structure, a2 is a schematic cross-sectional view of the first active structure at AA ', a3 is a schematic cross-sectional view of the first active structure at BB', a4 is a schematic cross-sectional view of the first active structure at CC ', and a5 is a schematic cross-sectional view of the first active structure at DD'. As shown in fig. 4A, a first active structure 31 is formed on a substrate 30, the first active structure 31 including a first support layer 311 and a first transistor layer 101 disposed within the first support layer 311, the first transistor layer 101 including a plurality of transistors 11, each transistor 11 including an active pillar 12 and a gate 13. Substrate 30 may be made of a semiconductor material such as one or more of silicon, germanium, silicon germanium compounds, and silicon carbon compounds.

Fig. 4B is a schematic top view and schematic cross-sectional views of a second active structure formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure, where B1 is a schematic top view of the second active structure, B2 is a schematic cross-sectional view of the second active structure at AA ', B3 is a schematic cross-sectional view of the second active structure at BB', B4 is a schematic cross-sectional view of the second active structure at CC ', and B5 is a schematic cross-sectional view of the second active structure at DD'. As shown in fig. 4B, a second active structure 32 is formed on the first active structure 31; the second active structure 32 includes a second support layer 321 and a second transistor layer 102 disposed in the second support layer, where the active pillars 12 of the transistors in the second transistor layer 102 and the active pillars 12 of the transistors in the first transistor layer 101 are offset from each other in a projection along the first direction.

In some embodiments, a third active structure may also be formed on the second active structure, a fourth active structure may be formed on the third active structure, and so on, until a set number of transistor layers is obtained. It is to be appreciated that embodiments of the present disclosure provide a method of forming a multi-layer transistor layer by layer.

In the embodiment of the disclosure, by forming the first active structure and the second active structure which are sequentially and repeatedly arranged along the first direction, two adjacent transistor layers along the first direction can be obtained, and projections of active pillars in the two adjacent transistor layers along the first direction are staggered with each other.

In some embodiments, the step S321 may include the following steps S3211 to S3213:

step S3211: forming a first support layer and a first active column layer arranged in the first support layer; the first active column layer comprises a plurality of active columns which are arranged at intervals along the second direction;

step S3212: etching the first support layer to expose a first channel in each active column in the first active column layer;

Step S3213: and forming a grid electrode surrounding the first channel outside the first channel.

Fig. 4C is a schematic top view and schematic cross-sectional views of a first support layer and a first active pillar layer formed in a method for forming a semiconductor structure according to an embodiment of the disclosure. Wherein c1 is a schematic top view of the first support layer and the first active pillar layer, c2 is a schematic cross-sectional view of the first support layer and the first active pillar layer at AA ', c3 is a schematic cross-sectional view of the first support layer and the first active pillar layer at BB', c4 is a schematic cross-sectional view of the first support layer and the first active pillar layer at CC ', and c5 is a schematic cross-sectional view of the first support layer and the first active pillar layer at DD'. As shown in fig. 4C, a first support layer 311 and a first active post layer 301 disposed within the first support layer 311 are formed on the substrate 30; the first active column layer 301 includes a plurality of active columns 12 therein disposed at intervals along the second direction X.

Here, the first support layer may use an insulating material, for example, silicon dioxide. Forming a first supporting layer and a first active column layer arranged in the first supporting layer, wherein a sub-layer of the first supporting layer, the active layer and the sub-layer of the first supporting layer can be sequentially formed on a substrate; etching the sub-layer of the first support layer, the active layer and the sub-layer of the first support layer along a third direction at a first reference position to form a plurality of grooves which extend along the third direction respectively and are distributed at intervals along a second direction; the active layer is divided into first active pillars extending along a third direction and spaced apart along a second direction by the spaced apart grooves. In some embodiments, after the first support layer and the first active pillar layer are formed, the grooves formed during the preparation of the first active pillar may be filled with an insulating material by depositing the insulating material.

Etching the first support layer to expose the first channel in each of the active pillars in the first active pillar layer, referring to fig. 4D, fig. 4D is a schematic top view of the first channel and schematic cross-sectional views of different cross-sections formed in the method for forming a semiconductor structure according to an embodiment of the disclosure. Wherein d1 is a schematic top view of the first channel, d2 is a schematic cross-sectional view of the first channel at AA ', d3 is a schematic cross-sectional view of the first channel at BB', d4 is a schematic cross-sectional view of the first channel at CC ', and d5 is a schematic cross-sectional view of the first channel at DD'. As shown in fig. 4D, the opening area 312 is defined in a top view, and the opening area 312 extends in the second direction. The portion of the first support layer corresponding to the opening area 312 is etched away, exposing the first channel 151 in each of the active pillars in the first active pillar layer 301.

Outside the exposed first channel, a gate material, such as polysilicon, a metal conductive material, etc., is deposited to form a gate around the first channel, which may be referred to as gate 13 in fig. 4A.

The above step S322 may include the following steps S3221 to S3223:

Step S3221: forming a second support layer and a second active column layer arranged in the second support layer; the second active column layer comprises a plurality of active columns which are arranged at intervals along the second direction; the projections of each active column in the second active column layer and each active column in the first active column layer along the first direction are staggered;

Step S3222: etching the second support layer to expose a second channel in each active column in the second active column layer;

step S3223: and forming a grid electrode surrounding the second channel outside the second channel.

Here, in the steps S3221 to S3223, similar to the methods of the steps S3211 to S3213 described above, it should be noted that, in the step of forming the second support layer and the second active pillar layer disposed in the second support layer, the sub-layer of the second support layer, the active layer, and the sub-layer of the second support layer are formed on the first support layer; etching the sub-layer of the second support layer, the active layer and the sub-layer of the second support layer along a third direction at a second reference position to form a plurality of grooves extending along the third direction and distributed at intervals along the second direction; the second reference position is offset relative to the first reference position along the second direction or the opposite direction of the second direction, and the offset is smaller than the maximum size of the active column along the second direction. The projections of the active pillars in the second active pillar layer and the first active pillar layer along the first direction are offset from each other. The embodiments of the present disclosure may form semiconductor structures in which the projections of the active pillars in each of the adjacent multilayer transistor layers along the first direction are offset from each other along the first direction.

In some embodiments, the step S320 may further include the following steps S323 to S327:

Step S323: forming a third supporting layer and a plurality of sacrificial structure layers arranged in the third supporting layer at intervals along a first direction; wherein each sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction; each sacrificial structure in each sacrificial structure layer is staggered with each sacrificial structure in the sacrificial structure layer adjacent to the sacrificial structure layer along the first direction;

step S324: etching to remove each sacrificial structure to form a plurality of through hole layers distributed at intervals along the first direction; wherein each through hole layer comprises a plurality of through holes which are arranged at intervals along the second direction;

step S325: filling and forming a plurality of active column layers which are arranged at intervals along a first direction in each through hole of each through hole layer;

Step S326: etching the third supporting layer to expose a third channel of each active column in each active column layer;

step S327: and forming a grid electrode surrounding the third channel outside the third channel.

Here, the material of the third support layer may include, but is not limited to, an insulating material such as silicon oxide. The material of the sacrificial structure layer may include, but is not limited to, a suitable material such as nitride, for example, silicon nitride. The sacrificial structures are etched away, for example, a wet etch may be used to remove all of the sacrificial structures.

The embodiment of the disclosure provides a method for forming active column layers which are distributed at intervals along a first direction and then forming a plurality of transistor layers.

In some embodiments, the step S323 may include the following steps S3231 to S3232:

step S3231: forming a first support sub-layer on the substrate and a first sacrificial structure layer arranged in the first support sub-layer; the first sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction;

Step S3232: forming a second support sub-layer and a second sacrificial structure layer arranged in the second support sub-layer on the first support sub-layer; the second sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction; the projections of the sacrificial structures in the second sacrificial structure layer and the sacrificial structures in the first sacrificial structure layer along the first direction are offset from each other.

Here, the first sacrificial layer material may be nitride, for example, silicon nitride. Referring to fig. 4E, fig. 4E is a schematic structural diagram of forming a first support sub-layer and a first sacrificial structure layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure, where E1 is a top view of the first support sub-layer and the first sacrificial structure layer, and E2 is a schematic sectional view of the first support sub-layer and the first sacrificial structure layer along a plane perpendicular to a third direction. A first support sub-layer 3311 and a first sacrificial structure layer 332 disposed within the first support sub-layer are formed over the substrate. The method of forming the first support sub-layer and the first sacrificial structure layer may be to deposit the first support sub-layer 3311 on the substrate; and etching the first support sub-layer at the first reference position along the third direction to form a plurality of grooves extending along the third direction and distributed at intervals along the second direction, and filling the grooves with a first sacrificial layer material to form a plurality of sacrificial structures 3321 distributed at intervals along the second direction. In some other embodiments, the first support sub-layer and the first sacrificial structure layer may also be formed with reference to the above-described forming manner of forming the first support layer and the first active layer disposed in the first support layer.

The process of step 3232 is similar to step 3231, and the second support sub-layer and the second sacrificial structure layer may be formed as described above with reference to step 3231. Regarding the method of forming the second sacrificial structure layer in which projections of the sacrificial structures and the first sacrificial structure layer in the first direction are offset from each other, similar to step S3221 described above, the second reference position is set to be offset in the second direction or the opposite direction of the second direction with respect to the first reference position by an amount smaller than the maximum dimension of the active column in the second direction. Referring to fig. 4F, fig. 4F is a schematic structural diagram of forming a second support sub-layer and a second sacrificial structure layer in a method for forming a semiconductor structure according to an embodiment of the disclosure, where F1 is a top view of the second support sub-layer and the second sacrificial structure layer, and F2 is a schematic sectional view of the second support sub-layer and the second sacrificial structure layer along a plane perpendicular to a third direction. As shown in fig. 4F, a second support sub-layer 3312 and a second sacrificial structure layer 333 disposed within the second support sub-layer 3312 are formed on the first support sub-layer 3311.

In some embodiments, a third support sub-layer and a third sacrificial structure layer may also be formed on the second support sub-layer, a fourth support sub-layer and a fourth sacrificial structure layer may be formed on the third support sub-layer and the third sacrificial structure layer, and so on, until a set number of crystalline sacrificial structure layers are obtained. With continued reference to fig. 4F, by the above method, a third support layer 331 and a plurality of sacrificial structure layers 332 or 333 disposed within the third support layer 331 at intervals along the first direction are formed. It is to be appreciated that the disclosed embodiments provide a method of forming sacrificial structure layers layer by layer.

Fig. 4G is a schematic structural diagram of a through hole layer formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure, where G1 is a top view of the through hole layer, and G2 is a schematic sectional view of the through hole layer along a plane perpendicular to a third direction. As shown in fig. 4G, each sacrificial structure is etched to form a plurality of via layers 334 spaced apart along the first direction; wherein each of the via layers 334 includes a plurality of vias arranged at intervals along the second direction.

Filling active layer materials in each through hole of each through hole layer to form a plurality of active column layers which are arranged at intervals along a first direction; defining an opening area for the third supporting layer, wherein the opening area is positioned at a corresponding position of the channel along a third direction and extends along a first direction and a second direction; etching the opening area defined by the third supporting layer to expose a third channel of each active column in each active column layer; and forming a grid electrode surrounding the third channel outside the third channel.

The embodiment of the disclosure provides a method for forming a memory, as shown in fig. 5, the method for forming a memory includes the following steps S510 to S520:

Step S510: providing a substrate;

step S520: forming a semiconductor structure and a plurality of capacitors on the surface of the substrate; each capacitor of the plurality of capacitors is correspondingly connected with the source electrode or the drain electrode of each active column of the semiconductor structure along the third direction.

In some embodiments, each of the active pillars further includes a capacitive contact structure therein connected to either a first end of the source in the active pillar remote from the drain or a second end of the drain remote from the source; step S520 may include the following steps S5211 to S5213:

Step S5211: forming a fourth support layer and a plurality of transistor layers arranged in the fourth support layer at intervals along a first direction on the surface of the substrate;

Step S5212: etching and removing part of the fourth supporting layer to expose the capacitance contact structure in each active column;

Step S5213: a first electrode surrounding the capacitor contact structure, a dielectric surrounding the first electrode, and a second electrode surrounding the dielectric are sequentially formed on the surface of each capacitor contact structure.

Here, the formation of the fourth support layer on the surface of the substrate and the plurality of transistor layers disposed in the fourth support layer at intervals along the first direction may be referred to the formation method for forming the semiconductor structure described above. For example, the above-described method of forming a plurality of transistor layers layer by layer, or a method of forming active column layers spaced apart in the first direction and then forming a plurality of transistor layers may be used. Accordingly, the fourth support layer may correspond to the first support layer and the second support layer repeatedly arranged along the first direction by the above method, and may also correspond to the third support layer formed by the above method, and the specific forming process is described with reference to the above explanation.

The step of etching away a portion of the fourth support layer to expose the capacitive contact structure in each of the active pillars may include: defining an opening area for the fourth supporting layer, wherein the opening area is positioned at a position corresponding to the capacitance contact structure along a third direction and extends along a first direction and a second direction; the open area defined in the fourth support layer is etched to remove a portion of the fourth support layer to expose the capacitive contact structures in each active pillar (e.g., capacitive contact structure 17 in fig. 2B).

With continued reference to fig. 2B, a first electrode 201 surrounding the capacitive contact structure, a dielectric 202 surrounding the first electrode 201, and a second electrode 203 surrounding the dielectric 202 are formed in sequence on each capacitive contact structure surface.

In some embodiments, with continued reference to fig. 2B, after forming the first electrode, dielectric, and second electrode, further comprising filling a conductive material outside the second electrode to form a first fill region 410, such as filled polysilicon.

The embodiment of the disclosure provides a method for forming a memory, which sequentially forms a transistor layer and a capacitor, wherein the connection mode of the capacitor and an active column corresponds to the embodiment of the capacitor wrapping part active column in the embodiment of the memory.

In some embodiments, step S520 may further include the following steps S5221 to S5225:

step S5221: forming a fifth supporting layer on the surface of the substrate, a plurality of transistor layers arranged in the fifth supporting layer at intervals along a first direction, and a third sacrificial structure connected with a first end surface of a source electrode far away from a drain electrode or a second end surface of the drain electrode far away from the source electrode in each active column in the transistor layers;

step S5222: etching to remove the third sacrificial structures corresponding to each active column, and forming first openings corresponding to each active column respectively;

Step S5223: filling each first opening corresponding to each active column to form a first electrode corresponding to the active column;

Step S5224: etching and removing part of the fifth supporting layer to expose each first electrode of the capacitance area;

Step S5225: a dielectric surrounding the first electrode and a second electrode surrounding the dielectric are sequentially formed on the surface of each first electrode.

Here, the fifth supporting layer, the plurality of transistor layers disposed in the fifth supporting layer at intervals along the first direction, and the third sacrificial structure connected to the first end surface of the source electrode far from the drain electrode or the second end surface of the drain electrode far from the source electrode in each of the transistor layers may be formed on the surface of the substrate, and it should be noted that the third sacrificial structure may be a sacrificial structure corresponding to each of the active pillars in each of the transistor layers, that is, the size of each of the active pillars may be prolonged in the preparation process to obtain each of the active pillars and the sacrificial structure corresponding thereto. The third sacrificial structure may also be other materials in some embodiments, such as silicon nitride. In the preparation process, sacrificial materials such as silicon nitride and the like are filled in the sacrificial structure positions, and the active column is formed at the source electrode, the channel and the drain electrode positions of the active column through deposition.

Etching to remove the third sacrificial structures corresponding to each active column to form first openings corresponding to each active column respectively; filling a first electrode corresponding to each active column in each first opening corresponding to each active column; etching to remove part of the fifth supporting layer to expose each first electrode of the capacitor region; a dielectric surrounding the first electrode and a second electrode surrounding the dielectric are sequentially formed on the surface of each first electrode.

The embodiment of the disclosure provides a method for forming a memory, which sequentially forms a transistor layer and a capacitor, wherein the connection mode of the capacitor and an active column corresponds to that of the capacitor in the embodiment of the memory and is directly connected with the end face of the active column.

In some embodiments, step S520 may further include the following steps S5231 to S5235:

Step S5231: forming a sixth support layer on the surface of the substrate, a plurality of active column layers arranged in the sixth support layer at intervals along a first direction, and a fourth sacrificial structure connected with a first end surface of a source electrode far away from a drain electrode or a second end surface of the drain electrode far away from the source electrode in each active column layer; each active column layer comprises a plurality of active columns which are arranged at intervals along a second direction; the semiconductor structure comprises a first active column layer and a second active column layer which are adjacent along the first direction, wherein the projection of each first active column in the first active column layer and each second active column in the second active column layer along the first direction is staggered;

Step S5232: etching to remove the fourth sacrificial structure corresponding to each active column in the active column layer, and forming a second opening corresponding to each active column in all the active column layers;

Step S5233: filling each second opening corresponding to each active column to form a first electrode corresponding to each active column; etching and removing part of the sixth supporting layer to expose each first electrode of the capacitance area; sequentially forming a dielectric surrounding one first electrode and a second electrode surrounding the dielectric on the surface of each first electrode;

Step S5234: etching the sixth support layer to expose the fourth channel of each active column in each active column layer;

step S5235: and forming a grid electrode surrounding the fourth channel outside the fourth channel.

Here, a sixth support layer, a plurality of active pillar layers disposed in the sixth support layer at intervals along a first direction, and a fourth sacrificial structure connected to a first end surface of the source electrode far from the drain electrode or a second end surface of the drain electrode far from the source electrode in each of the active pillar layers may be formed on the surface of the substrate.

Etching to remove the fourth sacrificial structure corresponding to each active column in the active column layer to form a second opening corresponding to each active column in all the active column layers; filling each first opening corresponding to each active column to form a first electrode corresponding to the active column; and etching and removing part of the fifth supporting layer to expose each first electrode of the capacitance region.

The embodiment of the disclosure provides a method for forming a memory, which sequentially forms active pillars, capacitors and gates which are distributed at intervals along a first direction, wherein the connection mode of the formed capacitors and the active pillars corresponds to the condition that the capacitors in the embodiment of the memory are directly connected with the end surfaces of the active pillars.

In some embodiments, the method of forming a memory further comprises:

Step S530: forming a plurality of bit lines extending along the first direction; each bit line is connected with one end, which is not connected with a capacitor, of a source electrode or a drain electrode of at least one column of the active columns arranged along the first direction;

step S540: and forming a plurality of word lines, wherein each word line extends along the second direction and is connected with one row of the gates arranged in the second direction.

Here, forming a plurality of bit lines extending in the first direction may continue with reference to fig. 2D or 2E. As shown in fig. 2D or 2E, a plurality of bit lines 21 extending in the first direction X are formed; each bit line 21 is connected to one end of the source or drain of at least one column of the active pillars arranged in the first direction X, which is not connected to a capacitor;

In addition, referring to fig. 6, fig. 6 is a schematic structural diagram of forming a word line in a method for forming a memory according to an embodiment of the disclosure. As shown in fig. 6, each gate 13 surrounds the channel 15, forming a plurality of word lines 22 connected to one row of the gates 13 arranged in the second direction X, each of the word lines 22 extending in the second direction X. A gate oxide layer 18 is provided between the gate electrode 13 and the channel 15, and the gate oxide layer is made of an insulating material, for example, a low dielectric constant material such as silicon oxide or silicon nitride.

The material of the word lines and bit lines includes, but is not limited to, at least one of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, and the like.

In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The above-described structural embodiments are merely illustrative, and for example, the division of the units is merely a logic function division, and there may be other division manners in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the components shown or discussed are coupled to each other or directly.

Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.

While the foregoing is directed to embodiments of the present disclosure, the scope of the embodiments of the present disclosure is not limited to the foregoing, and any changes and substitutions that are within the scope of the embodiments of the present disclosure will be readily apparent to those skilled in the art.

Claims

1. A semiconductor structure, comprising:

a plurality of transistor layers spaced apart along a first direction; wherein,

2. The semiconductor structure of claim 1, wherein the active pillars of transistors in each of the transistor layers and the active pillars of transistors in transistor layers adjacent to the transistor layer in the first direction are non-overlapping in projection along the first direction.

3. The semiconductor structure of claim 1, wherein the active pillars of transistors in each of the transistor layers and the active pillars of transistors in transistor layers adjacent to the transistor layer in the first direction are partially overlapping in projection along the first direction.

4. The semiconductor structure of claim 3, wherein the transistor layers include a first transistor layer and a second transistor layer adjacent in the first direction, wherein an area where a projection of an active pillar of each transistor in the first transistor layer in the first direction overlaps with a projection of an active pillar of each transistor in the second transistor layer in the first direction is a first area; the projected area of the active pillars of the transistors in the first transistor layer along the first direction is a second area; the ratio of the first area to the second area is less than or equal to 1/3.

5. A memory, comprising:

the semiconductor structure of any one of claims 1 to 4;

6. The memory of claim 5, further comprising:

7. The memory of claim 6, wherein the semiconductor structure includes a first transistor layer and a second transistor layer adjacent in the first direction, a capacitance connected to an active pillar in the first transistor layer being a first capacitance, a capacitance connected to an active pillar in the second transistor layer being a second capacitance; the projection of the first capacitor and the second capacitor along the first direction is non-overlapping;

8. The memory of claim 6, wherein the semiconductor structure includes a first transistor layer and a second transistor layer adjacent in the first direction, a capacitance connected to an active pillar in the first transistor layer being a first capacitance, a capacitance connected to an active pillar in the second transistor layer being a second capacitance; the projection of the first capacitance and the second capacitance along the first direction is partially overlapped;

each bit line is connected with one of the sources or drains of two adjacent columns of the active pillars arranged along the first direction, which is not connected with a capacitor.

9. The memory according to any one of claims 5 to 6, characterized in that the memory further comprises:

10. The memory of claim 5, wherein each of the capacitors comprises a first electrode, a dielectric, and a second electrode;

the dielectric surrounds the first electrode, and the second electrode surrounds the dielectric;

11. A method of forming a semiconductor structure, comprising:

Providing a substrate;

12. The method of forming a semiconductor structure of claim 11, wherein forming a plurality of transistor layers spaced apart along a first direction on the substrate comprises:

Forming a first active structure on the substrate; the first active structure comprises a first supporting layer and a first transistor layer arranged in the first supporting layer;

forming a second active structure on the first active structure; the second active structure comprises a second supporting layer and a second transistor layer arranged in the second supporting layer, and the projection of the active pillars of the transistors in the second transistor layer and the projection of the active pillars of the transistors in the first transistor layer along the first direction are staggered with each other.

13. The method of claim 12, wherein forming a first active structure on the substrate comprises:

Forming a first support layer and a first active column layer arranged in the first support layer; the first active column layer comprises a plurality of active columns which are arranged at intervals along the second direction;

Etching the first support layer to expose a first channel in each active column in the first active column layer;

Forming a gate surrounding the first channel outside the first channel;

the forming a second active structure on the first active structure includes:

forming a second support layer and a second active column layer arranged in the second support layer; the second active column layer comprises a plurality of active columns which are arranged at intervals along the second direction; the projections of each active column in the second active column layer and each active column in the first active column layer along the first direction are staggered;

etching the second support layer to expose a second channel in each active column in the second active column layer;

and forming a grid electrode surrounding the second channel outside the second channel.

14. The method of forming a semiconductor structure of claim 11, wherein forming a plurality of transistor layers spaced apart along a first direction on the substrate comprises:

forming a third supporting layer and a plurality of sacrificial structure layers arranged in the third supporting layer at intervals along a first direction; wherein each sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction; each sacrificial structure in each sacrificial structure layer is offset from each other in projection along a first direction with each sacrificial structure in a sacrificial structure layer adjacent to the sacrificial structure layer in the first direction;

etching to remove each sacrificial structure to form a plurality of through hole layers distributed at intervals along the first direction; wherein each through hole layer comprises a plurality of through holes which are arranged at intervals along the second direction;

filling and forming a plurality of active column layers which are arranged at intervals along a first direction in each through hole of each through hole layer;

Etching the third supporting layer to expose a third channel of each active column in each active column layer;

and forming a grid electrode surrounding the third channel outside the third channel.

15. The method of claim 14, wherein the third support layer comprises a first support sub-layer and a second support sub-layer, the forming the third support layer and the plurality of sacrificial structure layers disposed within the third support layer at intervals along the first direction comprising:

Forming a first support sub-layer on the substrate and a first sacrificial structure layer arranged in the first support sub-layer; the first sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction;

Forming a second support sub-layer and a second sacrificial structure layer arranged in the second support sub-layer on the first support sub-layer; the second sacrificial structure layer comprises a plurality of sacrificial structures which are arranged at intervals along the second direction; the projections of the sacrificial structures in the second sacrificial structure layer and the sacrificial structures in the first sacrificial structure layer along the first direction are offset from each other.

16. A method of forming a memory, comprising:

Providing a substrate;

forming a semiconductor structure as claimed in any one of claims 1 to 4, and a plurality of capacitors on a surface of the substrate; each capacitor of the plurality of capacitors is correspondingly connected with the source electrode or the drain electrode of each active column of the semiconductor structure along the third direction.

17. The method of claim 16, further comprising a capacitor contact structure in each of the active pillars connected to a first end of the source electrode in the active pillar away from the drain electrode or a second end of the drain electrode away from the source electrode; the forming the semiconductor structure of any one of claims 1 to 4 located in the transistor region and the plurality of capacitors located in the capacitor region on the substrate surface, comprising:

Forming a fourth support layer and a plurality of transistor layers arranged in the fourth support layer at intervals along a first direction on the surface of the substrate;

Etching and removing part of the fourth supporting layer to expose the capacitance contact structure in each active column;

A first electrode surrounding the capacitor contact structure, a dielectric surrounding the first electrode, and a second electrode surrounding the dielectric are sequentially formed on the surface of each capacitor contact structure.

18. The method of forming a memory device according to claim 16, wherein forming the semiconductor structure according to any one of claims 1 to 4 in the transistor region and the plurality of capacitors in the capacitor region on the substrate surface comprises:

Forming a fifth supporting layer on the surface of the substrate, a plurality of transistor layers arranged in the fifth supporting layer at intervals along a first direction, and a third sacrificial structure connected with a first end surface of a source electrode far away from a drain electrode or a second end surface of the drain electrode far away from the source electrode in each active column in the transistor layers;

Etching to remove the third sacrificial structures corresponding to each active column, and forming first openings corresponding to each active column respectively;

Filling each first opening corresponding to each active column to form a first electrode corresponding to the active column;

etching and removing part of the fifth supporting layer to expose each first electrode of the capacitance area;

a dielectric surrounding the first electrode and a second electrode surrounding the dielectric are sequentially formed on the surface of each first electrode.

19. The method of forming a memory device according to claim 16, wherein forming the semiconductor structure according to any one of claims 1 to 4 in the transistor region and the plurality of capacitors in the capacitor region on the substrate surface comprises:

Forming a sixth support layer on the surface of the substrate, a plurality of active column layers arranged in the sixth support layer at intervals along a first direction, and a fourth sacrificial structure connected with a first end surface of a source electrode far away from a drain electrode or a second end surface of the drain electrode far away from the source electrode in each active column layer; each active column layer comprises a plurality of active columns which are arranged at intervals along a second direction; the semiconductor structure comprises a first active column layer and a second active column layer which are adjacent along the first direction, wherein the projection of each first active column in the first active column layer and each second active column in the second active column layer along the first direction is staggered;

etching to remove the fourth sacrificial structure corresponding to each active column in the active column layer, and forming a second opening corresponding to each active column in all the active column layers;

Filling each second opening corresponding to each active column to form a first electrode corresponding to each active column; etching and removing part of the sixth supporting layer to expose each first electrode of the capacitance area; sequentially forming a dielectric surrounding one first electrode and a second electrode surrounding the dielectric on the surface of each first electrode;

Etching the sixth support layer to expose the fourth channel of each active column in each active column layer;

and forming a grid electrode surrounding the fourth channel outside the fourth channel.

20. The method of forming a memory of claim 16, further comprising:

Forming a plurality of bit lines extending along the first direction; each bit line is connected with one end, which is not connected with a capacitor, of a source electrode or a drain electrode of at least one column of the active columns arranged along the first direction;

and forming a plurality of word lines, wherein each word line extends along the second direction and is connected with one row of the gates arranged in the second direction.