CN117973304A - Layout and design method thereof, semiconductor structure, storage medium and electronic equipment - Google Patents
Layout and design method thereof, semiconductor structure, storage medium and electronic equipment Download PDFInfo
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- CN117973304A CN117973304A CN202211303746.0A CN202211303746A CN117973304A CN 117973304 A CN117973304 A CN 117973304A CN 202211303746 A CN202211303746 A CN 202211303746A CN 117973304 A CN117973304 A CN 117973304A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/02—System on chip [SoC] design
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Abstract
A layout and a design method thereof, a semiconductor structure, a storage medium and an electronic device. The layout corresponds to a semiconductor structure comprising: a second power line and a signal line. The layout comprises a plurality of standard units, wherein the standard units comprise: and the second power line pattern corresponds to the second power line. The second power line pattern is located on a second metal layer of the layout. The layout design method comprises the following steps: calculating the winding difficulty of the standard unit; marking a standard unit with winding difficulty greater than a difficulty threshold as a unit to be processed; removing the second power line pattern in the unit to be processed to form a region to be filled; and setting a signal line pattern in the region to be filled, wherein the signal line pattern corresponds to the signal line.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a low layout and a design method thereof, a semiconductor structure, a computer-readable storage medium, and an electronic device.
Background
Currently, a mainstream System On Chip (SOC) design uses a standard cell library to integrate and place and route based on logic codes, and thus, a PPA index of a final SOC is determined by a speed power consumption area (PPA) index of the standard cell library. In Low power consumption and high density designs, a Low height (Low track) cell library is often used for the design.
In practical designs, the power and ground networks formed by metal lines have parasitic resistances, and the current generated during the operation of the chip can cause a voltage drop (IR drop) across the network, resulting in poor timing, which is particularly serious in the prior art. As shown in fig. 1, the first cell X1 and the second cell X2 are connected between the first power line VDD and the second power line VSS, and the voltage actually reaching the second cell X2 is VDD- Δv1- Δv2, where VDD represents the voltage of the first power line VDD, Δv1 represents the voltage drop caused by the parasitic resistance of the first power line VDD before the first cell X1, and Δv2 represents the voltage drop caused by the parasitic resistance of the first power line VDD between the first cell X1 and the second cell X2.
In order to reduce the impedance of the power and ground networks, the power lines are typically arranged in a stacked parallel configuration during layout design. As shown in fig. 2, the power line to which the same power voltage is inputted is designed as two stacked power line patterns, namely, a power line pattern 11 located in a first metal layer and a power line pattern 12 located in a second metal layer, the power line pattern 11 and the power line pattern 12 being connected in parallel by a connector pattern 13. The power lines corresponding to the power line patterns 11 and 12 are adapted to input a power voltage or a ground voltage. However, this structure is prone to cause problems of integration density, resulting in difficulty in outgoing lines of input and output pins, waste of wiring resources, etc., and the layout and wiring tool usually solves the technical problem by expanding a large area, but this loses the advantage of adopting a low-height cell library design.
Disclosure of Invention
The invention solves the problem that the integration density in the existing layout is too high, which causes the increase of the layout area.
In order to solve the problems, the invention provides a design method of a layout, and the layout corresponds to a semiconductor structure. The semiconductor structure includes: a second power line and a signal line. The layout includes a number of standard cells. The standard cell includes: and a second power line pattern. The second power line pattern corresponds to the second power line. The second power line pattern is located on a second metal layer of the layout. The layout design method comprises the following steps: calculating the winding difficulty of the standard unit; marking a standard unit with winding difficulty greater than a difficulty threshold as a unit to be processed; removing the second power line pattern in the unit to be processed to form a region to be filled; and setting a signal line pattern in the region to be filled, wherein the signal line pattern corresponds to the signal line.
The invention also provides a layout. The layout corresponds to a semiconductor structure comprising: a second power line and a signal line. The layout comprises: a second power line pattern and a signal line pattern. The second power line pattern corresponds to the second power line, and is located on the second metal layer of the layout, and the second power line pattern is arranged in a discontinuous strip mode. The signal line pattern corresponds to the signal line, and the signal line pattern is located in the intermittent gap of the second power line pattern.
The invention also provides a semiconductor structure which is formed according to the layout.
The present invention also provides a computer-readable storage medium having stored thereon a computer program for execution by a processor to perform the steps of the layout design method described above.
The invention also provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the steps of the layout design method when running the computer program.
Compared with the prior art, the technical scheme of the invention has the following advantages:
According to the invention, the standard unit with tension winding is found out by calculating the winding difficulty, and the space is released to the signal line pattern by removing the second power line pattern in the standard unit, so that the whole impedance of the power line is not greatly influenced, and the problem of overlarge layout area caused by overlarge integration density can be solved.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit;
FIG. 2 is a schematic diagram of a standard cell configuration;
FIG. 3 is a flow chart of a layout design method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a layout structure according to an embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
The embodiment of the invention provides a design method of a layout, wherein the layout corresponds to a semiconductor structure, and the semiconductor structure comprises the following components: a second power line and a signal line. The layout comprises a plurality of standard units, and the standard units comprise second power line patterns. The second power line pattern corresponds to a second power line of the semiconductor structure and is positioned on a second metal layer of the layout.
Referring to fig. 3, the layout design method of the present embodiment includes:
step S1, calculating winding difficulty of a standard unit;
s2, marking a standard unit with winding difficulty greater than a difficulty threshold as a unit to be processed;
Step S3, removing the second power line pattern in the unit to be processed to form a region to be filled;
Step S4, setting a signal line pattern in the region to be filled, wherein the signal line pattern corresponds to the signal line in the semiconductor structure.
The design method is further described below in connection with the structure of the layout. As shown in fig. 4, the layout includes standard cells T1 and T2. The standard cell T1 includes a second power line pattern 221 located at the second metal layer, and the standard cell T2 includes a second power line pattern (not shown) connected to the second power line pattern 221.
In step S1, the winding difficulty of the standard cell T1 and the standard cell T2 is calculated. The calculation formula of the winding difficulty is as follows:
(pin number used channel number)/(width height) equation 1
In equation 1, the pin number indicates the number of input/output pins in the standard cell, for example, it may refer to the number of input/output pins necessary in the standard cell, the number of channels has been used to indicate the number of signal channels used in the standard cell, the width indicates the width of the standard cell, and the height indicates the height of the standard cell.
Generally, the greater the number of input/output pins in a standard cell, the greater the number of signal channels used, both of which are linearly related. The heights of the standard cell T1 and the standard cell T2 are 6.
Assuming that the standard cell T1 includes an inverter, the number of pins required is 2, the number of used channels is 0, the width is 2, and the winding difficulty calculated according to equation 1 is 0.
The standard cell T2 includes nor gates, which require 5 pins, 5 channels, 5 widths, and 0.83 winding difficulty calculated according to equation 1. And S1, obtaining the winding difficulty of all standard units in the layout.
In step S2, the winding difficulty of the standard cell is compared with a difficulty threshold, which may range from 0.4 to 1. After comparison, marking the standard unit with the winding difficulty greater than the difficulty threshold as a unit to be processed.
Assuming that the difficulty threshold is 0.5, the winding difficulty of the standard unit T1 is 0 and is smaller than the difficulty threshold of 0.5. The winding difficulty of the standard cell T2 is 0.83 and is greater than the difficulty threshold value of 0.5. At this time, the standard cell T2 may be marked as a unit to be processed through step S2. The labeling method can be set by parameters of layout design software and the like.
In step S3, the second power line pattern (not shown) connected to the second power line pattern 221 in the standard cell T2 is removed to form the region to be filled 222.
Through step S4, the signal line pattern 31 is provided in the standard cell T2, the signal line pattern 31 corresponding to the signal line in the semiconductor structure.
By the above method, the signal line pattern 31 can be disposed in the region where the second power line pattern originally present in the standard cell T2 is located. Therefore, the embodiment finds out the standard unit with tense winding by calculating the winding difficulty, and releases the space to the signal line graph by removing the second power line graph in the standard unit, so that the overall impedance of the power line is not greatly influenced, and the problem of overlarge layout area caused by overlarge integration density can be solved.
The semiconductor structure further includes: the first power line and the first connecting piece, corresponding to the first power line and the first connecting piece, the standard unit further comprises: a first power line pattern 21 and a first connector pattern 41. The first power line pattern 21 corresponds to a first power line of the semiconductor structure. The first connector pattern 41 corresponds to a first connector of a semiconductor structure.
The first power line pattern 21 is located at a first metal layer of the layout. The first power line pattern 21 and the second power line pattern 221 are connected in parallel through the first connector pattern 41, thereby reducing the overall impedance of the power lines. The first power line and the second power line are adapted to input the same voltage, such as a power voltage or a ground voltage.
The semiconductor structure may further include: the active region and the second connection member, corresponding thereto, the standard cell further comprises: an active area pattern 51 and a second connector pattern 42. The active region pattern 51 corresponds to an active region of the semiconductor structure, the second connection pattern 42 corresponds to a second connection of the semiconductor structure, and the active region pattern 51 is connected to the first power line pattern 21 through the second connection pattern 42.
It is to be understood that the first metal layer and the second metal layer described in this embodiment are a specific concept in layout design by those skilled in the art, and represent the first metal wiring layer and the second metal wiring layer, which have association relationships with other layers, and not any metal layer is equivalent to the first metal layer and the second metal layer.
In the layout, the first metal layer and the second metal layer belong to the bottom metal layout layer, so that the parallel structure of the first power line pattern 21 and the second power line pattern 221 causes difficult wire outgoing of the input/output pins, and winding resources are wasted. By using the technical scheme of the embodiment, the signal line pattern 31 is arranged in the area where the second power line pattern originally existing in the standard cell T2 is located, so that the overall impedance of the power line is not greatly affected, and the signal line pattern can be arranged by utilizing the space of part of the second power line pattern, thereby solving the problem of overlarge layout area caused by overlarge integration density.
Further, the present embodiment uses the second power line pattern 221 to release space without adopting the first power line pattern 21, because: the present inventors have found that most of the power connection is achieved by the first power line pattern 21, and that if the signal lines are provided by freeing up space in the first power line pattern 21, it is not easy to alleviate the problem of high integration density.
With continued reference to fig. 4, this embodiment provides a layout formed by the above-described design method, the layout including: a second power line pattern 221 and a signal line pattern 31.
The second power line pattern 221 is located on the second metal layer of the layout, and the second power line pattern is arranged in a discontinuous strip shape. The signal line pattern 31 is located in the intermittent gap of the second power line pattern 221.
The layout comprises a plurality of standard units, and the winding difficulty of the standard units where the signal lines are located is greater than a difficulty threshold. The calculation formula of the winding difficulty is as follows:
(pin number used channel number)/(width height) equation 1
The pin number represents the number of input and output pins in the standard unit, the number of signal channels used in the standard unit is represented by the number of channels, the width represents the width value of the standard unit, and the height represents the height value of the standard unit. The difficulty threshold may range from 0.4 to 1.
The layout further comprises: a first power line pattern 21 and a first connector pattern 41. The first power line pattern 21 and the second power line pattern 221 are connected in parallel through the first connector pattern 41.
The layout further comprises: an active area pattern 51 and a second connector pattern 42. The active region pattern 51 is connected to the first power line pattern 21 through the second connection member pattern 42.
The layout and the design method thereof provided in this embodiment are corresponding, and reference is made to the description of the design method for the details of the layout, which is not repeated here.
The embodiment of the invention also provides a semiconductor structure which is formed according to the layout.
Still another embodiment of the present invention provides a computer readable storage medium having stored thereon a computer program to be executed by a processor to implement the steps of the layout design method described above.
The embodiment of the invention also provides electronic equipment, which comprises a memory and a processor, wherein the memory stores a computer program capable of running on the processor, and the processor executes the steps of the layout design method when running the computer program.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of designing a layout, the layout corresponding to a semiconductor structure, the semiconductor structure comprising: the layout comprises a plurality of standard units, wherein each standard unit comprises: the second power line graph corresponds to the second power line, and is located on a second metal layer of the layout, and the layout design method is characterized by comprising the following steps: calculating the winding difficulty of the standard unit;
Marking a standard unit with winding difficulty greater than a difficulty threshold as a unit to be processed;
Removing the second power line pattern in the unit to be processed to form a region to be filled;
And setting a signal line pattern in the region to be filled, wherein the signal line pattern corresponds to the signal line.
2. The layout design method according to claim 1, wherein the calculation formula of the winding difficulty is:
(pin number used channel number)/(width height);
Wherein the pin number represents the number of input/output pins in the standard cell, the used channel number represents the number of signal channels used in the standard cell, the height represents the width of the standard cell, and the height represents the height of the standard cell.
3. The layout design method according to claim 1, wherein the difficulty threshold is in the range of 0.4-1.
4. The layout design method according to claim 1, wherein the semiconductor structure further comprises: the first power cord and first connecting piece, standard cell still includes: a first power line pattern and a first connector pattern;
The first power line pattern corresponds to the first power line, the first connecting piece pattern corresponds to the first connecting piece, the first power line pattern is located on a first metal layer of the layout, and the first power line pattern and the second power line pattern are connected in parallel through the first connecting piece pattern.
5. The layout design method according to claim 4, wherein the semiconductor structure further comprises: an active region and a second connection, the standard cell further comprising: an active region pattern and a second connection pattern;
The active region graph corresponds to the active region, the second connecting piece graph corresponds to the second connecting piece, and the active region graph is connected with the first power line graph through the second connecting piece graph.
6. A layout corresponding to a semiconductor structure, the semiconductor structure comprising: the second power line and the signal line, its characterized in that, the territory includes:
The second power line graph corresponds to the second power line, is positioned on the second metal layer of the layout and is arranged in a discontinuous strip shape;
And the signal line pattern corresponds to the signal line, and is positioned in the intermittent gap of the second power line pattern.
7. The layout according to claim 6, wherein the layout comprises a plurality of standard cells, and the difficulty of winding the standard cells where the signal lines are located is greater than a difficulty threshold.
8. The layout according to claim 7, wherein the calculation formula of the winding difficulty is:
(pin number used channel number)/(width height);
The pin number represents the number of input and output pins in the standard unit, the number of signal channels used in the standard unit is represented by the channel number, the height represents the width value of the standard unit, and the height represents the height value of the standard unit.
9. The layout according to claim 7, wherein the difficulty threshold is in the range of 0.4-1.
10. The layout according to claim 6, wherein the semiconductor structure further comprises: the layout further comprises a first power line and a first connecting piece: a first power line pattern and a first connector pattern;
The first power line pattern corresponds to the first power line, the first connecting piece pattern corresponds to the first connecting piece, the first power line pattern is located on a first metal layer of the layout, and the first power line pattern and the second power line pattern are connected in parallel through the first connecting piece pattern.
11. The layout according to claim 10, wherein the semiconductor structure further comprises: an active region and a second connection, the layout further comprising: an active region pattern and a second connection pattern;
The active region graph corresponds to the active region, the second connecting piece graph corresponds to the second connecting piece, and the active region graph is connected with the first power line graph through the second connecting piece graph.
12. A semiconductor structure, characterized in that it is formed in accordance with the layout of any of claims 6 to 11.
13. A computer readable storage medium having stored thereon a computer program, characterized in that the computer program is executed by a processor to implement the steps of the method of any of claims 1 to 5.
14. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program capable of being run on the processor, characterized in that the processor executes the steps of the method according to any of claims 1 to 5 when the computer program is run on the processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211303746.0A CN117973304A (en) | 2022-10-24 | 2022-10-24 | Layout and design method thereof, semiconductor structure, storage medium and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211303746.0A CN117973304A (en) | 2022-10-24 | 2022-10-24 | Layout and design method thereof, semiconductor structure, storage medium and electronic equipment |
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| CN117973304A true CN117973304A (en) | 2024-05-03 |
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| CN202211303746.0A Pending CN117973304A (en) | 2022-10-24 | 2022-10-24 | Layout and design method thereof, semiconductor structure, storage medium and electronic equipment |
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- 2022-10-24 CN CN202211303746.0A patent/CN117973304A/en active Pending
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