CN117992374A - Storage expansion device and computing device - Google Patents

Abstract

The embodiment of the application provides a storage expansion device and a computing device, comprising: the PCI device comprises a cable interface, a PCIE interface, a first CXL controller, a second CXL controller and a DIMM; the first CXL controller is connected with the first part of DIMM, and the second CXL controller is connected with the second part of DIMM; the first part CXL interface of the first CXL controller is connected with the PCIE interface; the first part CXL interface and the second part CXL interface of the first CXL controller can both access all DIMMs connected with the first CXL controller; the first part CXL interface of the second CXL controller is connected with the PCIE interface; the first part CXL interface and the second part CXL interface of the second CXL controller can both access all DIMMs connected with the second CXL controller, and the access space of a single memory access port of the storage expansion device can be improved.

Description

Storage expansion device and computing device

Technical Field

The present invention relates to the technical field of servers, and in particular to a storage expansion device and a computing device.

Background technique

With the development of computer technology, the number of CPU cores has increased rapidly and computing density has continued to grow. However, limited by the physical space and design cost of computing devices, the growth rate of memory performance has lagged behind the growth of computing density. The average memory performance per core has continued to decline, limiting the computing power of computing devices.

Compute Express Link (CXL) is an open industry standard that provides high-bandwidth, low-latency connections between dedicated computing, memory, I/O, and storage elements in data centers. Computing devices can effectively solve the bottlenecks of memory walls and IO walls by expanding memory through the CXL bus. Currently, various forms of hardware boards can expand memory through the CXL bus, such as Add-in-Card (AIC), E3.S form, or customized special-shaped cards.

Currently, a single AIC card supports two double data rate (DDR) channels, and a single DDR channel can support dual-rank inline memory modules per channel (DPC, DIMM Per Channel). Therefore, a single AIC card can connect to four dual-inline-memory-modules (DIMMs).

Therefore, in the prior art, only a portion of the DIMMs connected to the CXL controller can be accessed through the memory access port of a single AIC card, and the access space is limited.

Summary of the invention

The embodiments of the present invention provide a storage expansion device and a computing device, which can increase the access space of a single memory access port of the storage expansion device.

The embodiment of the present application provides a storage expansion device, comprising: a substrate and a cable interface, a PCIE interface, a first CXL controller, a second CXL controller and a plurality of dual in-line memory modules DIMMs arranged on the substrate; the first CXL controller is connected to a first part of the DIMMs in the plurality of DIMMs, and the second CXL controller is connected to a second part of the DIMMs in the plurality of DIMMs; a CXL interface of the first CXL controller is divided into a first part of the CXL interface and a second part of the CXL interface, the first part of the CXL interface of the first CXL controller is used to connect to the cable interface, and the second part of the CXL interface of the first CXL controller is used to connect to the PCIE interface; the first part of the CXL interface of the first CXL controller and the second part of the CXL interface of the first CXL controller are connected to the first part of the CXL interface of the first CXL controller. The interfaces can access the memory space of all DIMMs connected to the first CXL controller; the CXL interface of the second CXL controller is divided into a first part CXL interface and a second part CXL interface, the first part CXL interface of the second CXL controller is used to connect the cable interface, and the second part CXL interface of the second CXL controller is used to connect the PCIE interface; the first part CXL interface and the second part CXL interface of the second CXL controller can both access the memory space of all DIMMs connected to the second CXL controller; the cable interface is used to access all memory spaces connected to the first CXL controller and the second CXL controller; the PCIE interface is used to access all memory spaces connected to the first CXL controller and the second CXL controller.

The storage expansion device provided in the embodiment of the present application includes at least two CXL controllers, and the CXL interface of each CXL controller is divided into two parts, and each part of the CXL interface can access all the memory spaces of the DIMMs connected to the CXL controller. In this way, any CXL interface of the server connected to the CXL controller can access all the DIMMs extended by the CXL controller. For example, the memory access port may include a PCIE interface and a cable interface, and the memory space of all DIMMs connected to the CXL controller can be accessed through the PCIE interface or the cable interface. The CXL controller supports a bifurcation function, and bifurcation means that the CXL interface of the CXL controller can be divided into multiple parts, for example, two parts, or more parts, and can be four parts. Of course, the CXL interface can be divided into multiple parts in an equal manner, and the number of pins of each part is the same, or it can be divided into multiple parts in a non-equal manner, and the number of pins of any two parts in the multiple parts can be different.

The storage expansion device in this embodiment can be connected to two different computing devices through a cable interface and a PCIE interface respectively, so that the two computing devices can share the memory space of the storage expansion device.

In a possible implementation, the CXL interface of the first CXL controller is an X16 interface, and the first part CXL interface and the second part CXL interface of the first CXL controller are both X8 interfaces; the first part CXL interface of the first CXL controller is connected to the first X8 interface of the cable interface, and the first part CXL interface of the second CXL controller is connected to the second X8 interface of the cable interface; the cable interface is used to access all memory spaces of the first part DIMMs and access all memory spaces of the second part DIMMs.

The embodiment of the present application does not specifically limit the number of CXL interfaces included in the first CXL controller and the second CXL controller. The above is just an example, taking an X16 CXL interface as two parts, that is, the first CXL controller and the second CXL controller each include two X8 interfaces. The storage expansion device provided in the embodiment of the present application can access the memory space of all DIMMs connected to the first CXL controller through the cable interface, and can also access the memory space of all DIMMs connected to the second CXL controller through the cable interface.

In a possible implementation manner, the CXL interface of the second CXL controller is an X16 interface, and the first part CXL interface and the second part CXL interface of the second CXL controller are both X8 interfaces; the PCIE interface is divided into a first X8 interface and a second X8 interface; the second part CXL interface of the first CXL controller is connected to the first X8 interface of the PCIE interface, and the second part CXL interface of the second CXL controller is connected to the second X8 interface of the PCIE interface; the PCIE interface is used to access all memory spaces of the first part DIMMs and access all memory spaces of the second part DIMMs.

The storage expansion device provided in the embodiment of the present application can access the memory space of all DIMMs connected to the first CXL controller through the PCIE interface, and can also access the memory space of all DIMMs connected to the second CXL controller through the PCIE interface.

In a possible implementation, the first CXL controller stores a first mapping table and a second mapping table, the first mapping table corresponds to the first part of the CXL interface of the first CXL controller, and the second mapping table corresponds to the second part of the CXL interface of the first CXL controller, the first mapping table implements mapping conversion of the memory physical address of the server connected to the first part of the CXL interface of the first CXL controller to the memory physical addresses of all DIMMs of the first CXL controller; the second mapping table implements mapping conversion of the memory physical address of the server connected to the second part of the CXL interface of the first CXL controller to the memory physical addresses of all DIMMs of the first CXL controller.

The storage expansion device provided in the embodiment of the present application sets two mapping tables inside the first CXL controller, which correspond to the two parts of CXL interfaces respectively, so that the memory access interface connected to the two parts of CXL interfaces can access the memory space of all DIMMs connected to the first CXL controller through the corresponding mapping tables.

In a possible implementation, the second CXL controller stores a third mapping table and a fourth mapping table, the third mapping table corresponds to the first part of the CXL interface of the second CXL controller, and the third mapping table corresponds to the second part of the CXL interface of the first CXL controller, the third mapping table implements the mapping conversion of the memory physical address of the server connected to the first part of the CXL interface of the second CXL controller to the memory physical addresses of all DIMMs of the second CXL controller; the fourth mapping table implements the mapping conversion of the memory physical address of the server connected to the second part of the CXL interface of the second CXL controller to the memory physical addresses of all DIMMs of the second CXL controller.

The storage expansion device provided in the embodiment of the present application sets two mapping tables inside the second CXL controller, which correspond to the two parts of CXL interfaces respectively, so that the memory access interface connected to the two parts of CXL interfaces can access the memory space of all DIMMs connected to the first CXL controller through the corresponding mapping tables.

A possible implementation method also includes a sensor and a system management bus (SMbus) switch interface arranged on the substrate; the sensor is used to detect the temperature of the storage expansion device; the first end of the SMbus switch interface is connected to the first CXL controller and the second CXL controller; the second end of the SMbus switch interface is connected to the sensor; and the third end of the SMbus switch interface is used for a cable interface or a PCIE interface.

The server accesses at least one of the sensor, the first CXL controller and the second CXL controller through the SMbus switch interface by connecting to the SMbus switch interface. In addition, the server can access the sensor, the first CXL controller and the second CXL controller at the same time through the SMbus switch interface. The server accesses the first CXL controller and the second CXL controller, and can access data in the DIMMs expanded by the first CXL controller and the second CXL controller.

In a possible implementation, both the cable interface and the PCIE interface provide a clock pin, a reset pin, an SMbus pin, an in-position pin and a power pin, and the third end of the SMbus switch interface is connected to the SMbus pins of the cable interface and the PCIE interface.

In one possible implementation, the storage expansion device is in the form of a PCIE standard card, and the PCIE interface is arranged on the long side of the substrate for vertically plugging into the backplane of the computing device; or, the storage expansion device is in the form of a plug-in card, and the PCIE interface is arranged on the short side of the substrate for horizontally plugging into the backplane of the computing device.

The storage expansion device provided in the embodiment of the present application does not specifically limit the location of the PCIE interface setting and can be freely designed according to needs to facilitate connection to the backplane in the computing device.

In a possible implementation, the storage expansion device provided in an embodiment of the present application further includes a first full-duplex synchronous serial bus SPI flash memory and a second SPI flash memory arranged on the substrate; the first CXL controller is connected to the first SPI flash memory; and the second CXL controller is connected to the second SPI flash memory.

The first SPI flash memory C and the second SPI flash memory D are both in the form of electronically erasable programmable read-only memory, allowing multiple erasing or writing of SPI data.

In a possible implementation, the computing device provided in the embodiment of the present application further includes: a debugging Debug interface; the first CXL controller and the second CXL controller are both connected to the Debug interface.

The debug interface can be connected to an external device to test or debug the first CXL controller and the second CXL controller of the storage expansion device.

In a possible implementation manner, the storage expansion device provided in the embodiment of the present application further includes a supporting structure.

The support structure can fix the storage expansion device and the support plate relative to each other. For example, the support plate can be a metal plate, and the storage expansion device is fixed to the metal plate by the fixed support structure to play a role in strength support. The embodiment of the present application does not specifically limit the type of the support structure, for example, it can be screws or rivets, nor does it specifically limit the number of support structures, which can be set according to actual needs.

In a second aspect, an embodiment of the present application further provides a storage expansion device, including: a substrate and a cable interface, a PCIE interface, a CXL controller and a plurality of dual in-line memory modules DIMMs arranged on the substrate; the CXL controller is connected to the plurality of DIMMs, and the CXL interface of the CXL controller is divided into a first part CXL interface and a second part CXL interface, the first part CXL interface is connected to the cable interface, and the second part CXL interface is connected to the PCIE interface; both the first part CXL interface and the second part CXL interface can access the memory space of all DIMMs connected to the CXL controller; the cable interface is used to access all memory spaces of the CXL controller; the PCIE interface is used to access all memory spaces of the CXL controller.

In a third aspect, an embodiment of the present application further provides a computing device, including: a backplane and the storage expansion device introduced above; the storage expansion device is connected to the backplane.

The computing device provided in the embodiment of the present application can access all memories through the PCIE interface, i.e., the gold finger, and can also access all memories through the cable interface, thereby realizing the need to access high-density memory with fewer CXL bus interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device, thereby improving the memory density of the computing device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a storage expansion device provided in an embodiment of the present application;

FIG2 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG3 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG4A is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG4B is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG5 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG6 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG7 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG8 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG9 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of a computing device provided in an embodiment of the present application.

Detailed ways

The computing device provided in the embodiment of the present application does not specifically limit the application scenario. For example, the computing device is introduced by taking a server as an example, and the type of the server is not specifically limited. For example, the computing device can be a rack server or an edge server. The server can be located in a data center or in other areas, and the embodiment of the present application does not make specific limitations.

Servers are a type of computing device that runs faster and has a higher load than ordinary computers. Servers provide computing or application services to other clients in the network. For example, personal computers (PCs) or smart phones. Servers have high-speed CPU computing power, long-term reliable operation, strong external data throughput and better scalability. Servers are divided into rack-mounted, blade-mounted, tower-mounted and cabinet-mounted types.

The server generally includes a mainboard and a power supply, and the power supply is used to supply power to various loads of the mainboard. The embodiment of the present application does not specifically limit the voltage level provided by the power supply to the mainboard, for example, DC 12V is used as an example for introduction.

The motherboard is an important circuit board in the server. The motherboard includes a substrate and a baseboard manager controller (BMC) arranged on the substrate, a central processing unit (CPU), a controller, a memory, a connector and other components. In addition, the motherboard can include one CPU or multiple CPUs. The controller interface is limited, so the interface can be expanded through a connector to facilitate the connection of peripheral devices, such as expanding the USB port to connect devices such as a mouse and keyboard; expanding the serial data interface to connect devices such as a graphics card. The controller can be one or more of a micro controller unit (MCU), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA).

The embodiments of the present application do not specifically limit the specific type of memory. For example, the memory includes but is not limited to the following types: dual-inline-memory-modules (DIMM), hard disk drive (HDD), etc.

The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) card can be connected to the connector in the server to facilitate the expansion of peripheral devices for the server controller, such as connecting a graphics card or a memory card. The PCIE card belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, generally using differential signal channels, which can allocate exclusive channel bandwidth for connected devices and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliability transmission, hot plugging, and quality of service functions.

Serial Peripheral Interface (SPI), SPI is a high-speed, full-duplex, synchronous communication bus that only occupies four wires on the chip pins.

The System Management Bus (SMBus) was proposed by Intel in 1995 and is used for low-speed communication in mobile PCs and desktop PC systems. SMBus is a powerful bus that controls devices on the motherboard and collects corresponding information through two lines.

In order to enable those skilled in the art to better understand the technical solution provided by the embodiments of the present application, a detailed description is given below in conjunction with the accompanying drawings.

Refer to Figure 1, which is a schematic diagram of a storage expansion device provided in an embodiment of the present application.

The storage expansion device provided in the embodiment of the present application includes: a base plate 1000 and at least one of a cable interface 200 or a PCIE interface 100 provided on the base plate 1000, and at least one CXL controller; FIG1 takes the base plate of the storage expansion device as an example for introduction, in which the first CXL controller A and the second CXL controller B are provided. The first CXL controller A is used to connect a first group of 4 DIMMs. The second CXL controller B is used to connect a second group of 4 DIMMs.

For example, a plurality of PCIe slots are provided on the substrate, and the DIMMs are inserted into corresponding PCIe slots.

It should be understood that the CXL controller includes a CXL interface, and the CXL interface may include an X8 interface or an X16 interface. The X8 interface includes 8 pairs of differential signal pins, and the X16 interface includes 16 pairs of differential signal pins.

It should be noted that the memory access port of the storage expansion device in this embodiment can be provided with both the cable interface 200 and the PCIE interface 100, and the storage expansion device can also be provided with only the cable interface 200, or only the PCIE interface 100. The device or component connected to the line interface of the storage expansion device can access all DIMMs on the storage expansion device through the cable interface 200, and the device or component connected to the PCIE interface of the storage expansion device can also access all DIMMs on the storage expansion device through the PCIE interface 100. This embodiment is described below with the storage expansion device including both the cable interface 200 and the PCIE interface 100.

The embodiment of the present application does not specifically limit the number of CXL controllers provided on the storage expansion device, which may be one or more. However, each CXL controller on the storage expansion device provided by the embodiment of the present application may be connected to four DIMMs.

The first CXL controller A supports a bifurcation function. Bifurcation means that the CXL interface of the CXL controller can be divided into multiple parts, for example, two parts, or more parts, such as four parts. Of course, the CXL interface can be divided into multiple parts in an equal manner, and the number of pins in each part is the same, or it can be divided into multiple parts in a non-equal manner, and the number of pins in any two parts of the multiple parts can be different. In the embodiment of the present application, the CXL interface of the CXL controller is divided into two parts as an example for introduction.

For example, the CXL interface of the CXL controller includes an X16 interface, which is divided into two X8 interfaces. Correspondingly, the cable interface 200 includes an X16 interface, that is, includes two X8 interfaces. Similarly, the PCIE interface 100 also includes two X8 interfaces.

The CXL interface of the first CXL controller A includes a first part CXL interface and a second part CXL interface, the first part CXL interface of the first CXL controller A is connected to the first X8 interface of the cable interface 200, and the second part CXL interface of the first CXL controller A is connected to the first X8 interface of the PCIE interface 100; for example, if the CXL interface of the first CXL controller A is an X16 interface, the X16 interface is divided into two X8 interfaces. For example, one of the X8 interfaces is used to connect to the cable interface 200, and the other X8 interface is used to connect to the PCIE interface 100. It should be understood that the PCIE interface 100 is a gold finger interface, for example, a storage expansion device is connected to the backplane in the server through a gold finger to provide a memory access channel for the server.

In the embodiment of the present application, the X16 interface is divided into two X8 interfaces as an example. In other implementations, the X16 interface can also be divided into four X4 interfaces, etc., which is not specifically limited in the embodiment of the present application.

The X16 interface is divided into two X8 interfaces, which can be understood as follows: the X16 interface is an interface entity, half of the pins of the X16 interface are divided into a virtual X8 interface, and the other half of the pins of the X16 interface are divided into another virtual X8 interface, that is, the two X8 interfaces are obtained by dividing the pins of one X16 interface. Of course, in other embodiments, the CXL controller may also include two physical X8 interfaces.

The second CXL controller B supports a bifurcation function. The CXL interface of the second CXL controller B includes a first CXL interface and a second CXL interface. The first CXL interface of the second CXL controller B is connected to the second x8 interface of the cable interface 200, and the second CXL interface of the second CXL controller B is connected to the second x8 interface of the PCIE interface 100. For example, if the CXL interface of the second CXL controller B is an x16 interface, the x16 interface is equally divided into two x8 interfaces. One of the x8 interfaces is used to connect to the cable interface 200, and the other x8 interface is used to connect to the PCIE interface 100.

The server can access all memory spaces of the corresponding first CXL controller A expansion and all memory spaces of the corresponding second CXL controller B expansion through the cable interface 200. That is, when the storage expansion device includes two CXL controllers, the server can access the first group of 4 DIMMs of the first CXL controller A expansion and the second group of 4 DIMMs of the second CXL controller B expansion through the cable interface 200, that is, the server can access 8 DIMMs on the storage expansion device through the cable interface 200.

For example, the X8 interface of the first CXL controller is connected to the cable interface 200, and the X8 interface of the second CXL controller is also connected to the cable interface 200. The cable interface 200 includes an X16 interface, wherein the server can access all DIMMs expanded by the first CXL controller through the X8 interface of the cable interface 200, and the server can access all DIMMs expanded by the second CXL controller through another X8 interface of the cable interface 200. It should be understood that the first CXL controller is connected to 4 DIMMs, and the second CXL controller is connected to 4 DIMMs, that is, the server can access a total of 8 DIMMs on the storage expansion device through the cable interface 200.

The PCIE interface 100 of FIG1 is arranged on the long side of the substrate, and the cable interface 200 of FIG1 is arranged on the short side of the substrate. Moreover, the four DIMMs connected to each CXL controller are arranged parallel to the long side of the substrate. It should be understood that the positional relationship of each device in FIG1 is only for illustration and is not specifically limited in the embodiments of the present application.

The embodiment of the present application does not specifically limit the specific implementation form of the cable interface. For example, the storage expansion device may include one 16Lane CXL cable interface 200 or two 8Lane CXL cable interfaces 200.

The embodiment of the present application does not specifically limit the specific type of the cable interface 200, for example, it can be an optical-electric conversion interface, that is, converting the electrical signal of the CXL controller into an optical signal for external transmission, or converting the external optical signal into an electrical signal for transmission to the CXL controller. The CXL controller can access the data in the DIMM, and can read data or write data.

The server can access all memory spaces expanded by the corresponding first CXL controller A through the PCIE interface 100. That is, when the storage expansion device includes two CXL controllers, the server can access the 4 DIMMs expanded by the first CXL controller A and the 4 DIMMs expanded by the second CXL controller B through the PCIE interface 100, that is, the server can access the 8 DIMMs on the storage expansion device through the PCIE interface 100.

For example, the X8 interface of the first CXL controller is connected to the PCIE interface 100, and the X8 interface of the second CXL controller is also connected to the PCIE interface 100. The PCIE interface 100 includes an X16 interface, wherein the server can access all DIMMs connected to the first CXL controller through the X8 interface of the PCIE interface 100, and the server can access all DIMMs connected to the second CXL controller through another X8 interface of the PCIE interface 100. It should be understood that the first CXL controller is connected to 4 DIMMs, and the second CXL controller is connected to 4 DIMMs, that is, the server can access a total of 8 DIMMs on the storage expansion device through the PCIE interface 100.

It is understandable that the two X8 interfaces of the PCIE interface correspond to half of the pins of the PCIE interface, that is, the two X8 interfaces are obtained by dividing the pins of the PCIE interface. Of course, in other embodiments, the storage expansion device may include two physical X8 PCIE interfaces.

The storage expansion device provided in the embodiment of the present application includes a CXL controller supporting a bifurcation function, the CXL controller supports at least 2 DDR channels, each channel supports at least 2DPC, that is, a single CXL controller can support 4 DDR DIMMs. Half of the CXL interface of the CXL controller is connected to the cable interface, and the other half of the CXL interface of the CXL controller is connected to the gold finger for external data exchange. The gold finger can be in the form of a PCIE standard card, that is, it can be vertically plugged into the backplane.

The storage expansion device in this embodiment can be connected to two different computing devices through a cable interface and a PCIE interface respectively, so that the two computing devices can share the memory space of the storage expansion device.

The storage expansion device provided in the embodiment of the present application is a server that can access the memory of all DIMMs connected to the CXL controller through the PCIE interface, i.e., the gold finger, and can also access all the memory of all DIMMs connected to the CXL controller through the cable interface, thereby realizing the need to access high-density memory with fewer interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device.

FIG1 is an introduction using an example of a storage expansion device including two CXL controllers. It should be understood that the storage expansion device may also include only one CXL controller. One CXL controller is connected to four DIMMs. The four DIMMs can be accessed through a gold finger or cable interface. The gold finger or cable interface only requires an X8 interface to access the four DIMMs. Compared with traditional technologies, the number of interface pins can be reduced by half to access the same number of DIMMs.

In a possible implementation, the CXL controller of the embodiment of the present application enables external devices (such as servers) to access all memory spaces expanded by the CXL controller through cable interfaces or gold fingers through address mapping. That is, the CXL controller is used to map the addresses of all expanded memory spaces to the first part of the CXL interface and the second part of the CXL interface.

In a possible implementation, an address mapping table is set in the CXL controller, and the address mapping table can map all memory spaces extended by the CXL controller. The address mapping table can include two offsets. For example, when accessing all memory spaces extended by the CXL controller through the first part of the CXL interface, the first offset is used to calculate the address mapping relationship. When accessing all memory spaces extended by the CXL controller through the second part of the CXL interface, the second offset is used to calculate the address mapping relationship.

The CXL controller can complete the address mapping between all the expanded memory spaces and the CPU of the server (computing device). The CXL controller is responsible for mapping the physical address of the computing device to the physical address of the storage expansion device. For example, if the computing device is a server, the physical address of the computing device here can be the physical address of the motherboard CPU. For example, if the storage space of the storage expansion device is 64G, then the physical address read by the storage expansion device corresponding to the CPU is the address corresponding to 201G-264G, that is, the physical address is offset inside the CXL controller, so that the server CPU performs a physical address offset when reading the storage expansion device.

For example, the first CXL controller stores a first mapping table and a second mapping table, the first mapping table corresponds to a first part of the CXL interface of the first CXL controller, and the second mapping table corresponds to a second part of the CXL interface of the first CXL controller. The first mapping can implement a mapping conversion of a memory physical address of a first server (e.g., a server connected to a cable interface) received by the first part of the CXL interface to a memory physical address of all DIMMs (e.g., DIMMs 1 to 4) of the first CXL controller. The mapping conversion of the memory physical address can comply with the CXL spec or a custom method, for example, by calculating through an address offset.

The second mapping table can implement the mapping conversion of the memory physical address of the second server (for example, a server connected to the PCIE interface) received by the second part CXL interface to the memory physical addresses of all DIMMs (for example, DIMMs 1-4) of the first CXL controller. The mapping conversion of the memory physical address can follow the CXL protocol or a custom method, for example: calculation by address offset.

Since the first CXL interface and the second CXL interface may be connected to different servers, and the servers have different system address spaces, the memory physical addresses received by the first CXL interface and the second CXL interface may be different, but the physical addresses to be converted are the same. At the same time, the CXL controller can ensure that the addresses converted from the two mapping tables can access all DIMMs connected to the CXL controller, and the CXL controller guarantees the correct access order.

Similarly, the second CXL controller stores a third mapping table and a fourth mapping table. The third mapping table corresponds to the first part of the CXL interface of the second CXL controller, and the fourth mapping table corresponds to the second part of the CXL interface of the second CXL controller. The third mapping table can realize the mapping conversion of the memory physical address of the first server (for example, the server connected to the cable interface) received by the first part of the CXL interface to the memory physical address of all DIMMs (for example, DIMMs 5-8) on the second CXL controller. The mapping conversion of the memory physical address can follow the CXL spec or a custom method, for example: calculated by address offset.

The fourth mapping table can implement the mapping conversion of the memory physical address of the second server (for example, a server connected to the PCIE interface) received by the second part CXL interface to the memory physical addresses of all DIMMs (for example, DIMMs 5-8) on the second CXL controller. The mapping conversion of the memory physical address can follow the CXL protocol or a custom method, for example: calculation by address offset.

In view that the first part of the CXL interface and the second part of the CXL interface may be connected to different servers, and the servers have different system address spaces, the memory physical addresses received by the first part of the CXL interface and the second part of the CXL interface may be different, but the physical addresses that need to be converted are the same. At the same time, the CXL controller can ensure that the addresses converted by the two mapping tables can access all the addresses connected to the CXL controller, and the CXL controller guarantees the correct access order. It should be noted that when the first server sends a read-write operation instruction to the first CXL controller through the first part of the CXL interface of the first CXL controller, the first CXL controller confirms the destination address included in the read-write operation instruction based on the first mapping table, and performs corresponding read-write operations on the destination address. When the first server sends a read-write operation instruction to the second CXL controller through the first part of the CXL interface of the second CXL controller, the second CXL controller confirms the destination address included in the read-write operation instruction based on the third mapping table, and performs corresponding read-write operations on the destination address.

When the second server sends a read/write operation instruction to the first CXL controller through the second part of the CXL interface of the first CXL controller, the first CXL controller confirms the destination address included in the read/write operation instruction based on the second mapping table, and performs the corresponding read/write operation on the destination address. When the second server sends a read/write operation instruction to the second CXL controller through the second part of the CXL interface of the second CXL controller, the second CXL controller confirms the destination address included in the read/write operation instruction based on the fourth mapping table, and performs the corresponding read/write operation on the destination address.

Since the CXL interface of the CXL controller includes a first part of the CXL interface and a second part of the CXL interface, each CXL interface can access all memories connected to the CXL controller, and each interface can access all memory spaces connected to the CXL controller through a corresponding address mapping table, because the address mapping in the CXL controller can map all extended memories to any part of the CXL interface of the CXL controller, that is, each part of the CXL interface can access all CXL memory spaces, that is, all DIMMs, so that a server connected to the cable interface can access all memory spaces of the storage expansion device through a part of the interface of the first CXL controller and a part of the interface of the second CXL controller, and a server connected to the PCIE interface can access all memory spaces of the storage expansion device through another part of the interface of the first CXL controller and another part of the interface of the second CXL controller

The CXL interface is an X16 interface; the X16 interface of the CXL controller is equally divided into a first part CXL interface and a second part CXL interface, and both the first part CXL interface and the second part CXL interface are X8 interfaces.

The first portion CXL interface is connected to the cable interface.

The second part CXL interface is connected to the PCIE interface.

In FIG1 , the storage expansion device includes a cable interface and a PCIE interface. The following describes a case where the storage expansion device only includes a PCIE interface.

Refer to Figure 2, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in Figure 2 is the same as the storage expansion device shown in Figure 1 in that both include two CXL controllers, each of which is connected to four corresponding DIMMs. Moreover, the PCIE interface 100 in Figures 1 and 2 is arranged on the long side of the substrate, and the same parts are not repeated here.

The storage expansion device shown in FIG2 is different from the storage expansion device shown in FIG1 in that the storage expansion device shown in FIG2 only includes a PCIE interface 100 and may not include a cable interface. In addition, the storage expansion device shown in FIG2 has a PCIE interface 100 configured as a standard PCIE AIC form, that is, the gold finger may be externally provided in the form of a PCIE standard card and vertically plugged into the backplane of the computing device.

Refer to Figure 3, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in Figure 3 is the same as the storage expansion device shown in Figure 1 in that both include two CXL controllers, each CXL controller is connected to four corresponding DIMMs. Moreover, the cable interface 200 in Figures 1 and 3 is arranged on the short side of the substrate, and the same parts are not repeated here.

The storage expansion device shown in FIG3 is different from the storage expansion device shown in FIG1 in that the storage expansion device shown in FIG3 only includes a cable interface 200 and may not include a PCIE interface. The cable interface 200 of the storage expansion device shown in FIG3 may be connected to a server via an external cable, for example, the cable interface 200 of the storage expansion device may be connected to a server via an optical fiber, etc.

The PCIE interface of the storage expansion device provided in the embodiment of the present application can also be set as a plug-in card, that is, the entire storage expansion device can be pulled out and pushed in like a drawer, for example, it can be inserted into the backplane of the server.

See Figure 4A, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in FIG. 4A is the same as the storage expansion device shown in FIG. 1 in that both include two CXL controllers, each CXL controller is connected to corresponding four DIMMs, and both include a cable interface 200 and a PCIE interface 100 , and the same parts are not repeated here.

The storage expansion device shown in FIG4A is different from the storage expansion device shown in FIG1 in that the storage expansion device in FIG4A is configured as a plug-in card, which is mainly reflected in that the PCIE interface 100 is configured as a plug-in card and can be plugged into the backplane of the server. Moreover, the PCIE interface 100 of FIG1 is arranged on the long side of the substrate, while the PCIE interface 100 of FIG4A is arranged on the short side of the substrate.

The four DIMMs connected to each CXL controller are arranged parallel to the long side of the substrate. It should be understood that the positional relationship of the various components in FIG. 4A is only for illustration and is not specifically limited in the embodiments of the present application.

Since the PCIE interface 100 is arranged on the short side of the substrate, when the storage expansion device is set to a plug-in card form, the storage expansion device may shake and be unstable. Therefore, a fixed support structure is arranged on the storage expansion device to stabilize its state and prevent shaking. For example, the storage expansion device may be provided with a plurality of fixed structures, which are distributed at different positions of the storage expansion device. For example, a possible implementation method can be specifically shown in FIG. 4B, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The computing device provided in the embodiment of the present application also includes a support plate M, on which three fixed structures are arranged corresponding to the three vertices of a triangle formed by the three fixed structures of the memory expansion device. The three fixed positions are respectively O, P and Q for example. In specific implementation, the storage expansion device and the support plate can be fixed together by screws or rivets. The support plate can be located on the side of the substrate facing away from the DIMM so that the support plate can fix and support the storage expansion device. For example, the support plate is a metal plate, and the substrate of the storage expansion device is fixed on the metal plate by a fixed support structure to play a role in strength support. The embodiment of the present application does not specifically limit the number of fixed structures, and can be set according to actual needs.

See FIG. 5 , which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in Fig. 5 is the same as the storage expansion device shown in Fig. 4A in that both include two CXL controllers, each of which is connected to four corresponding DIMMs. The PCIE interface 100 is arranged on the short side of the substrate, and the same parts are not repeated here.

The storage expansion device shown in FIG. 4 is different from the storage expansion device shown in FIG. 4A in that the storage expansion device shown in FIG. 5 only includes a PCIE interface 100, and the PCIE interface 100 is configured as a plug-in card, that is, the gold finger can be horizontally plugged into the backplane of the server in the form of a plug-in card.

The implementation form of the storage expansion device provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

See FIG. 6 , which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device provided in the embodiment of the present application is in the form of a PCIE standard card, full height and full length. The storage expansion device can provide a DC 12V power supply interface. Similar to Figure 1, the storage expansion device includes a first CXL controller A and a second CXL controller B, the first CXL controller A is connected to the corresponding 4 DIMMs, and the second CXL controller B is connected to the corresponding 4 DIMMs. The entire storage expansion device can expand 8 DIMMs, and the same parts will not be repeated.

A gold finger interface is provided on the side of the baseboard of the storage expansion device. The gold finger interface is an X16 interface and complies with the PCIE standard specification.

The storage expansion device provided in the embodiment of the present application takes two X8 cable interfaces as an example, that is, the first cable interface 201 is an X8 interface, and the second cable interface 202 is an X8 interface. The first cable interface 201 is connected to the first CXL controller A, and the second cable interface 202 is connected to the second CXL controller B. The first cable interface 201 accesses the 4 DIMMs connected to the first CXL controller A, and the second cable interface 202 accesses the 4 DIMMs connected to the second CXL controller B. It should be understood that FIG. 6 may also include only one cable interface, which is an X16 interface.

The storage expansion device provided in the embodiment of the present application also includes a first SPI flash memory C and a second SPI flash memory D arranged on the substrate.

The first CXL controller A is connected to the first SPI flash memory C.

The second CXL controller B is connected to the second SPI flash memory D.

The first SPI flash memory C and the second SPI flash memory D are both in the form of electronic erasable programmable read-only memory, allowing multiple erasure or writing of SPI data. Since they can be erased and written, they can be reused.

The storage expansion device provided in the embodiment of the present application further includes a debugging Debug interface provided on the substrate; the first CXL controller A and the second CXL controller B are both connected to the Debug interface. The Debug interface can be connected to an external device to implement testing or debugging of the first CXL controller A and the second CXL controller B of the storage expansion device. It should be understood that the first CXL controller A and the second CXL controller B can both be connected to the Debug interface via a Joint Test Action Group (JTAG) interface or a Universal Asynchronous Receiver/Transmitter (UART) interface.

The storage expansion device provided in the embodiment of the present application further includes a system management bus SMbus switch interface F and a sensor E arranged on the substrate. The sensor E is used to detect the temperature of the storage expansion device.

A first end of the SMbus switch interface F is connected to the first CXL controller A and the second CXL controller B;

The second end of the SMbus switch interface F is connected to the sensor E. The third end of the SMbus switch interface F is used to connect to the server. For example, the SMbus switch interface F can be used to connect to the server. The server can manage the CXL controller on the storage expansion device through the SMbus switch interface F.

In a possible implementation, the server is connected to the SMbus switch interface and accesses at least one of the sensor E, the first CXL controller A and the second CXL controller B through the SMbus switch interface F. In addition, the server can simultaneously access the sensor E, the first CXL controller A and the second CXL controller B through the SMbus switch interface F. The server accesses the first CXL controller A and the second CXL controller B, and can access data in the DIMMs expanded by the first CXL controller A and the second CXL controller B.

In addition to the CXL data read and write pins, the interfaces provided by the first cable interface 201, the second cable interface 202 and the PCIE interface 100 also include a clock pin CLK, a reset pin RST, an SMbus pin, a position pin PRSNT and a power pin. In other words, the third end of the SMbus switch interface F can be connected to the cable interface or the PCIE interface. In the embodiment of the present application, the voltage of the power pin is 3.3V as an example for explanation.

The first CXL controller A is connected to the corresponding four DIMMs through the DDR controller, and obtains the (Serial Presence Detect, SPD) information of the corresponding four DIMMs through the integrated circuit interconnect communication circuit (Inter-Integrated Circuit, I2C) or the improved I2C bus interface (Improved Inter Integrated Circuit, I3C). The SPD information includes the memory size and bandwidth of the DIMM, which is convenient for mapping the physical address according to the memory size. Similarly, the second CXL controller B is connected to the corresponding four DIMMs through the DDR controller, and obtains the serial presence detection SPD information of the corresponding four DIMMs through I2C/I3C.

The storage expansion device provided in the embodiment of the present application can refresh the firmware of the first CXL controller A and the firmware of the second CXL controller B through a server, and modify the internal address mapping unit thereof, so that all interfaces after the CXL interfaces of the first CXL controller A and the second CXL controller B are equally divided can access all memory spaces connected to the corresponding CXL controllers, so that the entire CXL memory space of the storage expansion device, that is, all DIMMs, can be accessed through the cable interface and the PCIe interface.

The storage expansion device shown in Fig. 6 is provided with a first cable interface 201, a second cable interface 202 and a PCIE interface 100, wherein the PCIE interface 100 is provided on the long side of the substrate, and the first cable interface 201 and the second cable interface 202 are provided on the short side of the substrate. Each CXL controller is connected to four corresponding DIMMs.

In another implementation, the storage expansion device provided in the embodiment of the present application may only include a PCIE interface, but not a cable interface, which will be described in detail below in conjunction with the accompanying drawings.

See FIG. 7 , which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in Fig. 7 is the same as the storage expansion device shown in Fig. 6 in that both include two CXL controllers, each of which is connected to four corresponding DIMMs. The PCIE interface 100 is arranged on the long side of the substrate, and the same parts are not repeated here.

The storage expansion device shown in Figure 7 is different from the storage expansion device shown in Figure 6 in that the storage expansion device provided in the embodiment of the present application includes a PCIE interface 100, but does not include a cable interface. The PCIE interface 100 is in the form of a PCIE standard card and can be vertically plugged into the backplane of the server.

The 8Lane CXL bus of the first CXL controller A is connected to the PCIE interface 100, and the 8Lane CXL bus of the second CXL controller B is connected to the PCIE interface 100. Therefore, the 4 DIMMs expanded by the first CXL controller A and the 4 DIMMs expanded by the second CXL controller B can be accessed through the PCIE interface 100.

The storage expansion device shown in FIG. 7 includes a PCIE interface. In addition, the storage expansion device provided in the embodiment of the present application may only include a cable interface without a PCIE interface, which will not be described in detail here.

The following describes in detail with reference to the accompanying drawings how the storage expansion device includes a PCIE interface, but the PCIE interface is implemented as a plug-in card.

See FIG. 8 , which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The storage expansion device shown in FIG. 8 is the same as the storage expansion device shown in FIG. 6 in that both include two CXL controllers, each CXL controller is connected to corresponding four DIMMs, and the same parts are not repeated here.

Comparing FIG8 with FIG6 , it can be seen that the difference between the two is that the PCIE interface 100 in FIG8 is arranged on the short side of the substrate. The PCIE interface 100 in FIG8 is arranged in a plug-in card form, that is, the gold finger can be horizontally plugged into the backplane of the server in a plug-in card form.

Meanwhile, the storage expansion device provided in FIG. 8 includes a first cable interface 201 and a second cable interface 202 . For detailed description, please refer to the corresponding description in FIG. 6 , which will not be repeated here.

The storage expansion device shown in Figure 8 includes a cable interface and a PCIE interface. In addition, the storage expansion device provided in the embodiment of the present application may only include a PCIE interface without a cable interface, which will be described in detail below in conjunction with the accompanying drawings.

See Figure 9, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

The difference between the storage expansion device provided in FIG. 9 and the storage expansion device provided in FIG. 8 is that the storage expansion device provided in FIG. 9 does not include a cable interface but only includes a PCIE interface 100 .

The storage expansion device provided in the embodiment of the present application includes a PCIE interface 100, which is configured as a plug-in card. That is, the gold finger can be horizontally plugged into the backplane of the server in the form of a plug-in card.

The X8 interface of the first CXL controller A is connected to the PCIE interface 100, and the X8 interface of the second CXL controller B is connected to the PCIE interface 100. Therefore, the four DIMMs expanded by the first CXL controller A and the four DIMMs expanded by the second CXL controller B can be accessed through the PCIE interface 100.

The CXL controller on the storage expansion device provided in the embodiment of the present application supports Bifurcation, and the cable interface or PCIE interface can access all memory spaces on the storage expansion device through the address mapping unit. For example, the density memory improvement of connecting 8 DIMMs with the X16 interface can be realized, and the gold finger or cable interface is supported. The server only needs to connect one of the gold finger or cable interfaces to access all memory spaces.

Furthermore, the storage expansion device provided in the embodiment of the present application can be plugged in and out of the chassis of the computing device, making the CXL memory card easy to maintain and allowing manufacturers to not be restricted to the supply of E3.S-shaped memory particles.

The above embodiment is only introduced by taking the CXL controller connecting 4 DIMMs as an example. It should be understood that the CXL controller can also expand a larger number of DIMMs. Regardless of the number of DIMMs expanded by a CXL controller, using the technical solution provided in the embodiment of the present application, the cable interface or the PCIE interface can access all DIMMs expanded by each CXL controller, so that all CXL memories on the storage expansion device can be accessed through one interface of the storage expansion device, thereby improving memory density and saving costs.

In addition, the embodiments of the present application do not specifically limit the number of CXL controllers set on a storage expansion device. The above embodiments are introduced by taking two CXL controllers as an example. It should be understood that in other embodiments, a larger number of CXL controllers can be integrated on the storage expansion device, and then a larger number of DIMMs can be expanded on a storage expansion device. For example, if 4 CXL controllers are integrated, 16 DIMMs can be integrated, and the memory space of 16 DIMMs can be accessed through the cable interface or PCIE interface. The above is only an example, and it should be understood that an odd number of CXL controllers can also be set on the storage expansion device, which is not specifically limited here.

Based on the storage expansion device provided in the above embodiment, the present application embodiment further provides a computing device, which is described in detail below in conjunction with the accompanying drawings. The present application embodiment does not specifically limit the specific type of the computing device, for example, the computing device may be a server.

See FIG. 10 , which is a schematic diagram of a computing device provided in an embodiment of the present application.

The computing device provided in the embodiment of the present application includes: a backplane 2000 and a storage expansion device 3000 introduced in any one of the above embodiments;

The storage expansion device 3000 is connected to the backplane 2000 .

It should be understood that the embodiment of the present application does not specifically limit the number of storage expansion devices 3000 included in the computing device, which may be one or more and can be set according to actual scenarios.

Moreover, the computing device provided in the embodiment of the present application does not specifically limit the connection mode between the storage expansion device 3000 and the backplane 2000. As described in the above embodiment, the PCIE interface included in the storage expansion device 3000 can be set to a PCIE standard card form, and the storage expansion device can be vertically plugged into the backplane 2000. In addition, the PCIE interface included in the storage expansion device 3000 can also be set to a plug-in card form, and the storage expansion device 3000 can be horizontally plugged into the backplane 2000.

It should be understood that in FIG10 , the PCIE interface is in the form of a PCIE standard card, and the storage expansion device 3000 shown in FIG10 is a schematic diagram. If it is vertically plugged into the backplane 2000, that is, the storage expansion device 3000 and the backplane 2000 are perpendicular to each other, there is an obstruction between the storage expansion device 3000 and the backplane 2000 after vertical plugging. In order to understand the connection relationship between the backplane 2000 and the storage expansion device 3000, FIG10 is only a schematic diagram and does not represent the actual physical form and layout.

The computing device provided in the embodiment of the present application can access all memories through the PCIE interface, i.e., the gold finger, and can also access all memories through the cable interface, thereby realizing the demand for accessing high-density memory with fewer interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device, thereby improving the memory density of the computing device.

The above is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present application using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims (10)

1. A storage expansion device, comprising: the PCI device comprises a substrate, a cable interface, a PCIE interface, a first CXL controller, a second CXL controller and a plurality of dual in-line memory module DIMMs, wherein the cable interface, the PCIE interface, the first CXL controller, the second CXL controller and the plurality of dual in-line memory module DIMMs are arranged on the substrate;

the first CXL controller is connected with a first part of DIMMs in the plurality of DIMMs, and the second CXL controller is connected with a second part of DIMMs in the plurality of DIMMs;

The CXL interface of the first CXL controller is divided into a first part CXL interface and a second part CXL interface, the first part CXL interface of the first CXL controller is used for being connected with the cable interface, and the second part CXL interface of the first CXL controller is used for being connected with the PCIE interface; the first part CXL interface and the second part CXL interface of the first CXL controller can access the memory space of all connected DIMMs of the first CXL controller;

The CXL interface of the second CXL controller is divided into a first part CXL interface and a second part CXL interface, the first part CXL interface of the second CXL controller is used for being connected with the cable interface, and the second part CXL interface of the second CXL controller is used for being connected with the PCIE interface; the first part CXL interface and the second part CXL interface of the second CXL controller can access the memory space of all DIMMs connected with the second CXL controller;

The cable interface is used for accessing all memory spaces connected with the first CXL controller and the second CXL controller;

And the PCIE interface is used for accessing all memory spaces connected with the first CXL controller and the second CXL controller.

2. The storage expansion device of claim 1, wherein the CXL interface of the first CXL controller is an X16 interface, and the first and second portion CXL interfaces of the first CXL controller are both X8 interfaces; the first part CXL interface of the first CXL controller is connected with the first X8 interface of the cable interface, and the first part CXL interface of the second CXL controller is connected with the second X8 interface of the cable interface; the cable interface is used to access all memory spaces of the first portion of DIMMs and to access all memory spaces of the second portion of DIMMs.

3. The storage expansion device of claim 1 or 2, wherein the CXL interface of the second CXL controller is an X16 interface, the first and second portion CXL interfaces of the second CXL controller each being an X8 interface; the PCIE interface is divided into a first X8 interface and a second X8 interface; the second part CXL interface of the first CXL controller is connected with the first X8 interface of the PCIE interface, and the second part CXL interface of the second CXL controller is connected with the second X8 interface of the PCIE interface; the PCIE interface is configured to access all memory spaces of the first portion of DIMMs and to access all memory spaces of the second portion of DIMMs.

4. A storage expansion device according to any one of claims 1 to 3, wherein the first CXL controller has stored therein a first mapping table corresponding to a first portion of the CXL interfaces of the first CXL controller and a second mapping table corresponding to a second portion of the CXL interfaces of the first CXL controller, the first mapping table effecting a mapping of the memory physical addresses of the servers to which the first portion of the CXL interfaces of the first CXL controller are connected to all DIMM memory physical addresses of the first CXL controller; the second mapping table enables mapping of memory physical addresses of servers to which the second portion of the first CXL controller is connected to memory physical addresses of all DIMMs of the first CXL controller.

5. A storage expansion device according to any one of claims 1 to 3, wherein the second CXL controller has stored therein a third mapping table corresponding to a first portion of the CXL interfaces of the second CXL controller and a fourth mapping table corresponding to a second portion of the CXL interfaces of the first CXL controller, the third mapping table effecting a mapping of the memory physical addresses of the servers to which the first portion of the CXL interfaces of the second CXL controller are connected to all DIMM memory physical addresses of the second CXL controller; the fourth mapping table enables mapping of memory physical addresses of servers to which the second portion of the CXL controller is interfaced to all DIMM memory physical addresses of the second CXL controller.

6. The memory expansion device of claim 2, further comprising a sensor and system management bus SMbus switch interface disposed on the substrate;

The sensor is used for detecting the temperature of the storage expansion device;

A first end of the SMbus switch interface is connected to the first CXL controller and the second CXL controller;

The second end of the SMbus switch interface is connected with a sensor; and a third end of the SMbus switch interface is used for a cable interface or a PCIE interface.

7. The memory expansion device of any of claims 1-6, wherein the cable interface and the PCIE interface each provide a clock pin, a reset pin, a SMbus pin, an in-place pin, and a power pin, and a third end of the SMbus switch interface is connected to the cable interface and the SMbus pin of the PCIE interface.

8. The storage expansion device of any of claims 1-6, wherein the storage expansion device is in a PCIE standard card form, the PCIE interface is disposed on a long side of the substrate and is used for being vertically plugged into a back board in the computing device or the storage expansion device is in a card plug form, and the PCIE interface is disposed on a short side of the substrate and is used for being horizontally plugged into the back board in the computing device.

9. A storage expansion device, comprising: the device comprises a substrate, and a cable interface, a PCIE interface, a CXL controller and a plurality of dual in-line memory module DIMMs which are arranged on the substrate;

The CXL controller is connected with the plurality of DIMMs;

The CXL interface of the CXL controller is divided into a first part CXL interface and a second part CXL interface, the first part CXL interface is connected with the cable interface, and the second part CXL interface is connected with the PCIE interface; the first part CXL interface and the second part CXL interface can access the memory space of all DIMMs connected with the CXL controller;

the cable interface is used for accessing all memory spaces of the CXL controller;

The PCIE interface is configured to access all memory spaces of the CXL controller.

10. A computing device, comprising: a backplane and the storage expansion device of any of claims 1-9;

the storage expansion device is connected with the backboard.