CN118033392A

CN118033392A - Circuit detection method and device, electronic device, storage medium, and program product

Info

Publication number: CN118033392A
Application number: CN202410445926.5A
Authority: CN
Inventors: 徐浩丰
Original assignee: Innoda Chengdu Electronic Technology Co ltd
Current assignee: Innoda Chengdu Electronic Technology Co ltd
Priority date: 2024-04-15
Filing date: 2024-04-15
Publication date: 2024-05-14
Anticipated expiration: 2044-04-15
Also published as: CN118033392B

Abstract

The present application relates to the field of electronic circuits, and in particular, to a circuit detection method and apparatus, an electronic device, a storage medium, and a program product. The circuit detection method comprises the following steps: determining a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected based on a design file corresponding to the circuit to be detected; setting the output of a non-target logic unit in the circuit to be detected and the main input of the circuit to be detected as detection starting points; creating a working set, and adding a detection starting point as first objects in the working set, wherein all the first objects in the working set can be taken out in any order or randomly; and the first object is taken out from the working set through at least one thread running in parallel, and the detection of the loop to be detected is carried out according to the second object to which the first object is connected in the signal propagation direction of the circuit to be detected. The application improves the detection efficiency and can effectively detect the feedback loop except the combination logic loop.

Description

Circuit detection method and device, electronic device, storage medium, and program product

Technical Field

The present application relates to the field of electronic circuits, and in particular, to a circuit detection method and apparatus, an electronic device, a storage medium, and a program product.

Background

In the design of integrated circuits, certain types of feedback loops, such as combinational logic loops, latch (Latch) loops, memory (Memory) loops, etc., should be avoided as much as possible, in addition to special design intent (e.g., pseudo random number generator, design for testability Bypass (design for Test Bypass, abbreviated as DFT Bypass) logic, etc.), because these particular types of feedback loops can adversely affect the performance of the integrated circuit. For example, when a combinational logic loop occurs, there may be the following effects: 1. the combinational logic loop violates the synchronous design principle, and oscillations, burrs and timing violations are easy to generate, so that the whole system becomes extremely unstable, for example, a circuit is in a deadlock state, and an oscillating circuit is formed at a very high frequency; 2. the logic function implemented by the combinational logic loop is completely dependent on the delays and wiring delays of the combinational logic gates on the loop, if these delays change, the original logic function will change thoroughly, and the changed function is difficult to predict, which affects the correctness of the design function, resulting in that the design is basically not portable.

The feedback loop which does not meet the design intent is generally less in the conventional design based on the constraint of the design specification, when the conventional design file is detected, the situation that the feedback loop which does not meet the design intent is actually detected is less, most of time and resources are used for traversing each path of signal transmission, especially, under the current situation that the design of an integrated circuit is more and more complicated, the number of logic units is generally quite large, the path depth of the signal transmission is also generally quite large, and the detection method in the related art directly or indirectly involves the path backtracking operation, namely, the signal is retransmitted back to the starting point of a main path or a branch path, so that a great amount of time and resources are consumed for traversing the signal transmission path, and the detection efficiency is quite low. In addition, the related art relies on the data structure of a stack (stack) or a queue (queue) of first-in-first-out in the detection process, and there is a limitation on the processing sequence of the logic units, so that in practical application, it is difficult to effectively support multi-thread processing, and the detection efficiency of the feedback loop cannot be improved by using multi-thread implementation. Moreover, the current common feedback loop detection method is mainly aimed at detecting a combinational logic loop, and for other types of feedback loops, effective detection cannot be performed.

Disclosure of Invention

The application provides a circuit detection method and device, electronic equipment, storage medium and program product, which at least solve the problems that the detection efficiency of the related technology is low and feedback loops except for a combinational logic loop cannot be effectively detected.

According to a first aspect of an embodiment of the present application, there is provided a circuit detection method, including: determining a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected based on a design file corresponding to the circuit to be detected; setting the output of a non-target logic unit in the circuit to be detected and the main input of the circuit to be detected as detection starting points; creating a working set, and adding a detection starting point as first objects in the working set, wherein all the first objects in the working set can be taken out in any order or randomly; and the first object is taken out from the working set through at least one thread running in parallel, and the detection of the loop to be detected is carried out according to the second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

According to a second aspect of an embodiment of the present application, there is provided a circuit detection device including: the determining unit is configured to determine a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected based on the design file corresponding to the circuit to be detected; a setting unit configured to set an output of a non-target logic unit in the circuit to be detected and a main input of the circuit to be detected as detection start points; a creation unit configured to create a work set, adding the detection start point as first objects in the work set, wherein all the first objects in the work set can be fetched in any order or randomly; the detection unit is configured to take out a first object from the working set through at least one thread running in parallel, and detect a loop to be detected according to a second object to which the first object is connected in a signal propagation direction of the circuit to be detected.

According to a third aspect of an embodiment of the present application, there is provided an electronic apparatus including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute instructions to implement the circuit detection method according to the application.

According to a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium, which when executed by at least one processor, causes the at least one processor to perform a circuit detection method as described above according to the present application.

According to a fifth aspect of embodiments of the present application, there is provided a computer program product comprising computer instructions which, when executed by a processor, implement a circuit detection method according to the present application.

The technical scheme provided by the embodiment of the application at least has the following beneficial effects:

According to the circuit detection method and device, the electronic equipment, the storage medium and the program product, corresponding detection starting points can be set according to the types of the loops to be detected, and the loops to be detected are detected based on the set detection starting points, so that the circuit detection method is not limited to the detection of the combinational logic loops, and can support various types of loops to be detected; in addition, the application can add the set detection starting points into the working set, all the detection starting points in the working set can be taken out according to any sequence or randomly, and the limitation on the processing sequence of the logic unit is overcome, so that the parallel detection of the whole circuit is realized by supporting the parallel processing of objects in the working set by multiple threads, and when the number of parallel threads is 1, the parallel threads are equivalent to single threads, therefore, the application can be perfectly compatible with single threads and multiple threads; furthermore, each parallel thread only needs to take out the detection starting point from the working set to carry out loop detection, and the signal is not required to be retransmitted back to the starting point of the main path or the branch path, so that the path backtracking operation is not involved, and the time for traversing the path can be effectively reduced. Therefore, the application solves the problems that the detection efficiency of the related technology is low and the feedback loops except the combination logic loop cannot be effectively detected.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application and do not constitute a undue limitation on the application.

FIG. 1 is a schematic diagram of a combinational logic loop and a non-combinational logic loop in the related art;

FIG. 2 is a flow chart illustrating a method of circuit detection according to an exemplary embodiment;

FIG. 3 is an overall flow chart of a circuit detection method according to an exemplary embodiment;

FIG. 4 is a schematic diagram of a circuit to be detected, shown according to an exemplary embodiment;

FIG. 5 is a schematic diagram of another circuit to be detected, shown according to an exemplary embodiment;

FIG. 6 is a block diagram of a circuit detection device, according to an example embodiment;

Fig. 7 is a block diagram of an electronic device 700 according to an embodiment of the application.

Reference numerals illustrate:

60-determining unit; 62-setting up unit; a creation unit 64; a detection unit 66; 700-an electronic device; 701-memory; 702-a processor.

Detailed Description

In order to enable a person skilled in the art to better understand the technical solutions of the present application, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. The embodiments described in the examples below do not represent all embodiments consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

Here, "at least one of items" appearing in the present application means three cases in parallel including "any one of the items", "a combination of any of the items", "an entirety of the items". For example, "including at least one of a and B" includes three cases side by side as follows: (1) comprises A; (2) comprising B; (3) includes A and B. For example, "at least one of the first and second steps is executed", that is, three cases are juxtaposed as follows: (1) performing step one; (2) executing the second step; (3) executing the first step and the second step.

With the progress of manufacturing technology and design technology, the design method of electronic systems has undergone profound changes, from Computer aided design (Computer AIDED DESIGN, abbreviated as CAD), computer aided engineering (Computer AIDED ENGINEERING, abbreviated as CAE) to electronic design automation (Electronic Design Automation, abbreviated as EDA), the degree of automation of the design of electronic systems has been higher and the complexity of the design has been higher and higher.

The integrated circuit EDA refers to a design method for completing the processes of functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule inspection, etc.) and the like of a very large scale integrated circuit chip by using computer aided design software. Currently, EDA technology has become a powerful tool for modern electronic design, and without support of EDA technology, it is not conceivable to complete the design and fabrication of very large scale integrated circuits, and integrated circuit designers need to design complex integrated circuits of hundreds of thousands to hundreds of billions of transistors using EDA tools to reduce design bias, improve die success rate, and save die cost.

In the design of integrated circuits, certain types of feedback loops, such as combinational logic loops, latch (Latch) loops, memory (Memory) loops, etc., should be avoided as much as possible, in addition to special design intent (e.g., pseudo random number generator, design for testability Bypass (design for Test Bypass, abbreviated as DFT Bypass) logic, etc.), because these particular types of feedback loops can adversely affect the performance of the integrated circuit.

A brief description of the combinational logic loop, latch (Latch) loop, memory (Memory) loop, hybrid loop, etc.) follows:

1. Combinational logic loop (combinational loop)

Combinational loop is a feedback loop of the combinational logic gate, which is a loop formed by directly feeding back the output signal of the combinational logic circuit to the input node thereof without any sequential logic circuit (such as a register). An example of a combinational and non-combinational logic ring is shown in fig. 1, where D represents a data input pin (data input pin), SET represents a SET input pin (SET pin), CLR represents a reset input pin (clear pin), > represents a clock pin (clock pin), Q represents a data output pin (data output pin),Representing the inverted output of Q, if Q output is 1, then/>Output is 0, otherwise Q output is 0, then/>The output is 1.

Logic gates (logic gates) are basic gate level elements on an integrated circuit, such as NOT, OR, NOR, AND, exclusive OR, XNOR, AND the like. The logic gate circuit is classified into a combinational logic circuit and a sequential logic circuit at a high level:

Combinational logic circuit (combinational logic): the output at any instant depends only on the input at the current instant, is irrelevant to the historical state before the circuit (i.e. has no memory capacity), and does not involve the processing of jump edge signals in logic, such as multiplexers, encoders, decoders, shifters, comparators and the like;

Sequential logic (sequential logic): the output depends not only on the current input but also on the historical state of the circuit, with storage elements inside the circuit for memorizing state information, such as flip-flops, latches, etc.; in terms of circuit behavior, regardless of input variations, it is only when a rising or falling edge of the clock arrives that it is possible to vary the output.

2. Latch loop

Latch is a logic unit with memory function in integrated circuit, and can change state under the action of specific input pulse level.

When the Enable (Enable) pin signal of the latch is always 1 (always on), the effect is equal to that of a buffer, and the buffer is a combinational logic gate, in other words, the latch loop is equivalent to a combinational logic loop in a specific case, so that the circuit is adversely affected.

3. Memory loop

Memory (Memory) is a logic unit having a function of storing data in an integrated circuit, and can be largely classified into a random access Memory (Random Access Memory, abbreviated as RAM) and a Read Only Memory (abbreviated as ROM) according to the type of use.

The Memory loop itself does not adversely affect the logic of the circuit, but affects Test coverage such as Design For Test (DFT) tools, where a low coverage means that if a fault is present in some areas of the chip it is undetectable, the chip produced may have faults in those areas, thereby reducing the reliability of the chip.

4. Hybrid loop

To meet the specific design intent, the integrated circuit design is typically applied to specific logic cells with complex feedback loop structures, such as operational amplifiers, filters, oscillators, etc. In the case where various logic cell circuits are complicated to interleave with each other, a hybrid loop is involved, which means that two or more types of feedback loops exist simultaneously in one circuit.

Although the hybrid loop may perform more complex functions than a single feedback loop in some applications, such as gain control, bandwidth control, phase control, etc., the design of the hybrid loop requires consideration of interactions between the various feedback loops, which may lead to reduced performance of the circuit if there is interference between any two feedback loops.

At present, a common feedback loop detection method is mainly aimed at detecting a combined logic loop, namely, after a designer reads a design file (for example, verilog file) by using an EDA tool in an integrated circuit design, the EDA tool can detect the combined logic loop aiming at a combined logic gate in a code of the design file, and when the combined logic loop which does not accord with the design intent is detected, the EDA tool usually alarms or cuts off the combined logic loop. The common detection method of the combinational logic loop is mainly based on depth-first search (DEPTH FIRST SEARCH, abbreviated as DFS) for detection, and comprises the following steps: 1. detecting from the fan-out (fanout) of a combinational logic gate whether a signal arrives at itself, i.e. whether a signal arrives at its input from the output of a combinational logic gate; 2. traversing the whole circuit along the signal transmission direction, and labeling the same combinational logic gate twice in a labeling manner to find a combinational logic loop; 3. the whole circuit is traversed along the signal transmission direction, and the multi-point simultaneous inspection is performed by using a two-list mode.

Since the order of DFS traversal is depth-first, the above-mentioned related art involves path traceback operation in the process of detecting the feedback loop, and is inefficient in case of a large path depth. In addition, DFS is generally implemented using single thread because, although DFS theoretically supports multi-threaded implementation, new problems are generated in the multi-threaded processing thereof, such as consideration of processing order among branch paths, etc., and thus, the multi-threaded performance of DFS method is very poor and it is far from meeting the efficiency requirements of large-scale industrial software such as EDA, in other words, the related art based on DFS has difficulty in supporting multi-threads effectively in practical applications.

In addition to the DFS-based related art described above, there is currently a detection method based on breadth-first search (Breadth FIRST SEARCH, abbreviated BFS). Since the order of BFS traversal is breadth-first, BFS may generally not consider path backtracking, however, current BFS only can query one combinational logic loop at a time and needs to eliminate it after each query of the combinational logic loop, when there are multiple combinational logic loops in one logic circuit, the steps of searching and eliminating need to be repeatedly performed for the whole circuit, which is equivalent to the operation that the searching process still involves path backtracking. Meanwhile, the current BFS uses a data structure of a first-in first-out queue, which indicates that the combinational logic gates need to be processed according to a certain sequence, so that the processing sequence between the branch paths is also certain, and therefore, it is difficult to support multithreading.

In general, feedback loops which do not meet design intent are generally less likely to occur in conventional designs based on constraints of design specifications, and when conventional designs are detected, the feedback loops are less likely to be actually detected, most of time and resources are used for traversing each path of signal transmission, especially, under the current situation that integrated circuit designs are more and more complicated, the number of logic units is generally quite large, and the path depth of signal transmission is also generally quite large, and the conventional detection methods directly or indirectly involve path backtracking operation, namely, the signal is retransmitted back to the starting point of a main path or a branch path, which consumes a great amount of time and resources to traverse the signal transmission path, so that the detection efficiency is quite low. In addition, the above related technologies all rely on the data structure of the stack (stack) or the queue (queue) of the first-in-last-out in the detection process, and there is a limitation on the processing sequence of the logic unit, which makes it difficult to effectively support the multithreading in practical application, and cannot improve the detection efficiency of the feedback loop by using the multithreading implementation.

Moreover, for other types of feedback loops, no effective detection is currently possible.

In view of the above problems, the present application provides a circuit detection method and apparatus, an electronic device, a storage medium, and a program product, where, for a type of a loop to be detected, a corresponding detection start point and a detection end point may be set, and detection of the loop to be detected is performed based on the set detection start point and detection end point, so that the present application is not limited to detection of a combinational logic loop, and may support multiple types of loops to be detected. In addition, the application can add the set detection starting points into the working set, all the detection starting points in the working set can be taken out according to any sequence or randomly, and the limitation on the processing sequence of the logic unit is overcome, so that the parallel detection of the whole circuit is realized by supporting the parallel processing of objects in the working set by multiple threads, and when the number of parallel threads is 1, the parallel threads are equivalent to single threads, therefore, the application is perfectly compatible with single threads and multiple threads; furthermore, each parallel thread only needs to take out the detection starting point from the working set to carry out loop detection, and the signal is not required to be retransmitted back to the starting point of the main path or the branch path, so that the path backtracking operation is not involved, and the time for traversing the path can be effectively reduced.

Hereinafter, a circuit detection method and apparatus according to exemplary embodiments of the present application will be described in detail with reference to the accompanying drawings.

It should be noted that the circuit inspection method according to the exemplary embodiment of the present application may be applied to integrated circuit electronic design automation (Electronic Design Automation, EDA) software, for example, integrated circuit EDA software may be loaded on a user terminal, a user may read an integrated circuit design file using the integrated circuit EDA software on the user terminal, and the circuit inspection method may be performed on the design file.

The above-mentioned user terminal may be, for example, a tablet computer, a notebook computer, a digital assistant, a wearable device, etc., however, the implementation scenario of the above loop detection method is merely an example scenario, and the circuit detection method according to the exemplary embodiment of the present application may also be applied to other application scenarios, for example, it may also be that a user requests circuit detection from a server through a network at a user terminal (for example, a mobile phone, a desktop computer, a tablet computer, etc.), where the server may perform loop detection by executing the loop detection method according to the exemplary embodiment of the present application, and the server may be a stand-alone server, a server cluster, or a cloud computing platform or a virtualization center.

Although in embodiments of the present application the application of integrated circuit EDA software in an example scenario is described by way of example, embodiments of the present application are not limited thereto and may be applied to other application scenarios of integrated circuit EDA software.

Fig. 2 is a flow chart illustrating a circuit detection method according to an exemplary embodiment, as shown in fig. 2, including the steps of:

In step S201, a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected is determined based on the design file corresponding to the circuit to be detected.

Specifically, in the design of an integrated circuit chip, functions and behaviors of an electronic circuit are described by a hardware description language (Hardware Description Language, abbreviated as HDL), that is, a design file containing functions and behaviors of an electronic circuit of a circuit to be tested is a text form for describing structures and behaviors of digital system hardware by the hardware description language, for example, a logic circuit diagram, a logic expression, a logic function completed by a digital logic system, and the like, so that various abstract design levels such as an algorithm level, a register transmission level, a gate level, a switch level, and the like can be modeled. Currently, typical HDL includes Verilog HDL, VHDL (VERY HIGH SPEED INTEGRATED Circuit HDL), system Verilog HDL, etc., and the present application is not limited thereto.

By way of example, taking a hardware description language that is Verilog HDL (abbreviated as Verilog), an integrated circuit designer may use Verilog HDL to design an integrated circuit chip, where the design file is a Verilog design file (also referred to as a Verilog file).

By way of example, the types of loops to be detected described above may include, but are not limited to: the present disclosure is not limited in this regard as combinational logic loops, latch loops, memory loops.

As an example, in the integrated circuit design, a designer may read in a design file (e.g., verilog file) by using an EDA tool, where the EDA tool may perform detection of a combinational logic loop for a circuit to be detected in the design file, e.g., the EDA tool may analyze the design file corresponding to the circuit to be detected, and at least analyze and determine information such as Primary Input (PI), primary Output (PO), and various logic units of the circuit to be detected from all modules in the design file. It should be noted that, in most cases, loop detection is directed to a combinational logic gate, for example, in order to facilitate detection of a combinational logic loop, each logic unit in a design file may be simply divided into a combinational logic gate and a non-combinational logic gate, where the non-combinational logic gate includes a sequential logic unit (such as FF, latch, memory and the like) and other logic units (such as macro, blackbox and the like), the FF is a trigger (Flipflop), the macro is user-defined content, and the blackbox is a black box.

As an example, after analyzing the design file, the EDA tool may first determine the type of the loop to be detected, such as a combinational logic loop, a Latch loop, a Memory loop, and the like, according to the user requirement, so as to determine a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected.

According to an exemplary embodiment of the application, the type of loop to be detected comprises at least one of: the device comprises a combinational logic loop, a latch loop and a memory loop, wherein a target logic unit corresponding to the combinational logic loop is a combinational logic gate, a target logic unit corresponding to the latch loop is a latch unit, and a target logic unit corresponding to the memory loop is a memory unit. According to the embodiment, the types of the loops to be detected are not limited to one, namely, the coexisting loops of multiple types can be detected simultaneously, and for different types of the loops to be detected, only the corresponding detection starting point is required to be set, and the detection of the loops to be detected of the corresponding types is carried out based on the set detection starting point, so that the application can also support the detection of the mixed loops.

As an example, the type of the loop to be detected is a combinational logic loop, and the target logic unit is a combinational logic gate; for another example, if the type of the loop to be detected is a Latch loop, the target logic unit is Latch; for another example, if the type of the loop to be detected is a Memory loop, the target logic unit is a Memory; for another example, to detect both combinational logic loops and Latch loops, the target logic unit may be a combinational logic gate and Latch.

It should be noted that if other types of feedback loops are to be detected, and so on, this is not exhaustive.

Returning to fig. 2, in step S202, the output of the non-target logic unit in the circuit to be detected and the main input of the circuit to be detected are set as detection start points.

Specifically, after determining the type of the loop to be detected and the target logic unit corresponding to the type of the loop to be detected in the circuit to be detected according to the user requirement, the detection starting point may be set according to the target logic unit corresponding to the type of the loop to be detected. The non-target logic units are logic units except the target logic units in the circuit to be detected.

As an example, when setting the detection start point, excluding the target logical unit, in other words, when setting the detection start point, the target logical unit is not considered, only other logical units other than the target logical unit, that is, non-target logical units, i.e., the output of the non-target logical unit is set as the detection start point, and the specific setting may be divided into the following two parts:

it is necessary to set a section, that is, a section which needs to be set regardless of the type of loop to be detected: the non-power PI in the design file is set as the start point of detection, i.e. the start point at which the signal starts to propagate.

The on-demand setting section, i.e. the section that needs to be set according to the type of loop to be detected: the output (output) of the non-target logical unit in the design file is set as the start point of detection, i.e. the start point at which the signal starts to propagate.

As an example, if the type of loop to be detected is a combinational logic loop, the target logic unit is a combinational logic gate, at which time the outputs of PI and non-combinational logic gates may be set as the detection start point.

As an example, if the type of loop to be detected is a Latch loop, the target logic unit is Latch, and the outputs of PI and non-Latch units are set as the detection start points.

As an example, if the type of loop to be detected is a Memory loop, the target logical unit is a Memory, and the outputs of the PI and non-Memory units are set as the detection start points.

As an example, if the types of loops to be detected include two types, namely a combinational logic loop and a Latch loop, the target logic unit is a combinational logic gate and a Latch, and the outputs of the non-Latch units in the PI and non-combinational logic gates are set as the detection start points.

Returning to fig. 2, in step S203, a working set is created, and a detection start point is added as first objects in the working set, wherein all the first objects in the working set can be fetched in any order or randomly.

As an example, the data structure of the working set may be set to a nonlinear structure, that is, the data in the working set may be fetched in any order or randomly, without affecting the detection result, to be used with multithreading, whereas the conventional scheme sets the data structure for storing the detection start point to a linear structure, for example, a stack or a queue, that is, the detection start point needs to be processed in a certain order, resulting in that the processing order between branch paths is also certain, and thus it is difficult to support multithreading.

Returning to fig. 2, in step S204, the first object is fetched from the working set by at least one thread running in parallel, and the detection of the loop to be detected is performed according to the second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

As an example, a detection start point may be added to the working set, as first objects in the working set, all the first objects in the working set may be fetched in any order or randomly, the first objects may be fetched from the working set by at least one thread running in parallel, and the detection of the loop to be detected may be performed according to a second object to which the fetched first objects are connected in the signal propagation direction.

As an example, the present embodiment may be perfectly compatible with two processing modes, i.e., single-threaded and multi-threaded:

1) The processing mode of the single thread is as follows: the first object in the working set, e.g. the detection start point (output pin or PI), is processed one after the other.

2) The multithreading processing mode is as follows: a plurality of first objects in the working set, such as a plurality of detection starting points, are put into a plurality of threads in parallel for processing, for example, eight threads can process eight first objects at the same time at one time, and each thread is independent and not disturbed.

It should be noted that, in view of nanosecond or microsecond response during code running, in order to avoid errors, a locking and unlocking operation is usually involved in multithreading, and accordingly, when a working set is processed, a data stream supports thread locking, that is, when one thread is operating, when a target access number of the same target logic unit needs to be reduced by 1 at a certain key node, other parallel threads need to be queued.

By way of example, taking the process of a single detection start point as an example, when all detection start points are added to a work set and all detection start points in the work set can be taken out in any order or randomly, a current thread can take out one detection start point (i.e., one first object) from the work set, determine a second object to which the detection start point is connected in the signal propagation direction, and perform loop detection according to the second object.

As an example, from this second object, loop detection may be performed in a number of ways:

For example, if the second object is a target logic unit, the signal may pass through and continue to propagate forward, and may be marked 1 time at this time, if the second object is a non-target logic unit or a main output, that is, if the second object is a set detection endpoint, signal propagation of the current path is stopped, and if the same target logic unit is marked twice during the detection, a feedback loop may exist, that is, a loop to be detected exists.

For another example, if the second object is a target logic unit, the working set may be updated in conjunction with the target access number of the target logic unit, and the signal propagation of the current path may be stopped for corresponding processing, and if the second object is a non-target logic unit or a main output, that is, if the second object is a set detection endpoint, the signal propagation of the current path may be stopped, which will be specifically described in detail in the following embodiment, and will not be discussed herein.

According to an exemplary embodiment of the present application, the detecting of the loop to be detected by fetching a first object from the working set by at least one thread running in parallel and according to a second object to which the first object is connected in a signal propagation direction of the circuit to be detected may include: the method comprises the steps that a first object is taken out of a working set through at least one thread running in parallel, and the working set is updated according to a second object to which the first object is connected in the signal propagation direction of a circuit to be detected; and under the condition that the working set is empty and all threads in the at least one thread are in a finished state, detecting at least one loop to be detected. Further, the input of the non-target logic unit and the main output of the circuit to be detected may be set as detection end points; for each of at least one thread running in parallel, the following predetermined processing is performed: retrieving any one of the first objects from the working set and determining a second object to which any one of the first objects is connected in the signal propagation direction; responding to a second object connected to any one of the first objects as a target logic unit, updating a working set based on the target access times of the target logic unit, and continuing to execute predetermined processing to stop current signal propagation, and taking out the other first object from the working set to start continuing to propagate signals, wherein the target access times are determined based on the number of input pins of the target logic unit; in response to the second object to which any one of the first objects is connected being a detection endpoint, continuing to perform a predetermined process to terminate the current signal propagation, retrieving another of the first objects from the working set and starting to re-propagate the signal; and under the condition that the working set is empty and all threads running in parallel are in a finished state, aiming at a first target logic unit with target access times not being 0, detecting a loop to be detected.

According to the embodiment, the target access times of the target logic unit are introduced to update the working set, so that the working set is real-time and is not invariable, the traversal of the circuit to be detected can be quickened, the detection can be conveniently and rapidly completed, the path backtracking operation is not needed, and the time for traversing the path is shortened.

As an example, the above-mentioned updating of the working set based on the target access times of the target logical units may be implemented by performing subtraction processing on the target access times and determining whether the output of the target logical units may be added to the working set by whether the target access times are 0; updating the working set may also be accomplished in other ways, and the disclosure is not limited in this regard.

As an example, after determining, according to a user requirement, a type of a loop to be detected and a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected, a detection endpoint may be set according to the target logic unit corresponding to the type of the loop to be detected.

As an example, when the detection endpoint is set, the target logic unit is excluded, in other words, the detection endpoint is set without considering the target logic unit, and only other logic units except the target logic unit, that is, non-target logic units, namely, inputs of the non-target logic units are set as the detection endpoint, and the specific setting can be divided into the following two parts:

It is necessary to set a section, that is, a section which needs to be set regardless of the type of loop to be detected: the PO is set to the detection endpoint, i.e., the signal stops continuing to propagate forward when PO is encountered during signal propagation.

The on-demand setting section, i.e. the section that needs to be set according to the type of loop to be detected: the input (input) of the output of the non-target logic cell is set to the detection endpoint, i.e. the signal stops continuing to propagate forward when the non-target logic cell is encountered during signal propagation.

As an example, if the type of loop to be detected is a combinational logic loop, then the target logic cell is a combinational logic gate, at which point the inputs of the PO and non-combinational logic gates may be set to the detection endpoint.

As an example, if the type of loop to be detected is a Latch loop, then the target logic unit is Latch, at which point the inputs of the PO and non-Latch units are set to the detection endpoint.

As an example, if the type of loop to be detected is a Memory loop, the target logical unit is a Memory, and the inputs of the PO and non-Memory units are set as the detection endpoint.

As an example, if the type of loop to be detected includes two types, namely a combinational logic loop and a Latch loop, the target logic unit is a combinational logic gate and a Latch, and at this time, the inputs of the non-Latch units in the PO and non-combinational logic gates are set as detection end points.

According to an exemplary embodiment of the present application, updating the working set based on the target access times of the target logical unit may include: subtracting 1 from the target access times of the target logic unit; in response to the target access number of the target logical unit being 0, adding the output of the target logical unit as the first object in the working set, in one possible implementation, the output of the target logical unit may be set as the detection relay point, and the detection relay point may also be added as the first object in the working set; in response to the target access number of the target logical unit being other than 0, the working set is maintained unchanged. According to the embodiment, subtraction processing is performed on the target access times, whether the output of the target logic unit can be added to the working set is determined according to whether the target access times are 0, and repeated traversing of the target logic unit can be avoided on the basis that all input paths of the target logic unit are traversed, so that detection time is effectively shortened.

By way of example, still taking the processing procedure of a single detection start point as an example, the current thread takes one detection start point (i.e. one first object) from the working set, determines a second object to which the detection start point is connected in the signal propagation direction, and performs corresponding processing according to the second object:

If the second object is a target logic unit, subtracting 1 from the target access frequency of the target logic unit, and then judging whether the signal can continue to propagate forward through the target logic unit, specifically, if the target access frequency is subtracted by 1, the target access frequency of the target logic unit returns to 0, which means that the signal can continue to propagate forward through the target logic unit, otherwise, the signal cannot continue to propagate forward through the target logic unit; if the judgment result is that the signal can continue to propagate forwards through the target logic unit, putting all the outputs (namely output pins) of the target logic unit into a current working set, stopping signal propagation of a current path, and then continuing to take out another detection starting point from the current working set for processing; if the judgment result is that the signal can not continue to propagate forwards through the target logic unit, namely, the signal propagation of the current path is stopped, another detection starting point is directly taken out of the current working set for processing.

If the second object is the main output of the non-target logic unit or the circuit to be detected, the set detection end point is met, the signal propagation of the current path is stopped at the moment, and one detection start point is directly taken out from the current working set for processing.

After the above processing, when the current working set is empty and all threads are in a completed state, whether all target access times of all target logic units are 0 can be judged, if a first target logic unit with the target access times not being 0 exists, whether a feedback loop exists is further judged according to the first target logic unit.

According to an exemplary embodiment of the present application, before the detection of the loop to be detected is performed for the first target logic unit whose target access number is not 0, any thread is marked as a completed state in a case where the current predetermined processing is completed by any thread and the working set is empty.

As an example, when the current thread is idle, if the current working set has no first object available to fetch (i.e., the current working set is empty), the current thread is marked as complete, i.e., the current thread is represented as being in complete; the current working set is updated continuously during the processing, and as the first object is put into or taken out continuously, the first object in the working set may decrease or increase. When all threads are marked as being in a finished state, the current working set is necessarily empty, at this time, whether all target logic units have been accessed for 0 or not can be further judged, and if a first target logic unit with the target access for which the target access is not 0 exists, whether a feedback loop exists or not needs to be further judged for the first target logic unit.

According to an exemplary embodiment of the present application, for a first target logic unit with a target access number other than 0, the detection of a loop to be detected may include: taking the output of the first target logic unit as a new detection starting point respectively, detecting each signal path starting from the new detection starting point for each new detection starting point, and determining whether a loop to be detected exists or not based on the number of times that the propagated signal passes through each target logic unit; and ending the detection of the circuit to be detected under the condition that the first target logic unit finishes detection and the loop to be detected is not detected. According to the embodiment, the output of the first target logic unit is used as a new detection starting point, and the detection methods of the related technologies are adopted to detect loops respectively, so that the detection of the first target logic unit can be conveniently and rapidly completed; in addition, in the whole detection process, a loop is found, the original circuit can be continuously detected without eliminating the loop, even if a plurality of loops exist in the design file, the whole logic circuit does not need to be traversed repeatedly, the detection efficiency is greatly improved, the detection times can be effectively reduced, and the effect of reducing the detection time is achieved.

As an example, in the case where there is a target logic unit whose target access number is not 0, the output of the target logic unit whose target access number is not 0 may be used as a new detection start point, respectively, the detection of the loop to be detected may be performed along the signal propagation direction, specifically, the signal propagation may be performed from each new detection start point, and each signal path from the new detection start point may be detected, if the propagated signal passes through the same target logic unit twice, it is determined that there is a feedback loop, and it is required to be stated that, if a set detection end point is encountered in the detection process, the signal propagation of the current signal path is stopped. And when the target logic unit with the target access frequency not being 0 finishes detection and the loop to be detected is not detected, ending the detection of the circuit to be detected.

It should be noted that, in the above embodiment, the specific detection process for each new detection start point may also use other detection methods in the related art, and is not limited to the detection method defined in the above embodiment.

According to an exemplary embodiment of the present application, for a first target logic unit with a target access number other than 0, the detecting of the loop to be detected may further include: taking the output of any one of the first target logic units as a new first detection starting point, detecting each signal path starting from the first detection starting point, and determining whether a loop to be detected exists or not based on the number of times the propagated signal passes through each target logic unit; in response to the absence of a loop to be detected, taking the output of another first target logic unit in all the first target logic units as a new second detection starting point, detecting each signal path starting from the second detection starting point, and determining whether the loop to be detected exists or not based on the number of times the propagated signal passes through each target logic unit until the loop to be detected is detected; clearing 0 the target access times of any one first target logic unit in response to the existence of the loop to be detected, and adding a first detection starting point as a first object in the working set, and continuing to execute the preset processing; and ending the detection of the circuit to be detected under the condition that the target access times of all the first target logic units are 0 or the detection of all the first target logic units is finished and the loop to be detected is not detected.

Through the embodiment, the predetermined processing can be performed again when the loop is found, so that the path backtracking operation can be further reduced, the path traversing time is effectively reduced, and through the embodiment, if the loop does not exist, the detection of the whole circuit can be completed very quickly, because only when the loop is found, the specific units are accurately judged to be in the loop; in addition, in the whole detection process, the existence of a loop is found, the original circuit can be continuously detected without eliminating the loop, and even if a plurality of loops exist in the design file, the whole logic circuit does not need to be repeatedly traversed, so that the detection efficiency is greatly improved, the detection times can be effectively reduced, and the effect of reducing the detection time is achieved.

As an example, if there are a plurality of target logic units whose target access number is not 0, the output of any one of the target logic units is taken as a detection start point, and from this detection start point, it is determined whether or not there is a loop to be detected along the signal propagation direction, and the specific procedure may refer to the previous embodiment, and will not be discussed here. If the output of the target logic units is used as a detection starting point for detection, and when no loop to be detected exists, any one of the remaining target logic units is used as a next detection starting point, and whether the loop to be detected exists is determined along the signal propagation direction until the loop to be detected exists or all target logic units with the target access times not being 0 are detected; if the output of the target logic unit is used as the detection starting point to detect, and it is determined that the loop to be detected exists, the target access times of the target logic unit may be cleared to 0, and all the outputs (i.e. output pins) of the target logic unit may be put into the current working set, and the step of "predetermined processing" in the above embodiment may be returned. And ending the detection of the circuit to be detected under the condition that the target access times of all the first target logic units are 0 or the detection of all the first target logic units is finished and the loop to be detected is not detected.

According to an exemplary embodiment of the present application, before performing a predetermined process, determining the number of predetermined input pins of a target logic unit, wherein the predetermined input pins are input pins that access a circuit to be detected and are used for transmitting data; the number of predetermined input pins is determined as the target number of accesses of the target logical unit. According to the embodiment, the target access times of the target logic units can be rapidly and accurately determined through the number of the input circuits to be detected and used for inputting data.

This step may be performed, for example, after the EDA tool has analyzed the design file, or after the detection start point or the detection end point has been set, which is not limited in this disclosure.

As an example, calculating the target access times of each target logical unit, that is, calculating the target access times of all logical units corresponding to the non-detection start point and the non-detection end point, the calculation constraint condition may be as follows:

1) Only the input pins (input pins) of the logic cells are considered, i.e. the output pins (output pins) of the logic cells are excluded.

2) Only the input pins (i.e. data pins) of the logic cells for transmitting data are considered, i.e. power ground pins (abbreviated as pg pins) are excluded.

3) Only the input pins of the logic unit with the driver (driver) are considered, i.e. the input pins connected to the circuit to be detected, i.e. the input pins suspended (without driver) are excluded, i.e. the input pins not connected to the circuit to be detected.

When the target access times are calculated, the number of input pins which simultaneously meet the 3 limit conditions is taken as the target access times of the corresponding target logic units for each target logic unit.

According to an exemplary embodiment of the present application, in a case where a working set is empty and all threads running in parallel are not in a completed state, a thread in the completed state is selected from among the threads running in parallel to perform a predetermined process in response to a new first object being added to the working set. By the embodiment, the thread marked as the completion state is preferentially used in the processing process, so that the computing resource can be reasonably utilized.

As an example, when the current thread is idle, if the current working set has no first object available to fetch (i.e., the current working set is empty), the current thread is marked as complete, i.e., the current thread is represented as being in complete; when the current working set is empty, if a new first object is put into the working set, the thread marked as the finished state is preferentially used for processing.

According to an exemplary embodiment of the present application, before the detection of the loop to be detected is performed by fetching a first object from the working set by at least one thread running in parallel and according to a second object to which the first object is connected in a signal propagation direction of the circuit to be detected, the number of the at least one thread running in parallel is determined according to a user instruction or a remaining computing resource. According to the embodiment, the number of parallel threads is determined according to the user instruction or the residual computing resources, so that the user demand can be flexibly adapted, and the computing resources can be reasonably utilized.

As an example, before performing the predetermined processing in the above embodiment, that is, before processing the work set, the number of threads used in parallel may be determined according to the user execution or remaining computing resources. Specifically:

1) By default, single-threaded is used, with multi-threading as a functional option, pre-checked by the user for designation (e.g., designating 4 threads or 8 threads).

2) The number of threads used in parallel is determined according to whether the current computing resource is sufficient, and when the computing resource is insufficient, such as the remaining computing resource is 0, the single-thread processing working set is used, and when the computing resource is sufficient, such as the remaining computing resource can support multiple threads, the multiple-thread processing working set is used, wherein the number of threads used in parallel can be determined according to the redundant threads which can be provided by the current computing resource.

For a better understanding of the above embodiments, a description of the system is provided below in connection with fig. 3 to 5.

Fig. 3 is an overall flowchart of a circuit inspection method according to an exemplary embodiment, and as shown in fig. 3, taking an example that a design file is a Verilog file, the method mainly includes the following operations:

1. Beginning (i.e., reading Verilog file of circuit to be detected)

And reading the Verilog file provided by the user by using an EDA tool, analyzing the read Verilog file, and analyzing and determining information such as a main input (PI), a main output (PO), examples (instance) of each logic unit and the like at least from all modules of the Verilog file.

2. Setting a detection start point and a detection end point (i.e., setting a start point and an end point)

Before setting the detection starting point and the detection end point, the type of the loop to be detected, such as a combinational logic loop, a Latch loop, a Memory loop and the like, can be determined according to the user requirements, and then the corresponding detection starting point and detection end point are set according to the type of the loop to be detected.

Setting a principle: according to the type of the loop to be detected, determining a corresponding target logic unit, and excluding the target logic unit when setting a detection starting point and a detection end point, in other words, setting the detection starting point or the detection end point without considering the target logic unit, and only considering other logic units except the target logic unit, namely, non-target logic units, namely, setting the output and the input of the non-target logic unit as the detection starting point and the detection end point respectively.

3. Initializing target access times

The target access number of each target logical unit is calculated, i.e., the number of input pins satisfying the 3 constraints in the above embodiment at the same time is taken as the target access number of the corresponding target logical unit for each target logical unit.

4. Processing work sets

Before processing the working set, the set detection starting point is required to be added to the working set, wherein the data structure of the working set is set to be a nonlinear structure, and the data in the working set can be taken out in any order or randomly without influencing the detection result so as to be matched with the multithreading. This step is perfectly compatible with both single-threaded and multi-threaded processing, each of which has been described in detail in the above embodiments and will not be discussed further herein.

The number of threads used at this step may be determined based on user demand or remaining computing resources prior to processing the working set, the specific determination process also being described in detail in the above embodiments and will not be discussed further herein.

The specific procedure of this step is as follows (illustrated with a single detection start):

the processing procedure of a single detection starting point comprises the following steps: a detection start point (i.e. a first object) is taken from the current working set and a second object to which the detection start point is connected in the direction of signal propagation is determined.

If the second object is a target logical unit, subtracting 1 from the target access number of the target logical unit, and then determining whether the signal can continue to propagate forward through the target logical unit, specifically, determining a condition that the signal continues to propagate forward: the target access number of the target logical unit is 0. If the signal can continue to propagate forwards through the target logic unit, putting all output pins (output pins) of the target logic unit into a current working set, stopping signal propagation of a current path, and then taking out another detection starting point from the current working set for processing; if the signal can not continue to propagate forward through the target logic unit, stopping the signal propagation of the current path, and directly taking out another detection starting point from the current working set for processing.

If the second object is a non-target logic unit or a main output, the second object is a set detection end point, signal propagation of the current path is stopped at the moment, and a detection start point is directly taken out from the current working set for processing.

Logic for use of threads in this step:

1) When the current thread is idle, the current thread is marked as complete if the current working set has no new first object available to fetch (i.e., the current working set is empty).

2) When the current working set is empty, if a new first object is put into the current working set, the thread marked as the finished state is preferentially used for processing.

The current working set is updated continuously during the processing, and as the first object is put into or taken out continuously, the first object in the working set may decrease or increase. When all threads are marked as being in a finished state, the current working set is necessarily empty, at this time, whether all target logic units have been accessed for 0 or not can be judged, if the target logic units with the target access times not being 0 exist, the target logic units with the target access times not being 0 need to be aimed at, and whether a loop to be detected exists or not is further judged, namely, the next step of judging whether to loop is started.

5. Judging whether to circulate

When the current working set is empty and all threads are in a finished state, firstly judging whether the target access times of all target logic units are 0, if the target logic units with the target access times not being 0 exist, the target logic units with the target access times not being 0 are needed to be aimed at, and whether a loop to be detected exists or not.

Specifically, if there are a plurality of target logic units with the number of target accesses not being 0 at this time, the output of any one of the target logic units is taken as a detection start point, and whether a loop to be detected exists is determined along the signal propagation direction from the detection start point, and the specific process can refer to the above embodiment, and will not be discussed here. If the output of the target logic units is used as a detection starting point for detection, and when no loop to be detected exists, any one of the remaining target logic units is used as a next detection starting point, and whether the loop to be detected exists is determined along the signal propagation direction until the loop to be detected exists or all target logic units with the target access times not being 0 are detected; if the output of the target logic unit is used as the detection starting point to detect, when the loop to be detected is determined to exist, the target access times of the target logic unit can be cleared to 0, and all output pins (output pins) of the target logic unit are put into the current working set to return to the step of processing the working set.

6. Ending

And when the target access times of all the target logic units in the step of judging whether to circulate are 0, or the detection of the circuit to be detected is finished under the condition that all the target logic units with the target access times not being 0 are detected and the loop to be detected is not detected.

Fig. 4 is a schematic diagram of a circuit to be detected, according to an exemplary embodiment, and as shown in fig. 4, the circuit to be detected has a loop to be detected, and the detection of the circuit to be detected may include the following steps:

5.1 Read design

Taking a feedback loop for detecting the combination logic gate as an example, using an EDA tool to read a Verilog file provided by a user, analyzing the Verilog file, and finding out non-combination logic gates such as combination logic gates in PI, PO and a circuit, a timing logic unit and the like. It should be noted that the Verilog file is an abstract design file written in a hardware description language, and is not an intuitive logic circuit diagram, but will be described later for ease of understanding by taking fig. 4 as an example, wherein,A value of 1 representing 1 bit (bit) generally represents a direct power connection, i.e., the input is in a normally open or constant 1 state.

5.2 Setting a detection start point

The outputs of the PI and non-combinational logic gates are set as the detection start points. As shown in FIG. 4, PI is [ A, B, C, D, E, F ], the non-combinational logic gate is [ blackbox ], its output is [ balckbox/out ], and these detection origins are put into the current working set.

Current working set: [ A, B, C, D, E, F, blackbox/out ].

5.3 Setting a detection endpoint

The inputs of the PO and the non-combinational logic gate are set to the detection endpoint. As shown in FIG. 4, PO is [ Y ] and the input to the non-combinational logic gate is [ balckbox/in ]. After the detection endpoint is set, when the set detection endpoint is encountered in the signal forward propagation process, the signal forward propagation is stopped.

5.4 Initializing target access times

The target access times of all combinational logic gates (Comb 1 to Comb9 in fig. 4) are calculated, considering only the data pin in the input pin and only the pin with driver (driver) when calculating the times.

After calculation, the number of target accesses of Comb8 is 1, the number of target accesses of Comb6 is 3, and the number of target accesses of the remaining combs is 2.

5.5 Processing work sets

Two processing modes of single thread and four thread are respectively described:

5.5.1 Single-thread processing mode

Initial current working set: [ A, B, C, D, E, F, blackbox/out ]. It should be understood that the objects in the working set may be randomly fetched, without any limitation in order, with sequential fetching in the following examples being for ease of presentation only.

And taking out a detection starting point A from the current working set, subtracting 1 from the target access times of a combination logic gate (comb1) to which the A is connected, wherein the target access times of the comb1 after subtraction processing are 2-1=1, and the signal cannot continue to propagate forwards through the comb1 due to the fact that the target access times are not 0, so that the next event can be started.

Current working set: [ B, C, D, E, F, blackbox/out ]

And taking out a detection starting point B from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb2) to which the B is connected, wherein the target access frequency of the comb2 after subtraction processing is 2-1=1, and the signal cannot continue to propagate forwards through the comb2 due to the fact that the target access frequency is not 0, so that the next event can be started.

Current working set: [ C, D, E, F, blackbox/out ]

And taking out a detection starting point C from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb2) connected with the C, wherein the target access frequency of the comb2 is 1-1=0 after subtraction processing, and the signal can continue to propagate forwards through the comb2 due to the target access frequency of 0, and at the moment, the output (output) of the comb2 is put into the current working set, and the next event can be started.

Current working set: [ D, E, F, blackbox/out, comb2/out ]

And taking out a detection starting point D from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb3) to which the D is connected, wherein the target access frequency of the comb3 after subtraction processing is 2-1=1, and the signal cannot continue to propagate forwards through the comb3 due to the fact that the target access frequency is not 0, so that the next event can be started.

Current working set: [ E, F, blackbox/out, comb2/out ]

And taking out a detection starting point E from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb3) to which the E is connected, wherein the target access frequency of the comb3 is 1-1=0 after subtraction processing, and the signal can continue to propagate forwards through the comb3 due to the target access frequency being 0, and at the moment, the output (output) of the comb3 is put into the current working set, and the next event can be started.

Current working set: [ F, blackbox/out, comb2/out, comb3/out ]

And taking out a detection starting point F from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb4) to which the F is connected, wherein the target access frequency of the comb4 after subtraction processing is 2-1=1, and the signal cannot continue to propagate forwards through the comb4 due to the fact that the target access frequency is not 0, so that the next event can be started.

Current working set: [ blackbox/out, comb2/out, comb3/out ]

Taking out a detection starting point blackbox/out from the current working set, subtracting 1 from the target access times of the combination logic gates (comb7 and comb8) to which the blackbox/out is connected, wherein the target access times of comb7 after subtraction is 2-1=1, and the signal cannot continue to propagate forward through the comb7 due to the fact that the target access times are not 0, so that the next event can be started; the number of times of the Comb8 after the subtraction is 1-1=0, and since the target access number is 0, the signal can continue to propagate forward through the Comb8, and at this time, the output (output) of the Comb8 is put into the current working set, and the next event can be started.

Current working set: [ Comb2/out, comb3/out, comb8/out ]

Taking out a detection starting point comb2/out from the current working set, subtracting 1 from the target access times of the combination logic gates (comb1 and comb6) to which the comb2/out is connected, wherein the target access times of the comb1 after subtraction processing are 1-1=0, and the signal can continue to propagate forward through the comb1 due to the target access times being 0, and at the moment, the output (output) of the comb1 is put into the current working set, and the next event can be started; the target access frequency of the Comb6 after subtraction is 3-1=2, and since the target access frequency is not 0, the signal cannot continue to propagate forward through the Comb6, and the next event can be started.

Current working set: [ Comb3/out, comb8/out, comb1/out ]

Taking out a detection starting point comb3/out from the current working set, subtracting 1 from the target access times of the combination logic gates (comb6 and comb4) to which the comb3/out is connected, wherein the target access times of the comb6 after subtraction processing are 2-1=1, and the signal cannot continue to propagate forward through the comb6 due to the fact that the target access times are not 0, so that the next event can be started; the target access number of the Comb4 after the subtraction is 1-1=0, and since the target access number is 0, the signal can continue to propagate forward through the Comb4, and at this time, the output (output) of the Comb4 is put into the current working set, and the next event can be started.

Current working set: [ Comb8/out, comb1/out, comb4/out ]

And taking out a detection starting point comb8/out from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb9) to which the comb8/out is connected, wherein the target access frequency of the comb9 after subtraction is 2-1=1, and the signal cannot continue to propagate forward through the comb9 due to the fact that the target access frequency is not 0, so that the next event can be started.

Current working set: [ Comb1/out, comb4/out ]

And taking out a detection starting point comb1/out from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb5) connected with the comb1/out, wherein the target access frequency of the comb5 after subtraction is 2-1=1, and the signal cannot continue to propagate forward through the comb5 due to the fact that the target access frequency is not 0, so that the next event can be started.

Current working set: [ comb4/out ]

And a detection starting point comb4/out is taken out from the current working set, the logic unit connected to the comb4/out is a blackbox, namely, when the set detection ending point is met, the signal cannot continue to propagate forward through the blackbox, and the next event can be started.

Current working set: [ ]

At this time, the current thread is idle and the current working set is empty, the current thread is marked as a completion state, and the current thread is marked as a completion state due to single-thread processing, which is equivalent to all threads, so that the next step of judging whether to loop is entered.

5.5.2 Four-thread processing mode

Initial current working set: [ A, B, C, D, E, F, blackbox/out ]

Conditions of four threads: [ ],[ ],[ ],[ ]

The 4 detection starting points A, B, C and D are taken out from the current working set and put into four threads respectively to wait for processing (the situation that the taking-out sequence or the first-in first-out exists does not exist here, the multi-thread situation is considered at the beginning, and the sequential processing is not needed).

Current working set: [ E, F, blackbox/out ]

Conditions of four threads: [ C ] [ D ], [ A ], [ B ]

At this time, the four threads respectively perform the following processes:

Thread 1: the target access number of the combination logic gate (Comb 2) connected with C is reduced by 1 (the data structure used herein is a multi-thread data structure, so that the conflict problem can be automatically processed, and if a plurality of threads simultaneously operate one combination logic gate, the conflict can be automatically processed

Thread 2: the target access number of the D-connected combinational logic gate (comb3) is reduced by 1

Thread 3: the target access number of the combinational logic gate (comb1) to which A is connected is reduced by 1

Thread 4: the target access number of the combinational logic gate (comb2) to which B is connected is reduced by 1

In the above process, both thread 1 and thread 4 perform subtraction on the Comb2, but the speed of finding the Comb2 from C and the speed of finding the Comb2 from B generally differ, which may be caused by a physical layer (such as computer performance), and even if the speeds are the same, that is, when the Comb2 needs to be simultaneously found, thread lock occurs due to the fact that the thread 1 is locked when entering the multithreaded data structure in advance, that is, the thread 4 can perform processing after the thread 1 is finished.

Through the above processing, the target access number of Comb2 is returned to 0, and the signal can continue to propagate forward through Comb 2. Assuming that the speed found by the thread 4 is slightly slower than that found by the thread 1, the processing is performed on the Comb2 after the thread 4, that is, after the target access number of the Comb2 is returned to 0, the operation of adding the output of the Comb2 to the current working set is performed by the thread 4 (hereinafter referred to as processing of the Comb 2), at this time, the threads except for the thread 4 have already processed their own events, and the next event starts to be performed, that is, 3 detection starting points E, F and blackbox/out will be taken out from the current working set and placed into 3 threads which have processed their own events respectively to wait for processing.

Current working set: [ ]

Conditions of four threads: [ F ] [ blackbox/out ], [ E ], [ handle comb2 ]

At this time, the four threads respectively perform the following processes:

Thread 1: the target access number of the combinational logic gate (comb4) to which F is connected is reduced by 1

Thread 2: target access times-1 of combinational logic gates (comb7 and comb8) to which blackbox/out is connected

Thread 3: the target access number of the combinational logic gate (comb3) to which E is connected is reduced by 1

Thread 4: and putting the comb2/out into the current working set.

Current working set: [ comb2/out ]

At this time, the target access times of the Comb3 of the thread 3 and the Comb8 of the thread 2 are returned to 0, the signal can continue to propagate forward through the Comb3 and the Comb8, and an operation of adding the outputs of the Comb3 and the Comb8 to the current working set needs to be performed (the following is abbreviated as processing the Comb3 and processing the Comb 8); the target access number of the Comb4 of the thread 1 is not 0, the signal cannot continue to propagate forward through the Comb4, and the next event can be started, and similarly, the thread 4 can also start the next event. But there is only one detection origin (i.e., the just-placed comb2/out) for the current working set, thread 4 has not been reached by the detection origin, and thread 4 is marked as complete, provided that thread 1 can then process comb2/out.

Current working set: [ ]

Conditions of four threads: [ Comb2/out ], [ handle Comb8], [ handle Comb3], [ completion status ]

At this time, the four threads respectively perform the following processes:

thread 1: the target number of accesses of the combinational logic gates (comb1 and comb6) to which comb2/out is connected is reduced by 1

Thread 2: putting comb8/out into current working set

Thread 3: putting comb3/out into current working set

Thread 4: completion status

Current working set: [ Comb3/out, comb8/out ]

At this time, the number of target accesses of the Comb1 of the thread 1 is 0, the signal can continue to propagate forward through the Comb1, and an operation of adding the output of the Comb1 to the current working set (hereinafter referred to as processing the Comb 1) needs to be executed; while threads 2,3,4 may begin the next event. However, since the number of detection start points in the current working set is 2, the priority thread 4 takes out one detection start point and cancels the completion status of thread 4, and then marks the remaining thread 3 or thread 2 as the completion status, assuming that thread 3 is marked as the completion status.

Current working set: [ ]

Conditions of four threads: [ process Comb1 ], [ Comb8/out ], [ complete ], [ Comb3/out ]

At this time, the four threads respectively perform the following processes:

thread 1: putting comb1/out into current working set

Thread 2: the target number of accesses of the combinational logic gate (comb9) to which comb8/out is connected is reduced by 1

Thread 3: completion status

Thread 4: the target number of accesses of the combinational logic gates (comb4 and comb6) to which comb3/out is connected is reduced by 1

Current working set: [ Comb1/out ]

At this point, the number of sambac 4 target accesses by thread 4 has been returned to 0, and the signal may continue to propagate forward through sambac 4, requiring an operation to add the output of sambac 4 to the current working set (hereinafter referred to as processing sambac 4). While the target access number of the Comb9 of the thread 2 is not 0, the signal cannot continue to propagate forward through the Comb9, and the next event can be started, and similarly, the threads 1 and 3 can also start the next event. However, the current working set has only 1 detection start point, and priority thread 3 takes out the detection start point, cancels the thread 3 completion state, and marks threads 1 and 2 as the completion state.

Current working set: [ ]

Conditions of four threads: completion, comb1/out, handle comb4

At this time, the four threads respectively perform the following processes:

Thread 1: completion status

Thread 2: completion status

Thread 3: the target number of accesses of the combinational logic gate (comb5) to which comb1/out is connected is reduced by 1

Thread 4: putting comb4/out into current working set

Current working set: [ comb4/out ]

At this point, the target access number of the Comb5 of the thread 3 is not 0, the signal cannot continue to propagate forward through the Comb5, and the next event can be started, and similarly, the threads 1,2 and 4 can also start the next event. However, the current working set has only 1 detection start point, and threads 1 and 2 are prioritized to fetch the detection start point, assuming that thread 1 fetches the detection start point and cancels the thread 1 completion state, and threads 3 and 4 are marked as completion state.

Current working set: [ ]

Conditions of four threads: [ comb4/out ], [ done ]

At this time, the four threads respectively perform the following processes:

thread 1: the combinational logic gate (BlackBox) to which the comb4/out is connected is terminated

Thread 2: completion status

Thread 3: completion status

Thread 4: completion status

At this time, the logical unit to which the Comb4/out is connected is a blackbox, that is, the set detection endpoint is encountered, the signal cannot continue to propagate forward through the blackbox, and the current working set is empty, and the thread 1 is also marked as a completion state, so that all threads are marked as a completion state, and the next step of "judging whether to loop" is entered.

Current working set: [ ]

Thread status: completion, completion

5.6 Judging whether to circulate

When the current working set is empty and all threads are finished, judging whether the target access times of all target logic units are 0, and judging that the target logic units with the target access times not being 0 exist, wherein the target access times are found to be comb6=1, comb5=1, comb7=1 and comb9=1.

At this time, the output of any one of the target logical units with the target access times not being 0 is taken as a detection starting point, for example, the output of the Comb6 is taken as a detection starting point, and whether a loop exists is determined (specific processes can refer to the above embodiments, and will not be discussed here). If a loop is found to exist, clearing 0 the target access times of the Comb6, putting the output (output) of the Comb6 into the current working set, and returning to the step of processing the working set; if no loop is found, taking another target logic unit as a detection starting point again until the loop is determined to exist or the target logic unit with the target access frequency not being 0 is detected.

In the case where a loop is found to exist, the process of again "processing the working set" is as follows (only a single thread is taken as an example here):

current working set: [ comb6/out ]

And taking out a detection starting point comb6/out from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb5) to which the comb6/out is connected, wherein the target access frequency of the comb5 is 1-1=0 after subtraction, and the signal can continue to propagate forwards through the comb5 due to the fact that the target access frequency is 0, and at the moment, the output (output) of the comb5 is put into the current working set.

Current working set: [ comb5/out ]

Taking out a detection starting point comb5/out from the current working set, subtracting 1 from the target access times of the combination logic gates (comb6 and comb7) to which the comb5/out is connected, wherein the target access times of the comb6 after subtraction processing are 0-1= -1, and the signal cannot continue to propagate forwards through the comb6 due to the fact that the target access times are not 0; the target access number of the Comb7 after subtraction is 1-1=0, and since the target access number is 0, the signal can continue to propagate forward through the Comb7, and the output (output) of the Comb7 is put into the current working set.

Current working set: [ Comb7/out ]

And taking out a detection starting point comb7/out from the current working set, subtracting 1 from the target access frequency of a combination logic gate (comb9) to which the comb7/out is connected, wherein the target access frequency of the comb9 is 1-1=0 after subtraction, and the signal can continue to propagate forwards through the comb9 due to the target access frequency of 0, and putting the output (output) of the comb9 into the current working set.

Current working set: [ comb9/out ]

A detection start point comb9/out is taken from the current working set, comb9/out is connected to the end point Y, and the signal cannot advance.

Current working set: [ ]

5.7 Judging whether to end

And when the step of judging whether the loop is not found or the target access times of all the combinational logic gates are 0, ending the detection of the circuit.

Fig. 5 is a schematic diagram of another circuit to be detected, shown in fig. 5, with two feedback loops, according to an exemplary embodiment, the detection of the circuit to be detected may include the following steps:

According to the processing procedure similar to that shown in fig. 4, when the loop of "comb5-comb6" is processed and the "processing work set" is performed again, there is a case where the target access times of comb7 and comb9 are not returned to 0, but all threads are in the completed state, and then only the steps similar to that in the processing procedure of fig. 4, namely, the step of "judging whether or not to loop" and the step of "processing work set" are continued after the loop of "comb7-comb9" is judged, can be continued to check the whole circuit until the end without modifying the circuit (namely, eliminating the loop) and starting the check from the head.

For the two circuits to be detected in the above embodiment, if the existing detection method is used, when the entire Verilog file is checked, it is necessary to label each logic unit or traverse the design file in advance and perform a certain record, which consumes a lot of time and storage space. The application provides a method for supporting multithreading to find a combined logic loop in a design file, which uses a BFS mode similar to levelize (layer sequence traversal) to find a feedback loop after reading a Verilog file of a user, namely, only a current working set needs to be recorded, the current working set is updated continuously in the processing process, and a detection starting point is put in or taken out continuously, so that the whole Verilog file can be checked. Furthermore, the solution of the present application is based on BFS checking, so that the possibility of repeated checking is not existed, and the multi-thread mode is supported, and the checking time of both single thread and multi-thread is greatly reduced.

In summary, the detection method of the application supports loop detection of various types and detection of mixed loops, does not involve path backtracking operation, can perfectly compatible with two processing modes of single thread and multi-thread, can effectively reduce the time of path traversal, and can accurately judge which units are in circulation only when a feedback loop is found, if no feedback loop exists, the application can complete detection of the whole circuit very quickly. In addition, in the detection process, if the feedback loop is found to exist, the original circuit can be continuously detected without eliminating the feedback loop, specifically, the fact that the feedback loop is not eliminated means that the circuit structure is not changed, even if a plurality of feedback loops exist in a design file, the whole circuit does not need to be repeatedly traversed, the detection efficiency is greatly improved, the detection times can be effectively reduced, and the effect of reducing the detection time is achieved.

Fig. 6 is a block diagram illustrating a circuit detection device according to an exemplary embodiment. Referring to fig. 6, the apparatus includes a determination unit 60, a setting unit 62, a creation unit 64, and a detection unit 66.

A determining unit 60 configured to determine a target logic unit corresponding to a type of a loop to be detected in the circuit to be detected based on a design file corresponding to the circuit to be detected; a setting unit 62 configured to set an output of a non-target logic unit in the circuit to be detected and a main input of the circuit to be detected as detection start points; a creation unit 64 configured to create a work set, adding the detection start point as first objects in the work set, wherein all the first objects in the work set can be fetched in any order or randomly; the detection unit 66 is configured to take out the first object from the working set by at least one thread running in parallel and perform detection of the loop to be detected according to a second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

According to an embodiment of the application, the type of loop to be detected comprises at least one of: the device comprises a combinational logic loop, a latch loop and a memory loop, wherein a target logic unit corresponding to the combinational logic loop is a combinational logic gate, a target logic unit corresponding to the latch loop is a latch unit, and a target logic unit corresponding to the memory loop is a memory unit.

According to an embodiment of the present application, the detection unit 66 is further configured to set the input of the non-target logic unit and the main output of the circuit to be detected as detection end points; for each of at least one thread running in parallel, the following predetermined processing is performed: retrieving any one of the first objects from the working set and determining a second object to which any one of the first objects is connected in the signal propagation direction; responding to a second object connected to any one of the first objects as a target logic unit, updating a working set based on the target access times of the target logic unit, and continuing to execute preset processing, wherein the target access times are determined based on the number of input pins of the target logic unit; continuing to execute the predetermined process in response to the second object to which any one of the first objects is connected being the detection end point; and under the condition that the working set is empty and all threads running in parallel are in a finished state, aiming at a first target logic unit with target access times not being 0, detecting a loop to be detected.

According to an embodiment of the present application, the detection unit 66 is further configured to decrease the target access number of the target logical unit by 1; in response to the target access number of the target logical unit being 0, adding the output of the target logical unit as a first object in the working set; in response to the target access number of the target logical unit being other than 0, the working set is maintained unchanged.

According to an embodiment of the present application, the detecting unit 66 is further configured to use the output of the first target logic unit as a new detection start point, respectively, for each new detection start point, detect each signal path from the new detection start point, and determine whether a loop to be detected exists based on the number of times the propagated signal passes through each target logic unit; and ending the detection of the circuit to be detected under the condition that all the first target logic units are detected and the loop to be detected is not detected.

According to an embodiment of the present application, the detecting unit 66 is further configured to use the output of any one of the first target logic units as a new first detection start point, detect each signal path from the first detection start point, and determine whether or not a loop to be detected exists based on the number of times the propagated signal passes through each target logic unit; in response to the absence of a loop to be detected, detecting each signal path from a second detection start point by taking the output of another one of the first target logic units as a new second detection start point, and determining whether the loop to be detected exists or not based on the number of times the propagated signal passes through each target logic unit until the loop to be detected is detected; clearing 0 the target access times of any one first target logic unit in response to the existence of the loop to be detected, and adding a first detection starting point as a first object in the working set, and continuing to execute the preset processing; and ending the detection of the circuit to be detected under the condition that the target access times of all the first target logic units are 0 or the detection of all the first target logic units is finished and the loop to be detected is not detected.

According to an embodiment of the present application, the detecting unit 66 is further configured to determine, before performing the predetermined processing, the number of predetermined input pins of the target logic unit, wherein the predetermined input pins are input pins that access the circuit to be detected and are used for transmitting data; the number of predetermined input pins is determined as the target number of accesses of the target logical unit.

According to an embodiment of the present application, the detecting unit 66 is further configured to select, in response to the addition of the new first object in the working set, a thread in the completion state from among the threads running in parallel to perform the predetermined processing, in a case where the working set is empty and all the threads running in parallel are not in the completion state.

According to an embodiment of the present application, the detection unit 66 is further configured to mark any thread as a completed state if the current predetermined processing is completed by any thread and the working set is empty, before the detection of the loop to be detected is performed for the first target logic unit whose target access number is not 0.

According to an embodiment of the present application, the detection unit 66 is further configured to determine, before the detection of the loop to be detected is performed, the number of the at least one thread running in parallel according to the user instruction or the remaining computing resources, before fetching the first object from the working set by the at least one thread running in parallel and according to the second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

According to an embodiment of the present application, an electronic apparatus may be provided. Fig. 7 is a block diagram of an electronic device 700 including at least one memory 701 having a set of computer-executable instructions stored therein that, when executed by the at least one processor, performs a circuit detection method according to an embodiment of the application, and at least one processor 702, according to an embodiment of the application.

By way of example, the electronic device 700 may be a PC computer, tablet device, personal digital assistant, smart phone, or other device capable of executing the above-described set of instructions. Here, the electronic device 700 is not necessarily a single electronic device, but may be any apparatus or a collection of circuits capable of executing the above-described instructions (or instruction set) individually or in combination. The electronic device 700 may also be part of an integrated control system or system manager, or may be configured as a portable electronic device that interfaces with either locally or remotely (e.g., via wireless transmission).

In electronic device 700, processor 702 may include a Central Processing Unit (CPU), a Graphics Processor (GPU), a programmable logic device, a special purpose processor system, a microcontroller, or a microprocessor. By way of example, and not limitation, the processor 702 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, and the like.

The processor 702 may execute instructions or code stored in the memory, wherein the memory 701 may also store data. The instructions and data may also be transmitted and received over a network via a network interface device, which may employ any known transmission protocol.

The memory 701 may be integrated with the processor 702, for example, RAM or flash memory disposed within an integrated circuit microprocessor or the like. In addition, the memory 701 may include a separate device, such as an external disk drive, a storage array, or any other storage device usable by a database system. The memory 701 and the processor 702 may be operatively coupled or may communicate with each other, for example, through an I/O port, a network connection, etc., such that the processor 702 is able to read files stored in the memory 701.

In addition, the electronic device 700 may also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, mouse, touch input device, etc.). All components of the electronic device may be connected to each other via a bus and/or a network.

According to an embodiment of the present application, there may also be provided a computer-readable storage medium, wherein instructions in the computer-readable storage medium, when executed by at least one processor, cause the at least one processor to perform the circuit detection method of the embodiment of the present application. Examples of the computer readable storage medium herein include: read-only memory (ROM), random-access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, nonvolatile memory, CD-ROM, CD-R, CD + R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD + R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, blu-ray or optical disk storage, hard Disk Drives (HDD), solid State Disks (SSD), card-type memories (such as multimedia cards, secure Digital (SD) cards or ultra-fast digital (XD) cards), magnetic tapes, floppy disks, magneto-optical data storage devices, hard disks, solid state disks, and any other devices configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and to provide the computer programs and any associated data, data files and data structures to a processor or computer to enable the processor or computer to execute the programs. The computer programs in the computer readable storage media described above can be run in an environment deployed in a computer device, such as a client, host, proxy device, server, etc., and further, in one example, the computer programs and any associated data, data files, and data structures are distributed across networked computer systems such that the computer programs and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by one or more processors or computers.

According to an embodiment of the present application, there is provided a computer program product including computer instructions which, when executed by a processor, implement a circuit detection method of the embodiment of the present application.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A method of circuit detection, comprising:

determining a target logic unit corresponding to the type of a loop to be detected in a circuit to be detected based on a design file corresponding to the circuit to be detected;

setting the output of a non-target logic unit in the circuit to be detected and the main input of the circuit to be detected as detection starting points;

Creating a working set, and adding the detection starting point as first objects in the working set, wherein all the first objects in the working set can be taken out in any order or randomly;

and taking out a first object from the working set through at least one thread running in parallel, and detecting the loop to be detected according to a second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

2. The circuit detection method of claim 1, wherein the type of loop to be detected comprises at least one of: the logic circuit comprises a combinational logic loop, a latch loop and a memory loop, wherein a target logic unit corresponding to the combinational logic loop is a combinational logic gate, a target logic unit corresponding to the latch loop is a latch unit, and a target logic unit corresponding to the memory loop is a memory unit.

3. The circuit inspection method according to claim 1, wherein the fetching a first object from the working set by at least one thread running in parallel and performing the inspection of the loop to be inspected based on a second object to which the first object is connected in a signal propagation direction of the circuit to be inspected, comprises:

Setting the input of the non-target logic unit and the main output of the circuit to be detected as detection end points;

For each of at least one thread running in parallel, the following predetermined processing is performed: retrieving any one of the first objects from the working set and determining a second object to which the any one of the first objects is connected in a signal propagation direction; responding to the second object connected to any one of the first objects as the target logic unit, updating the working set based on the target access times of the target logic unit, and continuing to execute the preset processing, wherein the target access times are determined based on the number of input pins of the target logic unit; continuing to execute the predetermined process in response to the second object to which the any one of the first objects is connected being the detection end point;

And under the condition that the working set is empty and all threads running in parallel are in a finished state, aiming at a first target logic unit with target access times not being 0, detecting the loop to be detected.

4. The circuit detection method of claim 3, wherein the updating the working set based on the target number of accesses of the target logical unit comprises:

Subtracting 1 from the target access times of the target logic unit;

responsive to the target number of accesses of the target logical unit being 0, adding an output of the target logical unit as a first object in the working set;

And in response to the target access times of the target logic units being different from 0, maintaining the working set unchanged.

5. The circuit detection method as claimed in claim 3, wherein the detecting the loop to be detected for the first target logic unit having the target access number other than 0 includes:

Taking the output of the first target logic unit as a new detection starting point respectively, detecting each signal path starting from the new detection starting point for each new detection starting point, and determining whether the loop to be detected exists or not based on the number of times that the propagated signal passes through each target logic unit;

and ending the detection of the circuit to be detected under the condition that all the first target logic units are detected and the loop to be detected is not detected.

6. The circuit detection method as claimed in claim 3, wherein the detecting the loop to be detected for the first target logic unit having the target access number other than 0 includes:

Taking the output of any one of the first target logic units as a new first detection starting point, detecting each signal path starting from the first detection starting point, and determining whether the loop to be detected exists or not based on the number of times the propagated signal passes through each target logic unit;

In response to the absence of the loop to be detected, taking the output of another one of the first target logic units as a new second detection starting point, detecting each signal path starting from the second detection starting point, and determining whether the loop to be detected is present or not based on the number of times the propagated signal passes through each target logic unit until the loop to be detected is detected;

Clearing 0 the target access times of any one of the first target logic units in response to the existence of the loop to be detected, and adding the first detection starting point as a first object in the working set, and continuing to execute the predetermined processing;

And ending the detection of the circuit to be detected under the condition that the target access times of all the first target logic units are 0 or the detection of all the first target logic units is finished and the loop to be detected is not detected.

7. The circuit detection method according to claim 3, characterized by further comprising, before performing the predetermined processing:

Determining the number of preset input pins of the target logic unit, wherein the preset input pins are input pins which are connected to the circuit to be detected and used for transmitting data;

and determining the number of the preset input pins as the target access times of the target logic unit.

8. A circuit detection method according to claim 3, wherein in the case where the working set is empty and all threads running in parallel are not all in a completed state, the predetermined processing is performed by selecting a thread in a completed state from among the threads running in parallel in response to a new first object being added to the working set.

9. The circuit detection method according to claim 3, wherein before the detection of the loop to be detected is performed for the first target logic unit whose target access number is not 0, further comprising:

Any thread is marked as complete if it completes the current predetermined processing and the working set is empty.

10. The circuit inspection method of claim 1, further comprising, prior to the inspecting the loop to be inspected by fetching a first object from the working set by at least one thread running in parallel and based on a second object to which the first object is connected in a signal propagation direction of the circuit to be inspected:

the number of at least one thread running in parallel is determined based on the user instructions or the remaining computing resources.

11. A circuit detection device, comprising:

The determining unit is configured to determine a target logic unit corresponding to the type of the loop to be detected in the circuit to be detected based on a design file corresponding to the circuit to be detected;

a setting unit configured to set an output of a non-target logic unit in the circuit to be detected and a main input of the circuit to be detected as detection start points;

a creating unit configured to create a working set, adding the detection start point as first objects in the working set, wherein all the first objects in the working set can be fetched in any order or randomly;

The detection unit is configured to take out a first object from the working set through at least one thread running in parallel, and detect the loop to be detected according to a second object to which the first object is connected in the signal propagation direction of the circuit to be detected.

12. An electronic device, comprising:

a processor;

A memory for storing the processor-executable instructions;

Wherein the processor is configured to execute the instructions to implement the circuit detection method of any one of claims 1 to 10.

13. A computer-readable storage medium, wherein instructions in the computer-readable storage medium, when executed by at least one processor, cause the at least one processor to perform the circuit detection method of any one of claims 1 to 10.

14. A computer program product comprising computer instructions which, when executed by a processor, implement the circuit detection method of any one of claims 1 to 10.