CN118055561A - Circuit board and manufacturing method thereof - Google Patents

Abstract

The present disclosure provides a circuit board and a manufacturing method thereof. The circuit board comprises: an insulating layer having a first surface and a second surface opposite to each other; a first pad layer comprising a first connection pad and a first conductive layer stacked on the first connection pad, a portion of the first pad layer being buried in the insulating layer, and another portion of the first pad layer protruding from the first surface of the insulating layer; and a second conductive layer disposed on the first conductive layer.

Description

Circuit board and method for manufacturing the same

Technical Field

The present disclosure relates to a circuit board and a method for manufacturing the same.

Background technique

With the development of the electronics industry, electronic devices have gradually achieved higher performance, so semiconductor packages need to have a higher density and smaller design. As the number of integrated circuits (ICs) mounted in the package increases, the number of input/output (I/O) access terminals increases, and a requirement is given to reduce the gap between bonding pads.

Currently, the wire bonding method and the flip-chip bonding method are used for high-density packages, and when the number of I/O access terminals increases, the flip-chip bonding method is preferred. However, the wire bonding method also requires bonding fingers and nickel plating for fine circuits, and in this case, it is necessary to prevent the nickel plating from diffusing to the right and left sides of the bonding pad and to implement the bonding pad with a fine pitch.

Summary of the invention

The present disclosure seeks to provide a circuit board that implements connection pads for mounting a wire bonding chip having a fine pitch and has a protruding conductive layer suitable for a wire bonding environment, and a method for manufacturing the circuit board.

The objects of the present disclosure are not limited to the above objects and can be expanded in various ways within the scope of the concept and field of the present disclosure.

An embodiment of the present disclosure provides a circuit board, comprising: an insulating layer having a first surface and a second surface opposite to each other; a first pad layer comprising a first connecting pad and a first conductive layer stacked on the first connecting pad, a portion of the first pad layer being buried in the insulating layer, and another portion of the first pad layer protruding from the first surface of the insulating layer; and a second conductive layer disposed on the first conductive layer.

The first connection pad may be buried in the insulating layer, and an upper surface of the first connection pad may be recessed in the insulating layer.

The first conductive layer may overlap the upper surface of the first connection pad in a thickness direction of the insulating layer, and a portion of the first conductive layer may be buried in the insulating layer, and another portion of the first conductive layer may protrude from the first surface.

The second conductive layer may be disposed on an upper surface of the first conductive layer protruding from the first surface.

The second conductive layer may cover a side surface of the first conductive layer protruding from the first surface.

The first connection pad may include a copper (Cu) layer.

The first conductive layer may include a nickel (Ni) plated layer.

The second conductive layer may include a gold (Au) plated layer.

The width of the first conductive layer may be substantially equal to the width of the first connection pad.

The first pad layer may be disposed in the bonding finger region.

An upper surface of the insulating layer disposed in the bonding contact finger region may be lower than an upper surface of the insulating layer adjacent to the bonding contact finger region.

The circuit board may further include: a solder resist layer disposed on the insulating layer and adjacent to the bonding contact finger region.

The insulating layer may include a plurality of layers, and the plurality of layers may have circuit layers formed therein, respectively.

An embodiment of the present disclosure provides a method for manufacturing a circuit board, the method comprising: providing an embedded pattern substrate, the embedded pattern substrate comprising an insulating layer and a first connecting pad, the insulating layer having a first surface and a second surface opposite to each other, the first connecting pad being buried in the insulating layer to be recessed in the insulating layer; forming a first pad layer by stacking a first conductive layer on the first connecting pad to overlap with the first connecting pad; etching the insulating layer so that the first surface of the insulating layer is disposed between an upper surface and a lower surface of the first pad layer; and forming a second conductive layer on the first conductive layer.

The method may further include, before providing the embedded pattern substrate, forming the embedded pattern substrate, the step of forming the embedded pattern substrate comprising: burying the first connection pad in the insulating layer, and etching an upper surface of the first connection pad to be recessed in the insulating layer.

The step of etching the insulating layer may include etching using a plasma treatment process.

The step of etching the insulating layer may include: forming an upper surface of the first connection pad to be recessed in the insulating layer; and forming an upper surface of the first conductive layer to be higher than the first surface of the insulating layer.

Etching the insulating layer may be performed so that the first conductive layer may protrude from the insulating layer, and then forming the second conductive layer may include plating the second conductive layer on the first conductive layer.

The step of forming the second conductive layer may include plating the second conductive layer on the first conductive layer before etching the insulating layer.

An embodiment of the present disclosure provides a circuit board, comprising: an insulating layer having a first surface and a second surface opposite to each other; a first pad layer comprising a first portion buried in the insulating layer and a second portion protruding from the first surface of the insulating layer, the first portion comprising a material different from a material present in the second portion; and a second conductive layer disposed on the first pad layer.

The first portion may include a first connection pad buried in the insulating layer, and an upper surface of the first connection pad may be recessed in the insulating layer.

The second portion may include a first conductive layer overlapping an upper surface of the first connection pad in a thickness direction of the insulating layer, and a portion of the first conductive layer may be buried in the insulating layer and another portion of the first conductive layer protrudes from the first surface.

The material contained in the first portion may include copper (Cu).

The material contained in the second portion may include nickel (Ni).

The second conductive layer may include gold (Au).

The insulating layer may include resin.

An embodiment of the present disclosure provides a method for manufacturing a circuit board, the method comprising: forming a first pad layer in an embedded pattern substrate including an insulating layer, wherein the first pad layer includes a first portion buried in the insulating layer and a second portion protruding from a surface of the insulating layer, and the first portion includes a material different from a material present in the second portion; etching the insulating layer so that the surface of the insulating layer is disposed between an upper surface and a lower surface of the first pad layer; and forming a second conductive layer on the first pad layer.

The method may further include forming the embedded pattern substrate before forming the first pad layer, the step of forming the embedded pattern substrate comprising: burying the first portion in the insulating layer, and etching an upper surface of the first portion to be recessed in the insulating layer.

The step of etching the insulating layer may include etching using a plasma treatment process.

The etching of the insulating layer may include: forming an upper surface of the first portion to be recessed in the insulating layer; and forming an upper surface of the second portion to be higher than the surface of the insulating layer.

The first portion may include a first connecting pad buried in the insulating layer, and the second portion may include a first conductive layer, the first conductive layer overlaps with the upper surface of the first connecting pad in the thickness direction of the insulating layer, a portion of the first conductive layer may be buried in the insulating layer, and another portion of the first conductive layer may protrude from the surface of the insulating layer.

According to the method for manufacturing a circuit board according to the embodiment, connection pads for mounting a wire bonding chip can be implemented with a fine pitch, and a protruding conductive layer suitable for a wire bonding environment can be manufactured.

Therefore, the circuit board according to the embodiment can be configured with a fine pitch by manufacturing bonding fingers for wiring bonding using an embedded trace substrate (ETS) method.

Furthermore, the nickel plating of the bonding finger pads is raised, thereby eliminating the risk of false access during the wire bonding process.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a circuit board according to an embodiment.

2A to 2D , 3A to 3D , and 4A to 4C show a flow chart of a method for manufacturing the circuit board shown in FIG. 1 .

5A to 5C show a flowchart of a method for manufacturing a circuit board according to a modified example.

6 and 7 show a flow chart of a method for manufacturing a circuit board according to another embodiment.

Detailed ways

In the following detailed description, only certain embodiments of the present disclosure are shown and described briefly by way of illustration. The drawings and descriptions are considered to be illustrative and not restrictive in nature. Throughout the specification, the same reference numerals represent the same elements. Some constituent elements are exaggerated, omitted or briefly shown in the appended drawings, and the sizes of the corresponding constituent elements do not reflect the actual sizes.

The accompanying drawings are provided only to allow easy understanding of the embodiments disclosed in this specification and should not be interpreted as limiting the spirit disclosed in this specification, and it should be understood that the present disclosure includes all modifications, equivalents, and replacements without departing from the scope and spirit of the present disclosure.

Terms including ordinal numbers such as first, second, etc. will only be used to describe various constituent elements and should not be interpreted as limiting these constituent elements. These terms are only used to distinguish one constituent element from other constituent elements.

It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. The terms "on" or "over" mean being located on or below an object part, and do not necessarily mean being positioned on an upper surface of an object part based on the direction of gravity.

It should be understood that the terms "include", "comprising", "having" or "configured" indicate the presence of the features, numbers, steps, operations, constituent elements, components or combinations thereof described in the specification, but do not exclude the possibility of pre-existing or adding one or more other features, numbers, steps, operations, constituent elements, components or combinations thereof. Unless explicitly described to the contrary, the word "comprise" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

The phrase “in a plan view” or “on a plane” means observing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

Throughout the specification, when a part is described as being “connected” to another part, the part may be “directly connected” to the other part, may be “connected” to the other part through a third part, or may be physically or electrically connected to the other part, and may be represented by different subjects according to position or function, but corresponding parts that are basically integrated into one body may be connected to each other.

The substrate may be wide in a plan view and may be thin in a cross-sectional view, the “plane direction of the substrate” may refer to a direction parallel to the wide and flat side of the substrate, and the “thickness direction of the substrate” may refer to a direction perpendicular to the wide and flat side of the substrate.

The term "substantially equal" or "equal" includes not only those that are exactly the same in value, but also those that are designed to be the same size but may differ slightly within tolerances due to manufacturing processes or material properties, so that they would be considered the same by ordinary technicians in this field.

FIG. 1 shows a cross-sectional view of a circuit board according to an embodiment.

1, a circuit board 101 includes an insulating layer 110 and first connection pads 123 buried in the insulating layer 110. The insulating layer 110 and the first connection pads 123 may construct (compose) an embedded pattern substrate. The circuit board 101 may be used as a printed circuit board (PCB) of a semiconductor package.

The insulating layer 110 may include a first surface 1101 and a second surface 1102 opposite to each other. The first conductive layer 133 may be stacked on the first connection pad 123 to construct (form) the first pad layer 120. A portion of the first pad layer 120 may be buried in the insulating layer 110, and another portion of the first pad layer 120 may protrude from the first surface 1101 of the insulating layer 110. The second conductive layer 135 may be disposed on the first conductive layer 133.

The insulating layer 110 may include a resin insulating layer. The insulating layer 110 may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin (e.g., prepreg) impregnated with a reinforcing member such as glass fiber or an inorganic filler and may include a thermosetting resin and/or a photocurable resin, and is not limited thereto.

The first connection pad 123 is buried in the insulating layer 110, and the upper surface of the first connection pad 123 may be recessed from the exposed first surface 1101 of the insulating layer 110. The first conductive layer 133 overlaps the upper surface of the first connection pad 123, so a portion of the first conductive layer 133 may be buried in the insulating layer 110, and another portion of the first conductive layer 133 may protrude from the first surface 1101 of the insulating layer 110. The second conductive layer 135 may be disposed on the first pad layer 120, and may be disposed on the protruding upper surface and side surface of the first conductive layer 133.

The first connection pad 123 may include a copper (Cu) layer. The first conductive layer 133 may include a nickel (Ni) plated layer, and the second conductive layer 135 may include a gold (Au) plated layer. The first conductive layer 133 may be thicker than the second conductive layer 135.

In the present embodiment, the first conductive layer 133/the second conductive layer 135 may be formed by an electrolytic nickel/gold plating method. That is, the nickel/gold plating layer may be formed by a method for applying a current to the first connection pad 123 including copper to form a nickel/gold metal film. The first conductive layer 133/the second conductive layer 135 may be formed by an electroless nickel/gold plating method.

When the circuit board 101 is viewed in a cross-sectional view parallel to the thickness direction, the width of the first conductive layer 133 may be substantially equal to the width of the first connection pad 123. At the portion where the first conductive layer 133 contacts the first connection pad 123, the width of the first conductive layer 133 may be equal to the width of the first connection pad 123, and the width of the upper surface of the first conductive layer 133 may be equal to the width of the first connection pad 123. The width of the portion of the first conductive layer 133 buried in the insulating layer 110 may be equal to the width of the portion of the first conductive layer 133 protruding from the insulating layer 110. Therefore, the width of the portion of the first conductive layer 133 protruding from the first surface 1101 of the insulating layer 110 in the plane direction of the substrate may be formed to be not greater than the width of the portion of the first conductive layer 133 buried in the insulating layer 110. The width may be measured by an optical microscope or an electron microscope. Even if not described in the present disclosure, other methods and/or tools understood by those of ordinary skill in the art may also be used.

The insulating layer 110 may be provided with a wiring bonding pad having a bonding contact finger region BF. In this case, the first connection pad 123 may be a bonding contact finger provided in the bonding contact finger region BF, and a plurality of first connection pads 123 may configure a plurality of bonding contact fingers. That is, the first connection pad 123 may be configured with a bonding contact finger for the wiring bonding pad, and when the semiconductor chip is wire-bonded, the conductive wiring may be bonded to the first connection pad 123.

The upper surface of the insulating layer 110 disposed in the bonding contact finger region BF may be lower than the upper surface of the insulating layer 110 adjacent to the bonding contact finger region BF. That is, the upper surface of the insulating layer 110 in the region where the first connection pad 123 is disposed may be lower than the upper surface of the insulating layer 110 by a height difference d.

The first solder resist layer 141 may be disposed on the insulating layer 110 adjacent to the bonding finger region BF. The first solder resist layer 141 may overlap the circuit layer 125 disposed in the insulating layer 110 and may cover the circuit layer 125.

The second connection pad 126 may also be formed on the second surface 1102 of the insulating layer 110. The second solder resist layer 146 may be formed around the second connection pad 126 on the second surface 1102 of the insulating layer 110. The second connection pad 126 may include a copper (Cu) layer, and the conductive layer may be formed on the second connection pad 126. The conductive layer may include a first conductive layer 136 and a second conductive layer 138, the first conductive layer 136 including a nickel (Ni) plated layer, and the second conductive layer 138 including a gold (Au) plated layer. The nickel plated layer may be formed on the second connection pad 126 and the gold plated layer may be formed on the nickel plated layer.

A plurality of second connection pads 126 may be arranged adjacent to each other on the second surface 1102 of the insulating layer 110. A second solder resist layer 146 may be formed between the respective second connection pads 126. That is, the second solder resist layer 146 may separate adjacent second connection pads 126.

The circuit board 101 shown in FIG. 1 has a structure in which the connection pads 123 and 126 are arranged on the corresponding sides or both sides of the insulating layer 110, and the second connection pad 126 arranged on the second surface 1102 of the insulating layer 110 may be omitted, which also belongs to the scope of the present disclosure. Another embodiment and modified examples given below belong to the above scope.

The insulating layer 110 may include a plurality of insulating layers, and circuit layers may be formed in the plurality of insulating layers, respectively. Thus, the circuit layers are formed on at least three corresponding insulating layers, and vias may extend in a thickness direction of the insulating layers to connect the circuit layers.

2A to 2D , 3A to 3D , and 4A to 4C show a flow chart of a method for manufacturing the circuit board shown in FIG. 1 .

As shown in Fig. 2A and Fig. 2B, a carrier substrate 80 on which a first seed layer 121 is stacked is provided, and first circuit pattern layers 123a and 125a are formed on the first seed layer 121 according to a circuit forming process. That is, a plating resist patterned by exposure and development may be formed on a portion of the carrier substrate 80 other than a portion on which the first circuit pattern layers 123a and 125a are to be formed. The first circuit pattern layers 123a and 125a may be formed by plating a conductive metal on a portion of the first seed layer 121 exposed by an opening of the patterned plating resist. The plating resist pattern is removed after the first circuit pattern layers 123a and 125a are formed.

As the first seed layer 121, a conductive metal used for a circuit in the field of circuit boards can be applied without limitation, and copper is generally used. The carrier substrate 80 may represent a substrate in which a copper foil layer is stacked on a corresponding side or both sides of an insulator, and the first seed layer 121 may be separated from the copper foil layer. The first circuit pattern layers 123a and 125a may be connected to the first seed layer 121 of the carrier substrate 80, and may include the same type of metal as the first seed layer 121. For example, the first seed layer 121 and the first circuit pattern layers 123a and 125a may include copper.

In the present embodiment, the first circuit pattern layers 123a and 125a are formed on respective sides or both sides of the carrier substrate 80. The first circuit pattern layers 123a and 125a may also be formed on one side of the carrier substrate 80, which is within the scope of the present disclosure.

2C, an insulating layer 110b is stacked so that the first circuit pattern layers 123a and 125a can be buried, and a second seed layer 122 is formed on the upper surface of the insulating layer 110b. The second seed layer 122 can be formed to form an intermediate circuit layer 124, and a conductive metal can be used without limitation, and copper is generally used.

The insulating layer 110b may include a resin insulating layer. The insulating layer 110b may use a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin (e.g., prepreg) impregnated with a reinforcing member such as glass fiber or an inorganic filler and may include a thermosetting resin and/or a photocurable resin, and is not limited thereto.

2D, a second circuit pattern layer 126a may be formed on the outermost insulating layer 110a according to a circuit forming process. The second circuit pattern layer 126a may be formed by a method similar to the method for forming the first circuit pattern layers 123a and 125a, and the second circuit pattern layer 126a may include the same material as the first circuit pattern layers 123a and 125a. Thus, the embedded pattern substrate portion is formed on the corresponding side or both sides of the carrier substrate 80.

According to the illustrated embodiment, the corresponding embedded pattern substrate portion includes two insulating layers 110a and 110b and three metal layers including a first circuit pattern layer 123a and 125a, an intermediate circuit layer 124 and a second circuit pattern layer 126a, and is not limited thereto and may include a greater number of insulating layers and circuit patterns, which falls within the scope of the present disclosure.

3A, an embedded pattern substrate is provided by separating the first seed layer 121 and the carrier substrate 80. A pair of embedded pattern substrates may be obtained by separating the first seed layer 121 formed on respective sides or both sides of the carrier substrate 80, and separate processes may be applied to the pair of embedded pattern substrates.

3B, the first seed layer 121 is removed by soft etching the embedded pattern substrate obtained in FIG. 3A. The first circuit pattern layers 123a and 125a buried in the insulating layer 110b form the first connection pads 123 and the circuit layer 125, respectively, and the second circuit pattern layer 126a disposed on the insulating layer 110a forms the second connection pads 126. In the process of removing the first seed layer 121, the surfaces of the first circuit pattern layers 123a and 125a exposed from the insulating layer 110b are also partially etched, so that the first connection pads 123 and the circuit layer 125 can be formed to be recessed from the surface of the insulating layer 110b. The insulating layers 110a and 110b form the insulating layer 110.

3C , a solder mask process is used to form a first solder resist layer 141 covering the upper surface of a portion of the circuit layer 125 and the insulating layer 110, and a second solder resist layer 146 partially covering the second connection pads 126 and the lower surface of the insulating layer 110. In this case, the first solder resist layer 141 may be patterned to expose the bonding finger region BF, and the second solder resist layer 146 may be patterned to at least partially expose the second connection pads 126.

The solder resist layers 141 and 146 are used as a passivation layer to protect the outermost circuit and for electrical insulation. The solder resist layers 141 and 146 may include, for example, solder resist ink, solder resist film or encapsulant known to those skilled in the art, but are not limited thereto.

Referring to Fig. 3D, a first conductive layer 133 is formed on the first connection pad 123 exposed by the opening of the solder resist layer 141, and a first conductive layer 136 is formed on the second connection pad 126 exposed by the opening of the solder resist layer 146. The first conductive layers 133 and 136 include nickel plating layers, and they can be formed by an electroplating method. That is, the nickel plating layer can be formed by applying an electric current to the first connection pad 123 and the second connection pad 126 containing copper to form a nickel metal film. The first conductive layers 133 and 136 can also be formed by an electroless plating method. The first conductive layers 133 and 136 formed on the connection pads 123 and 126 can be recessed from the surface of the insulating layer 110 or the second solder resist layer 146, respectively.

Referring to FIG. 4A , a patterned cover mask 61 is covered on the surface of the embedded pattern substrate obtained in FIG. 3D , and plasma etching is performed. The cover mask 61 may have an opening 61a overlapping the bonding contact finger region BF formed on the first surface 1101 of the insulating layer 110 that constructs the embedded pattern substrate. Therefore, the first solder resist layer 141 disposed on the first surface 1101 of the insulating layer 110 is covered by the cover mask 61, and the region of the first surface 1101 of the insulating layer 110 on which the first pad layer 120 including the first connecting pad 123 and the first conductive layer 133 is disposed may be exposed. The exposed region of the first surface 1101 of the insulating layer 110 may be plasma etched. The second connecting pad 126, the first conductive layer 136, and the second solder resist layer 146 disposed on the second surface 1102 of the insulating layer 110 may be completely covered by the cover mask 61.

4B , when the first surface 1101 of the insulating layer 110 is etched according to the plasma process, a portion of the first conductive layer 133 of the first pad layer 120 may protrude from the first surface 1101. That is, before the plasma etching, the first conductive layer 133 is recessed and disposed below the first surface 1101 of the insulating layer 110 (see FIG. 4A ), and after the plasma etching, the surface of the insulating layer 110 may be disposed lower than the surface of the first conductive layer 133, the surface of the insulating layer 110 being disposed between the upper surface and the lower surface of the first pad layer 120.

4C, a second conductive layer 135 is formed along the surface of the first conductive layer 133 protruding at the first surface 1101 of the insulating layer 110. The second conductive layer 135 may include a gold (Au) plating layer and may be formed by a plating method (e.g., an electroplating method). That is, the gold plating layer may be formed by a method for applying an electric current to the first connection pad 123 to form a gold film. The second conductive layer 135 may be formed by an electroless plating method. Since the plating process is performed while the first conductive layer 133 is protruding from the insulating layer 110, the second conductive layer 135 may be plated on the protruding upper surface and side surface of the first conductive layer 133.

A second conductive layer 138 (see FIG. 1 ) may be formed on the first conductive layer 136 disposed on the second connection pads 126 exposed from the second solder resist layer 146 and disposed on the second surface 1102 of the insulating layer 110. Thus, the circuit board 101 shown in FIG. 1 may be completed.

5A to 5C show a flow chart of a method for manufacturing a circuit board according to a modified example. FIG5A shows a first connection pad 123' buried in an insulating layer 110 before plasma etching, FIG5B shows a first conductive layer 133' protruding from the insulating layer 110 after plasma etching, and FIG5C shows a second conductive layer 135' being plated on the protruding first conductive layer 133'.

5A, in the present modified example, when forming the first conductive layer 133' on the first connection pad 123', the first conductive layer 133' may be plated to be thicker than the first conductive layer 133 of the substrate shown in FIG4A. Therefore, a portion of the first conductive layer 133' disposed on the first connection pad 123' may protrude from the first surface 1101 of the insulating layer 110.

5B and 5C , in the present modified example, the first conductive layer 133 ′ may protrude by etching a portion of the upper surface of the insulating layer 110 by plasma etching, and the second conductive layer 135 ′ may be plated along the upper and side surfaces of the protruding first conductive layer 133 ′.

6 and 7 show a flow chart of a method for manufacturing a circuit board according to another embodiment.

According to the method for manufacturing the circuit board 102 according to the present embodiment, before the first pad layer 120 is protruded above the insulating layer 110, the second conductive layer 137 is formed on the first pad layer 120, and then an etching (eg, plasma etching) process is performed.

6, a second conductive layer 137 is formed on the first conductive layer 133 of the substrate obtained in FIG3D. The first pad layer 120 including the first connection pad 123 and the first conductive layer 133 may be recessed in the exposed first surface 1101 of the insulating layer 110. The second conductive layer 137 may be plated and disposed in the recessed space formed on the first conductive layer 133. The second conductive layer 138 may be plated and disposed on the first conductive layer 136, which is disposed on the second connection pad 126 on the second surface 1102 of the insulating layer 110.

7 , as shown in FIG4A , when a patterned cover mask is covered on the surface of the substrate and plasma etching is performed, the insulating layer 110 may be etched so that the first conductive layer 133 and the second conductive layer 137 may protrude above the first surface 1101. That is, a portion of the insulating layer 110 corresponding to the bonding finger region BF is etched so that the first conductive layer 133 and the second conductive layer 137 may be exposed and may protrude above the first surface 1101.

In the present embodiment, the second conductive layer 137 may be disposed on the upper surface of the first conductive layer 133 protruding above the first surface 1101, and may not be disposed on the exposed side surface of the first conductive layer 133. That is, when the first conductive layer 133 is buried below the surface of the insulating layer 110, the second conductive layer 137 is plated on the top of the first conductive layer 133. Therefore, the second conductive layer 137 is not disposed on the side surface of the first conductive layer 133.

While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (31)

1. A circuit board, comprising: an insulating layer having a first surface and a second surface opposite to each other; a first pad layer, comprising a first connection pad and a first conductive layer stacked on the first connection pad, a portion of the first pad layer being buried in the insulating layer, and another portion of the first pad layer protruding from the first surface of the insulating layer; and The second conductive layer is disposed on the first conductive layer. 2. The circuit board according to claim 1, wherein: The first connection pad is buried in the insulating layer, and an upper surface of the first connection pad is recessed in the insulating layer. 3. The circuit board according to claim 2, wherein: The first conductive layer overlaps the upper surface of the first connection pad in the thickness direction of the insulating layer, and a portion of the first conductive layer is buried in the insulating layer, and another portion of the first conductive layer protrudes from the first surface. 4. The circuit board according to claim 3, wherein: The second conductive layer is disposed on an upper surface of the first conductive layer protruding from the first surface. 5. The circuit board according to claim 4, wherein: The second conductive layer covers a side surface of the first conductive layer that protrudes from the first surface. 6. The circuit board according to claim 1, wherein: The first connection pad includes a copper layer. 7. The circuit board according to claim 1, wherein: The first conductive layer includes a nickel plated layer. 8. The circuit board according to claim 1, wherein: The second conductive layer includes a gold plated layer. 9. The circuit board according to claim 1, wherein: The width of the first conductive layer is equal to the width of the first connecting pad. 10. The circuit board according to claim 1, wherein: The first pad layer is disposed in the bonding contact finger region. 11. The circuit board according to claim 10, wherein: An upper surface of the insulating layer disposed in the bonding contact finger region is lower than an upper surface of the insulating layer adjacent to the bonding contact finger region. 12. The circuit board according to claim 11, further comprising: The solder resist layer is disposed on the insulating layer and is adjacent to the bonding contact finger region. 13. The circuit board according to claim 1, wherein: The insulating layer includes a plurality of layers, and Circuit layers are respectively formed in the plurality of layers. 14. A method for manufacturing a circuit board, comprising: providing an embedded pattern substrate, the embedded pattern substrate comprising an insulating layer and a first connection pad, the insulating layer having a first surface and a second surface opposite to each other, the first connection pad being buried in the insulating layer to be recessed in the insulating layer; forming a first pad layer by stacking a first conductive layer on the first connection pad to overlap the first connection pad; etching the insulating layer so that a first surface of the insulating layer is disposed between an upper surface and a lower surface of the first pad layer; and A second conductive layer is formed on the first conductive layer. 15. The method according to claim 14, further comprising, before providing the embedded pattern substrate, The embedded pattern substrate is formed, and the steps of forming the embedded pattern substrate include: burying the first connection pad in the insulating layer, and An upper surface of the first connection pad is etched to be recessed into the insulating layer. 16. The method according to claim 14, wherein: The step of etching the insulating layer includes etching using a plasma treatment process. 17. The method according to claim 14, wherein: The step of etching the insulating layer comprises: forming an upper surface of the first connection pad to be recessed in the insulating layer; and An upper surface of the first conductive layer is formed to be higher than the first surface of the insulating layer. 18. The method according to claim 14, wherein: The step of etching the insulating layer is performed so that the first conductive layer protrudes from the insulating layer, and then forming the second conductive layer includes plating the second conductive layer on the first conductive layer. 19. The method according to claim 14, wherein: The step of forming the second conductive layer includes plating the second conductive layer on the first conductive layer before etching the insulating layer. 20. A circuit board, comprising: an insulating layer having a first surface and a second surface opposite to each other; a first pad layer including a first portion buried in the insulating layer and a second portion protruding from the first surface of the insulating layer, the first portion including a material different from a material present in the second portion; and The second conductive layer is disposed on the first pad layer. 21. The circuit board according to claim 20, wherein: The first portion includes a first connection pad buried in the insulating layer, and an upper surface of the first connection pad is recessed in the insulating layer. 22. The circuit board according to claim 21, wherein The second portion includes a first conductive layer that overlaps an upper surface of the first connection pad in a thickness direction of the insulating layer, and a portion of the first conductive layer is buried in the insulating layer and another portion of the first conductive layer protrudes from the first surface. 23. The circuit board according to claim 20, wherein: The material contained in the first portion includes copper. 24. The circuit board according to claim 20, wherein: The material contained in the second portion includes nickel. 25. The circuit board according to claim 20, wherein: The second conductive layer includes gold. 26. The circuit board according to claim 20, wherein: The insulating layer includes resin. 27. A method for manufacturing a circuit board, comprising: forming a first pad layer in an embedded pattern substrate including an insulating layer, wherein the first pad layer includes a first portion buried in the insulating layer and a second portion protruding from a surface of the insulating layer, and the first portion includes a material different from a material present in the second portion; etching the insulating layer so that the surface of the insulating layer is disposed between an upper surface and a lower surface of the first pad layer; and A second conductive layer is formed on the first pad layer. 28. The method according to claim 27, further comprising, before forming the first pad layer, The embedded pattern substrate is formed, and the steps of forming the embedded pattern substrate include: burying the first portion in the insulating layer, and An upper surface of the first portion is etched to be recessed into the insulating layer. 29. The method according to claim 27, wherein: The step of etching the insulating layer includes etching using a plasma treatment process. 30. The method of claim 27, wherein: The step of etching the insulating layer comprises: forming an upper surface of the first portion to be recessed into the insulating layer; and An upper surface of the second portion is formed to be higher than the surface of the insulating layer. 31. The method of claim 27, wherein: The first portion includes a first connection pad buried in the insulating layer, The second portion includes a first conductive layer, the first conductive layer overlaps the upper surface of the first connection pad in the thickness direction of the insulating layer, A portion of the first conductive layer is buried in the insulating layer, and Another portion of the first conductive layer protrudes from the surface of the insulating layer.