CN118053772A

CN118053772A - Wafer and manufacturing method thereof, packaging structure and packaging method

Info

Publication number: CN118053772A
Application number: CN202211426790.0A
Authority: CN
Inventors: 隋凯
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2022-11-15
Filing date: 2022-11-15
Publication date: 2024-05-17

Abstract

The wafer comprises bonding areas, wherein the bonding areas comprise chip areas arranged in an array manner and dicing channel areas positioned between the chip areas, and the wafer comprises: a substrate; the dielectric layer is positioned on the substrate, and the exposed surface of the dielectric layer is a bonding surface; the groove is at least positioned in the dielectric layer of the cutting channel area close to the edge of the wafer; the protective layer is filled in the groove; the protective layer is used for being oppositely arranged and forming a sintered body when bonding between bonding surfaces of a plurality of wafers is realized. The embodiment of the invention reduces the probability of falling off of the film structure at the edge of the wafer in the process, and improves the reliability and the packaging yield of the wafer packaging.

Description

Wafer and manufacturing method thereof, packaging structure and packaging method

Technical Field

The embodiment of the invention relates to the technical field of semiconductor packaging, in particular to a wafer, a manufacturing method thereof, a packaging structure and a packaging method.

Background

Three-dimensional integrated circuits (3D ICs) are fabricated using advanced chip stacking techniques to stack chips with different functions into integrated circuits having a Three-dimensional structure. Compared with an integrated circuit with a two-dimensional structure, the stacking technology of the three-dimensional integrated circuit not only can shorten the signal transmission path of the three-dimensional integrated circuit, but also can accelerate the running speed of the three-dimensional integrated circuit, thereby meeting the requirements of higher performance, smaller size, lower power consumption and more functions of a semiconductor device.

Hybrid Bonding (Hybrid Bonding) is a technology for simultaneously Bonding a metal electrode and a dielectric insulating layer on a wafer/chip, and omits a micro bump (μbump), so that the Bonding interconnection pitch can be further reduced. Thus, high density integration can be achieved using hybrid bonding techniques, which play an irreplaceable role in 3D packaging.

In the packaging field, after bonding between wafers is achieved, a backside thinning and trimming (Trim) process is also typically included on the wafers.

But the reliability and the packaging yield of the packaging between wafers still need to be improved at present.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a wafer, a manufacturing method, a packaging structure and a packaging method thereof, reduces the probability of falling off of a film structure at the edge of the wafer in the process, and improves the reliability and the packaging yield of wafer packaging.

In order to solve the above-mentioned problems, an embodiment of the present invention provides a wafer, including a bonding region, the bonding region includes chip regions arranged in an array and scribe line regions located between the chip regions, the wafer includes: a substrate; the dielectric layer is positioned on the substrate, and the exposed surface of the dielectric layer is a bonding surface; the groove is at least positioned in the dielectric layer of the cutting channel area, which is close to the edge of the wafer; the protective layer is filled in the groove; the protective layer is used for being oppositely arranged and forming a sintered body when bonding between bonding surfaces of a plurality of wafers is realized.

Optionally, the wafer further comprises a rim region surrounding the bonding region; the grooves are located at least in the dielectric layer adjacent the dicing street area and the rim area.

Optionally, the distance between the groove and the rim area is 1mm to 10mm in the radial direction.

Optionally, the groove covers at least the dicing street area in the circumferential direction.

Optionally, the length of the groove is greater than the length of the scribe line region in the circumferential direction, and the difference between the lengths of the groove and the scribe line region is at least 400 microns.

Optionally, the groove circumferentially surrounds the edge of the wafer.

Optionally, the material of the protective layer comprises a metal oxide and/or an oxide of a semiconductor material.

Optionally, the material of the protective layer comprises glass.

Optionally, in the wafer, the number of grooves in the same scribe line region is multiple, and the multiple grooves are arranged at intervals along the radial direction.

Alternatively, the spacing between adjacent grooves is 20 μm to 1500 μm in the radial direction.

Alternatively, the number of grooves is 1 to 20.

Alternatively, the grooves have an opening width of 50 microns to 1000 microns in the radial direction.

Alternatively, the grooves have a depth of 0.3 microns to 50 microns.

Optionally, the wafer further includes: and the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface.

Correspondingly, the embodiment of the invention also provides a packaging structure, which comprises: the wafers provided by the embodiment of the invention comprise a first wafer and a second wafer; the bonding surfaces of the first wafer and the second wafer are oppositely arranged and bonded, and the protective layers of the first wafer and the second wafer are oppositely arranged and form a sintered body.

Alternatively, the chip areas of the first wafer and the second wafer are arranged opposite to each other up and down, and the scribe line areas of the first wafer and the second wafer are arranged opposite to each other up and down.

Optionally, the grooves of the first wafer and the second wafer are arranged up and down oppositely, and the shapes, positions, lengths and opening widths of the first wafer and the second wafer are the same.

Optionally, the wafer further includes: the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface; in the chip area, the bonding pads of the first wafer and the second wafer are arranged up and down oppositely and bonded.

Correspondingly, the embodiment of the invention also provides a packaging method, which comprises the following steps: providing a plurality of wafers provided by the embodiment of the invention, wherein the wafers comprise a first wafer and a second wafer; bonding the first wafer and the second wafer, wherein bonding surfaces of the first wafer and the second wafer are opposite, and protective layers of the first wafer and the second wafer are opposite to each other to form a sintered body.

Optionally, in the step of bonding the first wafer and the second wafer, grooves of the first wafer and the second wafer are disposed opposite to each other up and down, and shapes, positions, lengths and opening widths of the grooves of the first wafer and the second wafer are the same.

Optionally, the step of bonding the first wafer and the second wafer includes: bonding surfaces of the first wafer and the second wafer relatively, wherein the chip areas of the first wafer and the second wafer are arranged vertically oppositely, and the cutting channel areas of the first wafer and the second wafer are arranged vertically oppositely, so that the protective layers of the first wafer and the second wafer are in contact relatively; and welding the protective layers of the first wafer and the second wafer to form a sintered body.

Optionally, the step of performing a fusion process on the protective layers of the first wafer and the second wafer includes: presintering the protective layer; after the pre-sintering process, the protective layer is subjected to a laser irradiation process for welding the protective layers of the first and second wafers together to form a sintered body.

Optionally, the pre-sintering process parameters include: the temperature is 300 ℃ to 500 ℃.

Optionally, the protective layer is laser irradiated along the edge of the wafer and in a direction parallel to the wafer.

Optionally, in the step of providing a plurality of wafers according to the embodiments of the present invention, the wafer further includes: the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface; in the step of bonding the first wafer and the second wafer, bonding pads of the first wafer and the second wafer are arranged up and down oppositely in the chip area and bonded.

Correspondingly, the embodiment of the invention also provides a wafer manufacturing method, which comprises the following steps: providing a wafer, wherein the wafer comprises bonding areas, and the bonding areas comprise chip areas arranged in an array manner and dicing channel areas positioned between the chip areas; the wafer comprises a substrate and a dielectric layer positioned on the substrate, wherein the exposed surface of the dielectric layer is a bonding surface; forming a groove in the dielectric layer at least in the dicing street area near the edge of the wafer; and filling the grooves with protective layers, wherein the protective layers are used for being oppositely arranged and forming a sintered body when bonding between bonding surfaces of a plurality of wafers is realized.

Optionally, the wafer further comprises a rim region surrounding the bonding region; a recess is formed in at least the dielectric layer adjacent the bead region at the dicing street region.

Optionally, the groove circumferentially surrounds the edge of the wafer.

Optionally, the step of forming the protective layer includes: forming a mixed solution of nanospheres and a solvent in the groove; and carrying out heat treatment on the mixed solution, and gathering the rest nanospheres together to form a protective layer.

Optionally, a mixed solution of nanospheres and solvent is formed in the grooves by an inkjet printing process.

Optionally, the temperature at which the mixed liquor is heat treated is 80 ℃ to 450 ℃.

Optionally, the material of the nanospheres comprises silicate and/or derivative of silicate.

Alternatively, the volume doping ratio of nanospheres and solvent is 40% to 90%.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

The wafer provided by the embodiment of the invention comprises a groove, wherein the groove is at least positioned in a dielectric layer of a cutting channel area close to the edge of the wafer; the protective layer is filled in the groove; the protective layers are arranged oppositely and form a sintered body when bonding between bonding surfaces of a plurality of wafers is realized, so that when bonding between the plurality of wafers is realized, the sintered body is formed by arranging the protective layers of the plurality of wafers oppositely, the bonding surfaces of the sintered body can be formed at the edge of the cutting channel region close to the wafer, the sintered body is of an integrated structure, the bonding firmness between the bonding surfaces is improved, particularly the bonding strength of the cutting channel region close to the edge of the wafer is improved, the sintered body positioned at the cutting channel region close to the edge of the wafer can play a role in protecting the structure inside the wafer in the subsequent process (such as thinning process, trimming process and the like) so as to prevent stress change generated by external force from extending to the inside of the wafer, and further reduce the probability that the film structure at the edge of the cutting channel region falls off in the subsequent process, thereby being beneficial to improving the reliability and packaging yield of the wafer package.

The packaging structure provided by the embodiment of the invention comprises a plurality of wafers provided by the embodiment of the invention, including a first wafer and a second wafer; the bonding surfaces of the first wafer and the second wafer are oppositely arranged and bonded, and the protective layers of the first wafer and the second wafer are oppositely arranged and form a sintered body, so that the bonding surface of the sintered body is formed at the edge of the cutting channel area close to the wafer, the sintered body is of an integrated structure, the bonding firmness of the first wafer and the second wafer can be improved, particularly the bonding strength of the cutting channel area close to the edge of the wafer can be improved, the sintered body positioned at the cutting channel area close to the edge of the wafer can play a role in protecting the structure inside the wafer in the subsequent process (such as thinning process, trimming process and the like) so as to prevent stress changes generated by external force from extending to the inside of the wafer, and further reduce the probability that the film structure at the edge of the cutting channel area falls off in the subsequent process, and improve the reliability and packaging yield of the packaging structure.

The packaging method provided by the embodiment of the invention provides a plurality of wafers provided by the embodiment of the invention, including a first wafer and a second wafer; bonding the first wafer and the second wafer, wherein bonding surfaces of the first wafer and the second wafer are opposite, and protective layers of the first wafer and the second wafer are opposite to each other to form a sintered body, so that the bonding surfaces of the sintered body are formed at the edge of the cutting channel region close to the wafer, the sintered body is of an integrated structure, bonding firmness between the first wafer and the second wafer, particularly bonding strength of the cutting channel region close to the edge of the wafer, and the sintered body positioned at the cutting channel region close to the edge of the wafer can play a role in protecting the structure inside the wafer in subsequent process (such as thinning process, trimming process and the like) so as to prevent stress change generated by external force from extending to the inside of the wafer, further reduce the probability of falling off of the film structure at the edge of the cutting channel region in the subsequent process, and improve the reliability and packaging yield of the packaging structure.

In the wafer manufacturing method provided by the embodiment of the invention, a groove is formed in a dielectric layer which is at least positioned in a cutting channel area and is close to the edge of a wafer; the grooves are filled with the protective layers, the protective layers are arranged oppositely and form a sintered body when bonding between bonding surfaces of a plurality of wafers is achieved, so that when bonding between the wafers is achieved, the sintered body is formed oppositely between the protective layers of the wafers, the bonding surfaces of the sintered body can be formed at the edge of the cutting channel region close to the wafer, the sintered body is of an integrated structure, the bonding firmness between the bonding surfaces is improved, particularly the bonding strength of the cutting channel region close to the edge of the wafer is improved, the sintered body positioned at the cutting channel region close to the edge of the wafer can play a role in protecting the structure inside the wafer in the subsequent process (such as thinning process, trimming process and the like) so as to prevent stress changes generated by external force from extending to the inside of the wafer, and further reduce the probability that the film structure at the edge of the cutting channel region falls off in the subsequent process, and the reliability and packaging yield of the wafer package are improved.

Drawings

Fig. 1 to 12 are schematic structural diagrams corresponding to each step in a packaging method;

FIGS. 13-16 are schematic views of an embodiment of a wafer of the present invention;

FIGS. 17-18 are schematic views of another embodiment of a wafer according to the present invention;

FIGS. 19 to 27 are schematic views showing the structure of the wafer manufacturing method according to the present invention;

FIGS. 28-31 are schematic views illustrating the structure of the wafer manufacturing method according to another embodiment of the present invention;

FIG. 32 is a schematic diagram of an embodiment of a package structure according to the present invention;

fig. 33 to 34 are schematic structural views corresponding to each step in an embodiment of the packaging method of the present invention.

Detailed Description

As known from the background art, the reliability and the yield of the package between the wafers still need to be improved. Now, in combination with a packaging method, the reasons for the reliability and the yield of the package between the wafers still need to be improved are analyzed. Fig. 1 to 12 are schematic structural diagrams corresponding to each step in a packaging method.

Referring to fig. 1, a plurality of wafers 10 are provided, including a first wafer 11 and a second wafer 12; each wafer 10 includes: a base 13; the dielectric layer 14 is positioned on the substrate 13, and the exposed surface of the dielectric layer 14 is a bonding surface 15.

With continued reference to fig. 1, a first trimming process is performed on the dielectric layer 14 and a partial thickness substrate 13 of the first wafer 11.

With continued reference to fig. 1, after the first trimming process, the first wafer 11 and the second wafer 12 are bonded, the bonding surfaces of the first wafer 11 and the second wafer 12 are disposed opposite to each other, and the first wafer 11 is located on the second wafer 12.

Referring to fig. 2, after bonding the first wafer 11 and the second wafer 12, a first thinning process is performed on the back surface of the substrate 10 where the first wafer 11 is opposite to the bonding surface 15.

Referring to fig. 3, after the first thinning process, a second trimming process is performed on the dielectric layer 14 and the partial thickness substrate 13 of the second wafer 12.

Referring to fig. 4, after the second trimming process, a second thinning process is performed on the back surface of the substrate 13 where the first wafer 11 is opposite to the bonding surface.

Referring to fig. 5, after the second thinning process, a third thinning process is performed on the back surface of the substrate 13 where the first wafer 11 is opposite to the bonding surface.

As shown in fig. 6, a top view of a wafer 10 is shown, the wafer 10 includes a bonding area 10a and a rim area 10b surrounding the bonding area 10a, the bonding area 10a includes a plurality of chip areas 10c arranged in an array and scribe line areas 10d located between the chip areas 10c, in the step of bonding the first wafer 11 and the second wafer 12, the chip areas 10c of the first wafer 11 and the second wafer 12 are disposed opposite to each other up and down, and the scribe line areas 10d of the first wafer 11 and the second wafer 12 are disposed opposite to each other up and down.

In the above-described encapsulation method, after the third thinning process is performed, the edge of the dicing street 10d is liable to come off (as indicated by a broken line circle in fig. 5).

Referring to fig. 7 to 12 in combination, fig. 7 is a partial enlarged view of fig. 6 at a, fig. 8 is a partial plan view of fig. 7 at a chip region 10c, fig. 9 is a sectional view of fig. 7 along a direction 1-1, fig. 10 is a sectional view of fig. 7 along a direction 2-2, fig. 11 is a partial plan view of fig. 7 at a scribe line region 10d, fig. 12 is a sectional view of fig. 7 along a direction 3-3, and it has been found that each wafer 10 further includes: a bonding pad 16 located in the dielectric layer 14, and the bonding pad 16 is exposed from the bonding surface 15; in the step of bonding the first wafer 11 and the second wafer 12, as shown in fig. 9 and 10, in the chip region 10c, the bonding pads 16 of the first wafer 11 and the second wafer 12 are opposed to each other up and down and bonded, and as shown in fig. 12, in the scribe line region 10d, the bonding pads 16 are opposed to the dielectric layer 14 of the other wafer 10 and bonded, and the bonding strength of the scribe line region 10d is weak; in the process of performing the second thinning process, the bonding interface edge of the first wafer 11 and the second wafer 12 is prone to loosening due to the external force of the thinning process, particularly at the edge of the scribe line region 10d (as shown by the dashed circle in fig. 4); in the process of performing the third thinning process, when the thickness of the substrate 13 of the first wafer 11 is thin, a serious peeling (Peeling) abnormality (shown by a broken line circle in fig. 5) is liable to occur at the bonding interface edge of the dicing street 10 d.

Further analysis has found that, in connection with fig. 8 to 12, the dielectric layer 14 of each wafer is further formed with a stacked first top layer interconnect 17 and second top layer interconnect 18, and the bond pad 16 is in contact with the second top layer interconnect 18; by analyzing the film layer structures of the edges of the scribe line region 10d and the chip region 10c, it was found that the pattern density of the first top layer interconnect line 17 and the second top layer interconnect line 18 of the scribe line region 10d is higher (see fig. 11 to 12) than the pattern density of the first top layer interconnect line 17 and the second top layer interconnect line 18 of the chip region 10c (see fig. 8 to 10), and the stress variation is more remarkable due to the higher density of the top layer interconnect line of the scribe line region 10d during the first thinning process, the second trimming process, the second thinning process, and the third thinning process, and the problem of delamination is more likely to occur in the scribe line region 10d due to the external force of the trimming process and the thinning process, resulting in reduced reliability of packaging between wafers, and improved packaging yield.

One way to solve the above problems is to reduce the polishing rate of the wafer during the wafer thinning process, so as to reduce the impact force of the external force on the wafer. However, this method cannot fundamentally solve the problem that the dicing street area is liable to fall off and delaminate.

Therefore, how to improve the reliability and the yield of the package between the wafers is a urgent problem to be solved.

In order to solve the technical problem, the embodiment of the invention provides a wafer, which comprises a groove at least positioned in a dielectric layer of a dicing channel area close to the edge of the wafer; the protective layer is filled in the groove; the protective layers are arranged oppositely and form a sintered body when bonding between bonding surfaces of a plurality of wafers is realized, so that when bonding between the plurality of wafers is realized, the sintered body is formed by arranging the protective layers of the plurality of wafers oppositely, the bonding surfaces of the sintered body can be formed at the edge of the cutting channel region close to the wafer, the sintered body is of an integrated structure, the bonding firmness between the bonding surfaces is improved, particularly the bonding strength of the cutting channel region close to the edge of the wafer is improved, the sintered body positioned at the cutting channel region close to the edge of the wafer can play a role in protecting the structure inside the wafer in the subsequent process (such as thinning process, trimming process and the like) so as to prevent stress change generated by external force from extending to the inside of the wafer, and further reduce the probability that the film structure at the edge of the cutting channel region falls off in the subsequent process, thereby being beneficial to improving the reliability and packaging yield of the wafer package.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 13-16, schematic structural diagrams of an embodiment of a wafer of the present invention are shown. Fig. 13 is a top view of a wafer, fig. 14 is a partial enlarged view of fig. 13 at B, and fig. 15 to 16 are schematic sectional structures of two wafers in a radial direction.

In this embodiment, the wafer 100 includes a bonding region 100a, where the bonding region 100a includes chip regions 100c arranged in an array and scribe line regions 100d located between the chip regions 100 c; the wafer 100 includes: a substrate 130; the dielectric layer 140 is positioned on the substrate 130, and the exposed surface of the dielectric layer 140 is a bonding surface 150; a recess 190 in the dielectric layer 140 at least in the scribe line region 100d near the edge of the wafer 100; a protective layer 200 filled in the groove 190; the protective layer 200 is used to be disposed opposite to each other and form a sintered body when bonding between the bonding surfaces 150 of the plurality of wafers 100 is achieved.

In this embodiment, the wafer 100 is fabricated using integrated circuit fabrication techniques.

In this embodiment, the wafer 100 includes a bonding region 100a, and the bonding region 100a is a region for bonding a subsequent wafer 100.

In this embodiment, the bonding region 100a includes chip regions 100c arranged in an array and scribe line regions 100d located between the chip regions 100 c. The chip region 100c is used to form a plurality of chips, and the scribe line region 100d is used to scribe the wafer 100. Specifically, the wafer 100 is subsequently diced along the scribe line region 100d, and the wafer of the chip region 100c is separated into a plurality of chips.

For convenience of illustration and description, in the present embodiment, only a part of the chip region 100c and the scribe line region 100d are schematically shown in the cross-sectional view. In a specific implementation, the number of chip regions 100c and scribe line regions 100 is plural.

In this embodiment, the wafer 100 further includes a rim region 100b surrounding the bonding region 100 a.

In this embodiment, when the wafers 100 are bonded to each other later, the bonding areas 100a of the wafers 100 are disposed opposite to each other, and the edge ring areas 100b are disposed opposite to each other, so that the bonding area of the wafers 100 is larger and the surface planarization is better when the wafers 100 are bonded, which is beneficial to improving the bonding effect between the wafers 100.

In this embodiment, the rim area 100b is a region where trimming is required to be performed subsequently, so that the arc-shaped sidewall of the edge of the wafer 100 with a partial thickness is cut from the bonding surface 150 side, and a steep sidewall is formed for performing the subsequent process.

More specifically, the wafer 100 includes a first wafer 110 (fig. 15) and a second wafer 120 (fig. 16), wherein in the process of the first wafer 110, the method includes: the edge thinning process is performed on the rim area 100b, and the dielectric layer 140 and a portion of the thickness of the substrate 100 in the rim area 100b are removed to perform the trimming process on the first wafer 110, so that in the first wafer 130, the bonding surface 150 is higher than the top surface of the wafer 100 in the rim area 100 b.

After the wafers 100 are bonded to each other, the wafer 100 needs to be thinned at the back side (the surface of the wafer 100 opposite to the bonding surface 150), and since the edge of the wafer 100 is generally circular-arc, chipping of the circular-arc edge of the remaining wafer 100 is likely to occur during the back side thinning, and by trimming the wafer 100, the wafer 100 having a width of a portion of the wafer 100 thinned from the bonding surface 150 side along the edge of the wafer 100 makes the edge of the wafer 100 having a thickness of the portion of the wafer 100 on the bonding surface 150 side have a shape of a vertical plane, and accordingly, the surface of the wafer 100 has a step (as shown in fig. 15), and therefore, when the wafer 100 is thinned at the back side later, chipping of the wafer 100 is removed due to the sidewall shape of the remaining wafer 100 having a vertical plane after the trimming, which is beneficial to avoid chipping of the wafer 100 when the back side thinning is performed.

The substrate 130 is used to provide a process platform for the fabrication of the wafer 100.

As one example, the substrate 130 of the wafer 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

In this embodiment, the wafer 100 further includes: the bonding pad 160 is located in the dielectric layer 140, and the bonding pad 160 is exposed on the bonding surface 150.

The bond pads 160 are used to make electrical connection between the wafer 100 and external circuitry. In this embodiment, when bonding between different wafers 100 is implemented, bonding pads 160 of different wafers in the chip area 100c are disposed and bonded relatively, so that not only bonding between different wafers 100 is implemented, but also electrical connection between different wafers 100 is implemented through the bonding pads 160.

In this embodiment, the bonding pad 160 comprises one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is advantageous for obtaining better electrical conductivity.

The dielectric layer 140 is used to provide a process basis for forming bond pads 160 and also to isolate adjacent bond pads 160 from one another.

In this embodiment, the exposed surface of the dielectric layer 140 is the bonding surface 150, that is, when the different wafers 100 are bonded later, the dielectric layers 140 of the different wafers 100 are disposed opposite to each other and bonded.

Specifically, the bonding surface 150 is a top surface of the dielectric layer 140, and the bonding surface 150 is a surface for bonding the wafers 100, so that after bonding between the wafers 100 is achieved, electrical connection between circuit structure layers of the wafers 100 can be achieved, thereby achieving normal functions of the package structure.

In this embodiment, the material of the dielectric layer 140 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The dielectric layer 140 is further formed with a circuit structure, and the dielectric layer 140 is further used for providing a process foundation for forming the circuit structure and is further used for isolating adjacent circuit structures.

The circuit structure is used to electrically bring out the devices in the wafer 100 in order to make electrical connection with external circuitry or other structures.

In this embodiment, the circuit structure located in the scribe line region 100d is a dummy circuit structure, and the dummy circuit structure is used to improve the uniformity of the distribution of the circuit structures on the wafer 100.

In this embodiment, the circuit structure includes a first top-level interconnection line (not shown) and a second top-level interconnection line 180 stacked, and the bonding pad 160 is in contact with the second top-level interconnection line 180, so that an electrical connection between the circuit structure and an external circuit or other structure is achieved through the bonding pad 160.

In this embodiment, the materials of the first top layer interconnection line (not shown) and the second top layer interconnection line 180 include one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc and chromium, which is advantageous for obtaining better conductive performance.

It should be noted that, compared to the pattern density of the first top layer interconnection line and the second top layer interconnection line 180 of the chip area 100c, the pattern density of the first top layer interconnection line and the second top layer interconnection line 180 of the scribe line area 100d is greater, and the stress variation is more obvious due to the greater density of the top layer interconnection line of the scribe line area 100d during the subsequent thinning and trimming processes of the wafer, and if the processing is not performed, the risk of falling off and delamination of the film structure of the scribe line area 100d during the subsequent process (e.g., the trimming and/or thinning processes) is higher.

Furthermore, in some embodiments, when bonding between the wafers 100 is achieved, bonding pads 160 of the wafers 100 are opposed and bonded up and down between the die areas 100c to achieve a circuit connection between the wafers 100; in the scribe line region 100d, the bonding pad 160 is in contact with and bonded to the dielectric layer 140 of another wafer 100, so that the bond strength of the scribe line region 100d is weak, and the scribe line region 100d is more prone to loosening and delamination in the area near the edge of the wafer 100 under the action of external force in the subsequent process.

For this purpose, in this embodiment, a groove 190 is further provided in the wafer 100, and the groove 190 is further filled with a protective layer 200. Wherein the recess 190 is used to provide a spatial location for the protective layer 200.

In this embodiment, the grooves 190 are at least located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d, so that the protective layer 200 can be located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d, and further, when bonding between the wafers 100 is achieved, the protective layers 200 of the wafers 100 are arranged oppositely to form a sintered body, and a bonding surface of the sintered body can be formed near the edge of the wafer 100 in the scribe line region 100d, so that the sintered body is an integral structure, and further, the bonding strength between the bonding surfaces is improved, especially, the bonding strength near the edge of the wafer 100 in the scribe line region 100d, and the sintered body near the edge of the wafer 100 can play a protective role in the following processes (such as a thinning process and a trimming process), so as to prevent the stress variation generated by external force from extending into the wafer 100, and further reduce the probability of falling off of the film structure at the edge of the scribe line region 100d in the following processes, thereby being beneficial to improving the reliability and packaging yield of the wafer package.

Wherein the sintering process can cause bonding between powder particles, the strength of the sintered body is increased, and the aggregate of the powder particles is changed into an aggregate of crystal grains, thereby obtaining a structure with higher physical and mechanical properties.

Correspondingly, the material capable of forming the sintered body is selected as the protective layer 200, so that when the wafers 100 are bonded, the protective layers 200 of different wafers 100 are arranged oppositely and can be welded together to form the sintered body, so that the bonding firmness of the wafer 100 at the edge of the dicing channel area 100d is improved, the protection effect of the sintered body on the internal structure of the wafer 100 is ensured, and the stress variation generated at the edge of the wafer 100 is prevented from extending towards the inside of the wafer 100.

In this embodiment, the material of the protection layer 200 includes metal oxide and/or oxide of semiconductor material and composite material thereof. The oxides of metal oxides and semiconductor materials, as well as composites thereof, are typically capable of undergoing a sintering process and are in turn capable of being welded together to form a sintered body.

As one example, the material of the protective layer 200 includes glass. By adopting glass as the material of the protective layer 200, no by-products are generated, and the stress variation of the glass in different environments is small, so that the introduction of additional risks is avoided.

In other embodiments, the protective layer may also be other materials capable of forming a sintered body based on actual process requirements.

In this embodiment, the wafer 100 further includes a border region 100b surrounding the bonding region 100a, the border region 100b is a region to be trimmed later, that is, a region to be cut later, and the groove 190 is located at least in the dielectric layer 140 adjacent to the border region 100b in the dicing street region 100d, so that the protection layer 200 can be located at the edge of the bonding region 100a, and at least can protect the film structure inside the dicing street region 100d to prevent the stress variation generated by the external force from extending to the inside of the dicing street region 100 d.

It should be noted that, in the radial direction, the distance N1 (as shown in fig. 15 and 16) between the groove 190 and the rim area 100b is not too small or too large. If the distance N1 is too small, the probability of damage to the protective layer 200 in the groove 190 during the subsequent trimming process of the edge ring area 100b is easily increased; if the distance N1 is too large, the distance between the groove 190 and the film structure inside the scribe line region 100d is too short, which easily increases the probability of damaging the film inside the scribe line region 100d during the formation of the groove 190, and thus easily reduces the process stability. For this reason, in the present embodiment, the distance N1 between the groove 190 and the rim area 100b is 1mm to 10mm in the radial direction.

In this embodiment, the groove 190 at least covers the scribe line region 100d along the circumferential direction, so that the protection layer 200 can be located in the dielectric layer 140 of the entire scribe line region 100d along the circumferential direction, and further can protect the film structure inside the entire scribe line region 100d, thereby correspondingly improving the blocking effect of the protection layer 200 on the stress variation generated by the external force, and further reducing the probability of falling off and delamination of the film structure of the scribe line region 100 d.

More specifically, in the present embodiment, the length of the groove 190 is greater than the length of the scribe line region 100d along the circumferential direction, so as to prevent the groove from not completely covering the scribe line region along the circumferential direction due to process errors, and thus, it is beneficial to ensure that the groove 190 can cover at least the entire scribe line region 100d along the circumferential direction.

As a specific embodiment, the length L1 (as shown in fig. 14) of the groove 190 is greater than the length L0 (as shown in fig. 14) of the scribe line region 100d along the circumferential direction, and the difference between the lengths of the groove 190 and the scribe line region 100d is at least 400 micrometers, so as to further reduce the influence of factors such as process errors, ensure that the groove 190 can cover the entire scribe line region 100d along the circumferential direction, and accordingly ensure the blocking effect of the protection layer 200 on the extension of the stress variation into the wafer 100.

As an example, as shown in fig. 13, in the wafer 100, the number of grooves 190 in the same scribe line region 100d is plural, and the plural grooves 190 are arranged at intervals in the radial direction (the radial or diametrical direction of the wafer 100). The plurality of grooves 190 are formed in the dicing street region 100d, so that the number of the protective layers 200 in the dicing street region 100d is also multiple, and the plurality of protective layers 200 extend along the circumferential direction and are distributed at intervals along the radial direction, so that the bonding strength and the firmness of the edge of the dicing street region 100d during bonding between subsequent wafers 100 can be further improved, the protection effect of the subsequent sintered body on the internal film structure of the wafer 100 and the blocking effect of the internal extension of stress variation can be further improved, and the risk of delamination and falling of the edge of the wafer 100, particularly the film structure of the dicing street region 100 close to the edge of the wafer 100, is remarkably reduced.

In this embodiment, too many grooves 190 are not needed in the scribe line region 100d, otherwise, too much space is easily occupied in the scribe line region 100 d. As an example, the number of grooves is 1 to 20, for example: 3, 5, 10, etc. In other embodiments, the number of grooves in the scribe line region may be other based on actual process requirements.

It should also be noted that the spacing (space) between adjacent grooves 190 should not be too small or too large in the radial direction. If the spacing between adjacent grooves 190 is too small, the risk of chipping the dielectric layer 140 between adjacent grooves 190 tends to increase; if the interval between the adjacent grooves 190 is too large, it is easy to occupy an excessive area of the dicing street area 100 d. For this reason, in the present embodiment, the interval between adjacent grooves 190 is 20 μm to 1500 μm in the radial direction.

It should be noted that the opening width of the radial groove 190 should not be too small or too large. If the opening width of the groove 190 is too small in the radial direction, the difficulty of the process of filling the protective layer 200 in the groove 190 is easily increased, and the width of the protective layer 200 in the radial direction is too small, so that the blocking capability of the protective layer 200 to subsequent stress changes is easily insignificant; if the opening width of the groove 190 is too large in the radial direction, it is easy to cause the groove 190 to occupy an excessive area of the dicing street area 100 d. For this reason, in the present embodiment, the opening width of the radial groove 190 is 50 micrometers to 1000 micrometers.

It should also be noted that the depth of the groove 190 should not be too small or too large. If the depth of the groove 190 is too small, it is easy to increase the difficulty of the process of forming the protective layer 200 in the groove 190, for example: when the protective layer 200 is formed in the groove 190 by using the inkjet printing process, droplets of the inkjet printing easily overflow the groove 190, and too small a depth of the groove 190 easily causes too small a depth of the protective layer 200, so that the blocking effect of the protective layer 200 on the extension of the stress variation into the wafer 100 is not obvious; if the depth of the recess 190 is too large, the thickness of the wafer 100 remaining at the bottom of the recess 100 is easily too thin, which tends to increase the risk of contacting the protective layer located in the recess 190 during the subsequent back side thinning process of the wafer 100, and correspondingly tends to increase the process risk. For this purpose, the depth of the grooves 190 is 0.3 to 50 microns in this embodiment.

In this embodiment, the wafer may be formed by the wafer manufacturing method in this embodiment, or may be formed by another wafer manufacturing method.

Fig. 17 to 18 are schematic structural views of another embodiment of a wafer according to the present invention. Fig. 17 is a plan view, and fig. 18 is a partial enlarged view of fig. 17 at B. The points of the embodiments of the present invention that are the same as the foregoing embodiments are not described in detail herein, and the differences between the embodiments of the present invention are:

in this embodiment, the grooves 310 circumferentially surround the edge of the wafer 300.

The grooves 310 circumferentially surround the edges of the wafer 300, so that the grooves 310 are circumferentially located not only in the scribe line region 300d but also in the die region 300c, and accordingly, the protective layers 320 are circumferentially located not only in the scribe line region 300d but also in the die region 300c, and further, when bonding between the wafers 300 is subsequently performed, the protective layers 320 of the wafers 300 are disposed opposite to each other and the formed sintered body circumferentially surrounds the edges of the wafers 300, so that not only the bonding firmness of the scribe line region 300d but also the bonding firmness of the die region 300c can be improved, and accordingly, the blocking effect of the sintered body on the stress variation extending toward the inside of the wafer 300 can be further improved.

More specifically, in the present embodiment, the groove 310 surrounds the edge of the bonding region 300a in the circumferential direction, and the groove 310 is located in the rim region 300b in the radial direction with a distance between the groove 310 and the rim region 300b in the radial direction.

For a specific description of the wafer in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Correspondingly, the embodiment of the invention also provides a wafer manufacturing method. Fig. 19 to 27 are schematic structural views corresponding to each step in an embodiment of a wafer manufacturing method according to the present invention.

The wafer manufacturing method of the present embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 19 to 20, fig. 19 is a cross-sectional view, fig. 20 is a top view corresponding to fig. 19, and a wafer 100 is provided, including a bonding region 100a, where the bonding region 100a includes chip regions 100c arranged in an array and scribe line regions 100d located between the chip regions 100 c; the wafer 100 includes a substrate 130 and a dielectric layer 140 disposed on the substrate 130, where an exposed surface of the dielectric layer 140 is a bonding surface 150.

In this embodiment, the bonding region 100a includes chip regions 100c arranged in an array and scribe line regions 100d located between the chip regions 100 c. The chip region 100c is used to form a plurality of chips, and the scribe line region 100d is used to scribe the wafer 100. Specifically, the wafer 100 is subsequently diced along the scribe line region 100d, and the wafer 100 of the chip region 100c is separated into a plurality of chips.

More specifically, the wafer 100 includes a first wafer 110 (as shown in fig. 19 (a)) and a second wafer 120 (as shown in fig. 19 (b)), wherein in the process of the first wafer 110, the method includes: the edge thinning process is performed on the rim area 100b, and the dielectric layer 140 and a portion of the thickness of the substrate 100 in the rim area 100b are removed to perform the trimming process on the first wafer 110, so that in the first wafer 130, the bonding surface 150 is higher than the top surface of the wafer 100 in the rim area 100 b.

After the wafers 100 are bonded to each other, the wafer 100 needs to be thinned at the back side (the surface of the wafer 100 opposite to the bonding surface 150), and since the edge of the wafer 100 is generally circular-arc, chipping of the circular-arc edge of the remaining wafer 100 is likely to occur during the back side thinning, and by trimming the wafer 100, the wafer 100 having a width of a portion of the wafer 100 thinned from the bonding surface 150 side along the edge of the wafer 100 makes the edge of the wafer 100 having a thickness of the portion of the wafer 100 on the bonding surface 150 side have a shape of a vertical plane, and accordingly, the surface of the wafer 100 has a step (as shown in fig. 19 (a)), so that during the back side thinning of the wafer 100, chipping of the wafer 100 is avoided as much as possible due to the sidewall shape of the remaining wafer 100 after the trimming being a vertical plane.

The dielectric layer 140 is used to provide a process basis for forming bond pads 160 and also to isolate adjacent bond pads 160 from one another. In this embodiment, the exposed surface of the dielectric layer 140 is the bonding surface 150, that is, when bonding between different wafers 100 is performed subsequently, the dielectric layers 140 of different wafers 100 are disposed opposite to each other and bonded.

Specifically, the bonding surface 150 is a top surface of the dielectric layer 140, and the bonding surface 150 is a surface for bonding the wafer 100, so that after bonding the wafer 100, electrical connection between circuit structure layers of the wafer 100 can be realized, thereby realizing a normal function of the package structure.

Referring to fig. 21 to 23 in combination with fig. 19, fig. 21 is a cross-sectional view, fig. 22 is a top view corresponding to fig. 21, fig. 23 is a partial enlarged view of fig. 22 at B, and a recess 190 is formed in the dielectric layer 140 at least near the edge of the wafer 100 in the scribe line region 100 d.

The grooves 190 serve to provide a spatial location for the formation of the protective layer.

In this embodiment, the groove 190 is at least located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d, so that a protective layer is formed in the groove 190, and the protective layer can be located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d at least, so that when bonding between the wafers 100 is achieved, the protective layers of the wafers 100 are oppositely disposed to form a sintered body, and a bonding surface of the sintered body can be formed near the edge of the wafer 100 in the scribe line region 100d, so that the sintered body is in an integral structure, and further the bonding firmness of the bonding between the two layers is improved, especially the bonding strength near the edge of the wafer 100 in the scribe line region 100d, and the sintered body near the edge of the wafer 100 can play a protective role in the following process (e.g. thinning process and trimming process) to prevent the stress variation generated by the external force from extending into the wafer 100, thereby reducing the probability of falling off the film structure at the edge of the scribe line region 100d in the following process, and being beneficial to improving the reliability and packaging yield of the wafer.

Therefore, in the embodiment, the groove 190 is at least located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d, so that the subsequent protective layer can be at least located in the dielectric layer 140 near the edge of the wafer 100 in the scribe line region 100d, which can significantly improve the blocking effect of the stress variation generated by the external force of the sintered body in the subsequent process on the extension of the sintered body to the inside of the wafer 100, and further significantly reduce the probability of falling off of the film structure at the edge of the wafer 100 in the subsequent process.

In this embodiment, the wafer 100 further includes a border region 100b surrounding the bonding region 100a, where the border region 100b is a region to be trimmed later, that is, a region to be cut later, and the groove 190 is located at least in the dielectric layer 140 adjacent to the border region 100b in the dicing street region 100d, so that the protective layer can be located at the edge of the bonding region 100a, and at least can protect the film structure inside the dicing street region 100d, so as to prevent the stress variation generated by the external force from extending into the dicing street region 100 d.

It should be noted that, in the radial direction, the distance N1 (as shown in fig. 21) between the groove 190 and the rim area 100b should not be too small or too large. If the distance N1 is too small, the probability of damage to the protective layer 200 in the groove 190 during the subsequent trimming process of the edge ring area 100b is easily increased; if the distance N1 is too large, the distance between the groove 190 and the film structure inside the scribe line region 100d is too short, which easily increases the probability of damaging the film inside the scribe line region 100d during the formation of the groove 190, and thus easily reduces the process stability. For this reason, in the present embodiment, the distance N1 between the groove 190 and the rim area 100b is 1mm to 10mm in the radial direction.

In this embodiment, the groove 190 at least covers the scribe line region 100d along the circumferential direction, so that the protective layer can be located in the dielectric layer 140 of the entire scribe line region 100d along the circumferential direction, and further can protect the film structure inside the entire scribe line region 100d, thereby correspondingly improving the blocking effect of the protective layer on the stress variation generated by the external force, and further reducing the probability of falling delamination problem of the film structure of the scribe line region 100d.

As a specific embodiment, the length L1 (as shown in fig. 23) of the groove 190 is greater than the length L0 (as shown in fig. 23) of the scribe line region 100d along the circumferential direction, and the difference between the lengths of the groove 190 and the scribe line region 100d is at least 400 micrometers, so as to further reduce the influence of factors such as process errors, ensure that the groove 190 can cover the entire scribe line region 100d along the circumferential direction, and accordingly ensure the blocking effect of the protection layer on the extension of the stress variation toward the inside of the wafer 100.

As an example, as shown in fig. 22, in the wafer 100, the number of grooves 190 in the same scribe line region 100d is plural, and the plural grooves 190 are arranged at intervals in the radial direction (the radial or diametrical direction of the wafer 100). The plurality of grooves 190 are formed in the dicing street region 100d, so that the number of protective layers formed in the grooves 190 of the dicing street region 100d is also a plurality of, and the plurality of protective layers 200 extend along the circumferential direction and are distributed at intervals along the radial direction, so that the bonding strength and the firmness of the edge of the dicing street region 100d during bonding between the subsequent wafers 100 can be further improved, the protection effect of the subsequent sintered body on the internal film structure of the wafer 100 and the blocking effect of the subsequent sintered body on the internal extension of the stress variation can be further improved, and the risk of delamination and falling of the edge of the wafer 100, particularly the film structure of the dicing street region 100 close to the edge of the wafer 100, is remarkably reduced.

It should be noted that the opening width of the radial groove 190 should not be too small or too large. If the opening width of the groove 190 is too small in the radial direction, the difficulty of the process of filling the protective layer 200 in the groove 190 is easily increased, and the width of the protective layer in the radial direction is too small, so that the blocking capability of the protective layer to subsequent stress changes is easily not obvious; if the opening width of the groove 190 is too large in the radial direction, it is easy to cause the groove 190 to occupy an excessive area of the dicing street area 100 d. For this reason, in the present embodiment, the opening width of the radial groove 190 is 50 micrometers to 1000 micrometers.

It should also be noted that the depth of the groove 190 should not be too small or too large. If the depth of the groove 190 is too small, it is easy to increase the difficulty of the process of forming the protective layer in the groove 190, for example: when the protective layer is formed in the groove 190 by using the inkjet printing process, droplets of the inkjet printing easily overflow the groove 190, and too small a depth of the groove 190 easily causes too small a depth of the protective layer, so that the protective layer has no obvious blocking effect on the extension of the stress variation into the wafer 100; if the depth of the recess 190 is too large, the thickness of the wafer 100 remaining at the bottom of the recess 100 is easily too thin, which tends to increase the risk of contacting the protective layer located in the recess 190 during the subsequent back side thinning process of the wafer 100, and correspondingly tends to increase the process risk. For this purpose, the depth of the grooves 190 is 0.3 to 50 microns in this embodiment.

It should be noted that the position, shape, opening size, depth, interval, number, and distance between the rim areas 100b of the above grooves 190 are described as an example. In particular embodiments, the location, topography, opening size, depth, spacing, number of grooves 190, and distance from rim area 100b may be set based on actual process requirements.

As one example, the step of forming the groove 190 includes: as shown in fig. 19, a mask pattern layer 195 is formed on the bonding surface 150; as shown in fig. 21, dielectric layer 140 is etched using mask pattern layer 195 as a mask to form a recess 190 in dielectric layer 140 at least near the edge of wafer 100 in scribe line region 100 d; mask pattern layer 195 is removed.

In this embodiment, the material of the mask pattern layer 195 is photoresist. As one example, the step of forming mask pattern layer 195 includes: forming a photoresist layer (not shown) on the bonding surface 150; performing an edge exposure process on the photoresist layer by using a mask 205; the exposed photoresist layer is removed and the remaining unexposed photoresist layer is used as a mask pattern layer 195.

In this embodiment, the recess 190 is formed by etching the dielectric layer 140 using the mask pattern layer 195 as a mask and using an anisotropic etching process (e.g., an anisotropic dry etching process). The anisotropic etching process has better pattern transmission quality.

In this embodiment, the process of removing the mask pattern layer 195 includes one or both of an ashing process and a wet photoresist removing process.

Referring to fig. 24 to 27, the grooves 190 are filled with the protective layer 200, and the protective layer 200 is used to be disposed opposite to each other and form a sintered body when bonding between the bonding faces 150 of the plurality of wafers 100 is achieved.

The protective layer 200 is at least located in the dielectric layer 140 near the edge of the wafer 100 in the dicing street area 100d, and when bonding between the wafers 100 is achieved, the protective layers 200 of the wafers 100 are arranged oppositely to form a sintered body, so that a bonding surface of the sintered body can be formed near the edge of the wafer 100 in the dicing street area 100d, the sintered body is an integral structure, and further, the bonding firmness of the bonding between the two layers is improved, especially, the bonding strength near the edge of the wafer 100 in the dicing street area 100d is improved, and the sintered body near the edge of the wafer 100 in the dicing street area can play a protective role on the structure inside the wafer 100 in the subsequent process (such as a thinning process, a trimming process and the like) so as to prevent stress changes generated by external force from extending into the wafer 100, further, reduce the probability of falling off of the film structure at the edge of the dicing street area 100d in the subsequent process, and facilitate the improvement of the reliability and the packaging yield of the wafer package.

As one example, the step of forming the protective layer 200 includes: forming a mixture of nanospheres and solvent within recess 190; the mixed solution is heat-treated, and the remaining nanospheres are aggregated together to form the protective layer 200.

The mixed solution is used for forming a protective layer subsequently. Wherein the solvent is then volatilized and the nanospheres are subsequently used to adhere together to form a protective layer.

As an example, nanospheres have diameters of 3-200 nm, such as: 5nm.

In this embodiment, the nanospheres are nanospheres of glass. The material of the nanospheres comprises silicate and/or derivative of silicate.

In this example, a solvent was used to dissolve the nanospheres. As an example, the solvent may include one or more mixed solvents of ethanol, methylene chloride, petroleum ether, a sub-gram, a phenol resin, and the like.

As an example, the volume doping ratio of nanospheres to solvent should not be too low nor too high. If the volume doping ratio of the nanospheres to the solvent is too low, the volume of the residual nanospheres is too small after the subsequent heat treatment of the mixed solution, so that the nanospheres are difficult to aggregate together, or the protective layer formed by the aggregation together is difficult to fill the groove 190; if the volume doping ratio of the nanospheres to the solvent is too high, the nozzles of the inkjet printing apparatus are easily blocked when the mixed liquid is formed in the groove 190 by using the inkjet printing process, thereby easily affecting the service life of the inkjet printing apparatus and easily reducing the accuracy of inkjet printing. For this reason, in this embodiment, the volume doping ratio of the nanospheres and the solvent is 40% to 90%.

The volume doping ratio of the nanospheres to the solvent refers to the ratio between the volume of the nanospheres and the volume of the solvent in the mixed solution.

It should be noted that, in this embodiment, the mixed solution further includes an adhesive, and the adhesive is used to adhere the remaining nanospheres together when the solvent volatilizes in the subsequent heat treatment process of the mixed solution, so as to form the solid protection layer 200.

As one example, the adhesive includes a acrylic adhesive.

The volume doping ratio of the adhesive to the solvent is not too high or too low. If the volume doping ratio of the pectin binder to the solvent is too high, when the mixed liquid is formed in the groove 190 by using the inkjet printing process, the nozzle of the inkjet printing device is easily blocked, the service life of the inkjet printing device is easily affected, and the accuracy of inkjet printing is easily reduced; if the volume doping ratio of the pectin binder to the solvent is too low, the difficulty of adhering the residual nanospheres together to form a protective layer in the subsequent heat treatment process is easily increased. As an example, the volume doping ratio of the adhesive to the solvent is 10 to 60%.

As an example, as shown in fig. 24, a mixed solution of nanospheres and solvent is formed within the grooves 190 using an inkjet printing process.

By adopting the ink-jet printing process, the mixed solution of the nanospheres and the solvent can be directly sprayed at the position in need of the process, and the mixed solution can be directly formed in the groove 190, so that the step of removing the mixed solution or the protective layer material in the unnecessary area is not needed, and the step of forming the protective layer 200 is simplified.

As shown in fig. 25 to 27, fig. 25 is a cross-sectional view, fig. 26 is a plan view corresponding to fig. 25, fig. 27 is a partially enlarged view of fig. 26 at B, and the mixed solution is subjected to a heat treatment for volatilizing the solvent to reduce the solvent content in the mixed solution, so that the nanospheres are gathered together to form the protective layer 200.

More specifically, in this embodiment, the mixed solution contains an adhesive, and most of the solvent volatilizes during the heat treatment of the mixed solution, and the adhesive bonds the nano glass spheres together to form the protective layer 200.

The temperature at which the mixed solution is heat-treated should not be too low or too high. If the temperature of the heat treatment is too low, it is liable to cause the solvent to volatilize and the nanospheres to be aggregated together to form a protective layer with too low efficiency; if the temperature of the heat treatment is too high, devices inside the wafer 100 are easily adversely affected. For this reason, in this embodiment, the temperature at which the mixed solution is heat-treated is 80 ℃ to 450 ℃, for example: 400 ℃.

As an example, the wafer 100 with the mixed liquid is subjected to a heat treatment using an Alloy (Alloy) apparatus.

Fig. 28 to 31 are schematic structural views corresponding to steps in another embodiment of the wafer manufacturing method according to the present invention. The points of the embodiments of the present invention that are the same as the foregoing embodiments are not described in detail herein, and the differences between the embodiments of the present invention are:

referring to fig. 28 to 29, fig. 28 is a top view, and fig. 29 is a partially enlarged view of fig. 28 at B, in this embodiment, in the step of forming the groove 310, the groove 310 surrounds the edge of the wafer 300 in the circumferential direction.

Referring to fig. 30 to 31, fig. 30 is a top view, fig. 31 is a partial enlarged view of fig. 30 at B, and a protective layer 320 is formed in the groove 310.

For a specific description of the wafer manufacturing method of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, and the description of the embodiment is omitted here.

Correspondingly, the embodiment of the invention also provides a packaging structure. Fig. 32 is a schematic structural diagram of an embodiment of the package structure of the present invention.

In this embodiment, the package structure includes: the wafers 100 provided in the present embodiment include a first wafer 110 and a second wafer 120; the bonding surfaces 150 of the first and second wafers 110 and 120 are disposed opposite to each other and bonded, and the protective layers 200 of the first and second wafers 110 and 120 are disposed opposite to each other and form a sintered body 250.

The bonding surfaces 150 of the first wafer 110 and the second wafer 120 are oppositely arranged and bonded, and the protective layers 200 of the first wafer 110 and the second wafer 120 are oppositely arranged and form the sintered body 250, so that the bonding surfaces of the sintered body 200 are formed at the edge of the dicing street area 100d close to the wafer 100, the sintered body 250 is of an integrated structure, the bonding firmness between the first wafer 110 and the second wafer 120 can be improved, particularly the bonding strength of the dicing street area 100d close to the edge of the wafer 100 can be improved, and the sintered body positioned at the edge of the dicing street area 100d close to the edge of the wafer 100 can play a role in protecting the structure inside the wafer 100 in the subsequent process (such as a thinning process, a trimming process and the like) so as to prevent the stress change generated by external force from extending to the inside the wafer 100, further reduce the probability that the film structure at the edge of the dicing street area 100d falls off in the subsequent process, and improve the reliability and packaging yield of the packaging structure.

In the embodiment, in the package structure, the chip regions 100c of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down, and the scribe line regions 100d of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down, so as to achieve bonding between the chip regions 100c of the wafer 100, and then the package structure can be diced along the scribe line regions 100d, so that the chip regions 100c bonded together in the package structure are separated from each other, and a plurality of separated chips are formed.

In this embodiment, the grooves 190 of the first wafer 110 and the second wafer 120 are disposed vertically opposite to each other, and the shapes, positions, lengths and opening widths of the grooves 190 of the first wafer 110 and the second wafer 120 are the same, so that the protective layers 200 located in the grooves 190 can be vertically aligned, the sintering effect of the formed sintered body 250 is improved, and the bonding strength and the firmness can be further improved.

In this embodiment, the wafer 100 further includes: a bonding pad 180 located in the dielectric layer 140, and the bonding pad 180 is exposed on the bonding surface 150; in the chip area 100c, the bonding pads 180 of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down and bonded, so that not only the physical bonding of the first wafer 110 and the second wafer 120 but also the circuit connection of the chip area 100c are realized.

In addition, in the chip area 100c, the dielectric layers 140 of the first wafer 110 and the second wafer 120 are disposed and bonded up and down oppositely, that is, in the chip area 100c, the first wafer 110 and the second wafer 120 are bonded in a hybrid manner, so as to realize high-density integration.

In this embodiment, the bonding pad 160 located in the scribe line region 100d is used as the dummy bonding pad 160 for supporting and balancing stress.

As an example, in the scribe line region 100d, since the bonding pad 160 is in relative contact with and bonded to the dielectric layer 140 of another wafer 100 without implementing circuit connection, the bonding strength of the scribe line region 100d is weak, so that the problem of loosening and delamination is more likely to occur in the region of the scribe line region 100d close to the edge of the wafer 100 under the action of external force in the subsequent process, and thus, by providing the sintered body in the scribe line region 100d in the package structure of the present embodiment, the problem of loosening and delamination is likely to occur in the region of the scribe line region 100d close to the edge of the wafer 100 can be significantly improved.

As an example, compared with the pattern density of the first top layer interconnection line and the second top layer interconnection line 180 of the chip area 100c, the pattern density of the first top layer interconnection line and the second top layer interconnection line 180 of the scribe line area 100d is higher, and in the subsequent wafer thinning and trimming processes, the stress variation is more obvious due to the higher density of the top layer interconnection line of the scribe line area 100d, and if not processed, the risk of falling off and layering is higher in the subsequent process (e.g., trimming and/or thinning) of the film structure of the scribe line area 100d, so that by providing the sintered body in the scribe line area 100d in the package structure of the present embodiment, the problem of loosening and falling off and layering in the area of the scribe line area 100d near the edge of the wafer 100 can be significantly improved.

The package structure in this embodiment includes the wafer 100 in the previous embodiment. For a detailed description of the wafer 100 in the package structure of the present embodiment, please refer to the corresponding description in the foregoing embodiment, which is not repeated here.

In this embodiment, the package structure may be formed by using the packaging method in this embodiment, or may be formed by using other packaging methods.

Correspondingly, the embodiment of the invention also provides a packaging method. Fig. 33 to 34 are schematic structural views corresponding to each step in an embodiment of the packaging method of the present invention. The following describes the packaging method of the present embodiment in detail with reference to the accompanying drawings.

Referring to fig. 33, a plurality of wafers 100 provided by the foregoing embodiments are provided, including a first wafer 110 and a second wafer 120.

A plurality of the wafers 100 provided in the foregoing embodiments are provided for subsequent bonding of the first wafer 110 and the second wafer 120.

For a detailed description of the wafer 100 in this embodiment, please refer to the corresponding description in the foregoing embodiment, and the detailed description of this embodiment is omitted here.

Referring to fig. 33 and 34, the first wafer 110 and the second wafer 120 are bonded, the bonding surfaces 150 of the first wafer 110 and the second wafer 120 are disposed opposite to each other, and the protective layers 200 of the first wafer 110 and the second wafer 120 are disposed opposite to each other and form a sintered body 250.

The protection layers 200 of the first wafer 110 and the second wafer 120 are oppositely arranged to form the sintered body 250, so that a bonding surface of the sintered body 200 is formed at the edge of the dicing channel region 100d close to the wafer 100, the sintered body 250 is of an integrated structure, the bonding firmness of the first wafer 110 and the second wafer 120 can be improved, particularly the bonding strength of the dicing channel region 100d close to the edge of the wafer 100, the sintered body 250 positioned at the edge of the dicing channel region 100d close to the edge of the wafer 100 can play a role in protecting the structure inside the wafer 100 in the subsequent process (such as thinning process, trimming process and the like) so as to prevent stress variation generated by external force from extending to the inside of the wafer 100, and further reduce the probability of falling off of the film structure at the edge of the dicing channel region 100d in the subsequent process, and improve the reliability and packaging yield of packaging.

In this embodiment, the sintering process can bond the powder particles, the strength of the sintered body is increased, and the aggregate of the powder particles is changed into a conglomerate of crystal grains, so that a structure with higher physical and mechanical properties is obtained.

In this embodiment, the chip regions 100c of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down, and the scribe line regions 100d of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down, so as to achieve bonding between the chip regions 100c of the wafer 100, and then the first wafer 110 and the second wafer 120 can be diced along the scribe line regions 100d, so as to enable separation between the chip regions 100 c.

In this embodiment, the grooves 190 of the first wafer 110 and the second wafer 120 are disposed vertically opposite to each other, and the shapes, positions, lengths and opening widths of the grooves 190 of the first wafer 110 and the second wafer 120 are the same, so that the protective layers 200 located in the grooves 190 can be vertically opposite to each other, and the sintering effect of the formed sintered body 250 can be further improved, so that the bonding strength and the firmness can be further improved.

In this embodiment, the wafer 100 further includes: a bonding pad 180 located in the dielectric layer 140, and the bonding pad 180 is exposed on the bonding surface 150; in the chip area 100c, the bonding pads 180 of the first wafer 110 and the second wafer 120 are disposed opposite to each other up and down and bonded, thereby achieving circuit connection of the chip area 100 c.

As an example, the step of bonding the first wafer 110 and the second wafer 120 includes:

As shown in fig. 33, the bonding surfaces 150 of the first wafer 110 and the second wafer 120 are bonded to each other, the die areas 100c of the first wafer 110 and the second wafer 120 are disposed opposite to each other vertically, and the scribe line areas 100d of the first wafer 110 and the second wafer 120 are disposed opposite to each other vertically, so that the protective layers 200 of the first wafer 110 and the second wafer 120 are in contact with each other.

In this embodiment, in the step of bonding the bonding surfaces 150 of the first wafer 110 and the second wafer 120 relatively, a certain pressure is applied to the first wafer 110 and the second wafer 120 to bond the first wafer 110 and the second wafer 120.

The protective layers 200 of the first and second wafers 110, 120 are in opposite contact, so that the protective layers 200 are pressed together first, so that the protective layers 200 of the first and second wafers 110, 120 can be welded together subsequently.

As shown in fig. 34, the protective layers 200 of the first wafer 110 and the second wafer 120 are subjected to a fusion bonding process to form a sintered body 250.

The protective layer 200 of the first and second wafers 110 and 120 is subjected to a fusion bonding process, so that a sintered body 250 of an integrated structure can be formed, bonding strength and firmness of the first and second wafers 110 and 120, particularly bonding strength and firmness of the first and second wafers 110 and 120 at the edge of the scribe line region 100d are improved, and a blocking effect of the sintered body 250 on stress variation extending from the edge of the wafer 100 to the inside is improved.

As an example, the step of performing the fusion bonding process on the protective layer 200 of the first wafer 110 and the second wafer 120 includes: pre-sintering the protective layer 200; after the pre-sintering process, as shown in fig. 34, the protective layer 200 is subjected to a laser irradiation process for welding the protective layers 200 of the first and second wafers 110 and 120 together to form a sintered body 250.

The protective layers 200 are pre-sintered so that the protective layers 200 of the first and second wafers 110 and 120 can be initially simply welded together, and gaps between the protective layers 200 are avoided as much as possible, to improve sintering quality and mechanical strength of the subsequent sintered body 250.

More specifically, the pre-sintering treatment of the protective layer 200 refers to the heating treatment of the protective layer 200 at a temperature lower than the normal sintering temperature.

It should be noted that the temperature of the pre-sintering should not be too low or too high. If the temperature of the pre-sintering is too low, the efficiency of the pre-sintering is easily lowered, or the pre-sintering effect is easily caused to be poor, for example: it is easy to cause gaps between the protective layers 200; if the pre-sintering temperature is too high, it is likely to adversely affect the device performance within the wafer 100. As one example, the process parameters of pre-sintering include: the temperature is 300 ℃ to 500 ℃.

The protective layer 200 is subjected to laser irradiation treatment so that the protective layer 200 is completely welded together to form the sintered body 250.

As an example, the protective layer 200 is subjected to laser irradiation treatment along the edge of the wafer 100 and in a direction parallel to the wafer 100. In this embodiment, the grooves 200 are at least located in the dielectric layer 140 of the scribe line region 100d near the edge of the wafer 100, and correspondingly, the protection layer is also at least located in the dielectric layer 140 of the scribe line region 100d near the edge of the wafer 100, and the laser irradiation treatment is performed along the edge of the wafer 100 and along the direction parallel to the wafer 100, so as to reduce the possibility of blocking the laser by the structures inside the wafer 100, improve the efficiency of the laser irradiation treatment, and accordingly facilitate the improvement of the sintering effect and sintering quality of the protection layer 200

As an example, laser irradiation treatment is performed with laser light having a wavelength of 810nm or 1064 nm. The laser with the wavelength of 810nm or 1064nm is the laser commonly used in the semiconductor field, thereby being beneficial to reducing the difficulty and cost of laser irradiation treatment and improving the compatibility with the prior art.

The subsequent process steps also generally include: the trimming process is performed on the first wafer 110 and the second wafer 120, and the back surface thinning process is performed on the first wafer 110 at least once, and an external force is applied to the wafer 100 during the trimming process and the back surface thinning process. In this embodiment, by forming the sintered body, the bonding firmness of the dicing street area 100d near the edge of the wafer 100 is significantly improved, and the integrated sintered body 250 can extend to the inside of the wafer 100 due to the stress change caused by the external force impact, so as to perform a better blocking function, thereby reducing the risk of delamination and delamination at the edge of the wafer 100.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A wafer comprising bonding regions, the bonding regions comprising chip regions arranged in an array and scribe line regions between the chip regions, the wafer comprising:

A substrate;

The dielectric layer is positioned on the substrate, and the exposed surface of the dielectric layer is a bonding surface;

The groove is at least positioned in the dielectric layer of the cutting channel area close to the edge of the wafer;

The protective layer is filled in the groove; the protective layer is used for being oppositely arranged and forming a sintered body when bonding between bonding surfaces of a plurality of wafers is realized.

2. The wafer of claim 1, further comprising a rim region surrounding the bonding region; the grooves are at least located in the dielectric layer adjacent to the cutting track area and the rim area.

3. The wafer of claim 2, wherein the distance between the groove and the rim area is 1mm to 10mm in the radial direction.

4. The wafer of claim 1 or 2, wherein the grooves cover at least the scribe line region in a circumferential direction.

5. The wafer of claim 4, wherein the length of the groove is greater than the length of the scribe line region in the circumferential direction, and the difference in length between the groove and the scribe line region is at least 400 microns.

6. The wafer of claim 1 or 2, wherein the groove circumferentially surrounds an edge of the wafer.

7. The wafer of claim 1, wherein the material of the protective layer comprises a metal oxide and/or an oxide of a semiconductor material.

8. The wafer of claim 1, wherein the material of the protective layer comprises glass.

9. The wafer of claim 1, wherein a plurality of grooves are disposed in a same scribe line region of the wafer, the plurality of grooves being radially spaced apart.

10. The wafer of claim 9, wherein a spacing between adjacent ones of the grooves is in a radial direction from 20 μm to 1500 μm.

11. The wafer of claim 9, wherein the number of grooves is 1 to 20.

12. The wafer of claim 1, wherein the grooves have an opening width of 50 microns to 1000 microns in a radial direction.

13. The wafer of claim 1, wherein the grooves have a depth of 0.3 microns to 50 microns.

14. The wafer of claim 1, wherein the wafer further comprises: and the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface.

15. A package structure, comprising:

A plurality of wafers according to any one of claims 1 to 14, comprising a first wafer and a second wafer; the bonding surfaces of the first wafer and the second wafer are oppositely arranged and bonded, and the protective layers of the first wafer and the second wafer are oppositely arranged and form a sintered body.

16. The package structure of claim 15, wherein the die areas of the first and second wafers are disposed opposite one another and the scribe line areas of the first and second wafers are disposed opposite one another.

17. The package structure of claim 16, wherein the recesses of the first and second wafers are disposed opposite one another up and down, and wherein the first and second wafers are identical in shape, position, length, and opening width.

18. The package structure of claim 16, wherein the wafer further comprises: the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface; and in the chip area, bonding pads of the first wafer and the second wafer are arranged up and down oppositely and bonded.

19. A method of packaging, comprising:

providing a plurality of wafers according to any one of claims 1 to 14, including a first wafer and a second wafer;

And bonding the first wafer and the second wafer, wherein bonding surfaces of the first wafer and the second wafer are opposite, and protective layers of the first wafer and the second wafer are opposite to each other to form a sintered body.

20. The packaging method of claim 19, wherein in the step of bonding the first and second wafers, grooves of the first and second wafers are disposed opposite one another up and down, and the grooves of the first and second wafers are identical in shape, position, length, and opening width.

21. The packaging method of claim 19, wherein bonding the first and second wafers comprises: bonding surfaces of the first wafer and the second wafer relatively, wherein the chip areas of the first wafer and the second wafer are arranged up and down relatively, and the cutting channel areas of the first wafer and the second wafer are arranged up and down relatively, so that the protective layers of the first wafer and the second wafer are in contact relatively; and welding the protective layers of the first wafer and the second wafer to form the sintered body.

22. The packaging method of claim 21, wherein the step of fusion bonding the protective layers of the first and second wafers comprises: presintering the protective layer; after the pre-sintering process, the protective layer is subjected to a laser irradiation process for welding the protective layers of the first and second wafers together to form the sintered body.

23. The packaging method of claim 22, wherein the pre-sintering process parameters include: the temperature is 300 ℃ to 500 ℃.

24. The packaging method of claim 22, wherein the protective layer is laser irradiated along an edge of the wafer and in a direction parallel to the wafer.

25. The packaging method of claim 21, wherein in the step of providing a plurality of wafers according to any one of claims 1 to 14, the wafers further comprise: the bonding pad is positioned in the dielectric layer and exposed out of the bonding surface;

in the step of bonding the first wafer and the second wafer, bonding pads of the first wafer and the second wafer are arranged up and down oppositely and bonded in the chip area.

26. A method of manufacturing a wafer, comprising:

Providing a wafer, wherein the wafer comprises bonding areas, and the bonding areas comprise chip areas arranged in an array manner and dicing channel areas positioned between the chip areas; the wafer comprises a substrate and a dielectric layer positioned on the substrate, wherein the exposed surface of the dielectric layer is a bonding surface;

forming a groove in a dielectric layer at least positioned in the cutting channel area and close to the edge of the wafer;

And filling the grooves with protective layers, wherein the protective layers are used for being oppositely arranged and forming a sintered body when bonding between bonding surfaces of a plurality of wafers is realized.

27. The wafer manufacturing method of claim 26, wherein the wafer further comprises a rim region surrounding the bonding region; and forming the groove at least in the dielectric layer adjacent to the cutting channel region and the edge ring region.

28. The wafer manufacturing method according to claim 27, wherein a distance between the groove and the rim area in a radial direction is 1mm to 10mm.

29. The method of claim 26 or 27, wherein the grooves cover at least the scribe line region in a circumferential direction.

30. The wafer manufacturing method according to claim 29, wherein the length of the groove is longer than the length of the scribe line region in the circumferential direction, and the difference between the length of the groove and the length of the scribe line region is at least 400 μm.

31. The method of claim 26 or 27, wherein the groove circumferentially surrounds an edge of the wafer.

32. The wafer manufacturing method according to claim 26, wherein the step of forming the protective layer comprises: forming a mixed solution of nanospheres and a solvent in the grooves; and carrying out heat treatment on the mixed solution, and gathering the rest nanospheres together to form the protective layer.

33. The wafer fabrication method of claim 32, wherein a mixture of nanospheres and solvent is formed within the grooves using an inkjet printing process.

34. The wafer manufacturing method according to claim 32, wherein the temperature at which the mixed solution is heat-treated is 80 ℃ to 450 ℃.

35. The wafer fabrication method of claim 32, wherein the nanosphere material comprises silicate and/or a derivative of silicate.

36. The wafer fabrication method of claim 32, wherein the volume doping ratio of nanospheres to solvent is from 40% to 90%.