CN118072776B - Data transmission method, device, host and storage medium - Google Patents

Abstract

The present disclosure provides a data transmission method, device, host and storage medium, wherein the data transmission method includes: performing multiple data processing operations, and based on the execution results of each data processing operation, recording the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to execute; when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, the zeroth identifier is selected from the multiple consecutive zeroth identifiers, and the delay code corresponding to the selected zeroth identifier is used as the target delay code; the data processing operation is executed using the target delay code. The above technical solution can improve the stability of the data transmission process.

Description

Data transmission method, device, host and storage medium

Technical Field

The embodiments of the present specification relate to the field of communication technology, and in particular, to a data transmission method, device, host, and storage medium.

Background Art

With the rapid development of electronic information technology, multimedia data continues to grow, and storage systems that provide larger storage capacity have become particularly important. Among them, embedded memory has the characteristics of high integration, small size, low power consumption, and low cost, and is widely used in various storage scenarios such as mobile devices and consumer electronics; embedded memory can include embedded multimedia controllers (eMMC) and secure digital cards (SD).

For embedded memory, during the data transmission process, a clock signal is usually used to sample the data signal. During this process, the stability of the clock signal determines the processing quality of the data transmission.

However, due to the influence of process deviation, even the same embedded memory may be affected by changes in the working environment (such as changes in the temperature and working voltage of the working environment), which may affect the clock signal and thus make it impossible to sample the data signal.

In this context, how to provide a technical solution to improve the stability of data transmission processing has become a technical problem that technical personnel in this field need to solve urgently.

Summary of the invention

In response to the above technical problems, the present disclosure provides a data transmission method, device, host and storage medium, which can improve the stability of data transmission processing.

The present disclosure provides a data transmission method, comprising:

Execute multiple data processing operations, and based on the execution results of each data processing operation, record the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to execute;

When it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, the zeroth identifier is selected from the multiple consecutive zeroth identifiers, and the delay code corresponding to the selected zeroth identifier is used as the target delay code;

The data processing operation is performed using the target delay code.

Optionally, the data transmission method further includes:

According to the order of executing each data processing operation, the zeroth identifier and the first identifier of the record are sorted to obtain an identifier sequence table;

When it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, selecting the zeroth identifier from the multiple consecutive zeroth identifiers, and using the delay code corresponding to the selected zeroth identifier as the target delay code, includes:

Determine an area in the identifier sequence table where there are continuous zeroth identifiers;

Selecting the zeroth marker from the determined area, and recording the selected zeroth marker in sequence to obtain a corresponding selection window;

The delay code corresponding to the zeroth mark located at the preset position of the selection window is used as the target delay code when executing each data processing operation.

Optionally, there are multiple selection windows;

The method of using the delay code corresponding to the zeroth mark located at the preset position of the selection window as the target delay code when performing each data processing operation includes:

Selecting a selected window containing the largest number of zeroth identifiers from the plurality of selected windows as a target window;

The delay code corresponding to the zeroth marker located at the preset position of the target window is used as the target delay code.

Optionally, before executing the step of determining the area where there are continuous zeroth identifiers in the identifier sequence table, the method further includes:

Determine whether the total number of the zeroth identifier and the first identifier contained in the identifier sequence table is the same as the number of times the data processing operation is performed, and if it is determined to be the same, perform the step of determining an area in the identifier sequence table where at least a continuous zeroth identifier exists; otherwise, continue to record the identifier of the delay code used for subsequent data processing operations.

Optionally, the data processing operation includes a data write operation;

The identifier sequence table includes a zeroth identifier corresponding to when the data write operation is successfully executed, and a first identifier corresponding to when the data write operation fails to execute.

Optionally, the data processing operation includes a data read operation;

The identifier sequence table includes a zeroth identifier corresponding to when the data read operation is successfully executed, and a first identifier corresponding to when the data read operation fails to execute.

Optionally, the data processing operation includes a data write operation;

The performing of multiple data processing operations and recording the identification of the delay code used in each data processing operation based on the execution result of each data processing operation includes:

According to the delay time lengths corresponding to the multiple delay codes, the clock signal is delayed multiple times, wherein a data write operation uses a delay time length corresponding to a delay code to perform a delay process on the clock signal once, and the delay time lengths corresponding to the delay codes are different;

After executing the data write operation under each delay processing of the clock signal, obtaining verification information corresponding to each data write operation, wherein the verification information is used to determine whether the data write operation can be successfully executed;

According to the verification information corresponding to each data writing operation, the identifier of the delay code used in each data writing operation is recorded.

Optionally, recording the identifier of the delay code used in each data write operation according to the verification information corresponding to each data write operation includes:

For any data write operation, when it is determined that the verification information corresponding to the data write operation is the same as the preset verification information, the identifier of the delay code used for the data write operation is recorded as the zeroth identifier, and when it is determined that the verification information corresponding to the data write operation is different from the preset verification information, the identifier of the delay code used for the data write operation is recorded as the first identifier.

Optionally, the using the target delay code to perform the data processing operation includes:

The clock signal is delayed according to the delay duration corresponding to the target delay code to perform a data write operation.

Optionally, the data processing operation includes a data read operation;

The performing of multiple data processing operations and recording the identification of the delay code used in each data processing operation based on the execution result of each data processing operation includes:

Determine the type of transfer mode for performing multiple data read operations;

According to the delay durations corresponding to the multiple delay codes, the clock signal corresponding to the transmission mode type is subjected to multiple delay processing, wherein a data read operation uses a delay duration corresponding to a delay code to perform one delay processing on the clock signal corresponding to the transmission mode type, and the delay durations corresponding to the delay codes are different;

After performing a data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation, wherein the read result is used to determine whether the data read operation is successfully performed when in the transmission mode type;

According to the reading result corresponding to each data read operation, the identifier of the delay code used in each data read operation is recorded.

Optionally, the data reading operation includes reading data stored in the first memory;

The determining of the transmission mode type for performing multiple data read operations includes:

The type of transmission mode for performing a data read operation is determined according to a data transmission rate for reading data stored in the first memory.

Optionally, determining the type of transmission mode for performing a data read operation according to a data transmission rate of reading data stored in the first memory includes:

When the data transmission rate of reading the data stored in the first memory is the same as the set rate, determining that the transmission mode type is the first transmission mode;

When the data transmission rate of reading the data stored in the first memory is different from the set rate, the transmission mode type is determined to be the second transmission mode.

Optionally, when determining that the transmission mode type is the first transmission mode, determining that a clock signal corresponding to the first transmission mode is a synchronous clock signal, the synchronous clock signal comes from a party providing read data;

The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes:

The synchronous clock signal is delayed multiple times according to the delay time lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay time length corresponding to a delay code to perform a delay process on the synchronous clock signal, and the delay time lengths corresponding to the different delay codes are different.

Optionally, when determining that the transmission mode type is the second transmission mode, determining that a clock signal corresponding to the second transmission mode is an initial clock signal, the initial clock signal is an acquired original clock signal;

The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes:

The initial clock signal is delayed multiple times according to the delay durations corresponding to the multiple delay codes, wherein a data read operation uses a delay duration corresponding to a delay code to perform a delay processing on the initial clock signal once, and the delay durations corresponding to the different delay codes are different.

Optionally, after performing the data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation includes:

For any data read operation,

Determining whether sending a preset first sampling instruction is supported when reading data stored in the first memory;

If supported, according to a preset first sampling instruction, a data read operation is performed under a delay processing of a clock signal corresponding to the transmission mode type to obtain a read result of the data read operation related to the first sampling instruction;

Otherwise, according to the preset second sampling instruction, a data read operation is performed under the delay processing of the clock signal corresponding to the transmission mode type to obtain a read result of the data read operation related to the second sampling instruction.

Optionally, the data reading operation is reading data stored in the second memory;

The determining of the transmission mode type for performing multiple data read operations includes:

When determining to read the data stored in the second memory, the transmission mode type is determined to be a third transmission mode.

Optionally, when determining that the transmission mode type is the third transmission mode, determining that a clock signal corresponding to the third transmission mode is an initial clock signal, the initial clock signal is an acquired original clock signal;

The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes:

The initial clock signal is delayed multiple times according to the delay time lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay time length corresponding to a delay code to perform a delay process on the initial clock signal, and the delay time lengths corresponding to the different delay codes are different.

Optionally, after performing a data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation includes:

For any data read operation,

Determining whether sending a preset third sampling instruction is supported when reading data stored in the second memory in a third transmission mode;

If supported, performing a data read operation under the delay processing of the initial clock signal according to the preset third sampling instruction to obtain a read result of the data read operation related to the third sampling instruction;

Otherwise, according to the preset fourth sampling instruction, a data read operation is performed under the delay processing of the initial clock signal to obtain a read result of the data read operation related to the fourth sampling instruction.

Optionally, recording the identifier of the delay code used in each data read operation according to the read result corresponding to each data read operation includes:

For any data read operation, when it is determined that the read result is the same as the preset read result, the delay code used to perform the data read operation is recorded as the zeroth identifier, and when it is determined that the read result is different from the preset read result, the delay code used to perform the data read operation is recorded as the first identifier.

Optionally, the using the target delay code to perform the data processing operation includes:

According to the delay duration corresponding to the target delay code, a clock signal corresponding to the transmission mode type is delayed to perform a data read operation.

Accordingly, the present disclosure also provides a data transmission device, including:

The first processing unit is configured to execute multiple data processing operations, and based on the execution results of each data processing operation, record the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to execute; and according to the identifier selection signal, the delay code corresponding to the selected zeroth identifier is used as the target delay code to execute the data processing operation;

The second processing unit is configured to select a zeroth identifier from the multiple consecutive zeroth identifiers when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, and generate a corresponding identifier selection signal, wherein the identifier selection signal includes a delay code corresponding to the selected zeroth identifier.

Optionally, the data processing operation includes a data write operation;

The first processing unit comprises:

A first delay module is configured to perform multiple delay processing on the clock signal according to the delay durations corresponding to the multiple delay codes, wherein one data write operation uses a delay duration corresponding to one delay code to perform one delay processing on the clock signal, and the delay durations corresponding to the different delay codes are different;

The first processing module is configured to obtain verification information corresponding to each data write operation after executing the data write operation under each delay processing of the clock signal, and the verification information is used to determine whether the data write operation can be successfully executed; and according to the verification information corresponding to each data write operation, record the identifier of the delay code used for each data write operation.

Optionally, the first delay module includes: a plurality of first delay devices, a first logic operator and a first selector, wherein:

A plurality of the first delay devices are connected in sequence, wherein a first end of a first delay device among the plurality of the first delay devices is suitable for inputting a clock signal, an output end of a last first delay device among the plurality of the first delay devices is connected to a first end of the first logic operator, and a second end of each first delay device among the plurality of the first delay devices is connected to a second end of the first selector;

The first end of the first selector is adapted to input a first control signal, and generate a corresponding first selection signal according to the first control signal, wherein the first selection signal is used to control the number of first delay devices with a delay function enabled when selecting to perform a data write operation;

The second end of the first logic operator is suitable for inputting a second control signal, and the output end thereof is suitable for outputting a clock signal after delay processing to the first processing module, wherein the second control signal is used to control the output timing of the clock signal after delay processing.

Optionally, the delay durations corresponding to the first delay devices are the same.

Optionally, the first processing unit further includes: a mode selection module, coupled to the first delay module, and configured to control a working state of the first delay module in response to a mode selection signal.

Optionally, the data processing operation includes a data read operation;

The first processing unit comprises:

a second processing module, configured to determine a transmission mode type for performing multiple data read operations; and after performing a data read operation under each delay processing of a clock signal corresponding to the transmission mode type, obtain a reading result corresponding to each data read operation, wherein the reading result is used to determine whether the data read operation is successfully performed when in the transmission mode type, and record an identifier of a delay code used for each data read operation according to the reading result corresponding to each data read operation;

The second delay module performs multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay length corresponding to a delay code to perform a delay processing on the clock signal corresponding to the transmission mode type, and the delay lengths corresponding to the delay codes are different.

Optionally, the second delay module includes a plurality of second delay devices, a second logic operator and a second selector, wherein:

A plurality of second delay devices are connected in sequence, wherein a first end of a first second delay device among the plurality of second delay devices is suitable for inputting a clock signal corresponding to the transmission mode type, an output end of a last second delay device among the plurality of second delay devices is connected to a first end of the second logic operator, and a second end of each second delay device among the plurality of second delay devices is connected to a second end of the second selector;

The first end of the second selector is adapted to input a third control signal, and generate a corresponding second selection signal according to the third control signal, wherein the second selection signal is used to control the number of second delay devices with a delay function enabled when selecting to perform a data read operation;

The second end of the second logic operator is suitable for inputting a fourth control signal, and the output end thereof is suitable for outputting a clock signal corresponding to the transmission mode type after delay processing to the second processing module, wherein the fourth control signal is used to control the output timing of the clock signal corresponding to the transmission mode type after delay processing.

The present disclosure also provides a host, comprising: at least one processor and at least one memory, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the data transmission method as described in any of the aforementioned examples.

The present disclosure also provides a host storage medium, wherein the storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the data transmission method as described in any of the above examples is implemented.

By adopting the data transmission scheme provided by the present disclosure, based on the execution results of each data processing operation, it is possible to record that when the data processing operation is successfully executed, the delay code used for the identification is an available zeroth identification, and when the data processing operation fails to be executed, the delay code used for the identification is an unavailable first identification, and then when it is determined that there are multiple continuous zeroth identifications in the recorded identifications, the zeroth identification can be selected from them, and the delay code corresponding to the selected zeroth identification is used as the target delay code, and then based on the target delay code, the data processing operation can be executed. Since the target delay code is determined from multiple continuous and available zeroth identifications, that is, the target delay code is determined from the delay codes used for multiple consecutively executed data processing operations, wherein the zeroth identification is used to identify the delay code used and identify it as available when the data processing operation is successfully executed, even if the target delay code is affected by environmental factors and causes the target delay code to change, the target delay code is still available, thereby improving the stability of the data processing process.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

FIG1 shows a schematic diagram of a principle of data sampling;

FIG2 shows another schematic diagram of the principle of data sampling;

FIG3 shows a flow chart of a data transmission method in an example of the present disclosure;

FIG4 shows a flow chart for determining a target delay code in an example of the present disclosure;

FIG5 shows a flow chart for determining a target delay code in an application scenario in an example of the present disclosure;

FIG6 shows a schematic diagram of a process for determining a target delay code in an example of the present disclosure;

FIG7 shows a flow chart of an identification of a delay code used for recording a data write operation in an example of the present disclosure;

FIG8 shows a flow chart for determining a target delay code for a data write operation in an application scenario in an example of the present disclosure;

FIG9 shows a flow chart of an identification of a delay code used for recording a data read operation in an example of the present disclosure;

FIG10 shows a flow chart for obtaining a read result corresponding to a data read operation in an example of the present disclosure;

FIG11 shows a flow chart for determining a target delay code for a data read operation in an application scenario in an example of the present disclosure;

FIG12 shows another flowchart for obtaining a read result corresponding to a data read operation in an example of the present disclosure;

FIG13 shows a flow chart for determining a target delay code for a data read operation in another application scenario in the present disclosure;

FIG14 shows a schematic structural diagram of a data transmission device in an example of the present disclosure;

FIG. 15 shows a schematic diagram of a specific structure of a first processing unit in an example of the present disclosure.

DETAILED DESCRIPTION

As described in the background art, when the working environment changes (such as temperature increase, slight change in working voltage), the clock signal will be affected, which may make it impossible to sample the data signal.

In order to enable those skilled in the art to better understand the existing solution, an example is provided below in combination with a data processing scenario.

Referring to a schematic diagram of a data sampling principle shown in FIG. 1 , as shown in FIG. 1 , a waveform diagram corresponding to a Clock (clock signal) and a waveform diagram corresponding to a Data (data signal) varying with time are respectively shown.

As shown in FIG1 , when the Clock jumps from a low level to a high level, the Data can be sampled to obtain a sampling result.

For example, at time t2, Clock jumps from low level to high level, and Data is at high level at this time, so the corresponding valid data can be obtained; at time t4, Clock jumps from low level to high level, and Data is at low level at this time, so the obtained data is invalid data.

In the actual data sampling process, as the temperature changes or other environmental factors affect, the waveform of the Clock will change, making it impossible to sample the Data when the Clock jumps from a low level to a high level.

As an example, referring to another schematic diagram of data sampling principle shown in FIG2 , as shown in FIG2 , affected by environmental factors, the waveform of the Clock changes, for example, the moments when the Clock and Data jump from a low level to a high level are the same.

However, at the moments t1, t2, t3, t4 and t5 shown in FIG2 , Data is in a low level and high level transition state, and it is not possible to determine whether Data is in a low level or a high level, and thus the sampling result cannot be obtained according to Clock.

In order to solve the above technical problems, the present disclosure provides a data transmission scheme, which can record, based on the execution results of each data processing operation, the zeroth identifier that indicates that the delay code used is available when the data processing operation is successfully executed, and the first identifier that indicates that the delay code used is unavailable when the data processing operation fails to be executed. When it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, the zeroth identifier can be selected from them, and the delay code corresponding to the selected zeroth identifier can be used as the target delay code. Based on the target delay code, the data processing operation can be executed.

With the above scheme, the target delay code is determined from a plurality of consecutive and available zeroth identifiers, that is, the target delay code is determined from the delay codes used for a plurality of consecutively successfully executed data processing operations, wherein the zeroth identifier is used to identify the delay code used and mark it as available when the data processing operation is successfully executed, and even if the target delay code changes due to environmental factors, the target delay code is still available, thereby improving the stability of the data processing process.

In order to enable those skilled in the art to better understand the inventive concept, working principle and advantages of the examples of the present disclosure, the data transmission scheme in the embodiments of the present disclosure is described as an example below.

Referring to the flowchart of a data transmission method in an example of the present disclosure shown in FIG3 , in some examples, as shown in FIG3 , the following steps may be performed:

S11, executing multiple data processing operations, and based on the execution results of each data processing operation, recording the identifier of the delay code used in each data processing operation.

Specifically, in the process of executing data processing operations, delay processing can be performed by using delay codes, and then the execution results of each data processing operation after delay processing can be obtained. According to the obtained execution results, the identifier of the delay code used for each data processing operation can be determined.

In some examples, the identifier of the delay code used for each data processing operation may be determined based on whether the data processing operation is successfully executed.

For example, the identifier may include a zeroth identifier that identifies the delay code used by the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used by the data processing operation as unavailable when the data processing operation fails to execute.

Among them, "success" in the example of the present disclosure may refer to executing a data processing operation and being able to obtain an execution result that is the same as the set result; "failure" in the example of the present disclosure may refer to executing a data processing operation and being unable to obtain an execution result, or the obtained execution result is different from the set result.

In some optional examples, the data processing operation may include a data write operation and a data read operation, wherein the data write operation may refer to writing data to a memory with a storage function, and the data read operation may refer to reading data from a memory with a storage function.

In some optional examples, when performing data processing operations, the delay durations corresponding to the delay codes are different.

S12, when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, select the zeroth identifier from the multiple consecutive zeroth identifiers, and use the delay code corresponding to the selected zeroth identifier as the target delay code.

Specifically, the zeroth identifier can indicate that the delay code used in any data processing operation is available. When there are multiple consecutive zeroth identifiers, it means that within this continuous interval, the delay code corresponding to the zeroth identifier is less affected by environmental factors (for example, temperature, interference signals, voltage fluctuations, etc.). Even if the environmental factors change, the data processing operation can still be executed successfully. Therefore, when the delay code corresponding to one of the multiple consecutive zeroth identifiers is used as the target delay code, the stability of the target delay code can be improved.

In some optional examples, when it is determined that there are multiple consecutive zeroth identifiers, the delay code corresponding to the zeroth identifier at a preset position may be used as the target delay code.

As an example, the preset position may refer to the middle position of a plurality of consecutive intervals corresponding to the zeroth markers.

S13, using the target delay code, executing the data processing operation.

Specifically, by adopting steps S11 and S12, a target delay code that is less affected by environmental factors can be obtained, and then the target delay code can be used to perform subsequent data processing operations to improve the stability of the data processing process.

In some optional examples, a target delay code may be used to perform subsequent data write operations.

In some optional examples, a target delay code may be used to perform subsequent data read operations.

Using the data transmission method in the above example, since the target delay code is determined from multiple consecutive and available zeroth identifiers, and the zeroth identifier can indicate that the delay code used by any data processing operation is available, even if it is affected by environmental factors and causes the target delay code to change, the change in the target delay code is small and the target delay code is still available, thereby improving the stability of the data processing process.

In order to enable those skilled in the art to better understand and implement the data transmission scheme in the examples of the present disclosure, the following description is made with reference to the accompanying drawings and by way of examples.

In some embodiments, after recording the zeroth identifier used to identify the delay code used for the data processing operation as available and the first identifier used to identify the delay code used for the data processing operation as unavailable based on whether the data processing operation is executed successfully, a variety of methods can be used to use the delay code corresponding to at least one of the zeroth identifiers as the target delay code.

In some examples, when executing each data processing operation, the delay code used is different, and then when determining that the data processing operation is successfully executed, the delay code corresponding to the zeroth identifier recorded is different. The target delay code is determined by the delay code corresponding to the zeroth identifier, so the order of executing the data processing operation affects the position of the zeroth identifier in the recorded identifier, and thus affects the selection accuracy of the target delay code.

As an optional example, the zeroth identifier and the first identifier may be recorded according to the order in which the data processing operation is performed.

For example, the zeroth identifier and the first identifier of the record may be sorted according to the order in which each data processing operation is performed to obtain an identifier sequence list.

By following the order of each data processing operation, an identifier sequence table with the zeroth identifier and the first identifier arranged in sequence can be obtained, thereby improving the consistency between the data processing operation order and the identifier, and further improving the accuracy of the obtained target delay code.

In this application scenario, as an example, referring to a flowchart for determining a target delay code in an example of the present disclosure shown in FIG. 4 , in some examples, as shown in FIG. 4 , the following steps may be performed:

S21, determining an area in the identifier sequence table where there are continuous zeroth identifiers.

Specifically, when each data processing operation is executed, an identifier corresponding to the execution result is generated, and multiple identifiers can be obtained when multiple data processing operations are executed. When the zeroth identifier and the first identifier are sorted according to the order of each data processing operation, the area in the identifier sequence table where the zeroth identifier exists can be determined by judging whether there are multiple consecutive zeroth identifiers.

S22, selecting the zeroth marker from the determined area, and recording the selected zeroth marker in sequence to obtain a corresponding selection window.

Specifically, when it is determined that there is an area with continuous zeroth identifiers in the identifier sequence list, all zeroth identifiers in this area can be extracted, and the zeroth identifiers can be recorded in sequence according to the position of each zeroth identifier in the identifier sequence list, so that a selection window including the zeroth identifiers arranged in sequence can be obtained.

S23, using the delay code corresponding to the zeroth marker located at the preset position of the selection window as the target delay code when executing each data processing operation.

Specifically, by adopting steps S21 and S22, a selection window including the zeroth identifier can be obtained, so that the identifier code corresponding to the zeroth identifier located at a preset position of the selection window can be used as the target delay code.

In some examples, the zeroth marker of the preset position of the selection window may refer to the zeroth marker of the middle position of the selection window.

In some other examples, the zeroth marker at a preset position of the window may be selected as the zeroth marker at any position of the window, and the examples disclosed herein are not limited to this.

By adopting the scheme of the above example, by using the delay code corresponding to the zeroth identifier located at the preset position of the selection window as the target delay code when executing each data processing operation, when environmental factors change, even if the delay code corresponding to the zeroth identifier changes (for example, the delay duration corresponding to the delay code increases or decreases), the delay duration of the delay code corresponding to the changed zeroth identifier is still within the selection window. When using the target delay code corresponding to the selected zeroth identifier, the data processing operation can be successfully executed, further improving the stability of the data processing process.

It should be noted that, in some examples, if there is no zeroth identifier in the identifier sequence table, the device performing the data processing operation or the connection line between the devices can be checked, or the data processing operation can be performed here by reducing the data transmission frequency for performing the data processing operation.

In some embodiments, after performing multiple data processing operations and in the manner shown in FIG. 4 , there may be only one selection window or multiple selection windows formed. Therefore, according to the number of selection windows, different methods can be used to use the delay code corresponding to at least one of the zeroth identifiers as the target delay code.

For example, when a selection window is obtained, the delay code with the zeroth mark located at a preset position (eg, the middle position) of the selection window can be directly used as the target delay code.

When there are multiple selection windows, the target identification code can be selected from the selection window containing the largest number of zeroth identifications.

As an example, referring to the flowchart for determining the target delay code in an application scenario in the example of the present disclosure shown in FIG5 , as shown in FIG5 , the following steps may be included:

S31, selecting a selected window containing the largest number of zeroth identifiers from the multiple selected windows as a target window.

Specifically, the more zeroth identifiers included in the selection window, the less the delay code corresponding to the zeroth identifier in the selection window is affected by environmental factors, and the delay codes corresponding to each zeroth identifier have a larger variation margin. Even if the delay code corresponding to the zeroth identifier changes due to changes in environmental factors (for example, the delay duration corresponding to the delay code increases or decreases), the data processing operation can still be successfully performed when it is used as the target delay code.

S32, taking the delay code corresponding to the zeroth marker located at the preset position of the target window as the target delay code.

In some examples, the delay code corresponding to the zeroth marker located in the middle of the target window may be used as the target delay code.

By using the delay code with the zeroth marker located at the center of the target window as the target delay code, the target delay code has a larger variation margin, which can further improve the stability in the data processing process.

It should be noted that when there are an even number of zeroth identifiers in the target window, the delay code corresponding to any first identifier in the middle position can be used as the target delay code. For example, the delay code corresponding to the first first identifier in the middle position can be used as the target delay code.

In some examples, the delay code corresponding to the zeroth marker located at any position in the target window may be used as the target delay code.

To facilitate understanding of the process of obtaining the target delay code by selecting a window, an example is provided below.

Refer to the schematic diagram of a process for determining the target delay code shown in Figure 6. As shown in Figure 6, the identification sequence table formed according to the order of executing 64 data processing operations is schematically illustrated: 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0.

By judging that there is at least continuous zeroth identifier in the identifier sequence table, and according to the order of executing the data processing operations, 5 selection windows can be obtained, namely: [0, 0, 0], [0, 0, 0, 0, 0, 0, 0, 0, 0], [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], [0], [0, 0, 0, 0].

By comparing the number of zeroth identifiers contained in these five selection windows, we can obtain the target window: [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0], and the target window can include 25 zeroth identifiers “0”, so the delay code corresponding to the zeroth identifier “0” of the 13th bit of the target window (i.e., the zeroth identifier “0” indicated by the dotted box in Figure 6) can be used as the target delay code.

It should be noted that, first, the number of zeroth identifiers and first identifiers contained in the identifier sequence table shown in Figure 6 is for example description and can be determined according to the data processing operation performed; second, the symbols of the zeroth identifier "0" and the first identifier "1" are for example description, which are used to illustrate that different symbols can be used to identify the execution results, and cannot be understood as a limitation on the present invention. For example, the symbol "A" can be used to represent the zeroth identifier and the symbol "B" can be used to represent the first identifier, and the present disclosure does not impose any restrictions on this; third, the expression forms of the identifier sequence table, the selection window and the target window are also for example description, which are only used to illustrate that the scheme in the example of the present disclosure can record the zeroth identifier and the first identifier, and cannot be understood as a limitation on the present invention.

In some examples of the present disclosure, the selection window containing the largest number of zeroth identifiers is used as the target window for selecting the target delay code. The number of zeroth identifiers directly affects the target delay code finally selected, and the number of zeroth identifiers is related to the number of times the data processing operation is performed. Therefore, before the step of determining the area where at least continuous zeroth identifiers exist, it can also be determined whether the total number of zeroth identifiers and first identifiers contained in the identifier sequence table is the same as the number of times the data processing operation is performed.

For example, when it is determined that the total number of zeroth identifiers and first identifiers included in the identifier sequence list is the same as the number of times the data processing operation is performed, the step of determining a region in the identifier sequence list where at least continuous zeroth identifiers exist is performed.

For another example, when it is determined that the total number of the zeroth identifier and the first identifier included in the identifier sequence table is different from the number of times the data processing operation is performed, the identifier of the delay code used for the subsequent data processing operation continues to be recorded.

By determining that the total number of zeroth identifiers and first identifiers contained in the identifier sequence table is the same as the number of times the data processing operation is performed, an area in the identifier sequence table in which at least continuous zeroth identifiers exist can be determined. This can record the identifiers corresponding to all the data processing operations performed, thereby improving the accuracy of the zeroth identifier contained in each selection window and the accuracy of the target delay code obtained.

In other examples, after recording the zeroth identifier for identifying the delay code used for data processing operations as available and the first identifier for identifying the delay code used for data processing operations as unavailable, the delay code corresponding to any one of the zeroth identifier codes can be selected as the target delay code, and the examples disclosed herein do not limit the method for obtaining the target delay code.

In some examples of the present disclosure, based on the data transmission direction, the data processing operation can be divided into a data write operation and a data read operation. When determining the type of the data processing operation, the scheme in the above example can be used to obtain the identification sequence table and the target delay code corresponding to the data write operation, and the identification sequence table and the target delay code corresponding to the data read operation.

As an optional example, the data processing operation may include a data writing operation.

In this case, the identifier sequence table may include the zeroth identifier corresponding to when the data read operation is successfully executed, and the first identifier corresponding to when the data write operation fails to execute.

The delay code corresponding to the zeroth marker located at the preset position of the selection window can be used as the target delay code when executing each data write operation.

As an optional example, the data processing operation may include a data read operation.

In this case, the identifier sequence table may include a zeroth identifier corresponding to when the data read operation is successfully executed, and a first identifier corresponding to when the data read and write operation fails to be executed.

The delay code corresponding to the zeroth marker located at the preset position of the selection window can be used as the target delay code when executing each data read operation.

In some examples of the present disclosure, different schemes may be used to record the identifier of the delay code used for each data processing operation based on the type of data processing operation.

As an example, a data processing operation may include a data write operation.

Accordingly, referring to a flowchart of an example of the present disclosure for recording an identification of a delay code used in a data write operation as shown in FIG. 7 , as shown in FIG. 7 , the following steps may be performed:

S41, performing multiple delay processing on the clock signal according to the delay durations corresponding to the multiple delay codes.

In some examples, a data write operation uses a delay time length corresponding to a delay code to perform a delay process on the clock signal, that is, the number of times the data write operation is performed may be the same as the number of times the clock signal is delayed.

In some examples, the delay lengths corresponding to the delay codes may be different, so as to perform delay processing of different lengths on each data write operation.

In some optional examples, the number of devices with delay functions connected to the clock signal transmission path can be adjusted so that each data write operation has a different delay length.

S42, after executing the data write operation under each delay processing of the clock signal, obtaining verification information corresponding to each data write operation.

Specifically, after the clock signal is delayed, a data write operation can be performed to write the data into a memory with a storage function, and verification information for determining whether the data write operation can be successfully performed can be obtained.

In some examples, for different types of memories, the type of verification information obtained may be the same.

For example, when the memory is an embedded multimedia controller eMMC or a secure digital card SD, the check information corresponding to each data write operation may be cyclic redundancy check (CRC) information.

In some examples, the type of verification information obtained may be different for different types of memories.

It should be noted that the type of verification information described in the above scheme is for illustrative purposes only, and is used to indicate that when performing input write operations on different types of memories, corresponding verification information can be used for verification to determine whether the data write operation is successful, and it should not be understood as a limitation on the present invention.

S43, recording the identifier of the delay code used in each data writing operation according to the verification information corresponding to each data writing operation.

Specifically, the execution result of each data write operation (for example, the data write operation is executed successfully, or the data write operation is executed unsuccessfully) can be determined according to the verification information corresponding to each data write operation, and then the identifier of the delay code used for each data write operation can be determined.

For example, when it is determined that the data write operation is successful based on the verification information corresponding to each data write operation, the identifier of the delay code used for the data write operation can be recorded as the zeroth identifier "0"; or when it is determined that the data write operation fails based on the verification information corresponding to each data write operation, the identifier of the delay code used for the data write operation can be recorded as the first identifier "1".

By using a delay time corresponding to a delay code to delay the clock signal for a data write operation, and making the delay time corresponding to each delay code different, the actual environment of the data write operation can be simulated more realistically, and the accuracy of the verification information corresponding to each data write operation obtained can be improved.

In some examples, the identifier of the delay code used in each data write operation may be determined and recorded according to the relative relationship between the verification information corresponding to the data write operation and the preset verification information.

For example, for any data writing operation, when it is determined that the verification information corresponding to the data writing operation is the same as the preset verification information, the identifier of the delay code used for the data writing operation is recorded as the zeroth identifier "0".

For another example, for any data write operation, when it is determined that the verification information corresponding to the data write operation is different from the preset verification information, the identifier of the delay code used for the data write operation is recorded as the first identifier "1".

In some examples, the preset verification information may be determined according to the communication protocol of each type of memory.

For example, when the memory is an embedded multimedia controller eMMC, the preset verification information can be "010". When the verification information corresponding to the data write operation after parsing is "010", the identifier of the delay code used for the data write operation is recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used for the data write operation is recorded as the first identifier "1".

For example, when the memory is a secure digital card SD, the preset verification information can be "010". When the verification information corresponding to the data write operation after parsing is "010", the identifier of the delay code used for the data write operation is recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used for the data write operation is recorded as the first identifier "1".

By adopting the relative relationship between the verification information corresponding to the data writing operation and the preset verification information, the process of determining and recording the delay code identification used for each data writing operation can be carried out without manual processing, thereby improving the efficiency and accuracy of recording the delay code identification.

By adopting the above scheme, the recorded zeroth identifier and the first identifier can be sorted according to the order of executing each data write operation, and then the selection window containing only the zeroth identifier can be determined. According to the number of zeroth identifiers contained in the selection window, the target window for selecting the target delay code can be determined, and the delay code corresponding to the zeroth identifier located at the preset position of the target window is used as the target delay code, and then the clock signal can be delayed according to the delay time length corresponding to the target delay code to perform the data write operation.

In some examples, when the identifiers of the delay codes used for each data write operation are recorded, an available identifier may be selected as a target delay code for executing the data write operation.

As an example, the following steps may be performed to determine a target delay code for performing a data write operation.

A1) According to the sequence of each data writing operation, a write mark sequence table having a zeroth mark and a first mark arranged in sequence is obtained.

A2) Determine an area in the write mark sequence table where at least a continuous zeroth mark exists.

A3) Select the zeroth marker from the determined area, and record the zeroth marker in sequence to obtain the corresponding selection window.

A4) The delay code corresponding to the zeroth mark located at the preset position of the selection window is used as the target delay code when executing each data writing operation.

In some examples, when executing step A3) to obtain multiple selection windows, A4) may include:

A41) Selecting the selection window with the largest number of zero-th identifiers from multiple selection windows as the target window.

A42) The delay code corresponding to the zeroth mark located at the preset position of the target window is used as the target delay code.

In some examples, the delay code corresponding to the zeroth marker located in the middle of the target window may be used as the target delay code.

In some optional examples, before executing step A2), it can also be determined whether the total number of the zeroth identifier and the first identifier contained in the write identifier sequence table is the same as the number of data write operations performed, and when it is determined that the total number of the zeroth identifier and the first identifier contained in the write identifier sequence table is the same as the number of data write operations performed, step A2 is executed); otherwise, continue to record the identifier of the delay code used for subsequent data write operations.

By adopting the above method, the target delay code corresponding to the data write operation can be obtained, and then the data write operation can be performed according to the delay duration corresponding to the target delay code.

To facilitate understanding and implementation of the solution for determining the target delay code used for a data write operation, the following is an explanation by way of examples with reference to the accompanying drawings.

Referring to the flowchart for determining the target delay code for a data write operation in an application scenario in an example of the present disclosure shown in FIG8 , as shown in FIG8 , the following steps may be performed:

S51, performing multiple delay processing on the clock signal according to the delay durations corresponding to the multiple delay codes.

S52, after executing the data write operation under each delay processing of the clock signal, obtaining verification information corresponding to each data write operation.

S53, whether the verification information corresponding to the data write operation is the same as the set verification information, if so, execute step S54; if not, execute step S55.

S54, recording the identifier of the delay code used in the data write operation as the available zeroth identifier.

S55, recording the identifier of the delay code used in the data write operation as an unavailable first identifier.

S56, sorting the zeroth identifier and the first identifier of the record according to the order of executing each data write operation to obtain a write identifier sequence table.

S57, whether the total number of identifiers written into the identifier sequence table is the same as the number of times the data write operation is performed, if so, execute step S58; if not, continue to execute step S52.

The total number of identifiers includes the number of first identifiers and zeroth identifiers.

S58, determining an area in the write mark sequence table where there are continuous zeroth marks.

S59, selecting the zeroth marker from the determined area, and recording the selected zeroth marker in sequence to obtain a corresponding selection window.

S60, selecting a selection window containing the largest number of zeroth identifiers as a target window.

S61, the delay code corresponding to the zeroth mark in the middle of the target window is used as the target delay code.

S62, delaying the clock signal according to the delay duration corresponding to the target delay code to perform a subsequent data write operation.

The specific implementation of steps S51 to S62 may refer to the above examples.

It should be noted that the above example is based on a case where multiple selection windows are provided. If only one selection window is included, the delay code corresponding to the zeroth marker in the middle of the selection window can be directly used as the target delay code.

By adopting the scheme in the above example, a target delay code for performing subsequent data write operations can be selected so that data can be stably written into a memory with storage function, for example, writing input into a first memory and a second memory.

In some examples, when the data processing operation includes a data read operation, during the data read operation, different operations may be performed when determining the corresponding target delay code for memories of different types or different communication protocols.

As an example, referring to a flowchart of an example of the present disclosure for recording an identification of a delay code used in a data read operation as shown in FIG. 9 , as shown in FIG. 9 , the following steps may be performed:

S71, determining a transmission mode type for performing multiple data read operations.

Specifically, when performing data read operations on different types of memories, different types of transmission modes may be used. Therefore, it is necessary to determine the transmission mode type for each data read operation to determine a processing solution that is compatible with the transmission mode type.

In some examples, the type of memory that performs the current data read operation can be determined based on the feedback of the memory to the operation command when the enumeration process is executed.

S72, performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes.

Specifically, when performing a data read operation, the clock signal for performing delay processing is different depending on the type of transmission mode. Therefore, the clock signal for performing delay processing may be determined according to the type of transmission mode.

In some examples, a data read operation uses a delay duration corresponding to a delay code to perform a delay processing on a clock signal corresponding to the transmission mode type, that is, the number of data read operations performed is the same as the number of times the clock signal corresponding to the transmission mode type is delayed.

In some examples, the delay lengths corresponding to the delay codes may be different, so as to perform delay processing of different lengths on each data read operation.

In some optional examples, the number of devices with delay function on the access signal transmission path can be adjusted so that each data read operation has a different delay length.

S73, after performing data read operations under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation.

Specifically, after delaying the clock signal corresponding to the transmission mode type, a data read operation can be performed to read data from a memory with a storage function, and a reading result can be obtained to determine whether the data read operation is successfully executed when in the current transmission mode type.

In some examples, for different types of memories, different types of read results are obtained.

For example, when the memory is an embedded multimedia controller eMMC, the reading result corresponding to each data read operation may be a tuning pattern specified by a protocol related to the eMMC; or the reading result may be a value stored in a register (eg, register EXT_CSD) in the multimedia controller eMMC.

For example, when the memory is a secure digital card SD, the reading result corresponding to each data read operation may be a tuning sequence specified by a protocol related to the secure digital card SD; or may be a value stored in a register (eg, register CID) in the secure digital card SD.

It should be noted that, first, the type of reading result described in the above scheme is for illustrative purposes only, and is used to indicate that when performing an input read operation on different types of memories, the corresponding reading results can be used for verification to determine whether the data read operation is successful, and it should not be understood as a limitation on the present invention; second, for different types of memories, when performing a data read operation, the specific content of the corresponding tuning sequence is different, and the specific content of the tuning sequence is determined according to the specific protocol.

S74, recording the identifier of the delay code used in each data read operation according to the read result corresponding to each data read operation.

Specifically, the execution result of each data read operation (for example, the data read operation is executed successfully, or the data read operation is executed failed) can be determined according to the reading result corresponding to each data read operation, and then the identifier of the delay code used for each data read operation can be determined.

For example, when it is determined that the data read operation is successful based on the reading results corresponding to each data read operation, the identifier of the delay code used for the data read operation can be recorded as the zeroth identifier "0"; or when it is determined that the data read operation fails based on the verification information corresponding to each data read operation, the identifier of the delay code used for the data read operation can be recorded as the first identifier "1".

By making a data read operation use a delay time corresponding to a delay code to perform a delay processing on the clock signal corresponding to the transmission mode type, and making the delay time corresponding to each delay code different, it is possible to more realistically simulate the actual environment of the data read operation, improve the accuracy of the reading results corresponding to each data read operation, and thereby improve the accuracy of the identification of the delay code used in each data read operation.

In some implementations, the type of transmission mode for performing each data read operation may be determined according to the type of memory that performs the data read operation.

As an example, the data read operation may include reading data stored in the first memory.

In this application scenario, the type of transmission mode for performing the data read operation may be determined according to the data transmission rate of reading the data stored in the first memory.

As an example, when a data transmission rate of reading data stored in the first memory is the same as a set rate, the transmission mode type is determined to be the first transmission mode.

When the data transmission rate of reading the data stored in the first memory is different from the set rate, the transmission mode type is determined to be the second transmission mode.

For example, if the first memory is an embedded multimedia controller eMMC, when it is determined that the data transmission rate when performing a data read operation is 400MB/s, the transmission mode type can be determined to be the first transmission mode HS400; when it is determined that the data transmission rate when performing a data read operation is not 400MB/s, the transmission mode type can be determined to be the second transmission mode, for example, HS200.

In some examples, when the specific type of the transmission mode is determined, a clock signal for delay processing can be determined, and then a delay processing operation can be performed.

As an example, when the transmission mode type is determined to be the first transmission mode, it is determined that the signal corresponding to the first transmission mode is a synchronous clock signal, wherein the synchronous clock signal may come from a party providing read data.

For example, if the first transmission mode is HS400, the synchronization clock signal may be a data latch signal (Data Strobe, DS) from an embedded multimedia controller eMMC.

Correspondingly, executing the delay processing may include: performing multiple delay processing on the synchronous clock signal according to the delay durations corresponding to the multiple delay codes.

In some examples, a data read operation uses a delay time corresponding to a delay code to perform a delay process on the synchronous clock signal, that is, the number of times the data read operation is performed is the same as the number of times the synchronous clock signal is delayed.

In some examples, the delay durations corresponding to the delay codes may be different, so as to perform delay processing of different durations on the synchronous clock signal used in each data read operation.

As an example, when it is determined that the transmission mode type is the second transmission mode, it is determined that the signal corresponding to the second transmission mode is an initial clock signal, wherein the initial clock signal may be an acquired original clock signal.

For example, if the second transmission mode is HS200, the initial clock signal may be an original clock signal obtained when a write operation is performed on the embedded multimedia controller eMMC.

Correspondingly, executing the delay processing may include: performing multiple delay processing on the initial clock signal according to the delay durations corresponding to the multiple delay codes.

In some examples, a data read operation uses a delay time corresponding to a delay code to perform a delay process on the initial clock signal, that is, the number of times the data read operation is performed is the same as the number of times the delay process is performed on the initial clock signal.

In some examples, the delay lengths corresponding to the delay codes may be different, so as to perform delay processing of different lengths on the initial clock signal used in each data read operation.

In some implementations, after performing a delay process on a clock signal corresponding to the transmission mode type, a data read operation may be performed.

In some examples, during the process of executing the data read operation, different sampling instructions may be used to obtain the read result corresponding to the data read operation.

As an example, referring to a flowchart for obtaining a read result corresponding to a data read operation in an example of the present disclosure shown in FIG. 10 , in some examples, as shown in FIG. 10 , the following steps may be performed:

S81, for any data read operation, determine whether sending a preset first sampling instruction is supported when reading the data stored in the first memory, if so (if supported), execute step S82; otherwise, execute S83.

Specifically, in different transmission modes, different reading methods can be used to read the data stored in the first memory. Therefore, when performing any data reading operation, it can be determined whether the data stored in the first memory can be read through the preset first sampling instruction in the first transmission mode or the second transmission mode.

S82, according to a preset first sampling instruction, performing a data read operation under a delay processing of a clock signal corresponding to the transmission mode type to obtain a read result of the data read operation related to the first sampling instruction;

Specifically, when it is determined that the first transmission mode is in place and the data stored in the first memory can be read according to the preset first sampling instruction, the preset first sampling instruction can be sent to the first memory, and then after delaying the synchronous clock signal, the data stored in the first memory can be read according to the preset first sampling instruction, thereby obtaining the reading result of the data read operation related to the first sampling instruction.

When it is determined that the second transmission mode is in place and the data stored in the first memory can be read according to the preset first sampling instruction, the preset first sampling instruction can be sent to the first memory, and then after delaying the initial clock signal, the data stored in the first memory can be read according to the preset first sampling instruction, thereby obtaining the reading result of the data read operation related to the first sampling instruction.

S83, according to the preset second sampling instruction, executing a data read operation under the delay processing of the clock signal corresponding to the transmission mode type to obtain a reading result of the data read operation related to the second sampling instruction.

Specifically, when it is determined that the first transmission mode is in place and the data stored in the first memory cannot be read according to the preset first sampling instruction, a preset second sampling instruction can be sent to the first memory, and then after delaying the synchronous clock signal, the data stored in the first memory can be read according to the preset second sampling instruction, thereby obtaining the reading result of the data read operation related to the second sampling instruction.

When it is determined that the second transmission mode is in effect and the data stored in the first memory cannot be read according to the preset first sampling instruction, a preset second sampling instruction can be sent to the first memory, and then after delaying the initial clock signal, the data stored in the first memory can be read according to the preset second sampling instruction, thereby obtaining a read result of the data read operation related to the second sampling instruction.

In some examples, the types of the first sampling instruction and the second sampling instruction may be determined according to the type of the memory.

For example, if the memory includes an embedded multimedia controller eMMC, the first sampling instruction may be CMD21, and the second sampling instruction may be other general data read instructions, such as CMD8.

By adopting the above judgment process, when any data read operation is in the first transmission mode or the second transmission mode, different sampling instructions (such as the first sampling instruction and the second sampling instruction) can be used to obtain the reading result of the data read operation related to the sampling instruction, thereby being applicable to different transmission scenarios and improving the universality of the data read operation.

In some examples, after determining the transmission mode type and obtaining the read result of the data read operation related to the first sampling instruction or the read result of the data read operation related to the second sampling instruction according to the preset first sampling instruction or the second sampling instruction, the read result can be compared with the preset read result to determine the specific identifier of the delay code used for each data read operation.

In some examples, the identifier of the delay code used in each data read operation may be determined and recorded according to the relative relationship between the read result corresponding to the data read operation and the preset read result.

For example, for any data read operation, when it is determined that the read result corresponding to the data read operation is the same as the preset read result, the identifier of the delay code used by the data read operation is recorded as the zeroth identifier "0".

For another example, for any data read operation, when it is determined that the read result corresponding to the data read operation is different from the preset read result, the identifier of the delay code used by the data read operation is recorded as the first identifier "1".

In some examples, the read result may be determined according to a communication protocol of each type of memory.

For example, when the memory is an embedded multimedia controller eMMC, when the first sampling instruction is used to read data stored in the eMMC, the preset reading result may be a tuning sequence.

When the reading result corresponding to the data read operation is a tuning sequence after analysis, the identifier of the delay code used to perform the data read operation can be recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used to perform the data write operation can be recorded as the first identifier "1".

For example, when the memory is an embedded multimedia controller eMMC, when the second sampling instruction is used to read data stored in the eMMC, the preset reading result may be a value stored in a register in the multimedia controller eMMC.

When, after analysis and processing, it is determined that the read result corresponding to the data read operation is the value stored in the register, the identifier of the delay code used to perform the data read operation can be recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used to perform the data write operation can be recorded as the first identifier "1".

In some examples, when the identifiers of the delay codes used for each data read operation are recorded, an available identifier may be selected as a target delay code for executing the data read operation.

As an example, the following steps may be performed to determine a target delay code for performing a data read operation.

B1) According to the order of each data read operation, a read identifier sequence table having a zeroth identifier and a first identifier arranged in sequence is obtained.

B2) Determine an area in the read identifier sequence table where at least a continuous zeroth identifier exists.

B3) Select the zeroth marker from the determined area, and record the zeroth marker in sequence to obtain the corresponding selection window.

B4) The delay code corresponding to the zeroth mark located at the preset position of the selection window is used as the target delay code when executing each data read operation.

In some examples, when performing step B3) to obtain multiple selection windows, B4) may include:

B41) Select the selection window containing the largest number of zeroth identifiers from multiple selection windows as the target window.

B42) The delay code corresponding to the zeroth mark located at the preset position of the target window is used as the target delay code.

In some examples, the delay code corresponding to the zeroth marker located in the middle of the target window may be used as the target delay code.

In some optional examples, before executing step B2), it can also be determined whether the total number of the zeroth identifier and the first identifier contained in the read identifier sequence table is the same as the number of times the data read operation is performed, and when it is determined that the total number of the zeroth identifier and the first identifier contained in the read identifier sequence table is the same as the number of times the data read operation is performed, step B2 is executed); otherwise, continue to record the identifier of the delay code used for subsequent data read operations.

By adopting the above method, the target delay code corresponding to the data read operation can be obtained, and then the data read operation can be performed according to the delay duration corresponding to the target delay code.

To facilitate understanding and implementation of the solution for determining the target delay code used for performing a data read operation on the first memory, the following is a description through examples in conjunction with the accompanying drawings.

Referring to the flowchart for determining the target delay code for a data write operation in an application scenario in an example of the present disclosure shown in FIG11 , as shown in FIG11 , the following steps may be performed:

S91, whether the data transmission rate when executing the data read operation is the same as the set rate; if so, execute step S92; if not, execute step S94.

S92: Determine that the transmission mode type is the first transmission mode.

In some examples, the first transmission mode may refer to HS400.

S93, performing multiple delay processing on the synchronous clock signal according to the delay durations corresponding to the multiple delay codes.

S94: Determine that the transmission mode type is the second transmission mode.

In some examples, the second transmission mode may refer to HS200, or be compatible with MMC mode, high SDR (Single Data Rate) mode, and high speed DDR (Double Data Rate) mode.

S95, performing multiple delay processing on the initial clock signal according to the delay durations corresponding to the multiple delay codes.

S96, for any data read operation, determine whether the preset first sampling instruction is supported when reading the data stored in the first memory, if so, execute step 97; if not, execute step S98.

As an example, data stored in the first memory may be read in the first transmission mode to determine whether sending a preset first sampling instruction is supported when performing a data read operation.

As an example, data stored in the first memory may be read in the second transmission mode to determine whether sending a preset first sampling instruction is supported when performing a data read operation.

S97, sending a first sampling instruction, and performing a data read operation under delay processing to obtain a read result related to the first sampling instruction.

As an example, in the first transmission mode, a first sampling instruction may be sent to the first memory, and then after delaying the synchronous clock signal, when a data read operation is performed, a read result related to the first sampling instruction may be obtained.

As an example, in the second transmission mode, a first sampling instruction may be sent to the first memory, and then after delaying the synchronous clock signal, when a data read operation is performed, a read result related to the first sampling instruction may be obtained.

S98, sending a second sampling instruction, and performing a data read operation under delay processing to obtain a read result related to the second sampling instruction.

As an example, in the first transmission mode, a second sampling instruction may be sent to the first memory, and then after delaying the synchronous clock signal, a reading result related to the second sampling instruction may be obtained when a data read operation is performed.

As an example, in the second transmission mode, a second sampling instruction may be sent to the first memory, and then after delaying the synchronous clock signal, when a data read operation is performed, a read result related to the second sampling instruction may be obtained.

S99, for any data read operation, whether the read result is the same as the preset read result, if so, execute step S100; if not, execute step S101.

As an example, in the first transmission mode, it can be determined whether a read result associated with the first sampling instruction obtained when a data read operation is performed is the same as a preset read result; or in the first transmission mode, it can be determined whether a read result associated with the second sampling instruction obtained when a data read operation is performed is the same as a preset read result.

As an example, in the second transmission mode, it can be determined whether the read result associated with the first sampling instruction obtained when performing a data read operation is the same as the preset read result; or in the second transmission mode, it can be determined whether the read result associated with the second sampling instruction obtained when performing a data read operation is the same as the preset read result.

S100, recording the identifier of the delay code used in the data read operation as the available zeroth identifier.

As an example, the available zeroth identifier corresponding to the delay code used to perform the data read operation in the first transmission mode may be recorded.

As an example, the available zeroth identifier corresponding to the delay code used to perform the data read operation in the second transmission mode may be recorded.

S101, recording an identifier of a delay code used in a data read operation as a first identifier that is unavailable.

As an example, an unavailable first identifier corresponding to a delay code used to perform a data read operation in the first transmission mode may be recorded.

As an example, a first unavailable identifier corresponding to a delay code used for performing a data read operation in the second transmission mode may be recorded.

S102, sorting the zeroth identifier and the first identifier of the record according to the order of executing each data read operation to obtain a read identifier sequence table.

As an example, a read identification sequence table corresponding to a data read operation performed in the first transmission mode may be recorded.

As an example, a read identification sequence table corresponding to the data read operation performed in the second transmission mode may be recorded.

S103, read whether the total number of identifiers in the identifier sequence table is the same as the number of times the data read operation is performed, if so, execute step S104; if not, continue to execute step S97, or continue to execute step S98.

As an example, if the read identifier sequence table is obtained according to the first sampling instruction, when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed, step S97 is executed.

As an example, if the read identifier sequence table is obtained according to the second sampling instruction, when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed, step S98 is executed.

The total number of identifiers includes the number of first identifiers and zeroth identifiers.

S104, determining an area in the read identifier sequence table where there are continuous zeroth identifiers.

S105, selecting the zeroth marker from the determined area, and recording the selected zeroth marker in sequence to obtain a corresponding selection window.

S106, selecting a selection window containing the largest number of zeroth identifiers as a target window.

S107, the delay code corresponding to the zeroth mark located in the middle of the target window is used as the target delay code.

S108, delaying the clock signal according to the delay time corresponding to the target delay code to perform a subsequent data read operation.

The specific implementation of steps S91 to S108 can refer to the above examples.

It should be noted that the above example is based on a case where multiple selection windows are provided. If only one selection window is included, the delay code corresponding to the zeroth marker in the middle of the selection window can be directly used as the target delay code.

By adopting the solution in the above example, a target delay code for performing a subsequent data read operation can be selected, so that data can be stably read from a memory having a storage function, for example, data can be read from the first memory.

As another example, the data read operation may include an operation of reading data stored in the second memory.

The second memory and the first memory are memories of different types, and they perform data writing and reading processes according to different communication protocols.

In this application scenario, when determining to perform an operation of reading data stored in the second memory, it can be determined that the transmission mode type is the third transmission mode.

In some examples, when the specific type of the transmission mode is determined, the specific clock signal for delay processing can be determined, and then the delay processing can be performed.

As an example, when it is determined that the transmission mode type is the third transmission mode, it is determined that the clock signal corresponding to the third transmission mode is the initial clock signal, wherein the initial clock signal is the acquired original clock signal.

For example, if the third transmission mode is SDR104, the initial clock signal may be an original clock signal obtained when a write operation is performed on the secure digital card SD.

Correspondingly, executing the delay processing may include: performing multiple delay processing on the initial clock signal according to the delay durations corresponding to the multiple delay codes.

In some examples, a data read operation uses a delay time corresponding to a delay code to perform a delay process on the initial clock signal, that is, the number of times the data read operation is performed is the same as the number of times the delay process is performed on the initial clock signal.

In some examples, the delay lengths corresponding to the delay codes may be different, so as to perform delay processing of different lengths on the initial clock signal used in each data read operation.

In some implementations, after performing a delay process on a clock signal corresponding to the transmission mode type, a data read operation may be performed.

In some examples, during the process of executing the data read operation, different sampling instructions may be used to obtain the read result corresponding to the data read operation.

As an example, referring to another flowchart for obtaining a read result corresponding to a data read operation in an example of the present disclosure shown in FIG. 12 , in some examples, as shown in FIG. 12 , the following steps may be performed:

S111, for any data read operation, determine whether it supports sending a preset third sampling instruction when reading data stored in the second memory in the third transmission mode, if so (if supported), execute step S112; otherwise, execute S113.

Specifically, in different transmission modes, different reading methods can be used to read the data stored in the second memory. Therefore, when performing any data reading operation, it can be determined whether the data stored in the second memory can be read through the preset third sampling instruction in the third transmission mode.

S112, according to the preset third sampling instruction, performing a data read operation under the delay processing of the initial clock signal, performing the data read operation to obtain a read result of the data read operation related to the third sampling instruction;

Specifically, when it is determined that the third transmission mode is in place and the data stored in the second memory can be read according to the preset third sampling instruction, the preset third sampling instruction can be sent to the second memory, and then after delaying the initial clock signal, the data stored in the second memory can be read according to the preset third sampling instruction, thereby obtaining the reading result of the data read operation related to the third sampling instruction.

S113, according to the preset fourth sampling instruction, performing a data read operation under the delay processing of the initial clock signal to obtain a read result of the data read operation related to the fourth sampling instruction.

Specifically, when it is determined that the third transmission mode is in place and the data stored in the second memory cannot be read according to the preset third sampling instruction, a preset fourth sampling instruction can be sent to the second memory, and then after delaying the initial clock signal, the data stored in the fourth memory can be read according to the preset fourth sampling instruction, thereby obtaining the reading result of the data read operation related to the fourth sampling instruction.

In some examples, the types of the third sampling instruction and the fourth sampling instruction may be determined according to the type of the memory.

For example, if the memory includes a secure digital card SD, the third sampling instruction may refer to CMD19, and the fourth sampling instruction may be other general data read instructions, such as CMD8.

By adopting the above judgment process, when any data read operation is in the third transmission mode, different sampling instructions (such as the third sampling instruction and the fourth sampling instruction) can be used to obtain the reading result of the data read operation related to the sampling instruction, thereby being applicable to different transmission scenarios and improving the universality of the data read operation.

In some examples, after determining the transmission mode type and obtaining the read result of the data read operation related to the third sampling instruction or the read result of the data read operation related to the fourth sampling instruction according to the preset third sampling instruction or the fourth sampling instruction, the read result can be compared with the preset read result to determine the specific identifier of the delay code used for each data read operation.

In some examples, the identifier of the delay code used in each data read operation may be determined and recorded according to the relative relationship between the read result corresponding to the data read operation and the preset read result.

For example, for any data read operation, when it is determined that the read result corresponding to the data read operation is the same as the preset read result, the identifier of the delay code used by the data read operation is recorded as the zeroth identifier "0".

For another example, for any data read operation, when it is determined that the read result corresponding to the data read operation is different from the preset read result, the identifier of the delay code used by the data read operation is recorded as the first identifier "1".

In some examples, the read result may be determined according to a communication protocol of each type of memory.

For example, when the memory is a secure digital card SD, when the third sampling instruction is used to read data stored in the secure digital card SD, the preset reading result may be a tuning sequence.

After analysis, when the reading result corresponding to the data read operation is a tuning sequence, the identifier of the delay code used to perform the data read operation can be recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used to perform the data read operation can be recorded as the first identifier "1".

For another example, when the fourth sampling instruction is used to read data stored in the secure digital card SD, the preset reading result may be a value stored in a memory (eg, register CID) in the secure digital card SD.

After analysis and processing, when the read result corresponding to the data read operation is the value stored in the memory, the identifier of the delay code used to perform the data read operation can be recorded as the zeroth identifier "0"; otherwise, the identifier of the delay code used to perform the data read operation can be recorded as the first identifier "1".

In some examples, when the identifiers of the delay codes used for each data read operation are recorded, an available identifier may be selected as a target delay code for executing the data read operation.

In some optional examples, reference may be made to the aforementioned description of selecting a target delay code when performing a data read operation on the first memory, and the description is not expanded here.

To facilitate understanding and implementation of the solution for determining the target delay code used for performing a data read operation on the second memory, the following is a description through examples in conjunction with the accompanying drawings.

Referring to the flowchart for determining the target delay code for a data read operation in another application scenario in the present disclosure example shown in FIG. 13 , as shown in FIG. 13 , the following steps may be performed:

S121, determining that the transmission mode type is the third transmission mode.

In some examples, the third transmission mode may be SDR104, SDR50, and the like.

S122, performing multiple delay processing on the initial clock signal according to the delay durations corresponding to the multiple delay codes.

S123, for any data read operation, determine whether the preset third sampling instruction is supported when reading the data stored in the second memory, if so, execute step S124; if not, execute step S125.

S124, sending a third sampling instruction, and performing a data read operation under delay processing to obtain a read result related to the third sampling instruction.

As an example, in the third transmission mode, the first sampling instruction may be sent to the second memory to obtain a reading result associated with the third sampling instruction when a data read operation is performed after delaying the initial clock signal.

S125, sending a fourth sampling instruction, and performing a data read operation under delay processing to obtain a read result related to the fourth sampling instruction.

As an example, in the third transmission mode, a fourth sampling instruction may be sent to the second memory to obtain a reading result associated with the fourth sampling instruction when a data read operation is performed after delaying the initial clock signal.

S126, for any data read operation, whether the read result is the same as the preset read result, if so, execute step S127; if not, execute step S128.

As an example, in the third transmission mode, it is determined whether the read result associated with the third sampling instruction obtained when performing a data read operation is the same as the preset read result; or in the third transmission mode, it is determined whether the read result associated with the fourth sampling instruction obtained when performing a data read operation is the same as the preset read result.

S127, recording the identifier of the delay code used in the data read operation as the available zeroth identifier.

S128, recording the identifier of the delay code used in the data read operation as an unavailable first identifier.

S129, sorting the zeroth identifier and the first identifier of the record according to the order of executing each data read operation to obtain a read identifier sequence table.

S130, read whether the total number of identifiers in the identifier sequence table is the same as the number of times the data read operation is performed, if so, execute step S131; if not, continue to execute step S124, or continue to execute step S125.

As an example, if the read identifier sequence table is obtained according to the third sampling instruction, when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed, step S124 is executed.

As an example, if the read identifier sequence table is obtained according to the fourth sampling instruction, when it is determined that the total number of identifiers in the read identifier sequence table is different from the number of times the data read operation is performed, step S125 is executed.

The total number of identifiers includes the number of first identifiers and zeroth identifiers.

S131, determining the area where there are continuous zeroth identifiers in the identifier sequence table.

S132, selecting the zeroth marker from the determined area, and recording the selected zeroth marker in sequence to obtain a corresponding selection window.

S133, selecting a selection window containing the largest number of zeroth identifiers as a target window.

S134, the delay code corresponding to the zeroth mark located in the middle of the target window is used as the target delay code.

S135, delaying the clock signal according to the delay time corresponding to the target delay code to perform a subsequent data read operation.

The specific implementation of steps S121 to S135 may refer to the above examples.

It should be noted that the above example is based on a case where multiple selection windows are provided. If only one selection window is included, the delay code corresponding to the zeroth marker in the middle of the selection window can be directly used as the target delay code.

By adopting the solution in the above example, a target delay code for performing a subsequent data read operation can be selected, so that data can be stably read from a memory having a storage function, for example, data can be read from the second memory.

It should be noted that the above examples using the first memory and the second memory as examples to illustrate the scheme for performing a data read operation are only examples for illustrating that a target delay code for performing a data read operation can be obtained in different ways according to the type of memory, and should not be construed as a limitation of the present invention. In some examples, more types of memories may also be included.

By adopting the scheme in the above example and performing multiple delay processing, a target delay code for performing a data write operation or a data read operation can be selected from multiple consecutive zeroth identification times, thereby improving the stability of data transmission during the data write operation or the data read operation.

In a specific implementation, in a u-boot environment, the data transmission method in the disclosed example is used, and after application testing, data can be stably written and read within a temperature range of -40°C to 125°C.

The disclosed example also provides a data transmission device corresponding to the above data transmission method, which is introduced below by way of example with reference to the accompanying drawings.

Referring to FIG. 14 , a schematic diagram of a data transmission device in an example of the present disclosure, in some examples, as shown in FIG. 14 , the data transmission device 100 may include: a first processing unit 110 and a second processing unit 120, wherein:

The first processing unit 110 is configured to perform multiple data processing operations, and based on the execution results of each data processing operation, record the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to execute; and according to the identifier selection signal, the delay code corresponding to the selected zeroth identifier is used as the target delay code to execute the data processing operation;

The second processing unit 120 is configured to select a zeroth identifier from multiple consecutive zeroth identifiers when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, and generate a corresponding identifier selection signal, wherein the identifier selection signal includes a delay code corresponding to the selected zeroth identifier.

Using the data transmission device 100 in the above example, based on the execution results of each data processing operation, the first processing unit 110 can record the zeroth identifier that indicates the delay code used is available when the data processing operation is successfully executed, and the first identifier that indicates the delay code used is unavailable when the data processing operation fails to execute. Then, when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, the second processing unit 120 can select the zeroth identifier from them, and use the delay code corresponding to the selected zeroth identifier as the target delay code, and generate a corresponding identifier selection signal. Since the identifier selection signal can include the delay code corresponding to the selected zeroth identifier, the delay code corresponding to the selected zeroth identifier can be used as the target delay code to execute the data processing operation.

When using the above-mentioned data transmission device 100, since the target delay code is determined from multiple consecutive and available zeroth identifiers, that is, the target delay code is determined from the delay codes used for multiple consecutive and successful data processing operations, wherein the zeroth identifier is used to identify the used delay code and mark it as available when the data processing operation is successfully executed, even if the target delay code changes due to environmental factors, the target delay code is still available, thereby improving the stability of the data processing process.

In some examples of the present disclosure, data processing operations may be divided into data write operations and data read operations based on a data transmission direction, and different execution logics may be used when executing corresponding data processing operations.

In some examples, the data processing operations may include data write operations.

In this application scenario, referring to a specific structural diagram of a first processing unit in an example of the present disclosure shown in FIG. 15 , as shown in FIG. 15 , the first processing unit 110 may include: a first delay module 111 and a first processing module 112, wherein:

The first delay module 111 is configured to perform multiple delay processing on the clock signal according to the delay durations corresponding to the multiple delay codes, wherein one data write operation uses a delay duration corresponding to one delay code to perform one delay processing on the clock signal, and the delay durations corresponding to the different delay codes are different;

The first processing module 112 is configured to obtain verification information corresponding to each data write operation after executing the data write operation under each delay processing of the clock signal, and the verification information is used to determine whether the data write operation can be successfully executed; and according to the verification information corresponding to each data write operation, record the identifier of the delay code used for each data write operation.

Specifically, the first delay module 111 can perform delay processing on the clock signal according to the delay length corresponding to the delay code, and then perform data writing operations. For any data writing operation, a corresponding verification signal can be obtained. Since the verification information can be used to determine whether the data writing operation can be successfully executed, the first processing module 112 can record the identifier of the delay code used for each data writing operation according to the verification information corresponding to each data writing operation.

In some examples, the first processing module 112 may record the identifier of the delay code used for the data write operation as the zeroth identifier “0” when determining that the verification information corresponding to the data write operation is the same as the preset verification information.

In some examples, the first processing module 112 may record the identifier of the delay code used for the data write operation as the first identifier “1” when determining that the verification information corresponding to the data write operation is different from the preset verification information.

In some optional examples, delay modules with different structures may be used to implement delay processing of the clock signal.

As an example, referring to FIG. 15 , the first delay module 111 may include a plurality of first delay devices (for example, the first delay devices D10, D11, …, D1n shown in FIG. 15 , where n is an integer greater than 1), a first logic operator Lg1 and a first selector SC1, where:

A plurality of first delay devices are connected in sequence. For example, the first delay devices D10, D11, ..., D1n may be connected in series, wherein:

The first end of the first delay device Dl0 among the multiple first delay devices can input the clock signal dl_in, the output end of the last first delay device Dln among the multiple first delay devices can be connected to the first end of the first logic operator Lg1, and the second end of each first delay device among the multiple first delay devices is connected to the second end of the first selector SC1.

As an example, the second end of the first delay Dl0 can be connected to the second end of the first selector SC1, the second end of the first delay Dl1 can be connected to the second end of the first selector SC1, ..., the second end of the first delay Dln can be connected to the second end of the first selector SC1.

Next, referring to FIG. 15 , the first end of the first selector SC1 can input the first control signal dl_sel, and generate a corresponding first selection signal according to the first control signal dl_sel, wherein the first selection signal is used to control the number of first delay devices that enable the delay function when performing a data write operation.

Specifically, the clock signal can be transmitted to the first processing module 112 via each first delay device, and at this time, each first delay device only plays the role of data transmission. In response to the first control signal, the first selector SC1 can select to turn on the delay function of at least one of the first delay devices D10 to D1n, thereby changing the delay time length of the clock signal dl_in.

For example, in response to the first control signal dl_sel, the first selector SC1 can generate the first selection signal del0, thereby turning on the delay function of the first delay device Dl0; in response to the first control signal dl_sel, the first selector SC1 can generate the first selection signal deln, thereby turning on the delay function of all first delay devices Dl0.

In some optional examples, the first control signal dl_sel may be obtained from the first processing module, or may be obtained from other devices with logic processing capabilities, for example, from a central processing unit. The examples disclosed herein do not impose any restrictions on the source of the first control signal.

The second end of the first logic operator Lg1 can input the second control signal dl_update, and the output end thereof is suitable for outputting the clock signal after delay processing to the first processing module 112, wherein the second control signal dl_update can be used to control the output timing of the clock signal after delay processing.

For example, through the second control signal, after determining to perform a delay process, the corresponding clock signal is output to the first processing module.

That is, by setting the state of the second control signal (for example, the level corresponding to the second control signal is a low level), the output channel of the first logic operator is closed during the delay processing of the clock signal; and after determining that the delay processing of the clock signal is completed, by setting the state of the second control signal (for example, the level corresponding to the second control signal is a high level), the output channel of the first logic operator is opened to transmit the clock signal after the delay processing to the first processing module to realize normal data writing operation.

In some examples, the first logic operator may include an AND logic gate. In some examples, the second control signal may be obtained from the first processing module, or may be obtained from other devices with logic processing capabilities, such as a central processing unit. The examples disclosed herein do not impose any restrictions on the source of the second control signal.

In some optional examples, for some application scenarios with lower transmission rates, the frequency of the clock signal is relatively low and is less affected by environmental factors, so data write operations can be performed directly based on the clock signal.

Based on this, continuing to refer to Figure 15, the first processing unit 110 can also include a mode selection module 113, wherein the mode selection module 113 can be coupled to the first delay module 111 (for example, the mode selection module 113 can be connected to the first delay device dl0), and is configured to control the working state of the first delay module 111 in response to the mode selection signal pass_en.

More specifically, the mode selection signal pass_en can be used to control whether to use the first delay module 111 to perform delay processing on the clock signal dl_in.

For example, when the mode selection signal pass_en is a high level "1", there is no need to delay the clock signal dl_in; for another example, when the mode selection signal pass_en is a low level "0", the number of first delay devices that enable the delay function can be selected through the first control signal dl_sel to perform delay processing of different lengths on the clock signal dl_in.

It should be noted that when the first processing unit also includes a mode selection module, the mode selection module plays a delay role, but the delay duration corresponding to the mode selection module is much smaller than the delay duration of each first delay device, so in some examples, the delay duration of the mode selection module can be ignored.

In some optional examples, the delay durations corresponding to the first delay devices are the same, that is, when different numbers of first delay devices with delay functions are connected to the delay path, the corresponding delay durations may increase in order.

In some other optional examples, the delay durations corresponding to the first delay devices may be the same.

In some examples, after delaying the clock signal, a data write operation can be performed, and then a target delay code can be obtained. The method for obtaining the target delay code for performing the data write operation can be referred to the above example and will not be described in detail here.

In some examples, the data processing operation may include a data read operation.

In some implementations, when the data processing operation includes a data read operation, during the data read operation, different operations may be performed for memories of different types or different communication protocols when determining the corresponding target delay code.

In this application scenario, the first processing unit may include:

a second processing module, configured to determine a transmission mode type for performing multiple data read operations; and after performing a data read operation under each delay processing of a clock signal corresponding to the transmission mode type, obtain a reading result corresponding to each data read operation, wherein the reading result is used to determine whether the data read operation is successfully performed when in the transmission mode type, and record an identifier of a delay code used for each data read operation according to the reading result corresponding to each data read operation;

The second delay module performs multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay length corresponding to a delay code to perform a delay processing on the clock signal corresponding to the transmission mode type, and the delay lengths corresponding to the delay codes are different.

Specifically, the second processing module can determine the transmission mode type for executing multiple data read operations, and different transmission mode types have different types of corresponding clock signals, so the second delay module can perform delay processing on the signal corresponding to the transmission mode type according to the delay duration corresponding to each delay code, and then perform the data read operation. For any data read operation, the corresponding reading result can be obtained, because the reading result can be used to determine whether the data read operation is successfully executed in the current transmission mode type, so the second processing module can record the identification of the delay code used for each data read operation according to the reading result corresponding to each data read operation.

In some examples, the second processing module may record the identifier of the delay code used in the data read operation as the zeroth identifier “0” when determining that the read result corresponding to the data read operation is the same as the preset read result.

In some examples, the second processing module may record the identifier of the delay code used in the data read operation as a first identifier “1” when the read result corresponding to the data read operation is different from the preset read result.

In some optional examples, delay modules with different structures may be used to implement delay processing of the clock signal.

As an example, the second delay module may include a plurality of second delay devices, a second logic operator and a first selector, wherein:

The plurality of second delay devices are connected in sequence, for example, the plurality of second delay devices can be connected in series, wherein:

The first end of the first second delay device among the multiple second delay devices is suitable for inputting a clock signal corresponding to the transmission mode type, the output end of the last second delay device among the multiple second delay devices is connected to the first end of the second logic operator, and the second end of each second delay device among the multiple second delay devices is connected to the second end of the second selector.

As an example, the connection relationship between each second delay device and the second selector can refer to the description of the first delay module, which will not be repeated here.

In some examples, a third control signal is input to the first end of the second selector, and a corresponding second selection signal is generated based on the third control signal, wherein the second selection signal is used to control the number of second delay devices that enable a delay function when performing a data read operation.

Specifically, the clock signal corresponding to the transmission mode type can be transmitted to the second processing module via each second delay device, and at this time, each second delay device only plays the role of data transmission. In response to the second control signal, the second selector can select to turn on the delay function of at least one second delay device among the plurality of second delay devices, thereby changing the delay time length of the clock signal corresponding to the transmission mode type.

For example, in response to the third control signal, the second selector may generate a second selection signal to enable the delay function of the first second delay device; or in response to the third control signal, the second selector may generate a second selection signal to enable the delay function of all second delay devices.

In some optional examples, the third control signal can be obtained from the second processing module, or from other devices with logic processing capabilities, such as a central processing unit. The examples disclosed herein do not impose any restrictions on the source of the third control signal.

The second end of the second logic operator can input a fourth control signal, and the output end thereof can output a clock signal corresponding to the transmission mode type after delay processing to the second processing module, wherein the fourth control signal can be used to control the output timing of the clock signal corresponding to the transmission mode type after delay processing.

For example, through the fourth control signal, after determining to perform a delay process, a clock signal corresponding to the transmission mode type after the delay process is output to the second processing module.

Specifically, by setting the state of the fourth control signal, the output channel of the second logic operator is closed during the delay processing of the clock signal corresponding to the transmission mode type; and after determining that the delay processing of the clock signal corresponding to the transmission mode type is completed, by setting the state of the fourth control signal, the output channel of the second logic operator is opened to transmit the clock signal corresponding to the transmission mode type after the delay processing to the second processing module to realize normal read operation.

In some examples, the second logic operator may include an AND logic gate. In some examples, the fourth control signal may be obtained from the second processing module, or may be obtained from other devices with logic processing capabilities, for example, from a central processing unit. The examples disclosed herein do not impose any restrictions on the source of the fourth control signal.

In some optional examples, for some application scenarios with lower transmission rates, the frequency of the clock signal is relatively low and is less affected by environmental factors, so data read operations can be performed directly based on the clock signal.

Based on this, the second processing unit may further include a mode selection module, wherein the mode selection module may be coupled to the second delay module (for example, the mode selection module may be connected to the first second delay device), and is configured to control the working state of the second delay module in response to a mode selection signal.

More specifically, the mode selection signal can be used to control whether to use the second delay module to perform delay processing on the clock signal corresponding to the transmission mode type.

For example, when the level corresponding to the mode selection signal is a high level "1", there is no need to delay the clock signal corresponding to the transmission mode type; for another example, when the level corresponding to the mode selection signal is a low level "0", the number of second delay devices with the delay function enabled can be selected through a third control signal to perform delay processing of different lengths on the clock signal corresponding to the transmission mode type.

In some optional examples, the delay durations corresponding to the second delay devices are the same, that is, when different numbers of second delay devices with delay functions are connected to the delay path, the corresponding delay durations can be increased in order.

In some other optional examples, the delay durations corresponding to the second delay devices may be the same.

In some examples, after delaying the clock signal corresponding to the transmission mode type, a data read operation can be performed, and then a target delay code can be obtained. The method for obtaining the target delay code for performing the data read operation can be referred to the aforementioned example and will not be described in detail here.

The present disclosure also provides a host, which may include at least one processor and at least one memory, and the memory and the processor may communicate via a communication bus; the memory stores computer instructions that can be run on the processor, and when the processor calls the one or more computer executable instructions, the data transmission method described in any of the above embodiments may be executed. For details, please refer to the above-mentioned related content and will not be repeated here.

In a specific implementation, the processor may include a central processing unit (CPU), a field programmable gate array (FPGA), etc.

The memory may include a random access memory (RAM), a read-only memory (ROM), a non-volatile memory (NVM), etc. In a specific implementation, the computer instructions may include any suitable type of code implemented by using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc.

The present invention also provides a storage medium, which stores one or more computer-executable instructions. When the one or more computer-executable instructions are executed, the data transmission method described in any of the above embodiments can be implemented. For details, please refer to the above-mentioned related content and will not be repeated here.

The computer-readable storage medium may include any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, such as memory, removable or non-removable medium, erasable or non-erasable medium, writable or rewritable medium, digital or analog medium, hard disk, floppy disk, compact disk read-only memory (CDROM), compact disk recordable (CD-R), compact disk rewritable (CD-RW), optical disk, magnetic medium, magneto-optical medium, removable memory card or disk, various types of digital versatile disks (DVD), magnetic tape, cassette, etc.

Furthermore, the computer instructions may include any suitable type of code implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc.

Although the examples of the present disclosure are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (29)

1. A data transmission method, comprising: Execute multiple data processing operations, and based on the execution results of each data processing operation, record the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to be executed; When it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, at least one zeroth identifier is selected from the multiple consecutive zeroth identifiers, and the delay code corresponding to the selected zeroth identifier is used as the target delay code; The data processing operation is performed using the target delay code. 2. The data transmission method according to claim 1, further comprising: According to the order of executing each data processing operation, the zeroth identifier and the first identifier of the record are sorted to obtain an identifier sequence table; When it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, selecting the zeroth identifier from the multiple consecutive zeroth identifiers, and using the delay code corresponding to the selected zeroth identifier as the target delay code, includes: Determine an area in the identifier sequence table where there are continuous zeroth identifiers; Selecting the zeroth mark from the determined area, and recording the selected zeroth mark in sequence to obtain a corresponding selection window; The delay code corresponding to the zeroth mark located at the preset position of the selection window is used as the target delay code when executing each data processing operation. 3. The data transmission method according to claim 2, characterized in that the selection window is multiple; The method of using the delay code corresponding to the zeroth mark located at the preset position of the selection window as the target delay code when performing each data processing operation includes: Selecting a selected window containing the largest number of zeroth identifiers from the plurality of selected windows as a target window; The delay code corresponding to the zeroth marker located at the preset position of the target window is used as the target delay code. 4. The data transmission method according to claim 2 or 3, characterized in that before executing the step of determining the area where there are continuous zeroth identifiers in the identifier sequence table, it also includes: Determine whether the total number of the zeroth identifier and the first identifier contained in the identifier sequence table is the same as the number of times the data processing operation is performed, and if it is determined to be the same, perform the step of determining the area where there are continuous zeroth identifiers in the identifier sequence table; otherwise, continue to record the identifier of the delay code used for subsequent data processing operations. 5. The data transmission method according to claim 2 or 3, characterized in that the data processing operation comprises a data writing operation; The identifier sequence table includes a zeroth identifier corresponding to when the data write operation is successfully executed, and a first identifier corresponding to when the data write operation fails to execute. 6. The data transmission method according to claim 2 or 3, characterized in that the data processing operation comprises a data read operation; The identifier sequence table includes a zeroth identifier corresponding to when the data read operation is successfully executed, and a first identifier corresponding to when the data read operation fails to execute. 7. The data transmission method according to claim 5, characterized in that the data processing operation comprises a data writing operation; The performing of multiple data processing operations and recording the identification of the delay code used in each data processing operation based on the execution result of each data processing operation includes: According to the delay time lengths corresponding to the multiple delay codes, the clock signal is delayed multiple times, wherein a data write operation uses a delay time length corresponding to a delay code to perform a delay process on the clock signal once, and the delay time lengths corresponding to the delay codes are different; After executing the data write operation under each delay processing of the clock signal, obtaining verification information corresponding to each data write operation, wherein the verification information is used to determine whether the data write operation can be successfully executed; According to the verification information corresponding to each data writing operation, the identifier of the delay code used in each data writing operation is recorded. 8. The data transmission method according to claim 7, characterized in that the step of recording the identifier of the delay code used in each data writing operation according to the verification information corresponding to each data writing operation comprises: For any data write operation, when it is determined that the verification information corresponding to the data write operation is the same as the preset verification information, the identifier of the delay code used for the data write operation is recorded as the zeroth identifier, and when it is determined that the verification information corresponding to the data write operation is different from the preset verification information, the identifier of the delay code used for the data write operation is recorded as the first identifier. 9. The data transmission method according to claim 7 or 8, characterized in that the use of the target delay code to perform the data processing operation comprises: The clock signal is delayed according to the delay duration corresponding to the target delay code to perform a data write operation. 10. The data transmission method according to claim 6, wherein the data processing operation comprises a data reading operation; The performing of multiple data processing operations and recording the identification of the delay code used in each data processing operation based on the execution result of each data processing operation includes: Determine the type of transfer mode for performing multiple data read operations; According to the delay durations corresponding to the multiple delay codes, the clock signal corresponding to the transmission mode type is subjected to multiple delay processing, wherein a data read operation uses a delay duration corresponding to a delay code to perform one delay processing on the clock signal corresponding to the transmission mode type, and the delay durations corresponding to the delay codes are different; After performing a data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation, wherein the read result is used to determine whether the data read operation is successfully performed when in the transmission mode type; According to the reading result corresponding to each data read operation, the identifier of the delay code used in each data read operation is recorded. 11. The data transmission method according to claim 10, wherein the data reading operation comprises reading data stored in the first memory; The determining of the transmission mode type for performing multiple data read operations includes: The type of transmission mode for performing a data read operation is determined according to a data transmission rate for reading data stored in the first memory. 12. The data transmission method according to claim 11, wherein determining the transmission mode type for performing the data read operation according to the data transmission rate of reading the data stored in the first memory comprises: When the data transmission rate of reading the data stored in the first memory is the same as the set rate, determining that the transmission mode type is the first transmission mode; When the data transmission rate of reading the data stored in the first memory is different from the set rate, the transmission mode type is determined to be the second transmission mode. 13. The data transmission method according to claim 12, characterized in that when the transmission mode type is determined to be the first transmission mode, the clock signal corresponding to the first transmission mode is determined to be a synchronous clock signal, and the synchronous clock signal comes from the party providing the read data; The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes: The synchronous clock signal is delayed multiple times according to the delay time lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay time length corresponding to a delay code to perform a delay process on the synchronous clock signal, and the delay time lengths corresponding to the different delay codes are different. 14. The data transmission method according to claim 12, characterized in that when the transmission mode type is determined to be the second transmission mode, the clock signal corresponding to the second transmission mode is determined to be the initial clock signal, and the initial clock signal is the acquired original clock signal; The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes: The initial clock signal is delayed multiple times according to the delay durations corresponding to the multiple delay codes, wherein a data read operation uses a delay duration corresponding to a delay code to perform a delay processing on the initial clock signal once, and the delay durations corresponding to the different delay codes are different. 15. The data transmission method according to any one of claims 12 to 14, characterized in that after performing a data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation comprises: For any data read operation, determining whether sending a preset first sampling instruction is supported when reading data stored in the first memory; If supported, according to a preset first sampling instruction, a data read operation is performed under a delay processing of a clock signal corresponding to the transmission mode type to obtain a read result of the data read operation related to the first sampling instruction; Otherwise, according to the preset second sampling instruction, a data read operation is performed under the delay processing of the clock signal corresponding to the transmission mode type to obtain a read result of the data read operation related to the second sampling instruction. 16. The data transmission method according to claim 10, wherein the data reading operation comprises reading data stored in the second memory; The determining of the transmission mode type for performing multiple data read operations includes: When determining to read the data stored in the second memory, the transmission mode type is determined to be a third transmission mode. 17. The data transmission method according to claim 16, characterized in that when the transmission mode type is determined to be the third transmission mode, the clock signal corresponding to the third transmission mode is determined to be the initial clock signal, and the initial clock signal is the acquired original clock signal; The method of performing multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay durations corresponding to the multiple delay codes includes: The initial clock signal is delayed multiple times according to the delay time lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay time length corresponding to a delay code to perform a delay process on the initial clock signal, and the delay time lengths corresponding to the different delay codes are different. 18. The data transmission method according to claim 16 or 17, characterized in that after performing a data read operation under each delay processing of the clock signal corresponding to the transmission mode type, obtaining a read result corresponding to each data read operation comprises: For any data read operation, determining whether sending a preset third sampling instruction is supported when reading data stored in the second memory in a third transmission mode; If supported, performing a data read operation under the delay processing of the initial clock signal according to the preset third sampling instruction to obtain a read result of the data read operation related to the third sampling instruction; Otherwise, according to the preset fourth sampling instruction, a data read operation is performed under the delay processing of the initial clock signal to obtain a read result of the data read operation related to the fourth sampling instruction. 19. The data transmission method according to claim 10, characterized in that recording the identifier of the delay code used in each data read operation according to the reading result corresponding to each data read operation comprises: For any data read operation, when it is determined that the read result is the same as the preset read result, the delay code used to perform the data read operation is recorded as the zeroth identifier, and when it is determined that the read result is different from the preset read result, the delay code used to perform the data read operation is recorded as the first identifier. 20. The data transmission method according to claim 10, wherein the using the target delay code to perform the data processing operation comprises: According to the delay duration corresponding to the target delay code, a clock signal corresponding to the transmission mode type is delayed to perform a data read operation. 21. A data transmission device, comprising: The first processing unit is configured to execute multiple data processing operations, and based on the execution results of each data processing operation, record the identifier of the delay code used in each data processing operation; the identifier includes a zeroth identifier that identifies the delay code used in the data processing operation as available when the data processing operation is successfully executed, and a first identifier that identifies the delay code used in the data processing operation as unavailable when the data processing operation fails to execute; and according to the identifier selection signal, the delay code corresponding to the selected zeroth identifier is used as the target delay code to execute the data processing operation; The second processing unit is configured to select at least one zeroth identifier from the multiple consecutive zeroth identifiers when it is determined that there are multiple consecutive zeroth identifiers in the recorded identifiers, and generate a corresponding identifier selection signal, wherein the identifier selection signal includes a delay code corresponding to the selected zeroth identifier. 22. The data transmission device according to claim 21, characterized in that the data processing operation comprises a data writing operation; The first processing unit comprises: A first delay module is configured to perform multiple delay processing on the clock signal according to the delay durations corresponding to the multiple delay codes, wherein one data write operation uses a delay duration corresponding to one delay code to perform one delay processing on the clock signal, and the delay durations corresponding to the different delay codes are different; The first processing module is configured to obtain verification information corresponding to each data write operation after executing the data write operation under each delay processing of the clock signal, and the verification information is used to determine whether the data write operation can be successfully executed; and according to the verification information corresponding to each data write operation, record the identifier of the delay code used for each data write operation. 23. The data transmission device according to claim 22, characterized in that the first delay module comprises: a plurality of first delay devices, a first logic operator and a first selector, wherein: A plurality of the first delay devices are connected in sequence, wherein a first end of a first delay device among the plurality of the first delay devices is suitable for inputting a clock signal, an output end of a last first delay device among the plurality of the first delay devices is connected to a first end of the first logic operator, and a second end of each first delay device among the plurality of the first delay devices is connected to a second end of the first selector; The first end of the first selector is adapted to input a first control signal, and generate a corresponding first selection signal according to the first control signal, wherein the first selection signal is used to control the number of first delay devices with a delay function enabled when selecting to perform a data write operation; The second end of the first logic operator is suitable for inputting a second control signal, and the output end thereof is suitable for outputting a clock signal after delay processing to the first processing module, wherein the second control signal is used to control the output timing of the clock signal after delay processing. 24. The data transmission device according to claim 23 is characterized in that the delay durations corresponding to the first delay devices are the same. 25. The data transmission device according to claim 22 is characterized in that the first processing unit further comprises: a mode selection module, coupled to the first delay module, and configured to control the working state of the first delay module in response to a mode selection signal. 26. The data transmission device according to claim 21, wherein the data processing operation comprises a data read operation; The first processing unit comprises: a second processing module, configured to determine a transmission mode type for performing multiple data read operations; and after performing a data read operation under each delay processing of a clock signal corresponding to the transmission mode type, obtain a reading result corresponding to each data read operation, wherein the reading result is used to determine whether the data read operation is successfully performed when in the transmission mode type, and record an identifier of a delay code used for each data read operation according to the reading result corresponding to each data read operation; The second delay module performs multiple delay processing on the clock signal corresponding to the transmission mode type according to the delay lengths corresponding to the multiple delay codes, wherein a data read operation uses a delay length corresponding to a delay code to perform a delay processing on the clock signal corresponding to the transmission mode type, and the delay lengths corresponding to the delay codes are different. 27. The data transmission device according to claim 26, characterized in that the second delay module comprises a plurality of second delay devices, a second logic operator and a second selector, wherein: A plurality of second delay devices are connected in sequence, wherein a first end of a first second delay device among the plurality of second delay devices is suitable for inputting a clock signal corresponding to the transmission mode type, an output end of a last second delay device among the plurality of second delay devices is connected to a first end of the second logic operator, and a second end of each second delay device among the plurality of second delay devices is connected to a second end of the second selector; The first end of the second selector is adapted to input a third control signal, and generate a corresponding second selection signal according to the third control signal, wherein the second selection signal is used to control the number of second delay devices with a delay function enabled when selecting to perform a data read operation; The second end of the second logic operator is suitable for inputting a fourth control signal, and the output end thereof is suitable for outputting a clock signal corresponding to the transmission mode type after delay processing to the second processing module, wherein the fourth control signal is used to control the output timing of the clock signal corresponding to the transmission mode type after delay processing. 28. A host, characterized in that it comprises: at least one processor and at least one memory, wherein the memory stores one or more computer executable instructions, and the processor calls the one or more computer executable instructions to execute the data transmission method according to any one of claims 1 to 20. 29. A storage medium, characterized in that the storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the data transmission method according to any one of claims 1 to 20 is implemented.