CN118155682A - Memory, data reading method, chip system and electronic equipment - Google Patents

Abstract

The embodiment of the application provides a memory, a data reading method, a chip system and electronic equipment. The memory cell array includes memory cells. The memory cells are coupled through a read bitline pre-read circuit. The data voltage of the read bit line is charged to a first voltage value by the bit line charging circuit. When the voltage value of the data voltage is at the first voltage value, the bit line discharging circuit discharges the voltage value of the data voltage to a second voltage value, and the second voltage value is larger than the reading value comparison voltage of the reading circuit. Then in the stage of reading the stored data, when the value of the data in the memory cell corresponds to a low level, the data voltage is reduced from the second voltage value to below the read value comparison voltage, and the reading speed of the memory cell is faster due to the smaller difference value between the second voltage value and the read value comparison voltage, so that the reading speed of the memory is improved.

Description

A memory, data reading method, chip system and electronic device

Technical Field

The present application relates to the technical field of computer data storage, and in particular to a memory, a data reading method, a chip system and an electronic device.

Background technique

The memory includes a storage unit and a read circuit. The read circuit can be used to perform a data read operation to obtain the value of the data stored in the storage unit. Depending on the type of storage unit, the data read operation can be divided into single-end read and double-end read. Double-end read is: each read circuit is set with two read bit lines. One of the read bit lines is used to obtain a data voltage, and the magnitude of the data voltage is used to indicate the value of the data stored in the storage unit. The other bit line is used to obtain a reference voltage. The read circuit can obtain the value of the data stored in the storage unit by comparing the magnitude of the data voltage and the reference voltage. Single-end read is: each read circuit is set with a read bit line. The read bit line is used to output the data voltage. The read circuit determines the value of the data stored in the storage unit according to the magnitude of the voltage value of the data voltage.

In actual applications, different voltage values of the data voltage are used to represent the values of the data stored in the storage unit. In the implementation of dual-end reading, the recognition accuracy of different voltage values of the data voltage is tens of millivolts (mV). That is, in the dual-end reading mode, the setting span of different voltage values of the data voltage is between tens of millivolts (mV) and hundreds of millivolts, which can realize the reading of different values of the data. In the implementation of single-end reading, the recognition accuracy of different voltage values of the data voltage is several volts (V). That is, in the implementation of single-end reading, a larger data voltage needs to be applied to the read bit line. And a larger data voltage will reduce the read rate of the memory.

Summary of the invention

The embodiments of the present application provide a memory, a data reading method, a chip system and an electronic device, which improve the reading rate of the memory based on single-end reading when reading data.

To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

In a first aspect, a memory is provided, which includes: a memory cell array, a read bit line, a read circuit and a bit line discharge circuit; the memory cell array includes memory cells and; the memory cells are coupled to the input end of the read circuit through the read bit line; the bit line discharge circuit includes a first transistor; the first electrode of the first transistor is coupled to the read bit line; the gate of the first transistor is used to input a first control signal; and the first control signal is used to control the first transistor to be turned on or off.

In an embodiment of the present application, when data is read from the storage cell, it is divided into two stages: a bit line precharge stage and a storage data reading stage. In the bit line precharge stage, the data voltage of the read bit line is charged to a first voltage value. In the storage data reading stage, the storage cell is turned on, and the voltage value of the storage voltage in the storage cell is different, and the voltage value of the data voltage on the read bit line is also different. The reading circuit determines the value of the data indicated by the storage voltage in the storage cell according to the voltage value of the data voltage on the current read bit line. When the value of the data in the storage cell is 0, the data voltage needs to drop from the first voltage value to below the high and low level flip voltage, and the reading circuit can determine that the value of the data in the storage cell is 0. Because the difference between the first voltage value and the high and low level flip voltage is large, a longer discharge time is required to make the data voltage drop below the high and low level flip voltage. This will lead to a decrease in the reading rate of the memory. In the embodiment of the present application, the second electrode of the first transistor is grounded or connected to a negative voltage in the bit line precharge stage. When the voltage value of the data voltage is after the first voltage value, the first transistor is controlled to be turned on so that the first electrode of the first transistor and the second electrode of the first transistor are turned on, thereby causing the positive charge on the read bit line to flow from the first electrode of the first transistor to the second electrode of the first transistor to discharge the read bit line. The discharge time can be controlled by controlling the conduction time of the first transistor through the first control signal. The voltage value of the data voltage on the read bit line is discharged from the first voltage value to the second voltage value by controlling the discharge time.

The voltage value of the data voltage is discharged to a second voltage value through the bit line discharge circuit, and the second voltage value is greater than the high-low level flip voltage. Then, in the stage of reading the stored data, when the value of the data in the storage cell is 0, the data voltage drops from the second voltage value to below the high-low level flip voltage. Since the difference between the second voltage value and the high-low level flip voltage is small, the reading speed of the storage cell is faster, thereby improving the reading rate of the memory.

In one possible implementation, the bit line discharge circuit includes a first transistor, a second transistor and an energy storage unit; the first electrode of the first transistor is coupled to the read bit line; the second electrode of the first transistor is coupled to the first end of the energy storage unit; the second end of the energy storage unit is coupled to the first electrode of the second transistor; the second electrode of the second transistor is grounded or connected to a negative voltage; the gate of the first transistor is used to input a first control signal; the gate of the second transistor is used to input a second control signal; the first control signal is used to control the first transistor to be turned on or off, and the second control signal is used to control the second transistor to be turned on or off.

In an embodiment of the present application, the positive charge on the read bit line is stored by the energy storage unit to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value. At this time, the first transistor is turned on by the first control signal, so that the read bit line and the energy storage unit are connected, and the energy storage unit stores the positive charge on the read bit line. When the energy storage unit stores the maximum storage amount, the positive charge on the read bit line is no longer stored. By controlling the maximum storage amount of the energy storage unit, the discharge amount of the read bit line can be controlled. When the read bit line does not need to be discharged, the first transistor is turned off. When the positive charge stored in the storage unit reaches the maximum storage amount, the second control signal can be used to turn on the second transistor, and the positive charge stored in the energy storage unit is released by the turned-on second transistor, thereby clearing the charge storage space of the energy storage unit, so that in the next cycle, the energy storage unit can normally store the positive charge on the read bit line.

In a possible implementation, the energy storage unit includes a metal line coupling capacitor; the second electrode of the first transistor is coupled to the first electrode of the metal line coupling capacitor; the second electrode of the metal line coupling capacitor is coupled to the first electrode of the second transistor.

In the embodiment of the present application, a metal line coupling capacitor is formed by the second electrode of the first transistor and the metal line between the second transistor, and the capacitance value of the metal line coupling capacitor is used as the maximum charge storage capacity of a single discharge.

In one possible embodiment, the metal wire coupling capacitor includes a first winding metal wire and a second winding metal wire; the first winding metal wire is the first pole of the metal wire coupling capacitor, and the second winding metal wire is the second pole of the metal wire coupling capacitor; the total length of the first winding metal wire and the total length of the second winding metal wire respectively correspond to the number of storage cells coupled to the read bit line.

In an embodiment of the present application, two mutually insulated metal plates or metal wires can constitute a capacitor. In an embodiment of the present application, a metal wire coupling capacitor can be constituted by forming two poles of a metal wire coupling capacitor through a first winding metal wire and a second winding metal wire respectively. In a specific application, the number of storage units coupled to a single read bit line is different, and the load size on the read bit line is also different. In the circuit design stage, a metal wire coupling capacitor with a corresponding capacitance value is designed according to the load size of the read bit line. When the metal wire coupling capacitor includes a first winding metal wire and a second winding metal wire, the capacitance value of the metal wire coupling capacitor can be adjusted by controlling the capacitance value of each section of the winding metal wire, and controlling the total length of the first winding metal wire and the total length of the second winding metal wire. For example, the number of winding metal wires in each section of the metal wire coupling capacitor is set to correspond to the number of storage units of a single read bit line.

In a possible implementation, the memory further includes a metal layer; the first winding metal wire and the second winding metal wire are arranged in the metal layer.

In the embodiments of the present application, in the chip manufacturing process, it can generally be divided into the front end of line (FEOL) and the back end of line (BEOL). In the front end process, etching and other processing operations are performed on the wafer through the front end mask to generate basic circuits composed of transistors, such as the bit line charging circuit, reading circuit, bit line discharge circuit, memory cell array, etc. in the above embodiments. Then in the back end process, multiple metal layers are etched on the generated basic circuit through the back end mask, and metal traces are pulled out through different metal layers to complete the electrical connection between the inside and the inside of the integrated circuit, and/or between the inside and the outside. In the designed back end mask, multiple metal layers may be included, but only some of the metal layers in the multiple metal layers are used for the above electrical connection. We can define the metal layers used for connection as connecting metal layers. Some metal layers may be in a vacant state. We define these vacant metal layers as vacant metal layers. Take a memory design layout including four metal layers as an example, wherein the metal layers of the first and second layers are used to realize electrical connection, while the spare metal layers of the third layer and the spare metal layers of the fourth layer are not used for electrical connection. At this time, each section of winding metal wire can be set corresponding to the position above each storage unit on the spare metal layer of the third layer and/or the fourth layer, and these winding metal wires are connected and coupled to the first transistor and the second transistor as metal wire coupling capacitors. In an embodiment of the present application, if a metal wire coupling capacitor is set in the front-end process BEOL, because the metal wire coupling capacitor needs to have a certain capacitance value, a large number of metal wires need to be wound to obtain a coupling capacitor with the capacitance value, which will occupy a large amount of layout area of the chip, resulting in an increase in the actual chip area of the memory. Therefore, by setting a winding metal wire on the spare metal layer above the storage unit, there is no need to additionally design the layout area of the winding metal wire, which can save the chip area of the memory and make the chip layout of the memory more compact. The first winding metal wire and the second winding metal wire may form a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor according to different arrangements in the metal layer.

In a possible implementation, the energy storage unit further includes at least one adjustable capacitor group; an adjustable capacitor group includes a third transistor and a first capacitor; the first electrode of the third transistor is coupled to the metal wire coupling capacitor; and the second electrode of the third transistor is coupled to the first capacitor.

In the embodiment of the present application, in actual application, due to differences in production processes, etc., there may be differences in the load size of different read bit lines. Therefore, when the metal wire coupling capacitor is discharged through the manufactured metal wire coupling capacitor, the capacitance value of the metal wire coupling capacitor may not be able to adapt to the data voltage of all read bit lines to the second voltage value. It can be seen from the above embodiment that the second voltage value needs to meet the flip voltage greater than the high and low levels to ensure that there will be no interference in the reading and storage data stage. Therefore, if the capacitance value of the metal wire coupling capacitor is set larger, the winding metal wire is designed according to the larger capacitance value, and then the production is carried out. Then for multiple read bit lines in the memory cell array, after the metal wire coupling capacitor is discharged, the voltage value of the data voltage may be lower than the flip voltage of the high and low levels, or it may be close to the flip voltage of the high and low levels but still greater than the flip voltage of the high and low levels, or it may be lower than the flip voltage of the high and low levels. When the voltage value of the data voltage after discharge is greater than the flip voltage of the high and low levels, the impact of different voltage differences is the inconsistency of the discharge speed in the next reading and storage data stage. However, when the voltage value of the data voltage after discharge is equal to or less than the high-low level flip voltage, the data read in the subsequent stage of reading the stored data is unreliable. Based on this situation, the capacitance value of the metal line coupling capacitor can be set to be slightly smaller than the ideal value (the ideal value is to satisfy all read bit lines so that the second voltage value after discharge is just slightly greater than the theoretical value of the high-low level flip voltage) to ensure that after the metal line coupling capacitor is discharged, the voltage value of all read bit lines is greater than the high-low level flip voltage. Then, according to the actual load size of each read bit line, the third transistor in at least one adjustable capacitor group on each read bit line can be controlled to be turned on or off to achieve adaptive adjustment of the discharge amount of the bit line discharge circuit corresponding to each read bit line.

Optionally, the first electrode of the third transistor may be coupled to the input end of the metal line coupling capacitor, may be coupled to the output end of the metal line coupling capacitor, or may be coupled to the middle metal line of the metal line coupling capacitor.

In an embodiment of the present application, in the bit line pre-charging stage, when it is necessary to discharge the read bit line through the bit line discharge circuit, the first transistor is turned on and the second transistor is turned off. For a certain adjustable capacitor group, when the corresponding third transistor is turned on: if the first electrode of the third transistor is coupled to the input end of the metal wire coupling capacitor, when the first electrode of the third transistor is coupled to the input end of the metal wire coupling capacitor, the metal wire coupling capacitor is connected in parallel with the first capacitor, and the positive charge on the read bit line can be stored in the metal wire coupling capacitor and the first capacitor at the same time through the turned-on first transistor. If the first electrode of the third transistor is coupled to the output end of the metal wire coupling capacitor, when the first electrode of the third transistor is coupled to the output end of the metal wire coupling capacitor, the metal wire coupling capacitor and the first capacitor are in series, and the positive charge on the read bit line can be transmitted to the first capacitor through the metal wire coupling capacitor through the turned-on first transistor. If the first electrode of the third transistor is coupled to the middle metal wire of the metal wire coupling capacitor, the metal wire coupling capacitor includes a winding metal wire, and the first electrode of the third transistor is coupled between the winding metal wires, when the first transistor is turned on and the second transistor is turned off, the first capacitor is connected in series with part of the winding metal wire and in parallel with part of the winding metal wire. The above three methods are all possible implementation methods of the embodiments of the present application. The read bit line is discharged so that the voltage value of the data voltage on the read bit line drops to a second voltage value. The magnitude of the second voltage value is determined by the amount of charge that can be stored in the bit line discharge circuit. The amount of charge that can be stored in the bit line discharge circuit is mainly determined by the capacitance value of the metal line coupling capacitor. In addition, by turning on the third transistor, the first capacitor in the corresponding first adjustable capacitor group can be turned on with the metal line coupling capacitor, thereby adjusting the amount of charge that can be stored in the bit line discharge circuit. When the on state or off state of the third transistor is fixed, the capacitance that can be stored in the bit line discharge circuit is consistent, and its size is equal to the sum of the capacitance value of the metal line coupling capacitor and the capacitance value of the first capacitor corresponding to the turned-on third transistor. Under the above three different connection structures, what is affected is the speed at which the bit line discharge circuit stores and releases charges. In the embodiment of the present application, the corresponding connection structure can be adaptively selected according to the cycle length of the bit line pre-charging stage and the stage of reading and storing data.

In one possible implementation, the bit line discharge circuit further includes a switch control circuit; the switch control circuit is coupled to the gate of the first transistor and the gate of the second transistor respectively; the switch control circuit is used to output a first control signal to the gate of the first transistor and to output a second control signal to the gate of the second transistor; the first control signal is used to control the first transistor to be turned on or off, and the second control signal is used to control the second transistor to be turned on or off.

In an embodiment of the present application, a first control signal and a second control signal are respectively output to the gate of the first transistor and the gate of the second transistor by a switch control circuit, so that the first transistor and the second transistor are cross-conducted. In the case of such cross-conduction, the first transistor is turned on by the first control signal, and the second transistor is turned off by the second control signal, and the positive charge on the read bit line flows into the bit line discharge circuit. At this time, the second transistor is in the off state, and the positive charge stored in the bit line discharge circuit will not be released, so as to ensure that the storage capacity of the bit line discharge circuit can just reduce the voltage value of the data voltage to the second voltage value. After the discharge is completed, the first transistor is turned off by the first control signal, and the second transistor is turned on by the second control signal. At this time, the bit line discharge circuit is continuously discharged by the second transistor to ensure that the positive charge stored in the bit line discharge circuit is completely released, thereby ensuring that in the subsequent discharge process, the bit line discharge circuit has enough storage capacity to continue to store the positive charge on the read bit line.

In one possible implementation, the switch control circuit includes a NAND gate and a first inverter; the output end of the first inverter is respectively coupled to the first input end of the NAND gate and the gate of the second transistor, and the output end of the first inverter is used to output the second control signal; the second input end of the NAND gate is used to input an enable signal; the output end of the NAND gate is coupled to the gate of the first transistor; and the output end of the NAND gate is used to output the first control signal.

In the embodiment of the present application, if the first transistor and the second transistor are transistors of the same type (for example, both are P-type metal-oxide-semiconductor transistors, or both are N-type metal-oxide-semiconductor transistors, etc.), the first control signal and the second control signal can be set to opposite levels to achieve cross coupling between the first transistor and the second transistor. By using a switch control circuit including a NAND gate and a first inverter, the output first control signal and the second control signal can be constantly output as control signals of opposite levels.

In a possible implementation, the memory further includes an output buffer circuit; an input end of the output buffer circuit is coupled to an output end of the read circuit; and the output buffer circuit is used to periodically latch data output by the read circuit.

In the embodiment of the present application, the data output by the reading circuit is latched and buffered by the output buffer circuit, so that the data output by the reading circuit can be periodically obtained from the output buffer circuit, thereby avoiding the data output by the reading circuit having no timeliness and distinction, causing reading confusion, etc.

In one possible implementation, the output buffer circuit includes a first charging circuit, a high-level holding circuit and a latch; the input end of the latch is the input end of the output buffer circuit, and the input end of the latch is coupled to the output end of the reading circuit; the output end of the first charging circuit and the holding end of the high-level holding circuit are respectively coupled to the input end of the latch; the first charging circuit is used to output a high-level voltage to the output end of the reading circuit.

In an embodiment of the present application, in the bit line pre-charging stage, a charging voltage is outputted through the first charging circuit, so that the first electrode of the sixth transistor and the first electrode of the latch are at a high level. When the sixth transistor is turned on, the charging voltage outputted by the first charging circuit flows into the second electrode of the sixth transistor to pull down the voltage of the first electrode of the sixth transistor. When the sixth transistor is turned off, the first electrode of the sixth transistor is always kept at a high level through a high level holding circuit, a high level is inputted to the input end of the latch, the high level is latched and buffered, and then outputted.

In one possible implementation, the latch includes a clock control circuit and a latch circuit; the clock control circuit includes two cascaded fourth inverters; the latch circuit includes three cascaded fifth inverters; the input end of the fifth inverter of the first stage serves as the input end of the latch; the output end of the fifth inverter of the third stage serves as the output end of the latch; the output end of the fourth inverter of the first stage is coupled with the first voltage end of the fifth inverter of the first stage and the first voltage end of the fifth inverter of the third stage; the output end of the fourth inverter of the second stage is also coupled with the second voltage end of the fifth inverter of the first stage and the second voltage end of the fifth inverter of the third stage.

In an embodiment of the present application, the fifth inverter of the first stage and the third stage are controlled not to work by the clock control circuit to realize the input level signal is locked in the fifth inverter of the second stage. And the fifth inverter of the first stage and the fifth inverter of the third stage are controlled to work by the clock control circuit to realize the output of the level signal locked in the fifth inverter of the second stage. The clock control circuit realizes that the level between the output signal of the fourth inverter of the first stage and the output signal of the fourth inverter of the second stage is always opposite through two cascaded fourth inverters. By inputting different levels of the fourth inverter of the first stage, the fifth inverter of the first stage and the fifth inverter of the third stage can be controlled to work or not work.

In a possible implementation manner, the output buffer circuit further includes a second inverter; an input terminal of the second inverter is coupled to an output terminal of the latch.

In the embodiment of the present application, the data output by the output buffer circuit is inverted by the second inverter.

In one possible implementation, the reading circuit includes a third inverter and a sixth transistor; the input end of the third inverter is the input end of the reading circuit, and the input end of the third inverter is coupled to the reading bit line; the output end of the third inverter is coupled to the gate of the sixth transistor; the second pole of the sixth transistor is grounded or connected to a negative voltage; the first pole of the sixth transistor is the output end of the reading circuit.

In the embodiment of the present application, the sixth transistor is an NMOS transistor as an example. In the reading and storage stage, the voltage value of the data voltage on the read bit line is obtained by the third inverter. When the voltage value is higher than the high-low level flip voltage, the third inverter outputs a low level to the gate of the sixth transistor (NMOS transistor) to control the sixth transistor to turn off. When the voltage value is lower than the high-low level flip voltage, the third inverter outputs a high level to the gate of the sixth transistor (NMOS transistor) to control the sixth transistor to turn on. The second pole of the sixth transistor is connected to the ground voltage or negative voltage, so that when the sixth transistor is turned on and off, the voltage value of the first pole of the sixth transistor is different, and the voltage value of the first pole of the sixth transistor is used to indicate the value of the data in the storage unit. For example, when the first pole of the sixth transistor is a high level, the value of the data in the storage unit is indicated to be 1; when the first pole of the sixth transistor is a low level, the value of the data in the storage unit is indicated to be 0.

In a possible implementation, the memory further includes a state holder, and the state holder further includes at least one fifth transistor; the at least one fifth transistor is coupled to the first electrode of the fourth transistor, and the at least one fifth transistor is connected in series with the fourth transistor.

In an embodiment of the present application, during the stage of reading stored data, a floating signal may exist on the read bit line, causing interference to the read data. The output end of the third inverter is coupled to the gate of the fourth transistor. When the output end of the third inverter outputs a low level, the fourth transistor is turned on, and a certain value of holding current is input to the data bit line through the fourth transistor to prevent the generation of a floating signal. The current value of the current input by the fourth transistor needs to be set relatively small, generally less than the degree that the third inverter can recognize and read, so as to avoid interference with the read data of the third inverter.

In a possible implementation, the state holder further includes at least one fifth transistor; the at least one fifth transistor is coupled to the first electrode of the fourth transistor, and the at least one fifth transistor is connected in series with the fourth transistor.

In the embodiment of the present application, the number of the fifth transistor can be one or more, and the fifth transistor is connected in series with the fourth transistor. The fifth transistor is controlled to be always turned on. The stability of the state holder can be increased by setting the fifth transistor.

In a possible implementation, the memory further includes a bit line charging circuit; the bit line charging circuit is coupled to the read bit line.

In the embodiment of the present application, in the bit line precharging stage, the read bit line is charged by the bit line charging circuit so that the voltage value of the data voltage on the read bit line is the first voltage value.

In some possible implementations, the bit line charging circuit includes a seventh transistor. A first electrode of the seventh transistor is used to input a charging voltage, and a second electrode of the seventh transistor is coupled to the read bit line. A gate of the seventh transistor is used to input a first charging control signal, and the first charging control signal is used to control the seventh transistor to turn on, so as to charge the read bit line.

In the embodiment of the present application, the charging voltage is input through the first electrode of the seventh transistor. When the first control signal controls the seventh transistor to be turned on, the charging voltage is conducted from the first electrode of the seventh transistor to the second electrode of the seventh transistor, and is output from the second electrode of the seventh transistor to the read bit line, thereby realizing charging of the read bit line.

Exemplarily, by setting the voltage value of the charging voltage to a first voltage value, it is possible to charge the voltage value of the data voltage on the read bit line to the first voltage value through the charging voltage.

In some possible implementations, all memory cells in the memory cell array are single-end read memory cells.

In an embodiment of the present application, when all memory cells in the memory cell array are single-ended read memory cells, the read word line coupled to each memory cell is correspondingly provided with the read circuit, bit line charging circuit and bit line discharging circuit described in the above embodiment.

In some possible implementations, a portion of the memory cells in the memory cell array are single-end read memory cells, and another portion of the memory cells are double-end read memory cells.

In the embodiment of the present application, the read circuit, the bit line discharge circuit and the bit line charging circuit described in the above embodiment are arranged on the read bit line coupled to the single-end read type memory cell. The corresponding read bit line is discharged by the bit line discharge circuit, thereby improving the read rate of the single-end read type memory cell, so as to improve the read rate of the memory.

In some possible implementations, when the memory cell is a dual-terminal read memory cell, the memory cell may be a memory cell including six transistors.

Exemplarily, when the memory cell is a dual-end read memory cell, the memory cell array includes a memory cell, a word line, and a bit line. Each bit line includes a first bit line and a second bit line. The six transistors are respectively a first conduction transistor, a second conduction transistor, a first storage transistor, a second storage transistor, a third storage transistor, and a fourth storage transistor. The first storage transistor and the third storage transistor are PMOS transistors. The first conduction transistor, the second conduction transistor, the second storage transistor, and the fourth storage transistor are NMOS transistors. The reading circuit includes a readout amplifier. Wherein: the first electrode of the first conduction transistor is coupled to the first bit line. The second electrode of the first conduction transistor is respectively coupled to the second electrode of the first storage transistor, the first electrode of the second storage transistor, the gate of the third storage transistor, and the gate of the fourth storage transistor to the first storage point. The gate of the first conduction transistor is coupled to the word line. The first electrode of the second conduction transistor is coupled to the second bit line. The second electrode of the second conduction transistor is respectively coupled to the second electrode of the third storage transistor, the first electrode of the fourth storage transistor, the gate of the first storage transistor, and the gate of the second storage transistor to the second storage point. The gate of the second conduction transistor is coupled to the word line. The first bit line and the second bit line are both coupled to the bit line charging circuit and the readout amplifier.

In the embodiment of the present application, the value indicated by the storage voltage of the first storage point is opposite to the value indicated by the storage voltage of the second storage point. The value indicated by the storage voltage of the first storage point is used as the value of the data stored in the storage unit 21. The specific operation of reading data in the two-terminal read storage unit including six transistors is as follows:

1. Bit line precharge stage: The word line is not charged, so that the first conduction transistor (NMOS transistor) and the second conduction transistor (NMOS transistor) are turned off by the low level. Then the first bit line and the second bit line are precharged by the bit line charging circuit, so that when the first conduction transistor (NMOS transistor) and the second conduction transistor (NMOS transistor) are turned off, the voltage value of the data voltage on the first bit line and the data voltage on the second bit line is the first voltage value.

2. Reading the stored data phase: charging the word line so that the first conduction transistor (NMOS transistor) and the second conduction transistor (NMOS transistor) are turned on by the high level. The readout amplifier determines the value indicated by the storage voltage of the first storage point by comparing the data voltage on the first bit line and the data voltage on the second bit line at this time, and then determines the value of the data stored in the storage unit. The specific determination method is: if the value of the data corresponding to the storage voltage at the first storage point is 1, and the value corresponding to the storage voltage at the second storage point is 0, then the storage voltage at the first storage point is higher than the storage voltage at the second storage point. Because the storage voltage at the second storage point is lower than the first voltage value, it will pull down the data voltage at the second bit line, thereby causing the data voltage on the second bit line to be lower than the data voltage on the first bit line. At this time, the readout amplifier compares the voltage value of the data voltage on the first bit line and the data voltage on the second bit line. The voltage value of the data voltage on the first bit line is greater than the voltage value of the data voltage on the second bit line. Then it can be determined that the value of the data corresponding to the storage voltage at the first storage point corresponding to the first bit line is 1 (that is, the value of the data in the storage unit is 1). If the value of the data corresponding to the storage voltage at the first storage point is 0, and the value of the storage voltage at the second storage point is 1, then the storage voltage at the first storage point is lower than the storage voltage at the second storage point. Because the storage voltage at the first storage point is lower than the first voltage value, the data voltage at the first bit line will be pulled down, which will cause the data voltage on the first bit line to be lower than the data voltage on the second bit line. At this time, the read amplifier compares the voltage values of the data voltage on the first bit line and the data voltage on the second bit line. The voltage value of the data voltage on the first bit line is less than the voltage value of the data voltage on the second bit line. It can be determined that the value of the data corresponding to the storage voltage at the first storage point corresponding to the first bit line is 0 (that is, the value of the data in the storage cell is 0).

In some possible implementations, when the memory cell is a single-end read memory cell, the memory cell may be a memory cell including eight transistors, or a memory cell including one transistor.

Exemplarily, when the memory cell is a memory cell including eight transistors. Each word line includes a write word line (write wordline, WWL) and a read word line (read wordline, RWL). Each bit line includes a first write bit line, a second write bit line, and a read bit line. The eight transistors are respectively a first conduction transistor, a second conduction transistor, a third conduction transistor, a fourth conduction transistor, a first storage transistor, a second storage transistor, a third storage transistor, and a fourth storage transistor. The first storage transistor and the third storage transistor are PMOS transistors. The first conduction transistor, the second conduction transistor, the third conduction transistor, the fourth conduction transistor, the second storage transistor, and the fourth storage transistor are NMOS transistors. The reading circuit includes a third inverter and a sixth transistor. Wherein:

The first electrode of the first pass transistor is coupled to the first write bit line. The second electrode of the first pass transistor is respectively coupled to the second electrode of the first storage transistor, the first electrode of the second storage transistor, the gate of the third storage transistor and the gate of the fourth storage transistor to the first storage point. The gate of the first pass transistor is coupled to the write word line. The first electrode of the second pass transistor is coupled to the second write bit line. The second electrode of the second pass transistor is respectively coupled to the second electrode of the third storage transistor, the first electrode of the fourth storage transistor, the gate of the first storage transistor and the gate of the second storage transistor to the second storage point. The gate of the second pass transistor is coupled to the write word line. The gate of the third pass transistor is coupled to the second storage point. The second electrode of the third pass transistor is grounded or connected to a negative voltage. The first electrode of the third pass transistor is coupled to the second electrode of the fourth pass transistor. The gate of the fourth pass transistor is coupled to the read word line. The first electrode of the fourth pass transistor is coupled to the read bit line. The input end of the bit line charging circuit, the bit line discharging circuit and the third inverter are all coupled to the read bit line. The output end of the third inverter is coupled to the gate of the sixth transistor.

In the embodiment of the present application, a single-ended read storage unit is used, and the operation of reading data is as follows:

1. Bit line precharge stage: The read word line is not charged, so that the fourth conduction transistor (NMOS transistor) is turned off by the low level. Then the read bit line is precharged by the bit line charging circuit, so that when the fourth conduction transistor is turned off, the voltage value of the data voltage on the read bit line is the first voltage value.

2. Bit line discharge stage: the read bit line is discharged through the bit line discharge circuit, so that the voltage value of the data voltage of the read bit line is equal to the second voltage value.

3. Memory cell conduction stage: charging the read word line to conduct the fourth conduction transistor (NMOS transistor), so that the memory cell is connected to the read bit line.

4. Reading the stored data phase: Determine whether to turn on the third conduction transistor according to the voltage value of the storage voltage at the second storage point. Depending on whether the third transistor is turned on or not, the data voltage on the read bit line presents different voltage values. Then the third inverter determines the value of the data in the storage cell according to the voltage value of the data voltage on the read bit line. The specific determination method is:

When the value of the data corresponding to the storage voltage at the first storage point is 0, and the value corresponding to the storage voltage at the second storage point is 1. The storage voltage at the second storage point is at a high level, so that the third conduction transistor (NMOS transistor) is turned on. Then the turned-on third conduction transistor and the turned-on fourth conduction transistor make the second electrode of the third conduction transistor conductive with the read bit line, and the ground voltage or negative voltage at the second electrode of the third conduction transistor will pull down the data voltage on the read bit line, so that the voltage value of the data voltage is lower than the high-low level flip voltage. The high-low level flip voltage is the working point of the third inverter. For a voltage whose voltage value is higher than the high-low level flip voltage, the third inverter determines it as a high-level voltage; conversely, for a voltage whose voltage value is lower than the high-low level flip voltage, the third inverter determines it as a low-level voltage. The reading circuit uses the third inverter to read the data voltage on the read bit line. At this time, the data voltage is lower than the high-low level flip voltage. The third inverter inputs a low level, and the third inverter outputs a high level to the gate of the sixth transistor (NMOS transistor). The sixth transistor is turned on, and the ground voltage or negative voltage at the second pole of the sixth transistor pulls the voltage at the first pole of the sixth transistor down to a low level. At this time, the voltage value at the first pole of the sixth transistor is 0, which is used to indicate that the data value corresponding to the storage voltage of the first storage point is 0 (that is, the data value in the storage unit is 0).

When the value of the data corresponding to the storage voltage at the first storage point is 1, and the value of the storage voltage at the second storage point is 0. The storage voltage at the second storage point is at a low level, so that the third conduction transistor (NMOS transistor) is turned off. Because the third conduction transistor is turned off, the second electrode of the third conduction transistor is also turned off from the read bit line, and the data voltage on the read bit line is between the second voltage value and the first voltage value. The third inverter reads the data voltage on the read bit line. At this time, the voltage value of the data voltage is higher than the high-low level flip voltage. The third inverter inputs a high level, then the third inverter outputs a low level to the gate of the sixth transistor (NMOS transistor), and the sixth transistor is turned off. The voltage of the first electrode of the sixth transistor remains at a high level state. At this time, the value of the voltage value at the first electrode of the sixth transistor is 1, which is used to indicate that the value of the data corresponding to the storage voltage of the first storage point is 1 (that is, the value of the data in the storage unit is 1).

In an embodiment of the present application, when the storage cell is a single-ended read type storage cell, the read circuit uses a third inverter to read the data voltage on the read bit line. The voltage value of the storage voltage at the second storage point is different, and there are two situations: turning on the third conduction transistor, or turning off the third conduction transistor. The voltage value of the data voltage on the read bit line is different in the two situations, and the value of the data indicated by the storage voltage at the second storage point is obtained according to the voltage value of the data voltage. Because the value of the data indicated by the storage voltage at the first storage point and the value indicated by the storage voltage at the second storage point are opposite values. In an embodiment of the present application, the value of the data at the second storage point can be used as the value of the data stored in the storage cell. The value of the data at the first storage point can also be used as the value of the data stored in the storage cell, and the value of the data at the first storage point can be obtained according to the value of the data at the second storage point.

In the second aspect, an embodiment of the present application also proposes a data reading method, which is applied to a memory; the memory includes a memory cell array, a read bit line and a bit line discharge circuit; the memory cell array includes a memory cell; the memory cell and the bit line discharge circuit are respectively coupled to the read bit line; the method includes: controlling the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value; the second voltage value is greater than the read value comparison voltage; turning on the memory cell and the read bit line; obtaining the data in the memory cell according to the voltage value of the data voltage; when the voltage value of the data voltage is greater than the read value comparison voltage, judging that the value of the data in the memory cell is the first value; when the voltage value of the data voltage is less than the read value comparison voltage, judging that the value of the data in the memory cell is the second value.

Exemplarily, the first value may be 1, and the second value may be 0.

In a possible implementation, the above-mentioned control bit line discharge circuit discharges the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value, including: controlling the discharge time of the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value.

In a possible implementation, the above-mentioned control bit line discharge circuit discharges the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value, including: controlling the discharge amount of the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value.

In one possible implementation, the bit line discharge circuit includes a metal line coupling capacitor; controlling the discharge amount of the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value, including: controlling the bit line discharge circuit to be turned on with the read bit line to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value.

In a possible implementation, the bit line discharge circuit further includes at least one first capacitor; the method further includes: controlling whether each first capacitor is turned on with the metal line coupling capacitor according to a first voltage difference and/or a first quantity to adjust the discharge amount of the bit line discharge circuit; the first voltage difference is the difference between the first voltage value and the read value comparison voltage; the first quantity is the number of storage cells coupled to a single read bit line.

In a possible implementation, the method further includes: controlling the bit line discharge circuit to store the charge on the read bit line by a first control signal; and controlling the bit line discharge circuit to release the charge stored in the bit line discharge circuit by a second control signal.

In a possible implementation, the method further includes: after obtaining the value of the data in the storage unit according to the voltage value of the data voltage, latching and outputting the obtained data in the storage unit.

In a third aspect, an embodiment of the present application further proposes a chip system, which includes a processor and a memory as described in the first aspect above; the processor is used to write data to the memory, read data stored in the memory, or refresh data stored in the memory.

In a fourth aspect, an embodiment of the present application further proposes an electronic device, which includes a chip system and a circuit board as described in the third aspect above, and the chip system is arranged on the circuit board.

For the description of the technical effects of the second, third and fourth aspects mentioned above, reference may be made to the relevant description of the first aspect mentioned above, and no further details will be given here.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

FIG2 is a schematic diagram of the structure of a chip system provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of a dual-end read storage unit provided in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of a single-ended read storage unit provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

FIG8 is a schematic structural diagram of a bit line discharge circuit provided in an embodiment of the present application;

FIG9 is a schematic structural diagram of another bit line discharge circuit provided in an embodiment of the present application;

FIG10 is a schematic diagram of the structure of another bit line discharge circuit provided in an embodiment of the present application;

FIG11 is a schematic diagram of a chip layout of a memory provided in an embodiment of the present application;

FIG12 is a schematic diagram of the structure of another bit line discharge circuit provided in an embodiment of the present application;

FIG13 is a schematic diagram of the structure of another bit line discharge circuit provided in an embodiment of the present application;

FIG14 is a schematic structural diagram of another bit line discharge circuit provided in an embodiment of the present application;

FIG15 is a schematic diagram of the structure of a bit line charging circuit provided in an embodiment of the present application;

FIG16 is a schematic diagram of the structure of a reading circuit and an output buffer circuit provided in an embodiment of the present application;

FIG17 is a schematic diagram of the structure of another output buffer circuit provided in an embodiment of the present application;

FIG18 is a schematic diagram of the structure of a latch provided in an embodiment of the present application;

FIG19 is a schematic diagram of the structure of a state holder provided in an embodiment of the present application;

FIG20 is a schematic diagram of the structure of a memory cell array provided in an embodiment of the present application;

FIG21 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

FIG22 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

FIG23 is a schematic diagram of a flow chart of a data reading method provided in an embodiment of the present application;

FIG24 is a timing diagram of the voltage or level states of various signals when the value of the stored data is 0, provided by an embodiment of the present application;

FIG. 25 is a timing diagram of the voltage or level state of each signal when the value of the stored data is 1, provided in an embodiment of the present application.

Detailed ways

It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the related concepts in a specific way.

The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

First, some basic concepts are explained:

The transistor includes a P-type metal-oxide-semiconductor (PMOS) transistor, an N-type metal-oxide-semiconductor (NMOS) transistor, etc. The gate of the NMOS transistor is subjected to a high level, so that the first and second electrodes of the NMOS transistor are turned on; the gate of the NMOS transistor is subjected to a low level, so that the first and second electrodes of the NMOS transistor are turned off. Conversely, the gate of the PMOS transistor is subjected to a low level, so that the first and second electrodes of the PMOS transistor are turned on; the gate of the PMOS transistor is subjected to a high level, so that the first and second electrodes of the PMOS transistor are turned off.

The embodiment of the present application proposes an electronic device, as shown in FIG1 , the electronic device 1000 includes a chip system 100. As shown in FIG2 , the chip system 100 includes a memory 10 and a processor 20. The processor 20 is used to write data to the memory 10, read data stored in the memory 10, or refresh data stored in the memory 10.

Exemplarily, the electronic device 1000 may be a desktop computer, a laptop computer, a tablet computer, a mobile phone, a smart watch, or the like, which is a device that needs to perform processing operations such as data storage, data reading, or data refreshing.

Exemplarily, the electronic device 1000 further includes a circuit board, and the chip system 100 is arranged on the circuit board.

As shown in FIG3 , the memory 10 includes a peripheral circuit 1 and a memory cell array 2, a plurality of word lines WL and a plurality of bit lines BL. The memory cell array 2 includes a plurality of memory cells 21. Each memory cell 21 is coupled to a corresponding word line WL and a corresponding bit line BL. The peripheral circuit 1 includes a plurality of bit line charging circuits 11 and a plurality of reading circuits 12. Each reading circuit 12 is coupled to a plurality of memory cells 21 on the bit line BL through the bit line BL. Each bit line charging circuit 11 is coupled to a bit line BL.

In the embodiment of the present application, the word line WL can correspond to the row of the memory cell array 2, and the bit line BL can correspond to the column of the memory cell array 2. Then, a corresponding row address can be set for each word line WL, and a corresponding column address can be set for each bit line BL. By combining the row address and the column address, the address of the corresponding memory cell 21 can be determined. The operation of reading the data in a certain memory cell 21 is:

First, the data voltage of the bit line BL corresponding to the row address is precharged to a first voltage value through the bit line charging circuit 11 .

Next, the word line WL corresponding to the column address is precharged to turn on the storage cell 21 from which data needs to be read. A storage voltage is stored in the storage cell 21, and different voltage values of the storage voltage are used to indicate different values of the stored data. The voltage value of the storage voltage in the turned-on storage cell 21 affects the voltage value of the data voltage on the coupled bit line BL, and the voltage value of the data voltage is also different according to the different voltage values of the storage voltage.

Finally, the reading circuit 12 obtains the data voltage on the bit line BL and confirms the value of the data stored in the memory cell according to the data voltage on the bit line BL.

When the data voltage is greater than the read value comparison voltage, the value of the data stored in the storage unit 21 is determined to be the first value; when the data voltage is less than the read value comparison voltage, the value of the data stored in the storage unit 21 is determined to be the second value.

It should be noted that in the embodiment of the present application, the word line WL corresponds to the column address and the bit line BL corresponds to the row address. However, in actual applications, the word line WL may correspond to the row address and the bit line BL may correspond to the column address. The definition of row and column is only used as a self-defined distinguishing name and should not be regarded as a limitation on the structure of the memory cell array 2.

In some possible implementations, the storage unit 21 is a dual-terminal read storage unit.

Exemplarily, as shown in FIG4 , when the memory cell 21 is a dual-end read memory cell, the memory 10 includes a word line WL and a bit line BL. The memory cell 21 may include six transistors. Each bit line BL includes a first bit line BL1 and a second bit line BL2. The six transistors are a first conduction transistor PG, a second conduction transistor PGB, a first storage transistor PU, a second storage transistor PD, a third storage transistor PUB, and a fourth storage transistor PDB. The first storage transistor PU and the third storage transistor PUB are PMOS transistors. The first conduction transistor PG, the second conduction transistor PGB, the second storage transistor PD, and the fourth storage transistor PDB are NMOS transistors. The read circuit 12 includes a sense amplifier (SA) 121. Wherein:

The first electrode of the first pass transistor PG is coupled to the first bit line BL1. The second electrode of the first pass transistor PG is respectively coupled to the second electrode of the first storage transistor PU, the first electrode of the second storage transistor PD, the gate of the third storage transistor PUB and the gate of the fourth storage transistor PDB to the first storage point BIT. The gate of the first pass transistor PG is coupled to the word line WL.

The first electrode of the second pass transistor PGB is coupled to the second bit line BL2. The second electrode of the second pass transistor PGB is respectively coupled to the second electrode of the third storage transistor PUB, the first electrode of the fourth storage transistor PDB, the gate of the first storage transistor PU and the gate of the second storage transistor PD to the second storage point NBIT. The gate of the second pass transistor PGB is coupled to the word line WL.

Both the first bit line BL1 and the second bit line BL2 are coupled to the bit line charging circuit 11 and the sense amplifier 121 .

In the embodiment of the present application, under the structure shown in FIG4, the value indicated by the storage voltage of the first storage point BIT and the value indicated by the storage voltage of the second storage point NBIT are two opposite values. And the value indicated by the storage voltage of the first storage point BIT is used as the value of the data stored in the storage unit 21. For the storage unit 21 shown in FIG4, the specific operation of reading data is:

1. Bit line precharge stage: The word line WL is not charged, so that the first conduction transistor PG (NMOS transistor) and the second conduction transistor PGB (NMOS transistor) are turned off by the low level. Then the first bit line BL1 and the second bit line BL2 are precharged by the bit line charging circuit 11, so that when the first conduction transistor PG (NMOS transistor) and the second conduction transistor PGB (NMOS transistor) are turned off, the voltage value of the data voltage on the first bit line BL1 and the data voltage on the second bit line BL2 is the first voltage value.

2. Reading the stored data phase: charging the word line WL so that the first conduction transistor PG (NMOS transistor) and the second conduction transistor PGB (NMOS transistor) are turned on by the high level. The sense amplifier 121 determines the value indicated by the storage voltage of the first storage point BIT by comparing the data voltage on the first bit line BL1 with the data voltage on the second bit line BL2 at this time, and then determines the value of the data stored in the storage unit 21. The specific determination method is as follows:

If the value of the data corresponding to the storage voltage at the first storage point BIT is 1, and the value of the storage voltage at the second storage point NBIT is 0, then the storage voltage at the first storage point BIT is higher than the storage voltage at the second storage point NBIT. Because the storage voltage at the second storage point NBIT is lower than the first voltage value, the data voltage at the second bit line BL2 will be pulled down, which will cause the data voltage on the second bit line BL2 to be lower than the data voltage on the first bit line BL1. At this time, the read amplifier 121 compares the voltage value of the data voltage on the first bit line BL1 and the data voltage on the second bit line BL2. The voltage value of the data voltage on the first bit line BL1 is greater than the voltage value of the data voltage on the second bit line BL2. It can be determined that the value of the data corresponding to the storage voltage at the first storage point BIT corresponding to the first bit line BL1 is 1 (that is, the value of the data in the storage unit 21 is 1).

If the value of the data corresponding to the storage voltage at the first storage point BIT is 0, and the value of the storage voltage at the second storage point NBIT is 1, then the storage voltage at the first storage point BIT is lower than the storage voltage at the second storage point NBIT. Because the storage voltage at the first storage point BIT is lower than the first voltage value, the data voltage at the first bit line BL1 will be pulled down, which will cause the data voltage on the first bit line BL1 to be lower than the data voltage on the second bit line BL2. At this time, the read amplifier 121 compares the voltage values of the data voltage on the first bit line BL1 and the data voltage on the second bit line BL2. The voltage value of the data voltage on the first bit line BL1 is less than the voltage value of the data voltage on the second bit line BL2. It can be determined that the value of the data corresponding to the storage voltage at the first storage point BIT corresponding to the first bit line BL1 is 0 (that is, the value of the data in the storage unit 21 is 0).

In the embodiment of the present application, as shown in FIG. 4 , a memory cell 21 of a dual-end read memory cell is used to read data, write data, and refresh data through the first bit line BL1 and the second bit line BL2. When reading data, the specific reading method is to compare the voltage value of the data voltage on the first bit line BL1 and the second bit line BL2 through the read amplifier 121. In this comparison method, the accuracy of the voltage value of the data voltage by the read amplifier 121 is required to be at the level of tens of millivolts (mV). That is, the difference between the voltage value of the data voltage on the first bit line BL1 and the voltage value of the data voltage on the second bit line BL2 reaches tens of millivolts, and the read amplifier 121 can compare the two. In actual applications, considering that there may be deviations between different memory cells 21, the voltage difference when reading data can also be set to be larger, such as about 150 millivolts (mV).

In some possible implementations, the storage unit 21 is a single-end read type storage unit.

Exemplarily, as shown in FIG5 , when the memory cell 21 is a single-ended read memory cell, the memory cell 21 may include eight transistors. Each word line WL includes a write word line (write wordline, WWL) WWL and a read word line (read wordline, RWL) RWL. Each bit line BL includes a first write bit line WBL, a second write bit line WNBL, and a read bit line RBL. The eight transistors are respectively a first conduction transistor PG, a second conduction transistor PGB, a third conduction transistor RPD, a fourth conduction transistor RPG, a first storage transistor PU, a second storage transistor PD, a third storage transistor PUB, and a fourth storage transistor PDB. The first storage transistor PU and the third storage transistor PUB are PMOS transistors. The first conduction transistor PG, the second conduction transistor PGB, the third conduction transistor RPD, the fourth conduction transistor RPG, the second storage transistor PD, and the fourth storage transistor PDB are NMOS transistors. The read circuit 12 includes a third inverter INV3 and a sixth transistor M6. Wherein:

The first electrode of the first pass transistor PG is coupled to the first write bit line WBL. The second electrode of the first pass transistor PG is respectively coupled to the second electrode of the first storage transistor PU, the first electrode of the second storage transistor PD, the gate of the third storage transistor PUB and the gate of the fourth storage transistor PDB to the first storage point BIT. The gate of the first pass transistor PG is coupled to the write word line WWL.

The first electrode of the second pass transistor PGB is coupled to the second write bit line WNBL. The second electrode of the second pass transistor PGB is respectively coupled to the second electrode of the third storage transistor PUB, the first electrode of the fourth storage transistor PDB, the gate of the first storage transistor PU and the gate of the second storage transistor PD to the second storage point NBIT. The gate of the second pass transistor PGB is coupled to the write word line WWL.

The gate of the third pass transistor RPD is coupled to the second storage point NBIT. The second electrode of the third pass transistor RPD is grounded or connected to a negative voltage. The first electrode of the third pass transistor is coupled to the second electrode of the fourth pass transistor RPG. The gate of the fourth pass transistor RPG is coupled to the read word line RWL. The first electrode of the fourth pass transistor RPG is coupled to the read bit line RBL.

The input terminals of the bit line charging circuit 11 and the third inverter INV3 are coupled to the read bit line RBL. The output terminal of the third inverter INV3 is coupled to the gate of the sixth transistor M6.

In the embodiment of the present application, a single-ended read type memory cell as shown in FIG5 is used. Compared with the dual-ended read type memory cell as shown in FIG4, the two have the same principle when writing data. However, in terms of reading data, the single-ended read type memory cell shown in FIG5 adds a read word line RWL, a read bit line RBL, a third conduction transistor RPD, and a fourth conduction transistor RPG. The voltage value of the storage voltage at the second storage point NBIT is read by the fourth conduction transistor RPG, and whether the fourth conduction transistor RPG is turned on is controlled by the read word line RWL to determine the voltage value of the data voltage on the read bit line RBL. Then, the level corresponding to the voltage value of the data voltage on the read bit line RBL is inverted by the third inverter INV3 to obtain the level corresponding to the storage voltage at the first storage point BIT. The level corresponding to the storage voltage at the first storage point BIT is used to indicate the value of the data in the storage cell 21. For the storage cell 21 shown in FIG5, the operation of reading data is:

1. Bit line precharge stage: The read word line RWL is not charged to turn off the fourth conduction transistor RPG (NMOS transistor). Then the read bit line RBL is precharged by the bit line charging circuit 11, so that when the fourth conduction transistor RPG is turned off, the voltage value of the data voltage on the read bit line RBL is the first voltage value.

2. Reading and storing data stage: charging the read word line RWL to turn on the fourth conduction transistor RPG (NMOS transistor). Then the third inverter INV3 determines the value of the data in the storage unit 21 according to the voltage value of the data voltage on the read bit line RBL. The specific determination method is:

When the value of the data corresponding to the storage voltage at the first storage point BIT is 0, and the value corresponding to the storage voltage at the second storage point NBIT is 1. The storage voltage at the second storage point NBIT is at a high level, so that the third conduction transistor RPD (NMOS transistor) is turned on. Then the turned-on third conduction transistor RPD and the turned-on fourth conduction transistor RPG make the second pole of the third conduction transistor RPD conductive with the read bit line RBL, and the ground voltage or negative voltage at the second pole of the third conduction transistor RPD will pull down the data voltage on the read bit line RBL, so that the voltage value of the data voltage is lower than the read value comparison voltage. The read value comparison voltage is the flip voltage value of the third inverter INV3. The specific principle is: for a voltage whose voltage value is higher than the read value comparison voltage, the third inverter INV3 judges it as a high-level voltage; conversely, for a voltage whose voltage value is lower than the read value comparison voltage, the third inverter INV3 judges it as a low-level voltage. The reading circuit 12 uses the third inverter INV3 to read the data voltage on the read bit line RBL. At this time, the data voltage is lower than the reading value comparison voltage. The third inverter INV3 inputs a low level, and the third inverter INV3 outputs a high level to the gate of the sixth transistor M6 (NMOS transistor). The sixth transistor M6 is turned on, and the ground voltage or negative voltage of the second electrode of the sixth transistor M6 pulls the voltage of the first electrode of the sixth transistor M6 down to a low level. At this time, the voltage value at the first electrode of the sixth transistor M6 is 0, which is used to indicate that the value of the data corresponding to the storage voltage of the first storage point BIT is 0 (that is, the value of the data in the storage unit 21 is 0).

When the value of the data corresponding to the storage voltage at the first storage point BIT is 1, and the value of the storage voltage at the second storage point NBIT is 0. The storage voltage at the second storage point NBIT is low, so that the third conduction transistor RPD (NMOS transistor) is turned off. Because the third conduction transistor RPD is turned off, the second electrode of the third conduction transistor RPD is also turned off from the read bit line RBL, and the data voltage on the read bit line RBL remains at the first voltage value. The third inverter INV3 reads the data voltage on the read bit line RBL. At this time, the voltage value of the data voltage is the first voltage value, which is higher than the read value comparison voltage. The third inverter INV3 inputs a high level, and the third inverter INV3 outputs a low level to the gate of the sixth transistor M6 (NMOS transistor), and the sixth transistor M6 is turned off. The voltage of the first electrode of the sixth transistor M6 remains at a high level state. At this time, the value of the voltage value at the first electrode of the sixth transistor M6 is 1, which is used to indicate that the value of the data corresponding to the storage voltage of the first storage point BIT is 1 (that is, the value of the data in the storage unit 21 is 1).

In the embodiment of the present application, when the storage unit 21 is a single-ended read type storage unit as shown in FIG5 , the read circuit 12 uses the third inverter INV3 to read the data voltage on the read bit line RBL. The third inverter INV3 has a flip voltage value (i.e., a read value comparison voltage). When the voltage value of the input voltage exceeds the flip voltage value, the third inverter INV3 determines that the input is a high level and outputs a low level. When the voltage value of the input voltage is lower than the flip voltage value, the third inverter INV3 determines that the input is a low level and outputs a high level. The read value comparison voltage is generally half of the power supply voltage VDD. The value of the power supply voltage VDD is generally at a level of several volts (V), so the value of the read value comparison voltage is also above 1 volt (V) (1V=1000mV). It can be seen that when a single-end read type memory cell is used, the data voltage of the read bit line RBL is precharged to a first voltage value (generally the voltage value is the power supply voltage VDD) in the precharge grounding, and in the stage of reading the stored data, if the storage voltage at the second storage point NBIT is high, the third conduction transistor RPD is turned on and the read bit line RBL is discharged through the second electrode of the third conduction transistor RPD. When the data voltage of the read bit line RBL is discharged to less than VDD/2, the third inverter INV3 can output the required high level. Since the voltage span required to be discharged by the single-end read type memory cell (generally more than 1V) is larger than the voltage span required to be discharged by the dual-end read type memory cell (generally between tens of mV and more than one hundred mV), more discharge time is required to complete the discharge operation. Due to the excessively long discharge time, the rate of the memory cell 21 during the read operation is reduced. This problem exists in all single-end read type memory cells. Therefore, for the single-end read type memory cell, how to reduce the discharge time during the read operation to improve the read rate is a big problem.

In order to improve the read rate of a memory using a single-ended read type memory cell, an embodiment of the present application further proposes a memory, as shown in FIG6 , the memory 10 includes a peripheral circuit 1, a memory cell array 2, a plurality of read word lines RWL, and a plurality of read bit lines RBL. The memory cell array 2 includes a plurality of memory cells 21. Each memory cell 21 is coupled to a corresponding read word line RWL and a corresponding read bit line RBL, respectively. The peripheral circuit 1 includes a plurality of bit line charging circuits 11, a plurality of reading circuits 12, and a plurality of bit line discharging circuits 13. Each reading circuit 12 is coupled to a plurality of memory cells 21 on the read bit line RBL through the read bit line RBL. Each bit line charging circuit 11 and the bit line discharging circuit 13 are coupled to a read bit line RBL, respectively. The memory cell 21 is a single-ended read type memory cell.

Exemplarily, in the bit line pre-charging stage, the read bit line RBL is charged by the bit line charging circuit 11, so that the voltage value of the data voltage on the read bit line RBL is a first voltage value. Then, the read bit line RBL is discharged by the bit line discharge circuit 13, so that the voltage value of the data voltage on the read bit line RBL is a second voltage value. The second voltage value is greater than the read value comparison voltage. The read value comparison voltage is the flip voltage value of the read circuit 12. When the voltage input to the read circuit 12 is greater than the read value comparison voltage, the read circuit 12 determines that the input voltage is a high level; conversely, when the voltage input to the read circuit 12 is less than the read value comparison voltage, the read circuit 12 determines that the input voltage is a low level. Then, in the stage of reading the stored data, the read word line RWL is charged so that the storage cell 21 is connected to the read bit line RBL. If the data stored in the storage cell 21 is 1, the voltage value of the data voltage on the read bit line RBL will not be pulled down below the read value comparison voltage, and the read circuit 12 determines that the value of the data in the storage cell 21 is 1. On the contrary, if the data stored in the memory cell 21 is 1, the voltage value of the data voltage on the read bit line RBL will be pulled down to below the read value comparison voltage, and the read circuit 12 determines that the value of the data in the memory cell 21 is 0.

In the embodiment of the present application, the voltage value of the data voltage on the read bit line RBL is discharged to the second voltage value in advance through the bit line discharge circuit 13. Since the second voltage value is greater than the read value comparison voltage, the discharge operation will not affect the stage of reading and storing data. In the stage of reading and storing data, if the value of the data in the storage unit 21 is 0, in the process of lowering the data voltage of the read bit line RBL, it is only necessary to lower the voltage value of the data voltage from the second voltage value to below the read value comparison voltage. Compared with lowering the voltage value of the data voltage from the first voltage value to below the read value comparison voltage, the discharge time is shorter, thereby making the reading rate of the read data faster.

In some possible implementations, in the memory 10 shown in FIG. 6 , the data voltage may be discharged from the first voltage value to the second voltage value through the bit line discharge circuit 13 by controlling the discharge time of the bit line discharge circuit 13 .

For example, the voltage difference between the first voltage value and the second voltage value, or the voltage difference between the second voltage value and the reading comparison voltage, can be adjusted by adjusting the length of the discharge time.

In some possible implementations, as shown in FIG. 7 , the bit line discharge circuit 13 includes a first transistor M1 ; a first electrode of the first transistor M1 is coupled to the read bit line RBL; and a second electrode of the first transistor M1 is grounded or connected to a negative voltage.

Exemplarily, in the bit line pre-charging stage, the first transistor M1 is first controlled to be turned off, and then the bit line charging circuit 11 charges the read bit line RBL so that the voltage value of the data voltage of the read bit line RBL reaches the first voltage value. Then, the first control signal is input to the gate of the first transistor M1, and the first transistor M1 is controlled to be turned on by the first control signal. Because the second electrode of the first transistor M1 is connected to the ground voltage or the negative voltage, all positive charges on the read bit line RBL will flow from the first electrode of the first transistor M1 to the second electrode of the first transistor M1, so that the voltage value of the data voltage on the read bit line RBL is reduced. By adjusting the on-time of controlling the first transistor M1 to be turned on by the first control signal, the second voltage value can be adjusted.

In the embodiment of the present application, the voltage difference between the first voltage value and the second voltage value is adjusted by adjusting the discharge time, or the voltage difference between the second voltage value and the reading comparison voltage is adjusted.

In some possible implementations, in the memory 10 shown in FIG. 6 , the data voltage may be discharged from a first voltage value to a second voltage value through the bit line discharge circuit 13 by controlling the discharge amount of the bit line discharge circuit 13 .

In some possible implementations, as shown in FIG8 , the bit line discharge circuit 13 includes a first transistor M1, a second transistor M2, and an energy storage unit 131; the first electrode of the first transistor M1 is coupled to the read bit line RBL; the second electrode of the first transistor M1 is coupled to the first end of the energy storage unit 131; the second end of the energy storage unit 131 is coupled to the first electrode of the second transistor M2; and the second electrode of the second transistor M2 is grounded or connected to a negative voltage.

Exemplarily, in the bit line pre-charging stage, the first transistor M1 is first controlled to be turned off, and then the bit line charging circuit 11 charges the read bit line RBL so that the voltage value of the data voltage of the read bit line RBL reaches the first voltage value. Then, a first control signal is input to the gate of the first transistor M1, and the first transistor M1 is controlled to be turned on by the first control signal. After the first transistor M1 is turned on, the energy storage unit 131 stores the positive charge on the read bit line RBL in the energy storage unit 131 through the turned-on first transistor M1. Then, in the stage of reading and storing data, the first transistor M1 is controlled to be turned off. By adjusting the maximum charge storage amount of the energy storage unit 131, the amount of charge that the energy storage unit 131 can absorb from the read bit line RBL can be controlled, and then the adjustment of the second voltage value can be achieved.

Exemplarily, when in the stage of reading stored data, the first transistor M1 is controlled to be turned off, and the second transistor M2 can be controlled to be turned on by the second control signal. After being turned on, the second transistor M2 can release the charge stored in the energy storage unit 131, so that in the next bit line pre-charging stage, the energy storage unit 131 can still work normally to discharge the data voltage from the first voltage value to the second voltage value.

In the embodiment of the present application, the voltage difference between the first voltage value and the second voltage value is adjusted by adjusting the discharge amount, or the voltage difference between the second voltage value and the reading comparison voltage is adjusted.

In some possible implementations, as shown in FIG. 9 , the energy storage unit 131 includes a metal wire coupling capacitor C1 ; the second electrode of the first transistor M1 is coupled to the first electrode of the metal wire coupling capacitor C1 ; the second electrode of the metal wire coupling capacitor C1 is coupled to the first electrode of the second transistor M1 .

In the embodiment of the present application, a metal line coupling capacitor C1 is formed by a metal line between the second electrode of the first transistor M1 and the second transistor M2, and the capacitance value of the metal line coupling capacitor C1 is used as the maximum charge storage capacity of a single discharge. In a specific application, the number of memory cells 21 coupled to a single read bit line RBL is different, and the load size on the read bit line RBL is also different. In the circuit design stage, the metal line coupling capacitor C1 with a corresponding capacitance value is designed according to the load size of the read bit line RBL.

Exemplarily, as shown in FIG. 10 , the metal wire coupling capacitor C1 includes a first winding metal wire L1 and a second winding metal wire L2 ; the total length of the first winding metal wire L1 and the second winding metal wire L2 corresponds to the number of memory cells 21 coupled to the read bit line RBL.

In the embodiment of the present application, two insulated metal plates or two metal wires can constitute a capacitor. In the embodiment of the present application, in the chip processing stage of the memory 10, the first winding metal wire and the second winding metal wire respectively constitute the two poles of the metal wire coupling capacitor, so as to constitute the metal wire coupling capacitor. In a specific application, the number of storage cells 21 coupled to a single read bit line is different, and the load size on the read bit line RBL is also different. In the circuit design stage, according to the load size of the read bit line RBL, the metal wire coupling capacitor C1 of the corresponding capacitance value is designed. When the metal wire coupling capacitor C1 includes the first winding metal wire L1 and the second winding metal wire L2, the capacitance value of the metal wire coupling capacitor C1 can be adjusted by controlling the capacitance value of each winding metal wire, and controlling the total length of the first winding metal wire L1 and the total length of the second winding metal wire L2. For example, the number of winding metal wires in the metal wire coupling capacitor C1 is set to correspond to the number of storage cells 21 of the single read bit line RBL, so that the capacitance value of the metal wire coupling capacitor C1 can be automatically matched with the number of storage cells 21 and the amount of charge stored on the read bit line RBL.

In some possible implementations, the first winding metal wire L1 and the second winding metal wire L2 are disposed on a metal layer on the storage unit 21 .

Exemplarily, a plurality of metal layers are disposed above the memory cell 21, and the metal layers are used to electrically connect the memory 10. In practical applications, part of the layout area on the metal layer can be used to electrically connect the memory 10, and another part of the layout area on the metal layer can be used to set the first winding metal wire L1 and the second winding metal wire L2.

Exemplarily, a metal layer for electrical connection of the memory 10 is disposed above the memory cell 21. In addition to the metal layer for electrical connection, another metal layer may be provided. A first winding metal wire L1 and a second winding metal wire L2 are provided on the additional metal layer.

Exemplarily, as shown in FIG. 11 , a plurality of metal layers ML are disposed above the memory cell 21 , and the first winding metal wire L1 and the second winding metal wire L2 are disposed on a metal layer ML_D in the metal layers ML above the memory cell 21 .

In the embodiment of the present application, as shown in FIG11 , in the chip manufacturing process, it can generally be divided into the front-end of line (FEOL) and the back-end of line (BEOL). In the front-end process, etching and other processing operations are performed on the wafer through the front-end mask to generate a basic circuit composed of transistors, such as the bit line charging circuit 11, the reading circuit 12, the bit line discharge circuit 13, the memory cell array 2, etc. in the above embodiment. Then in the back-end process, multiple metal layers ML are etched on the generated basic circuit through the back-end mask, and metal traces are pulled out through different metal layers ML to complete the electrical connection between the inside and the inside of the integrated circuit, and/or between the inside and the outside. In the designed back-end mask, multiple metal layers ML may be included, but only some of the metal layers ML in the multiple metal layers ML are used for the above electrical connection. We can define the metal layer ML used for connection as the connection metal layer ML_L. Some metal layers ML may not be used for the above electrical connection. We define these metal layers ML that are not used for the above electrical connection as spare metal layers ML_D. As shown in FIG11, take a memory 10 design layout including four metal layers ML as an example, wherein the first and second metal layers ML are used to realize electrical connection, while the spare metal layer ML_D of the third layer and the spare metal layer ML_D of the fourth layer are not used for electrical connection. At this time, the first winding metal wire L1 and the second winding metal wire L2 can be set correspondingly at the position above each storage unit 21 on the spare metal layer ML_D of the third layer and/or the fourth layer, and the first winding metal wire L1 and the second winding metal wire L2 are respectively coupled to the first transistor M1 and the second transistor M2 as metal wire coupling capacitor C1. In the layout shown in FIG11, if the metal wire coupling capacitor C1 is set in the front-end process BEOL, because the metal wire coupling capacitor C1 needs to have a certain capacitance value, a large number of metal wires need to be wound to obtain a coupling capacitor with the capacitance value, which will occupy a large amount of layout area of the chip, resulting in an increase in the actual chip area of the memory 10. Therefore, as shown in FIG11 , by setting the first winding metal wire L1 and the second winding metal wire L2 on the vacant metal layer ML_D located above the memory cell 21, there is no need to additionally design the layout area of the first winding metal wire L1 and the second winding metal wire L2, which can save the chip area of the memory 10 and make the chip layout of the memory 10 more compact. The number of metal layers ML in FIG11 is only an example, and the shape of each metal layer ML is not necessarily a plate layer. The number of metal layers ML can also be adjusted according to the actual application and layout design. The shape of each metal layer ML can also be adjusted according to the actual electrical connection requirements.

In some possible implementations, as shown in FIG. 12 and FIG. 13 , the energy storage unit 131 further includes at least one adjustable capacitor group 1311; an adjustable capacitor group 1311 includes a third transistor M3 and a first capacitor C2. The second electrode of the third transistor M3 is coupled to the first capacitor C2. As shown in FIG. 12 , the first electrode of the third transistor M3 is coupled to the first electrode of the metal wire coupling capacitor C1. Alternatively, as shown in FIG. 13 , the first electrode of the third transistor M3 is coupled to the second electrode of the metal wire coupling capacitor C1.

In the embodiment of the present application, in the bit line pre-charging stage, when it is necessary to discharge the read bit line RBL through the bit line discharge circuit 13, the first transistor M1 is turned on and the second transistor M2 is turned off. For a certain adjustable capacitor group 1311, when the corresponding third transistor M3 is turned on: as shown in FIG12, when the first electrode of the third transistor M3 is coupled to the first electrode of the metal line coupling capacitor C1, the metal line coupling capacitor C1 and the first capacitor C2 are connected in parallel, and the positive charge on the read bit line RBL can be stored in the metal line coupling capacitor C1 and the first capacitor C2 at the same time through the turned-on first transistor M1. As shown in FIG13, when the first electrode of the third transistor M3 is coupled to the second electrode of the metal line coupling capacitor C1, the metal line coupling capacitor C1 and the first capacitor C2 are connected in series, and the positive charge on the read bit line RBL can be transmitted to the first capacitor C2 after passing through the metal line coupling capacitor C1 through the turned-on first transistor M1. The above two methods are both possible implementation methods of the present application embodiment, and the read bit line RBL is discharged so that the voltage value of the data voltage on the read bit line RBL drops to the second voltage value. The magnitude of the second voltage value is determined by the amount of charge that the bit line discharge circuit 13 can store. The amount of charge that the bit line discharge circuit 13 can store is mainly determined by the capacitance value of the metal line coupling capacitor C1. In addition, by turning on the third transistor M3, the first capacitor C2 in the corresponding first adjustable capacitor group 1311 can be turned on with the metal line coupling capacitor C1, thereby adjusting the amount of charge that the bit line discharge circuit 13 can store. In actual applications, due to differences in production processes, etc., there may be differences in the load size of different read bit lines RBL. Therefore, when discharging through the manufactured metal line coupling capacitor C1, the capacitance value of the metal line coupling capacitor C1 may not be able to adapt to reducing the data voltage of all read bit lines RBL to the second voltage value. It can be seen from the above embodiment that the second voltage value needs to be greater than the read value comparison voltage to ensure that there will be no interference in the reading and storage data stage. Therefore, if the capacitance value of the metal line coupling capacitor C1 is set to be larger, the first winding metal wire L1 and the second winding metal wire L2 are designed according to the larger capacitance value, and then production is carried out. Then for the multiple read bit lines RBL in the memory 10, after being discharged through the metal line coupling capacitor C1, the voltage value of the data voltage may be lower than the read value comparison voltage, may be close to the read value comparison voltage but still greater than the read value comparison voltage, or may be lower than the read value comparison voltage. When the voltage value of the data voltage after discharge is greater than the read value comparison voltage, the impact of different voltage differences is the inconsistency of the discharge speed in the subsequent reading and storing data stage. However, when the voltage value of the data voltage after discharge is equal to or less than the read value comparison voltage, the data read in the subsequent reading and storing data stage is unreliable. Based on this situation, the capacitance value of the metal line coupling capacitor C1 can be set to be slightly smaller than the ideal value (the ideal value is to satisfy all the read bit lines RBL so that the second voltage value after discharge is just slightly greater than the theoretical value of the read value comparison voltage) to ensure that after the metal line coupling capacitor C1 is discharged, the voltage value of all the read bit lines RBL is greater than the read value comparison voltage. Then, according to the actual load size of each read bit line RBL, the third transistor M3 in at least one adjustable capacitor group 1311 on each read bit line RBL can be controlled to be turned on or off, so as to achieve adaptive adjustment of the discharge amount of the bit line discharge circuit 13 corresponding to each read bit line RBL. In the connection conditions shown in Figures 12 and 13, when the on state or off state of the third transistor M3 is fixed, the capacitance that can be stored in the bit line discharge circuit 13 is consistent, and its size is equal to the sum of the capacitance value of the metal line coupling capacitor C1 and the capacitance value of the first capacitor C2 corresponding to the turned-on third transistor M3. Under the connection structure of Figures 12 and 13, what is affected is the speed of storing and releasing charges in the bit line discharge circuit 13. In the embodiment of the present application, the corresponding connection structure can be adaptively selected according to the cycle length of the bit line pre-charging stage and the stage of reading and storing data.

In some possible implementations, as shown in FIG. 14 , the bit line discharge circuit 13 further includes a switch control circuit 132; the switch control circuit 132 is coupled to the gate of the first transistor M1 and the gate of the second transistor M2, respectively; the switch control circuit 132 is used to output a first control signal to the gate of the first transistor M1, and to output a second control signal to the gate of the second transistor M2; the first control signal and the second control signal are signals of opposite levels.

In the embodiment of the present application, the switch control circuit 132 outputs the first control signal and the second control signal of opposite levels to the gate of the first transistor M1 and the gate of the second transistor M2, respectively, so that the first transistor M1 and the second transistor M2 are cross-conducted. In this cross-conducted state, the first transistor M1 is turned on by the first control signal, and the second transistor M2 is turned off by the second control signal, and the positive charge on the read bit line RBL flows into the bit line discharge circuit 13. At this time, the second transistor M2 is in the off state, and the positive charge stored in the bit line discharge circuit 13 will not be released, so as to ensure that the storage capacity of the bit line discharge circuit 13 can just reduce the voltage value of the data voltage to the second voltage value. After the discharge is completed, the first transistor M1 is turned off by the first control signal, and the second transistor M2 is turned on by the second control signal. At this time, the bit line discharge circuit 13 is continuously discharged by the second transistor M2 to ensure that the positive charge stored in the bit line discharge circuit 13 is completely released, thereby ensuring that in the subsequent discharge process, the bit line discharge circuit 13 has enough storage capacity to continue to store the positive charge on the read bit line RBL.

Exemplarily, as shown in FIG14 , the switch control circuit 132 includes a NAND gate 1321 and a first inverter INV1; the output end of the first inverter INV1 is coupled to the first input end of the NAND gate 1321 and the gate of the second transistor M2, respectively, and the output end of the first inverter INV1 is used to output the second control signal; the second input end of the NAND gate 1321 is used to input an enable signal; the output end of the NAND gate 1321 is coupled to the gate of the first transistor M1; and the output end of the NAND gate 1321 is used to output the first control signal.

In the embodiment of the present application, the switch control circuit 132 including the NAND gate 1321 and the first inverter INV1 can realize that the output first control signal and the second control signal are constant control signals of opposite levels. The enable signal can be used to control whether the energy storage unit 131 performs a discharge operation.

In some possible implementations, exemplarily, as shown in FIG15 , the bit line charging circuit 11 includes a seventh transistor M7. A first electrode of the seventh transistor M7 is used to input a charging voltage, and a second electrode of the seventh transistor M7 is coupled to the read bit line RBL. A gate of the seventh transistor M7 is used to input a first charging control signal, and the first charging control signal is used to control the seventh transistor M7 to turn on, so as to charge the read bit line RBL.

Exemplarily, the seventh transistor M7 is a PMOS transistor. The input terminal of the first inverter INV1 is used to input the first charging control signal.

In the embodiment of the present application, the switch control circuit 132 can be used to control whether the bit line discharge circuit 13 is discharged. The operation logic of the NAND gate 1321 is: when all inputs are high level, the NAND gate 1321 outputs a low level; otherwise, when there is a low level in the input signal, the NAND gate 1321 outputs a high level. As shown in Figure 15, when the seventh transistor M7 is a PMOS transistor, the first charging control signal (low level) controls the seventh transistor M7 to be turned on. At this time, the first charging control signal (low level) is input to the first inverter INV1. The first inverter INV1 outputs the second control signal (high level) to the first input terminal of the NAND gate 1321. Conversely, the first charging control signal (high level) controls the seventh transistor M7 to be turned off. At this time, the first charging control signal (high level) is input to the first inverter INV1. The first inverter INV1 outputs the second control signal (low level) to the first input terminal of the NAND gate 1321. In summary, by inverting the first charging control signal through the first inverter INV1 and generating the second control signal to control the on and off of the second transistor M2, it can be ensured that the second transistor M2 is turned on to discharge the energy storage unit 131 only when the seventh transistor M7 of the bit line charging circuit 11 does not charge the read bit line RBL. In this way, it can be avoided that the first transistor M1 and the second transistor M2 are turned on at the same time when the read bit line RBL is charged, so that the positive charge on the read bit line RBL is stored and the stored positive charge is released, resulting in a waste of power consumption. By controlling the signal at the second input terminal of the input NAND gate 1321 to be a high level or low level enable signal, it is possible to control whether the energy storage unit 131 performs a discharge operation.

In some possible implementations, as shown in Fig. 16, the read circuit 12 includes a third inverter INV3 and a sixth transistor M6. The input end of the third inverter INV3 serves as the input end of the read circuit 12, and the output end of the third inverter INV3 is coupled to the gate of the sixth transistor M6.

In the embodiment of the present application, the sixth transistor M6 is an NMOS transistor as an example. In the reading and storage stage, the voltage value of the data voltage on the read bit line RBL is obtained by the third inverter INV3. When the voltage value is higher than the read value comparison voltage, the third inverter INV3 outputs a low level to the gate of the sixth transistor M6 (NMOS transistor) to control the sixth transistor M6 to turn off. When the voltage value is lower than the read value comparison voltage, the third inverter INV3 outputs a high level to the gate of the sixth transistor M6 (NMOS transistor) to control the sixth transistor M6 to turn on. The second pole of the sixth transistor M6 is connected to the ground voltage or the negative voltage, so that when the sixth transistor M6 is turned on and off, the voltage value of the first pole of the sixth transistor M6 is different, and the voltage value of the first pole of the sixth transistor M6 is used to indicate the value of the data in the storage unit 21. For example, when the first pole of the sixth transistor M6 is at a high level, it indicates that the value of the data in the storage unit 21 is 1; when the first pole of the sixth transistor M6 is at a low level, it indicates that the value of the data in the storage unit 21 is 0.

In some possible implementations, as shown in FIG16 , the peripheral circuit 1 further includes an output buffer circuit 14; an input end of the output buffer circuit 14 is coupled to an output end of the read circuit 12. The output buffer circuit 14 is used to periodically latch data output by the read circuit 12.

In the embodiment of the present application, the signal output by the reading circuit 12 is latched by the output buffer circuit 14 .

Exemplarily, as shown in FIG16 , the output buffer circuit 14 includes a first charging circuit 141, a high-level holding circuit 142, a latch 143 and a second inverter INV2; the input end of the latch 143 is the input end of the output buffer circuit 14, and the input end of the latch 143 is coupled to the first electrode of the sixth transistor M6 in the reading circuit 12; the output end of the first charging circuit 141 and the holding end of the high-level holding circuit 142 are respectively coupled to the input end of the latch 143; the output end of the latch 143 is coupled to the input end of the second inverter INV2.

In the embodiment of the present application, in the bit line pre-charging stage, the charging voltage is outputted by the first charging circuit 141, so that the first electrode of the sixth transistor M6 and the first electrode of the latch 143 are at a high level. When the sixth transistor M6 is turned on, the charging voltage outputted by the first charging circuit 141 flows into the second electrode of the sixth transistor M6 to pull down the voltage of the first electrode of the sixth transistor M6. When the sixth transistor M6 is turned off, the first electrode of the sixth transistor M6 is always kept at a high level through the high level holding circuit 142, and a high level is inputted to the input end of the latch 143. After latching the high level, it is outputted as a low level signal to the second inverter INV2, and the second inverter INV2 converts the input low level signal into a high level for output.

Exemplarily, as shown in FIG17 , the first charging circuit 141 includes an eighth transistor M8, a first electrode of the eighth transistor M8 is used to input a charging voltage, and a second electrode of the eighth transistor M8 is coupled to the output terminal of the reading circuit 12 and the input terminal of the latch 143. The gate of the eighth transistor M8 is used to input a second charging control signal; the second charging control signal is used to control the conduction of the eighth transistor M8 to output the charging voltage to the input terminal of the latch 143.

Optionally, the eighth transistor M8 is a PMOS transistor. When the second charging control signal is at a low level, the eighth transistor M8 is turned on, and when the second charging control signal is at a high level, the eighth transistor M8 is turned off.

Exemplarily, as shown in Figure 17, the latch 143 includes a clock control circuit 1431 and a latch circuit 1432; the clock control circuit 1431 includes two cascaded fourth inverters INV4; the latch circuit 1432 includes three cascaded fifth inverters INV5; the output end of the fourth inverter INV4_1 of the first stage is also coupled with the first voltage end of the fifth inverter INV5_1 of the first stage and the first voltage end of the fifth inverter INV5_3 of the third stage; the output end of the fourth inverter INV4_2 of the second stage is also coupled with the second voltage end of the fifth inverter INV5_1 of the first stage and the second voltage end of the fifth inverter INV5_3 of the third stage.

In the embodiment of the present application, the fifth inverter INV_1 and the fifth inverter INV_3 are controlled not to work by the clock control circuit 1431 to realize that the input level signal is locked in the fifth inverter INV_2. And the fifth inverter INV_1 and the fifth inverter INV_3 are controlled to work by the clock control circuit 1431 to realize the output of the level signal locked in the fifth inverter INV_2. The clock control circuit 1431 realizes that the level between the output signal of the fourth inverter INV4_1 and the output signal of the fourth inverter INV4_2 is always opposite through two cascaded fourth inverters INV4. By inputting different levels of the fourth inverter INV4_1, the fifth inverter INV_1 and the fifth inverter INV_3 can be controlled to work or not work.

Exemplarily, as shown in Figure 18, the fifth inverter INV_1 and the fifth inverter INV_3 can be an inverter structure including an NMOS transistor and a PMOS transistor. When the inverter needs to work normally, it is necessary to input a high level to the first pole (first voltage terminal) of the PMOS transistor and a low level to the second pole (second voltage terminal) of the NMOS transistor. When a low level is input to the first pole (first voltage terminal) of the PMOS transistor and a high level is input to the second pole (second voltage terminal) of the NMOS transistor, the inverter cannot perform the inversion processing operation normally. Therefore, by inputting a high level or a low level to the input terminal of the fourth inverter INV_1, different level signals are input to the first voltage terminal and the second voltage terminal to realize the control of the fifth inverter INV_1 and the fifth inverter INV_3 to work or not work.

In some possible implementations, a clock control signal with a fixed period is input to the input terminal of the fourth inverter INV_1.

In some possible implementations, as shown in FIG. 19 and FIG. 22 , the peripheral circuit 1 further includes a state holder 15 , which includes a fourth transistor M4 ; a second electrode of the fourth transistor M4 is coupled to the read bit line RBL; and a gate of the fourth transistor M4 is coupled to the output end of the third inverter INV3 .

In an embodiment of the present application, the fourth transistor M4 can be a PMOS transistor. As shown in Figure 19, in the stage of reading stored data, a floating signal may exist in the read bit line RBL, causing interference with the read data. The output end of the third inverter INV3 is coupled with the gate of the fourth transistor M4. When the output end of the third inverter INV3 outputs a low level, the fourth transistor M4 (PMOS transistor) is turned on, and a certain value of holding current is input to the data bit line BL3 through the fourth transistor M4 to prevent the generation of a floating signal. The current value of the current input by the fourth transistor M4 needs to be set relatively small, generally less than the degree to which the third inverter INV3 can identify and read, so as to avoid interference with the read data caused by the third inverter INV3.

Exemplarily, as shown in FIG. 19 and FIG. 22 , the state holder 15 further includes at least one fifth transistor M5 ; the at least one fifth transistor M5 is coupled to the first electrode of the fourth transistor M4 , and the at least one fifth transistor M5 is connected in series with the fourth transistor M4 .

In the embodiment of the present application, as shown in FIG. 19 and FIG. 22 , the number of the fifth transistor M5 can be one or more, and the fifth transistor M5 is connected in series with the fourth transistor M4. The fifth transistor M5 is controlled to be always turned on. By setting the fifth transistor M5, the stability of the state holder 15 can be increased.

In some possible implementations, the memory 10 includes a plurality of word lines WL and a plurality of bit lines BL. The memory cell array 2 includes a plurality of memory cells 21. Each memory cell 21 is respectively coupled to a word line WL and a bit line BL. As shown in FIG20 , when the memory cell 21 is a single-ended read memory cell, for the word line WL and the bit line BL corresponding to each memory cell 21 in the memory cell array 2 that is a single-ended read memory cell, each word line WL includes a write word line WWL and a read word line RWL. Each bit line BL includes a first write bit line WBL, a second write bit line WNBL, and a read bit line RBL. As shown in FIG21 , the peripheral circuit 1 also includes a logic control circuit 16, a row decoding circuit 17, a write circuit 18, an input buffer circuit 19, etc. The logic control circuit 16 is respectively coupled to the bit line charging circuit 11, the read circuit 12, the bit line discharging circuit 13, the output buffer circuit 14, the row decoding circuit 17, the write circuit 18, the input buffer circuit 19, etc. The bit line charging circuit 11, the input end of the reading circuit 12, and the bit line discharging circuit 13 are coupled to the reading bit line RBL respectively, and the output end of the reading circuit 12 is coupled to the input end of the output buffer circuit 14. The output end of the input buffer circuit 19 is coupled to the input end of the writing circuit 18, and the output end of the writing circuit 18 is coupled to the first writing bit line WBL and the second writing bit line WNBL respectively. The output end of the row decoding circuit 17 is coupled to the writing word line WWL and the reading word line RWL respectively.

In the embodiment of the present application, the row decoding circuit 17 is controlled by the logic control circuit 16 to charge and discharge the write word line WWL and the read word line RWL respectively, so as to control whether the first conduction transistor PG and the second conduction transistor PGB in the storage unit 21 are turned on respectively. The logic control circuit 16 charges and discharges the first write bit line WBL and the second write bit line WNBL respectively by controlling the write circuit 18, and charges and discharges the write word line WWL by controlling the row decoding circuit 17, so as to write data in the storage unit 21. The logic control circuit 16 charges and discharges the read bit line RBL by controlling the bit line charging circuit 11 and the bit line discharging circuit 13, and charges and discharges the read word line RWL by controlling the row decoding circuit 17, so as to read the data stored in the storage unit 21.

Exemplarily, the logic control circuit 16 may be a control circuit including a controller. Optionally, the controller may be an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

Exemplarily, the logic control circuit 16 may be a digital hardware control circuit composed of a digital logic circuit.

In some possible implementations, all storage cells 21 in the memory 10 are single-end read storage cells. Alternatively, some storage cells 21 in the memory 10 are dual-end read storage cells, and another part of the storage cells 21 are single-end read storage cells.

Exemplarily, the memory 10 may be a static random-access memory (SRAM), a read-only memory (ROM), or the like.

Optionally, when the memory 10 is a static random access memory, all of the memory cells 21 therein may be single-ended read memory cells including eight transistors as described in the above embodiment. Optionally, part of the memory cells 21 therein may be single-ended read memory cells including eight transistors as described in the above embodiment, and the other part of the memory cells 21 may be double-ended read memory cells including six transistors as described in the above embodiment.

Optionally, when the memory 10 is a read-only memory, the memory cell 21 therein may be a single-ended read-type memory cell including one transistor.

In some possible embodiments, corresponding discharge circuits and charging circuits are respectively provided for at least one data line among the write word line WWL, the read word line RWL, the first write bit line WBL, the second write bit line WNBL, and the read bit line RBL to respectively perform charging and discharging operations on the at least one data line.

In the embodiment of the present application, when the memory 10 includes a dual-end read type memory cell as shown in FIG. 4 and a single-end read type memory cell as shown in FIG. 5 , the two types of memory cells 21 have the same principle and operation in writing data, so the memory 10 has the same write rate when writing data to all memory cells. However, when reading data from all memory cells 21, the read rate of the single-end read type memory cell as shown in FIG. 5 is slower than that of the dual-end read type memory cell as shown in FIG. 4 . At this time, for the single-end read type memory cell, the peripheral circuit including the related structures described in FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , FIG. 15 , FIG. 16 , FIG. 17 , FIG. 18 , FIG. 19 , FIG. 20 and FIG. 21 can improve the read rate of the single-end read type memory cell, thereby improving the read rate of the memory 10.

Based on the memory 10 including the structure described in FIGS. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 and 22, a data reading method including steps S110 to S130 as shown in FIG. 23 may be executed:

Step S110 , pre-charging the read bit line RBL so that the voltage value of the data voltage on the read bit line RBL is a first voltage value.

In some possible implementations, as shown in FIG. 6 , in the bit line precharging stage of the data reading operation, the read bit line RBL is charged by the bit line charging circuit 11 so that the voltage value of the data voltage on the read bit line RBL is a first voltage value.

For example, the memory cell 21 for data reading is a single-ended read memory cell as shown in FIG5. As shown in FIG18 and FIG19, the row decoding circuit 17 is controlled by the logic control circuit 16 to discharge the write word line WWL and the read word line RWL respectively, so as to control the first conduction transistor PG in the memory cell 21 to be non-conductive, and control the second conduction transistor PGB to be non-conductive. The bit line discharge circuit 13 is controlled by the logic control circuit 16 not to discharge, and the bit line charging circuit 11 is controlled to charge the read bit line RBL, so that the voltage value of the data voltage reaches the first voltage value.

Exemplarily, as shown in Figures 8, 9, 10, 12, 13 and 14, when the logic control circuit 16 controls the bit line charging circuit 11 to charge the read bit line RBL, the logic control circuit 16 controls the first transistor M1 to be non-conductive, and controls the second transistor M2 to be conductive, so as to release the positive charge stored in the bit line discharge circuit 13.

Exemplarily, as shown in FIG14 , the logic control circuit 16 outputs a first charging control signal to the gate of the seventh transistor M7 in the bit line charging circuit 11, and outputs the first charging control signal to the input end of the first inverter INV1, so that when the bit line charging circuit 11 is controlled by the first charging control signal to charge the read bit line RBL, the second transistor M2 is synchronously controlled by the first charging control signal to release the positive charge stored in the bit line discharge circuit 13.

Step S120 , discharging the read bit line RBL so that the voltage value of the data voltage on the read bit line RBL is a second voltage value.

Exemplarily, the second voltage value is greater than the read value comparison voltage. The read value comparison voltage is a flip voltage value of the read circuit 12. When the voltage value of the data voltage on the read bit line RBL is greater than the read value comparison voltage, the read circuit 12 determines it as a high level; conversely, when the voltage value of the data voltage on the read bit line RBL is less than the read value comparison voltage, the read circuit 12 determines it as a low level.

In the embodiment of the present application, after the read bit line RBL is precharged so that the voltage value of the data voltage on the read bit line RBL is the first voltage value, and before the voltage value of the data voltage on the read bit line RBL is read, the voltage value of the data voltage on the read bit line RBL is reduced to the second voltage value. Then, in the subsequent reading and storing data phase of reading the voltage value of the data voltage on the read bit line RBL, if the value indicated by the voltage value of the storage voltage in the storage cell 21 is 1, the voltage value of the data voltage will not decrease, and the reading circuit 12 determines that the input is a high level; if the value indicated by the voltage value of the storage voltage in the storage cell 21 is 0, the voltage value of the data voltage will decrease below the read value comparison voltage, and the reading circuit 12 determines that the input is a low level. Because the voltage value of the data voltage is the second voltage value, the difference between the second voltage value and the read value comparison voltage is smaller than the difference between the first voltage value and the read value comparison voltage, so the discharge speed of the storage cell 21 can be made faster, thereby improving the data reading rate.

In some possible implementations, the data voltage is discharged from the first voltage value to the second voltage value through the bit line discharge circuit 13 by controlling the discharge time of the bit line discharge circuit 13 .

7 , 20 and 21 , the bit line discharge circuit 13 includes a first transistor M1 . The logic control circuit 16 controls the discharge by controlling the conduction time of the first transistor M1 in the bit line discharge circuit 13 .

In some possible implementations, the data voltage is discharged from the first voltage value to the second voltage value through the bit line discharge circuit 13 by controlling the discharge amount of the bit line discharge circuit 13 .

Exemplarily, as shown in FIG8, FIG20 and FIG21, the bit line discharge circuit 13 includes a first transistor M1, a second transistor M2 and an energy storage unit 131. The logic control circuit 16 outputs a first control signal to the first transistor M1 and a second control signal to the second transistor M2. The first control signal controls the first transistor M1 to be turned on, and the second control signal controls the second transistor M2 to be turned off. Then, the energy storage unit 131 stores the positive charge on the read bit line RBL to discharge the read bit line RBL.

9, 10 and 11, the energy storage unit 131 includes a metal line coupling capacitor C1. The positive charge on the read bit line RBL is stored by the metal line coupling capacitor C1 to discharge the read bit line RBL.

In some possible implementations, as shown in Figures 12 and 13, the energy storage unit 131 further includes at least one adjustable capacitor group 1311; an adjustable capacitor group 1311 includes a third transistor M3 and a first capacitor C2. The storage capacity of the energy storage unit 131 for positive charges is adjusted by adjusting whether the third transistor M3 is turned on.

In the embodiment of the present application, in the bit line pre-charging stage, when it is necessary to discharge the read bit line RBL through the bit line discharge circuit 13, the first transistor M1 is turned on and the second transistor M2 is turned off. For a certain adjustable capacitor group 1311, when the corresponding third transistor M3 is turned on: as shown in FIG12, when the first electrode of the third transistor M3 is coupled to the first electrode of the metal line coupling capacitor C1, the metal line coupling capacitor C1 and the first capacitor C2 are connected in parallel, and the positive charge on the read bit line RBL can be stored in the metal line coupling capacitor C1 and the first capacitor C2 at the same time through the turned-on first transistor M1. As shown in FIG13, when the first electrode of the third transistor M3 is coupled to the second electrode of the metal line coupling capacitor C1, the metal line coupling capacitor C1 and the first capacitor C2 are connected in series, and the positive charge on the read bit line RBL can be transmitted to the first capacitor C2 after passing through the metal line coupling capacitor C1 through the turned-on first transistor M1. The above two methods are both possible implementation methods of the present application embodiment, and the read bit line RBL is discharged so that the voltage value of the data voltage on the read bit line RBL drops to the second voltage value. The magnitude of the second voltage value is determined by the amount of charge that the bit line discharge circuit 13 can store. The amount of charge that the bit line discharge circuit 13 can store is mainly determined by the capacitance value of the metal line coupling capacitor C1. In addition, by turning on the third transistor M3, the first capacitor C2 in the corresponding first adjustable capacitor group 1311 can be turned on with the metal line coupling capacitor C1, thereby adjusting the amount of charge that the bit line discharge circuit 13 can store. In actual applications, due to differences in production processes, etc., there may be differences in the load size of different read bit lines RBL. Therefore, when discharging through the manufactured metal line coupling capacitor C1, the capacitance value of the metal line coupling capacitor C1 may not be able to adapt to reducing the data voltage of all read bit lines RBL to the second voltage value. It can be seen from the above embodiment that the second voltage value needs to be greater than the read value comparison voltage to ensure that there will be no interference in the reading and storage data stage. Therefore, if the capacitance value of the metal line coupling capacitor C1 is set to be larger, the first winding metal wire L1 and the second winding metal wire L2 are designed according to the larger capacitance value, and then production is carried out. Then for the multiple read bit lines RBL in the memory 10, after being discharged through the metal line coupling capacitor C1, the voltage value of the data voltage may be lower than the read value comparison voltage, may be close to the read value comparison voltage but still greater than the read value comparison voltage, or may be lower than the read value comparison voltage. When the voltage value of the data voltage after discharge is greater than the read value comparison voltage, the impact of different voltage differences is the inconsistency of the discharge speed in the subsequent reading and storage data stage. However, when the voltage value of the data voltage after discharge is equal to or less than the read value comparison voltage, the data read in the subsequent reading and storage data stage is unreliable. Based on this situation, the capacitance value of the metal line coupling capacitor C1 can be set to be slightly smaller than the ideal value (the ideal value is to satisfy all the read bit lines RBL so that the second voltage value after discharge is just slightly greater than the theoretical value of the read value comparison voltage) to ensure that after the metal line coupling capacitor C1 is discharged, the voltage value of all the read bit lines RBL is greater than the read value comparison voltage. Then, according to the actual load size of each read bit line RBL, the third transistor M3 in at least one adjustable capacitor group 1311 on each read bit line RBL can be controlled to be turned on or off, so as to achieve adaptive adjustment of the discharge amount of the bit line discharge circuit 13 corresponding to each read bit line RBL. In the connection conditions shown in Figures 12 and 13, when the on state or off state of the third transistor M3 is fixed, the capacitance that can be stored in the bit line discharge circuit 13 is consistent, and its size is equal to the sum of the capacitance value of the metal line coupling capacitor C1 and the capacitance value of the first capacitor C2 corresponding to the turned-on third transistor M3. Under the connection structure of Figures 12 and 13, what is affected is the speed of storing and releasing charges in the bit line discharge circuit 13. In the embodiment of the present application, the corresponding connection structure can be adaptively selected according to the cycle length of the bit line pre-charging stage and the stage of reading and storing data.

Exemplarily, whether the third transistor M3 is turned on is controlled according to the first voltage difference, wherein the first voltage difference is the difference between the first voltage value and the reading value comparison voltage.

In the embodiment of the present application, the data voltage needs to be reduced from the first voltage value to the second voltage value, and the second voltage value needs to satisfy that it is greater than the reading value comparison voltage, so the size of the second voltage value needs to be determined according to the difference between the first voltage value and the reading value comparison voltage. According to the determined second voltage value, the amount of positive charge that needs to be stored on the read bit line 23 is determined, and the amount of stored positive charge is related to the capacitance value of the energy storage unit 131, so the capacitance value of the energy storage unit 131 actually required is compared with the capacitance value of the metal line coupling capacitor C1 in the energy storage unit 131. When the capacitance value of the metal line coupling capacitor C1 is less than the capacitance value of the energy storage unit 131 actually required, the corresponding number of third transistors M3 can be turned on, and the capacitance value of the energy storage unit 131 is increased by the capacitance value of the first capacitor C2, so that the capacitance value of the energy storage unit 131 is equal to the required capacitance value.

Exemplarily, whether the third transistor M3 is turned on is controlled according to a first number, wherein the first number is the number of storage cells 21 coupled to a single read bit line RBL.

In the embodiment of the present application, a single read bit line RBL is coupled with a plurality of storage cells 21. The number of storage cells 21 coupled to a single read bit line RBL is different, and the load size on the read bit line RBL is also different. Under different load sizes, the charging voltage output by the bit line charging circuit 11 to each read bit line RBL is the same, but after the read bit lines RBL with different load sizes input the charging voltage, the consumption of the charging voltage is different due to different load sizes, so the first voltage value of the data voltage obtained after charging is also different. Therefore, it is necessary to adaptively adjust the capacitance value of the energy storage unit 131.

In some possible embodiments, the logic control circuit 16 outputs an adjustment control signal to the energy storage unit 131, the bit of the adjustment control signal corresponds to the number of adjustable capacitor groups 1311, and the value of each bit of the adjustment control signal is used to control whether the third transistor M3 in the corresponding adjustable capacitor group 1311 is turned on.

Exemplarily, taking the two first adjustable capacitor groups 1311 as an example, the adjustment control signal can be a two-bit control signal. The two first adjustable capacitor groups 1311 are respectively the 0-bit first adjustable capacitor group and the 1-bit first adjustable capacitor group. When the value of the adjustment control signal is 00, the two third transistors M3 are controlled to be turned off, and at this time, the capacitance value of the energy storage unit 131 is equal to the capacitance value of the metal wire coupling capacitor C1. When the value of the adjustment control signal is 01, the third transistor M3 corresponding to the 1-bit is controlled to be turned off, and the third transistor M3 corresponding to the 0-bit is controlled to be turned on. At this time, the capacitance value of the energy storage unit 131 is equal to the capacitance value of the metal wire coupling capacitor C1 and the capacitance value of the first capacitor C2 corresponding to the 0-bit. Similarly, when the value of the adjustment control signal is 10, the capacitance value of the energy storage unit 131 is equal to the capacitance value of the metal wire coupling capacitor C1 and the capacitance value of the first capacitor C2 corresponding to the 1-bit. When the value of the adjustment control signal is 11, the capacitance value of the energy storage unit 131 is equal to the sum of the capacitance value of the metal line coupling capacitor C1, the capacitance value of the first capacitor C2 corresponding to the 0 bit, and the capacitance value of the first capacitor C2 corresponding to the 0 bit.

In some possible implementations, as shown in FIG. 14 , the bit line discharge circuit 13 further includes a switch control circuit 132; the switch control circuit 132 is coupled to the gate of the first transistor M1 and the gate of the second transistor M2, respectively; the switch control circuit 132 is used to output a first control signal to the gate of the first transistor M1, and to output a second control signal to the gate of the second transistor M2; the first control signal and the second control signal are signals of opposite levels.

In the embodiment of the present application, the switch control circuit 132 outputs the first control signal and the second control signal of opposite levels to the gate of the first transistor M1 and the gate of the second transistor M2, respectively, so that the first transistor M1 and the second transistor M2 are cross-conducted. In this cross-conducted state, the first transistor M1 is turned on by the first control signal, and the second transistor M2 is turned off by the second control signal, and the positive charge on the read bit line RBL flows into the bit line discharge circuit 13. At this time, the second transistor M2 is in the off state, and the positive charge stored in the bit line discharge circuit 13 will not be released, so as to ensure that the storage capacity of the bit line discharge circuit 13 can just reduce the voltage value of the data voltage to the second voltage value. After the discharge is completed, the first transistor M1 is turned off by the first control signal, and the second transistor M2 is turned on by the second control signal. At this time, the bit line discharge circuit 13 is continuously discharged by the second transistor M2 to ensure that the positive charge stored in the bit line discharge circuit 13 is completely released, thereby ensuring that in the subsequent discharge process, the bit line discharge circuit 13 has enough storage capacity to continue to store the positive charge on the read bit line RBL.

Exemplarily, as shown in FIG14 , the switch control circuit 132 includes a NAND gate 1321 and a first inverter INV1; the output end of the first inverter INV1 is respectively coupled to the first input end of the NAND gate 1321 and the gate of the second transistor M2, and the output end of the first inverter INV1 is used to output the second control signal; the output end of the NAND gate 1321 is coupled to the gate of the first transistor M1; the output end of the NAND gate 1321 is used to output the first control signal.

In the embodiment of the present application, the switch control circuit 132 including the NAND gate 1321 and the first inverter INV1 can achieve that the output first control signal and the second control signal are control signals of constant opposite levels.

Step S130 , turning on the memory cell 21 and the read bit line RBL.

In some possible implementations, when the memory cell 21 is a single-ended read memory cell as shown in FIG5 , as shown in FIG5 , FIG6 , FIG20 , FIG21 , and FIG22 , the fourth conduction transistor RPG is turned on by charging the read word line RWL corresponding to the memory cell 21 , thereby conducting between the memory cell 21 and the read bit line RBL. If the voltage value of the storage voltage in the memory cell 21 is different, the voltage value of the data voltage on the read bit line RBL will also be different. The relationship between the storage voltage and the data voltage can be referred to the description of FIG5 in the above embodiment, which will not be repeated here.

Step S140 , obtaining the voltage value of the data voltage on the read bit line to obtain the value of the data in the storage unit 21 .

In some possible implementations, as shown in FIG6, FIG7, FIG8, FIG9, FIG10, FIG12, FIG13, FIG14, FIG15, FIG16, FIG17, FIG18, FIG19, FIG20, FIG21 and FIG22, the logic control circuit 16 controls the bit line charging circuit 11 not to charge the read bit line RBL, and controls the bit line discharging circuit 13 not to discharge the read bit line RBL. Then, the logic control circuit 16 controls the read circuit 12 to obtain the voltage value of the data voltage on the read bit line RBL. When the voltage value of the data voltage is less than the read value comparison voltage, the read circuit 12 determines that the input is a low level; when the voltage value of the data voltage is greater than the read value comparison voltage, the read circuit 12 determines that the input is a high level.

Exemplarily, taking the storage unit 21 as the structure shown in Figure 5 as an example, as shown in Figures 5, 20 and 21, in the stage of reading stored data, the logic control circuit 16 discharges the write word line WWL through the row decoding circuit 17 to control the first pass transistor PG and the second pass transistor PGB to be turned off, and charges the read word line RWL through the row decoding circuit 17 to control the fourth pass transistor RPG to be turned on.

When the value of the data stored in the second storage point NBIT is 1 (i.e., the value of the data stored in the first storage point BIT is 0), the third conduction transistor RPD is turned on, so that the voltage value of the data voltage of the read bit line RBL drops from the second voltage value to below the read value comparison voltage. The read circuit 12 determines that the input is a low level, which corresponds to the value 0 of the data stored in the first storage point BIT, and also corresponds to the value 0 of the data in the storage unit 21.

When the value of the data stored in the second storage point NBIT is 0 (that is, the value of the data stored in the first storage point BIT is 1), the third conduction transistor RPD is turned off, and the voltage value of the data voltage of the read bit line RBL is not reduced. At this time, the voltage value of the data voltage of the read bit line RBL is maintained at the second voltage value, which is higher than the read value comparison voltage. The read circuit 12 determines that the input is a high level, and the high level of the input corresponds to the value 1 of the data stored in the first storage point BIT, and also corresponds to the value 1 of the data in the storage unit 21.

Exemplarily, as shown in FIG16 , the reading circuit 12 includes a third inverter INV3 and a sixth transistor M6. The third inverter INV3 inverts the input level, and then controls whether the sixth transistor M6 is turned on or not by the inverted level, and indicates the value of the data in the storage unit 21 according to different values of the voltage of the first electrode of the sixth transistor M6 in the two cases of on and off.

In some possible implementations, as shown in Fig. 16, an output buffer circuit 14 is provided at the output end of the reading circuit 12. The output buffer circuit 14 caches and latches the read data and then outputs the data.

Exemplarily, as shown in FIG16 , the output buffer circuit 14 includes a first charging circuit 141 and a latch 143. The logic control circuit 16 outputs a second charging control signal to the first charging circuit 141, and controls the first charging circuit 141 to output a charging voltage to the latch 143 and the first electrode of the sixth transistor M6 through the second charging control signal, so that the input terminal of the latch 143 and the first electrode of the sixth transistor M6 are kept at a high level. When the sixth transistor M6 is turned on, the charging voltage output by the first charging circuit 141 is pulled down, so that the first electrode of the sixth transistor M6 and the input terminal of the latch 143 are at a low level. The latch 143 latches the low level and then outputs it.

In the embodiment of the present application, the storage unit 21 is a single-ended read type storage unit including eight transistors as shown in FIG5 , and the storage unit 21 includes a first storage point BIT and a second storage point NBIT, and the first storage point BIT and the second storage point NBIT store opposite data. In the above embodiments, the data stored in the first storage point BIT is used as the data stored in the storage unit 21. In actual applications, the data stored in the second storage point NBIT can also be used as the data stored in the storage unit 21. In the structure shown in FIG16 , the level output by the latch 143 corresponds to the data stored in the second storage point NBIT.

Exemplarily, as shown in Figure 17, when the first charging circuit 141 includes an eighth transistor M8, if the eighth transistor M8 is a PMOS transistor, a second charging control signal of a low level is output to the gate of the eighth transistor M8 to control the eighth transistor M8 to output a charging voltage to the input end of the latch 143 and the first electrode of the sixth transistor M6 in the reading circuit 12.

Exemplarily, as shown in FIG16 , the output buffer circuit 14 further includes a second inverter INV2. The output end of the latch 143 is coupled to the input end of the second inverter INV2. As shown in FIG17 , the latch 143 includes a clock control circuit 1431 and a latch circuit 1432; the clock control circuit 1431 includes two fourth inverters INV4 in cascade connection; the latch circuit 1432 includes three fifth inverters INV5 in cascade connection; the output end of the fourth inverter INV4_1 of the first stage is also coupled to the first voltage end of the fifth inverter INV5_1 of the first stage and the first voltage end of the fifth inverter INV5_3 of the third stage; the output end of the fourth inverter INV4_2 of the second stage is also coupled to the second voltage end of the fifth inverter INV5_1 of the first stage and the second voltage end of the fifth inverter INV5_3 of the third stage.

In an embodiment of the present application, as shown in Figure 17, the latch circuit 1432 includes three fifth inverters INV5 in cascade. As shown in Figure 18, each fifth inverter INV5 can be an inverter including a PMOS transistor and an NMOS transistor. The gate of the PMOS transistor and the gate of the NMOS transistor are coupled together as the input end of the fifth inverter INV5, and the second pole of the PMOS transistor and the first pole of the NMOS transistor are coupled together as the output end of the fifth inverter INV5. When a low level is input to the input end of the fifth inverter INV5, the PMOS transistor is turned on and the NMOS transistor is turned off. At this time, if the first pole of the PMOS transistor (i.e., the first voltage end of the fifth inverter INV5) is input with a high level, a high level can be output from the second pole of the PMOS transistor (i.e., the output end of the fifth inverter INV5), thereby realizing the inversion effect. On the contrary, if a low level is input from the first pole of the PMOS transistor (i.e., the first voltage end of the fifth inverter INV5), the fifth inverter INV5 is not inverted. Similarly, if a high level is input to the input end of the fifth inverter INV5, so that the PMOS transistor is turned off and the NMOS transistor is turned on, at this time, if the second pole of the NMOS transistor (i.e., the second voltage end of the fifth inverter INV5) is input with a low level, a low level can be output from the first pole of the NMOS transistor (i.e., the output end of the fifth inverter INV5), thereby achieving the inversion effect, on the contrary, if a high level is input from the second pole of the NNMOS transistor (i.e., the second voltage end of the fifth inverter INV5), the fifth inverter INV5 does not perform inversion. As shown in FIG17 , the clock control circuit 1431 includes two cascaded fourth inverters INV4, and the control signal output by the fourth inverter INV4_1 and the control signal output by the fourth inverter INV4_2 are always at opposite levels. The output end of the fourth inverter INV4_1 is coupled to the first voltage end of the fifth inverter INV5_1 and the first voltage end of the fifth inverter INV5_3, and the output end of the fourth inverter INV4_2 is coupled to the second voltage end of the fifth inverter INV5_1 and the second voltage end of the fifth inverter INV5_3; or, the output end of the fourth inverter INV4_1 is coupled to the second voltage end of the fifth inverter INV5_1 and the second voltage end of the fifth inverter INV5_3, and the output end of the fourth inverter INV4_2 is coupled to the first voltage end of the fifth inverter INV5_1 and the first voltage end of the fifth inverter INV5_3. By inputting different levels to the input end of the fourth inverter INV4_1, it is possible to control whether the latch circuit 1432 is latched. Because the level of the input end of the output buffer circuit 14 is equal to the level at the first pole of the sixth transistor M6, the level is used to indicate the value of the data in the storage unit 21. After the level is input into the fifth inverter INV5_1 in the latch circuit 1432, the level opposite to the data in the storage unit 21 is output, and after passing through the fifth inverter INV5_2, the level corresponding to the data in the storage unit 21 is output, and after passing through the fifth inverter INV5_3, the value of the level output from the latch circuit 1432 is the same as the value of the data stored in the second storage point NBIT, and opposite to the value of the data stored in the first storage point BIT. Therefore, when the data stored in the first storage point BIT is used as the data stored in the storage unit 21, the level output by the latch circuit 1432 needs to be inverted through the second inverter INV2 to obtain the level corresponding to the value of the data stored in the first storage point BIT.

Exemplarily, a clock control signal can be set, and the clock control signal can be generated by a counter, a clock unit, etc. The clock control signal is a fixed-cycle signal, including a control signal with a fixed effective pulse width (i.e., a continuous high level). The clock control signal is input to the input end of the clock control circuit 1431 (i.e., the input end of the fourth inverter INV4_1), so as to periodically latch the read data. At the same time, according to the cycle of the clock control signal, the subsequent device coupled to the output end of the output buffer circuit 14 can also periodically obtain the read data.

For example, in the specific implementation of the above step S120 and step S130, step S120 may be implemented first, and then step S130. Step S120 and step S130 may also be implemented synchronously. When step S120 and step S130 are implemented synchronously, the time for reading data can be reduced, and the operation of discharging the read bit line RBL through the bit line discharge circuit 13 is avoided to increase the time for reading data.

Taking the simultaneous implementation of step S120 and step S130 as an example, when using a memory 10 including a structure as shown in Figures 17, 19 and 22, when the value of the read data is 0, the timing changes of each signal voltage or level state are as shown in Figure 24; when the value of the read data is 1, the timing changes of each signal voltage or level state are as shown in Figure 25.

The embodiment of the present application provides a memory, a data reading method, a chip system and an electronic device, wherein the memory includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells and a read bit line. When some or all of the memory cells in the memory cell array are single-ended read memory cells, the peripheral circuit includes a bit line charging circuit, a bit line discharging circuit and a reading circuit. The memory cell is coupled through a read bit line pre-reading circuit. The bit line charging circuit and the bit line discharging circuit are respectively coupled to the read bit line. When data is read from the memory cell, it is divided into two stages: a bit line pre-charging stage and a read storage data stage. In the bit line pre-charging stage, the data voltage of the read bit line is charged to a first voltage value by the bit line charging circuit. In the read storage data stage, the memory cell is turned on, and the voltage value of the storage voltage in the memory cell is different, and the voltage value of the data voltage on the read bit line is also different. The reading circuit determines the value of the data indicated by the storage voltage in the memory cell according to the voltage value of the data voltage on the current read bit line. When the value of the data in the memory cell is 0, the data voltage needs to drop from the first voltage value to below the read value comparison voltage, and the reading circuit can determine that the value of the data in the memory cell is 0. Because the difference between the first voltage value and the read value comparison voltage is large, a longer discharge time is required to make the data voltage drop below the read value comparison voltage. This will lead to a decrease in the read rate of the memory. In the embodiment of the present application, in the bit line precharge stage, when the voltage value of the data voltage is after the first voltage value, the voltage value of the data voltage is discharged to a second voltage value through the bit line discharge circuit, and the second voltage value is greater than the read value comparison voltage. Then in the stage of reading the stored data, when the value of the data in the storage cell is 0, the data voltage drops from the second voltage value to below the read value comparison voltage. Because the difference between the second voltage value and the read value comparison voltage is small, the reading speed of the storage cell is faster, thereby improving the read rate of the memory.

The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one device or distributed on multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

In addition, each functional module in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or may contain one or more servers, data centers and other data storage devices that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (25)

1. A memory, characterized in that it comprises a memory cell array, a read bit line, a read circuit and a bit line discharge circuit; the memory cell array comprises a memory cell; the memory cell is coupled to an input end of the read circuit through the read bit line; the bit line discharge circuit comprises a first transistor; a first electrode of the first transistor is coupled to the read bit line; a second electrode of the first transistor is grounded or connected to a negative voltage; a gate of the first transistor is used to input a first control signal; and the first control signal is used to control the first transistor to be turned on or off. 2. The memory according to claim 1 is characterized in that the bit line discharge circuit includes a first transistor, a second transistor and an energy storage unit; the first electrode of the first transistor is coupled to the read bit line; the second electrode of the first transistor is coupled to the first end of the energy storage unit; the second end of the energy storage unit is coupled to the first electrode of the second transistor; the second electrode of the second transistor is grounded or connected to a negative voltage; the gate of the first transistor is used to input a first control signal; the gate of the second transistor is used to input a second control signal; the first control signal is used to control the first transistor to be turned on or off, and the second control signal is used to control the second transistor to be turned on or off. 3. The memory according to claim 2 is characterized in that the energy storage unit includes a metal line coupling capacitor; the second electrode of the first transistor is coupled to the first electrode of the metal line coupling capacitor; the second electrode of the metal line coupling capacitor is coupled to the first electrode of the second transistor. 4. The memory according to claim 3 is characterized in that the metal wire coupling capacitor includes a first winding metal wire and a second winding metal wire; the first winding metal wire is the first pole of the metal wire coupling capacitor, and the second winding metal wire is the second pole of the metal wire coupling capacitor; the total length of the first winding metal wire and the total length of the second winding metal wire respectively correspond to the number of the storage units coupled to the read bit line. 5 . The memory according to claim 4 , wherein the memory further comprises a metal layer; and the first winding metal wire and the second winding metal wire are arranged in the metal layer. 6. The memory according to any one of claims 3 to 5, characterized in that the energy storage unit further comprises at least one adjustable capacitor group; one of the adjustable capacitor groups comprises a third transistor and a first capacitor; The first electrode of the third transistor is coupled to the metal line coupling capacitor; the second electrode of the third transistor is coupled to the first capacitor. 7. The memory according to any one of claims 3-6 is characterized in that the bit line discharge circuit also includes a switch control circuit; the switch control circuit is coupled to the gate of the first transistor and the gate of the second transistor respectively; the switch control circuit is used to output the first control signal to the gate of the first transistor and output the second control signal to the gate of the second transistor. 8. The memory according to claim 7 is characterized in that the switch control circuit includes a NAND gate and a first inverter; the output end of the first inverter is coupled with the first input end of the NAND gate and the gate of the second transistor respectively, and the output end of the first inverter is used to output the second control signal; the second input end of the NAND gate is used to input an enable signal; the output end of the NAND gate is coupled with the gate of the first transistor; the output end of the NAND gate is used to output the first control signal. 9. The memory according to any one of claims 1-8 is characterized in that the memory further comprises an output buffer circuit; the input end of the output buffer circuit is coupled to the output end of the read circuit; the output buffer circuit is used to periodically latch the data output by the read circuit. 10. The memory according to claim 9 is characterized in that the output buffer circuit comprises a first charging circuit, a high-level holding circuit and a latch; the input end of the latch is the input end of the output buffer circuit, and the input end of the latch is coupled to the output end of the reading circuit; the output end of the first charging circuit and the holding end of the high-level holding circuit are respectively coupled to the input end of the latch; the first charging circuit is used to output a high-level voltage to the output end of the reading circuit. 11. The memory according to claim 10, characterized in that the latch comprises a clock control circuit and a latch circuit; the clock control circuit comprises two cascaded fourth inverters; the latch circuit comprises three cascaded fifth inverters; the input end of the first stage of the fifth inverter serves as the input end of the latch; the output end of the third stage of the fifth inverter serves as the output end of the latch; The output end of the fourth inverter of the first stage is coupled with the first voltage end of the fifth inverter of the first stage and the first voltage end of the fifth inverter of the third stage; the output end of the fourth inverter of the second stage is also coupled with the second voltage end of the fifth inverter of the first stage and the second voltage end of the fifth inverter of the third stage. 12 . The memory according to claim 10 , wherein the output buffer circuit further comprises a second inverter; an input terminal of the second inverter is coupled to an output terminal of the latch. 13. The memory according to any one of claims 1-12 is characterized in that the read circuit includes a third inverter and a sixth transistor; the input end of the third inverter is the input end of the read circuit, and the input end of the third inverter is coupled to the read bit line; the output end of the third inverter is coupled to the gate of the sixth transistor; the second pole of the sixth transistor is grounded or connected to a negative voltage; the first pole of the sixth transistor is the output end of the read circuit. 14. The memory according to claim 13, characterized in that the memory further comprises a state holder, the state holder comprising a fourth transistor; a second electrode of the fourth transistor is coupled to the read bit line; and a gate of the fourth transistor is coupled to the output end of the third inverter. 15. The memory according to claim 14, wherein the state holder further comprises at least one fifth transistor; the at least one fifth transistor is coupled to the first electrode of the fourth transistor, and the at least one fifth transistor is connected in series with the fourth transistor. 16 . The memory according to claim 1 , further comprising a bit line charging circuit; wherein the bit line charging circuit is coupled to the read bit line. 17. A data reading method, characterized in that it is applied to a memory; the memory comprises a memory cell array, a read bit line and a bit line discharge circuit; the memory cell array comprises a memory cell; the memory cell and the bit line discharge circuit are respectively coupled to the read bit line; the method comprises: Controlling the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value; the second voltage value is greater than the read value comparison voltage; Turning on the memory cell and the read bit line; The value of the data in the storage cell is obtained according to the voltage value of the data voltage; when the voltage value of the data voltage is greater than the read value comparison voltage, the value of the data in the storage cell is determined to be a first value; when the voltage value of the data voltage is less than the read value comparison voltage, the value of the data in the storage cell is determined to be a second value. 18. The method according to claim 17, wherein controlling the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value comprises: The discharge time of the bit line discharge circuit is controlled to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value. 19. The method according to claim 17, wherein controlling the bit line discharge circuit to discharge the voltage value of the data voltage on the read bit line from a first voltage value to a second voltage value comprises: The bit line discharge circuit is controlled to be conductive with the read bit line, so that the voltage value of the data voltage on the read bit line is discharged from the first voltage value to the second voltage value. 20. The method according to claim 19, wherein the bit line discharge circuit comprises a metal line coupling capacitor; and the step of controlling the bit line discharge circuit to be conductive with the read bit line to discharge the voltage value of the data voltage on the read bit line from the first voltage value to the second voltage value comprises: The metal line coupling capacitor is controlled to be conductive with the read bit line, so that the voltage value of the data voltage on the read bit line is discharged from the first voltage value to the second voltage value. 21. The method according to claim 20, wherein the bit line discharge circuit further comprises at least one first capacitor; the method further comprises: Whether each of the first capacitors is turned on with the metal line coupling capacitor is controlled according to a first voltage difference and/or a first quantity to adjust the discharge amount of the bit line discharge circuit; the first voltage difference is the difference between the first voltage value and the read value comparison voltage; the first quantity is the number of the storage cells coupled to the single read bit line. 22. The method according to any one of claims 19 to 21, characterized in that the method further comprises: Controlling whether the bit line discharge circuit stores the charge on the read bit line by a first control signal; Whether the bit line discharge circuit releases the charges stored in the bit line discharge circuit is controlled by a second control signal. 23. The method according to any one of claims 17 to 22, characterized in that the method further comprises: After the value of the data in the storage unit is obtained according to the voltage value of the data voltage, the obtained data in the storage unit is latched and then output. 24. A chip system, characterized in that it comprises a processor and a memory as described in any one of claims 1 to 16; the processor is used to write data into the memory, read data stored in the memory, or refresh data stored in the memory. 25. An electronic device, characterized in that it comprises the chip system and a circuit board as claimed in claim 24, wherein the chip system is arranged on the circuit board.