CN118156152B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
- Publication number
- CN118156152B CN118156152B CN202410566533.XA CN202410566533A CN118156152B CN 118156152 B CN118156152 B CN 118156152B CN 202410566533 A CN202410566533 A CN 202410566533A CN 118156152 B CN118156152 B CN 118156152B
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- alumina layer
- aluminum oxide
- reaction gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 106
- 239000012495 reaction gas Substances 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 45
- 239000000758 substrate Substances 0.000 claims description 35
- 238000000231 atomic layer deposition Methods 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 23
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 22
- 239000001301 oxygen Substances 0.000 claims description 22
- 229910052760 oxygen Inorganic materials 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 21
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 238000002360 preparation method Methods 0.000 claims description 15
- 239000003795 chemical substances by application Substances 0.000 claims description 10
- 239000002981 blocking agent Substances 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 5
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 5
- 238000002207 thermal evaporation Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000007789 gas Substances 0.000 description 24
- 238000010926 purge Methods 0.000 description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 8
- 238000013532 laser treatment Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- IJOOHPMOJXWVHK-UHFFFAOYSA-N chlorotrimethylsilane Chemical compound C[Si](C)(C)Cl IJOOHPMOJXWVHK-UHFFFAOYSA-N 0.000 description 4
- 239000008367 deionised water Substances 0.000 description 4
- 229910021641 deionized water Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000001307 helium Substances 0.000 description 4
- 229910052734 helium Inorganic materials 0.000 description 4
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- 238000009423 ventilation Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- POPACFLNWGUDSR-UHFFFAOYSA-N methoxy(trimethyl)silane Chemical compound CO[Si](C)(C)C POPACFLNWGUDSR-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- -1 polydimethylsiloxane Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 239000005051 trimethylchlorosilane Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention relates to a semiconductor device and a forming method thereof, and relates to the technical field of semiconductors.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
The semiconductor production process comprises wafer manufacturing, wafer testing, chip packaging and post-packaging testing. And the semiconductor packaging process is to protect the semiconductor chip. Conventional semiconductor packages include dual in-line packages, ball grid array packages, plastic quad flat packages, plastic flat pack packages, pin grid array packages, multi-chip module packages, chip scale packages, and the like. In the existing manufacturing process of semiconductor packaging structure, metal material is directly deposited on the surface of semiconductor chip or the surface of packaging body to be used as electromagnetic shielding layer, and the semiconductor chip is easy to be polluted by forming the metal material layer by electroplating or chemical plating, and when the metal material layer is formed by vapor deposition, the semiconductor chip is easy to be damaged due to higher deposition temperature. And the electromagnetic shielding layer, the plastic sealing layer and the semiconductor chip are easy to peel due to different thermal expansion coefficients.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned shortcomings of the prior art and providing a semiconductor device and a method of forming the same.
In order to achieve the above object, the present invention provides a method of forming a semiconductor device, the method comprising the steps of: providing a packaging substrate, and arranging a semiconductor chip on the packaging substrate; forming a first dense alumina layer on the surface and the side surface of the semiconductor chip by utilizing an atomic layer deposition process; forming a second alumina layer on the first dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the second alumina layer comprises the following steps of: sequentially and circularly introducing a first reaction gas and a second reaction gas into the cavity, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then performing heat treatment on the second aluminum oxide layer to form nano pits on the surface of the second aluminum oxide layer; forming a first metal shielding layer on the second aluminum oxide layer, wherein the first metal shielding layer is tightly combined with the second aluminum oxide layer through the nano pits; forming a packaging layer on the packaging substrate; forming a third dense alumina layer on the encapsulation layer by utilizing an atomic layer deposition process; forming a fourth alumina layer on the third dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the fourth alumina layer comprises the following steps of: sequentially and circularly introducing a first reaction gas and a second reaction gas into the chamber, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then performing heat treatment on the fourth aluminum oxide layer to form nano pits on the surface of the fourth aluminum oxide layer; and forming a second metal shielding layer on the fourth aluminum oxide layer, wherein the second metal shielding layer is tightly combined with the fourth aluminum oxide layer through the nano pits.
As a preferred technical solution, the semiconductor chip is electrically connected with the package substrate.
As a preferable technical scheme, the ratio of the end capping agent in the first reaction gas is 20-30%.
As a preferable technical scheme, the thicknesses of the first dense alumina layer and the third dense alumina layer are 300-800 nanometers.
As a preferred technical solution, the first metal shielding layer and the second metal shielding layer are formed by magnetron sputtering, thermal evaporation, electroplating, electroless plating or electron beam evaporation.
As a preferable technical scheme, a fifth dense alumina layer is formed on the back surface of the packaging substrate, a sixth alumina layer is formed on the fifth dense alumina layer, the preparation process of the sixth alumina layer is the same as that of the fourth alumina layer, and a third metal shielding layer is formed on the sixth alumina layer.
The invention also provides a semiconductor device which is prepared and formed by adopting the forming method.
Compared with the prior art, the semiconductor device and the forming method thereof have the following beneficial effects: in the process of forming the electromagnetic shielding layer, a dense alumina layer is formed in advance through an ALD (atomic layer deposition) process, then another alumina layer is formed on the dense alumina layer, and in the process of forming the alumina layer, a proper amount of end capping agent is introduced into a reaction chamber, so that nanometer pits can be formed on the surface of the alumina layer in a subsequent heat treatment process, and when a metal shielding layer is formed, the metal shielding layer is tightly combined with the second alumina layer through the nanometer pits, so that the bonding force of the metal shielding layer and the second alumina layer can be improved, the peeling phenomenon of the electromagnetic shielding layer caused by different thermal expansion coefficients can be avoided, the preparation process is simple, an additional etching process is not added, and the manufacturing cost is reduced.
Drawings
Fig. 1 is a schematic view of a structure in which a semiconductor chip is disposed on a package substrate in a method of forming a semiconductor device according to the present invention.
Fig. 2 is a schematic structural diagram of forming a first dense alumina layer, a second alumina layer and a first metal shielding layer on a semiconductor chip in the method for forming a semiconductor device of the present invention.
Fig. 3 is a schematic structural diagram of a package layer formed on a package substrate in the method for forming a semiconductor device according to the present invention.
Fig. 4 is a schematic structural diagram of forming a third dense alumina layer, a fourth alumina layer and a second metal shielding layer on a package layer in the method for forming a semiconductor device according to the present invention.
Fig. 5 is a schematic structural diagram of forming a fifth dense alumina layer, a sixth alumina layer and a third metal shielding layer on the back surface of a package substrate in the method for forming a semiconductor device according to the present invention.
Detailed Description
For a better understanding of the technical solution of the present invention, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 5, the present embodiment provides a method for forming a semiconductor device, the method comprising the steps of:
As shown in fig. 1, a package substrate 10 is provided, and a semiconductor chip 11 is disposed on the package substrate 10.
In a specific embodiment, the semiconductor chip 11 is electrically connected to the package substrate 10.
In a specific embodiment, the package substrate 10 may be one of a glass substrate, a semiconductor substrate, a metal substrate, and a resin substrate, more specifically one of a silicon substrate, an aluminum substrate, a copper substrate, and a PET substrate, and has conductive traces and conductive pads thereon, and the package substrate 10 may also be a printed circuit board.
In a specific embodiment, the electrodes of the semiconductor chip 11 are electrically connected to the conductive pads of the package substrate 10.
In a specific embodiment, an underfill layer (not shown) may be optionally disposed between the semiconductor chip 11 and the package substrate 10, and the underfill layer includes an epoxy resin.
As shown in fig. 2, a first dense alumina layer 12 is formed on the surface and side of the semiconductor chip 11 using an atomic layer deposition process.
In a specific embodiment, under the condition of 220-260 ℃, an aluminum source gas and an oxygen source gas are alternately introduced into a reaction chamber of the atomic layer deposition equipment to form the first dense aluminum oxide layer 12, wherein the aluminum source gas is trimethylaluminum, and the oxygen source is any one of deionized water, oxygen, ozone and hydrogen peroxide.
In a specific embodiment, the flow rate of the aluminum source gas is 60-120 sccm, the pulse time is 5-10s, the flow rate of the oxygen source is 100-200sccm, the pulse time is 5-10s, the reaction chamber is purged in a gap where the aluminum source gas and the oxygen source gas are introduced, the purging gas is argon or helium, the flow rate of the purging gas is 800-1500sccm, the purging time is 10-30s, and the appropriate times are alternated, so that the thickness of the first dense alumina layer is 300-800 nanometers.
As shown in fig. 2, the second alumina layer 13 is formed on the first dense alumina layer 12 by using an atomic layer deposition process, and the specific method for forming the second alumina layer 13 is as follows: and sequentially and circularly introducing a first reaction gas and a second reaction gas into the chamber, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer 13, and then the second aluminum oxide layer 13 is subjected to heat treatment, so that nano pits are formed on the surface of the second aluminum oxide layer 13.
In a specific embodiment, the capping agent in the first reaction gas is 20-30%, preferably 25%.
In a specific embodiment, the aluminum source gas is trimethylaluminum, the end capping agent is one of polydimethylsiloxane, trimethylchlorosilane and trimethylmethoxysilane, and the oxygen source is any one of deionized water, oxygen, ozone and hydrogen peroxide.
In a specific embodiment, the specific preparation process of the second alumina layer 13 is as follows: alternately introducing a first reaction gas and a second reaction gas into a reaction chamber of the atomic layer deposition equipment at the temperature of 200-300 ℃, wherein the flow rate of the first reaction gas is 120-200sccm each time, and the ventilation time is 5-10 seconds each time; the flow rate of the second reaction gas is 100-180sccm each time, and the ventilation time is 5-10 seconds each time; and introducing a purge gas into the gap between the first reaction gas and the second reaction gas, wherein the purge gas can be argon or helium, the flow rate of the purge gas is 800-1500sccm, the purge time is 10-30s, and the cycle is alternately performed for 100-300 times to obtain the second alumina layer 13, then the second alumina layer 13 is subjected to heat treatment, more specifically, the heat treatment can be heat treatment or laser treatment, the heating temperature of the heat treatment is 280-320 ℃, the heating time is 20-50 minutes, and the laser irradiation power is 20-300W, preferably 100-200W during the laser treatment, the laser can be laser with ultraviolet band or visible light band, for example, 355 nm wavelength laser or 532 nm wavelength laser, by using a laser with proper power, the surface of the second alumina layer 13 can be rapidly decomposed, and the semiconductor chip 11 is not damaged, compared with the heat treatment, the laser treatment can effectively reduce the damage to the semiconductor chip, and the second alumina layer 13 can form nano pits on the surface.
As shown in fig. 2, a first metal shielding layer 14 is formed on the second alumina layer 13, and the first metal shielding layer 14 is tightly bonded with the second alumina layer 13 through the nano pits.
In a specific embodiment, the first metal shielding layer 14 is formed by magnetron sputtering, thermal evaporation, electroplating, electroless plating or electron beam evaporation, and the material of the first metal shielding layer 14 is one or more of silver, copper, aluminum, titanium, palladium and gold, and the thickness of the first metal shielding layer is 100-200 nm.
In other preferred embodiments, the first metal shielding layer having a thickness of 10-30 nm and the aluminum oxide layer having nano-pits, each having a total thickness similar to that of the second aluminum oxide layer 13, may be alternately formed, and the number of times of alternation may be 5-10 times, the process of preparing the aluminum oxide layer having nano-pits is the same as that of the second aluminum oxide layer 13.
As shown in fig. 3, an encapsulation layer 15 is then formed on the encapsulation substrate 10.
In a specific embodiment, the encapsulation layer 15 may be an epoxy layer, and the encapsulation layer 15 may be formed by a molding process.
As shown in fig. 4, a third dense alumina layer 21 is formed on the encapsulation layer 15 using an atomic layer deposition process.
In a specific embodiment, the preparation process of the third dense alumina layer 21 is the same as that of the first dense alumina layer 12, that is, the aluminum source gas and the oxygen source gas are alternately introduced into the reaction chamber of the atomic layer deposition apparatus at 220-260 ℃ to form the third dense alumina layer 21, wherein the aluminum source gas is trimethylaluminum, and the oxygen source is any one of deionized water, oxygen, ozone and hydrogen peroxide.
In a specific embodiment, the flow rate of the aluminum source gas is 60-120 sccm, the pulse time is 5-10s, the flow rate of the oxygen source is 100-200sccm, the pulse time is 5-10s, and the reaction chamber is purged in a gap where the aluminum source gas and the oxygen source gas are introduced, the purge gas is argon or helium, the flow rate of the purge gas is 800-1500sccm, the purge time is 10-30s, and the appropriate times are alternated, so that the thickness of the third dense alumina layer 21 is 300-800 nm.
As shown in fig. 4, a fourth alumina layer 22 is formed on the third dense alumina layer 21 by using an atomic layer deposition process, and a specific method for forming the fourth alumina layer 22 is as follows: and sequentially and circularly introducing a first reaction gas and a second reaction gas into the chamber, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then the fourth aluminum oxide layer 22 is subjected to heat treatment, so that nano pits are formed on the surface of the fourth aluminum oxide layer 22.
In a specific embodiment, the capping agent in the first reaction gas is 20-30%, preferably 25%.
In a specific embodiment, the aluminum source gas is trimethylaluminum, the end capping agent is one of polydimethylsiloxane, trimethylchlorosilane and trimethylmethoxysilane, and the oxygen source is any one of deionized water, oxygen, ozone and hydrogen peroxide.
In a specific embodiment, the preparation process of the fourth alumina layer 22 is the same as the preparation process of the second alumina layer 13, that is, the specific preparation process of the fourth alumina layer 22 is: alternately introducing a first reaction gas and a second reaction gas into a reaction chamber of the atomic layer deposition equipment at the temperature of 200-300 ℃, wherein the flow rate of the first reaction gas is 120-200sccm each time, and the ventilation time is 5-10 seconds each time; the flow rate of the second reaction gas is 100-180sccm each time, and the ventilation time is 5-10 seconds each time; and introducing a purge gas into the gap between the first reaction gas and the second reaction gas, wherein the purge gas may be argon or helium, the flow rate of the purge gas is 800-1500sccm, the purge time is 10-30s, and the cycle is alternately performed for 100-300 times to obtain the fourth alumina layer 22, and then the fourth alumina layer 22 is subjected to heat treatment, more specifically, heat treatment may be heat treatment or laser treatment, the heating temperature of the heat treatment is 280-320 ℃, the heating time is 20-50 minutes, and during the laser treatment, the laser irradiation power is 20-300W, preferably 100-200W, the laser may be ultraviolet-band laser or visible-band laser, for example, 355 nm wavelength laser or 532 nm wavelength laser, and by using a laser with appropriate power to irradiate the surface of the fourth alumina layer 22, the capping agent may be rapidly decomposed.
As shown in fig. 4, a second metal shielding layer 23 is formed on the fourth alumina layer 22, and the second metal shielding layer 23 is closely bonded to the fourth alumina layer 22 through the nano pits.
In a specific embodiment, the second metal shielding layer 23 is formed by magnetron sputtering, thermal evaporation, electroplating, electroless plating or electron beam evaporation, the material of the second metal shielding layer 23 is one or more of silver, copper, aluminum, titanium, palladium and gold, and the thickness of the second metal shielding layer 23 is 100-200 nm.
In other preferred embodiments, the second metal shielding layer having a thickness of 10-30 nm and the aluminum oxide layer having nano-pits, each having a total thickness similar to that of the fourth aluminum oxide layer 22, may be alternately formed, and the number of times of alternation may be 5-10 times, the process of preparing the aluminum oxide layer having nano-pits is the same as that of the fourth aluminum oxide layer 22.
As shown in fig. 5, in order to further improve the battery shielding performance of the semiconductor device, a fifth dense alumina layer 31 may be formed on the back surface of the package substrate 10, and a sixth alumina layer 32 may be formed on the fifth dense alumina layer 31, the sixth alumina layer 32 may be prepared by the same process as the fourth alumina layer 22, and a third metal shielding layer 33 may be formed on the sixth alumina layer 32.
In a specific embodiment, the preparation process of the fifth dense alumina layer 31 is the same as the preparation process of the third dense alumina layer 21, the preparation process of the sixth alumina layer 32 is the same as the preparation process of the fourth alumina layer 22, and the preparation process of the third metal shielding layer 33 is the same as the preparation process of the second metal shielding layer 23.
As shown in fig. 5, the present invention also proposes a semiconductor device manufactured by the above-described forming method.
In other embodiments, the method for forming a semiconductor device according to the present invention includes the following steps:
a package substrate is provided, and a semiconductor chip is arranged on the package substrate.
And forming a first dense alumina layer on the surface and the side surface of the semiconductor chip by utilizing an atomic layer deposition process.
Forming a second alumina layer on the first dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the second alumina layer comprises the following steps of: and sequentially and circularly introducing a first reaction gas and a second reaction gas into the cavity, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then the second aluminum oxide layer is subjected to heat treatment, so that nano pits are formed on the surface of the second aluminum oxide layer.
And forming a first metal shielding layer on the second aluminum oxide layer, wherein the first metal shielding layer is tightly combined with the second aluminum oxide layer through the nano pits.
And forming a packaging layer on the packaging substrate.
And forming a third dense alumina layer on the packaging layer by utilizing an atomic layer deposition process.
Forming a fourth alumina layer on the third dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the fourth alumina layer comprises the following steps of: and sequentially and circularly introducing a first reaction gas and a second reaction gas into the cavity, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then the fourth aluminum oxide layer is subjected to heat treatment, so that nano pits are formed on the surface of the fourth aluminum oxide layer.
And forming a second metal shielding layer on the fourth aluminum oxide layer, wherein the second metal shielding layer is tightly combined with the fourth aluminum oxide layer through the nano pits.
According to a preferred embodiment of the present invention, the semiconductor chip is electrically connected to the package substrate.
According to a preferred embodiment of the present invention, the capping agent is present in the first reaction gas in a proportion of 20 to 30%.
According to a preferred embodiment of the present invention, the first dense alumina layer and the third dense alumina layer each have a thickness of 300 to 800 nm.
According to a preferred embodiment of the present invention, the first metal shielding layer and the second metal shielding layer are formed by magnetron sputtering, thermal evaporation, electroplating, electroless plating or electron beam evaporation.
According to a preferred embodiment of the present invention, a fifth dense alumina layer is formed on the back surface of the package substrate, and a sixth alumina layer is formed on the fifth dense alumina layer, the sixth alumina layer being prepared in the same process as the fourth alumina layer, and a third metal shielding layer is formed on the sixth alumina layer.
According to a preferred embodiment of the present invention, the present invention also proposes a semiconductor device manufactured by the above-described forming method.
In the process of forming the electromagnetic shielding layer, a dense alumina layer is formed in advance through an ALD (atomic layer deposition) process, then another alumina layer is formed on the dense alumina layer, and in the process of forming the alumina layer, a proper amount of end capping agent is introduced into a reaction chamber, so that in the subsequent heat treatment process, nano pits can be formed on the surface of the alumina layer, and when a metal shielding layer is formed, the metal shielding layer is tightly combined with the second alumina layer through the nano pits, so that the bonding force of the metal shielding layer and the second alumina layer can be improved, the peeling phenomenon of the electromagnetic shielding layer caused by different coefficients of thermal expansion can be avoided, the preparation process is simple, no additional etching process is added, and the manufacturing cost is reduced.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (7)
1. A method of forming a semiconductor device, characterized by: the method for forming the semiconductor device comprises the following steps:
providing a packaging substrate, and arranging a semiconductor chip on the packaging substrate;
Forming a first dense alumina layer on the surface and the side surface of the semiconductor chip by utilizing an atomic layer deposition process;
Forming a second alumina layer on the first dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the second alumina layer comprises the following steps of: sequentially and circularly introducing a first reaction gas and a second reaction gas into the cavity, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then performing heat treatment on the second aluminum oxide layer to form nano pits on the surface of the second aluminum oxide layer;
Forming a first metal shielding layer on the second aluminum oxide layer, wherein the first metal shielding layer is tightly combined with the second aluminum oxide layer through the nano pits;
Forming a packaging layer on the packaging substrate;
Forming a third dense alumina layer on the encapsulation layer by utilizing an atomic layer deposition process;
Forming a fourth alumina layer on the third dense alumina layer by utilizing an atomic layer deposition process, wherein the specific method for forming the fourth alumina layer comprises the following steps of: sequentially and circularly introducing a first reaction gas and a second reaction gas into the chamber, wherein the first reaction gas comprises an aluminum source and a blocking agent, the second reaction gas is an oxygen source to form a second aluminum oxide layer, and then performing heat treatment on the fourth aluminum oxide layer to form nano pits on the surface of the fourth aluminum oxide layer;
and forming a second metal shielding layer on the fourth aluminum oxide layer, wherein the second metal shielding layer is tightly combined with the fourth aluminum oxide layer through the nano pits.
2. The method for forming a semiconductor device according to claim 1, wherein: the semiconductor chip is electrically connected with the package substrate.
3. The method for forming a semiconductor device according to claim 1, wherein: the ratio of the end capping agent in the first reaction gas is 20-30%.
4. The method for forming a semiconductor device according to claim 1, wherein: the thickness of the first dense alumina layer and the third dense alumina layer is 300-800 nanometers.
5. The method for forming a semiconductor device according to claim 1, wherein: the first metal shielding layer and the second metal shielding layer are formed through magnetron sputtering, thermal evaporation, electroplating, electroless plating or electron beam evaporation.
6. The method for forming a semiconductor device according to claim 1, wherein: and forming a fifth dense alumina layer on the back surface of the packaging substrate, forming a sixth alumina layer on the fifth dense alumina layer, wherein the preparation process of the sixth alumina layer is the same as that of the fourth alumina layer, and forming a third metal shielding layer on the sixth alumina layer.
7. A semiconductor device, characterized in that: the semiconductor device is formed by the formation method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410566533.XA CN118156152B (en) | 2024-05-09 | 2024-05-09 | Semiconductor device and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410566533.XA CN118156152B (en) | 2024-05-09 | 2024-05-09 | Semiconductor device and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118156152A CN118156152A (en) | 2024-06-07 |
| CN118156152B true CN118156152B (en) | 2024-07-19 |
Family
ID=91285307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410566533.XA Active CN118156152B (en) | 2024-05-09 | 2024-05-09 | Semiconductor device and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118156152B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118380337B (en) * | 2024-06-25 | 2024-09-06 | 日月新半导体(威海)有限公司 | Packaging structure of semiconductor wafer and forming method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124291A (en) * | 2010-12-07 | 2012-06-28 | Seiji Kagawa | Electromagnetic wave absorber |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9209138B2 (en) * | 2013-12-09 | 2015-12-08 | Aeroflex Colorado Springs, Inc. | Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion |
| US9871005B2 (en) * | 2016-01-07 | 2018-01-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| JP2018060991A (en) * | 2016-09-28 | 2018-04-12 | 住友ベークライト株式会社 | Sealing film, method for sealing electronic component-mounted substrate, and sealing film-covered electronic component-mounted substrate |
| CN110760818A (en) * | 2019-10-31 | 2020-02-07 | 长春长光圆辰微电子技术有限公司 | Process for growing alumina by using atomic layer deposition technology |
| CN110958828B (en) * | 2019-11-25 | 2022-03-22 | 维达力实业(深圳)有限公司 | Electromagnetic shielding function chip, electromagnetic shielding film layer thereof and electromagnetic shielding method |
| CN111584372A (en) * | 2020-05-21 | 2020-08-25 | 沈佳慧 | Radio frequency chip packaging structure and preparation method thereof |
| CN111883433B (en) * | 2020-07-03 | 2022-03-22 | 徐彩芬 | Semiconductor chip package and method for forming the same |
-
2024
- 2024-05-09 CN CN202410566533.XA patent/CN118156152B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012124291A (en) * | 2010-12-07 | 2012-06-28 | Seiji Kagawa | Electromagnetic wave absorber |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118156152A (en) | 2024-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN118136525B (en) | Semiconductor packaging structure and preparation method thereof | |
| CN118156152B (en) | Semiconductor device and forming method thereof | |
| TWI842797B (en) | Wiring board and manufacturing method thereof | |
| CN100592501C (en) | Conductor substrate, semiconductor device and manufacturing method thereof | |
| CN111276404A (en) | Manufacture of packages using platable encapsulant | |
| JPH0244738A (en) | Manufacture of electronic device | |
| CN112530896A (en) | Lead frame for semiconductor packaging and preparation method thereof | |
| TWI535890B (en) | Method of forming nickel layer on surface of aluminum material, method of forming nickel layer on surface of aluminum electrode of semiconductor wafer by using the same and semiconductor wafer manufactured thereby | |
| TWI359214B (en) | Electroplating method | |
| JP2854963B2 (en) | Solid phase bonding method and apparatus | |
| KR101540583B1 (en) | Method of manufacturuing Electro-Magnetic Shielding Layer for semiconductor package | |
| CN102760722A (en) | Integrated circuit structure containing copper-aluminum circuit connection line and preparation method thereof | |
| JPS59231840A (en) | Semiconductor device and manufacture thereof | |
| JP2009302160A (en) | Manufacturing method for semiconductor device, and semiconductor device | |
| JP7119307B2 (en) | Manufacturing method for semiconductor device manufacturing member | |
| JP2802650B2 (en) | Electronic equipment | |
| CN112802760B (en) | Multi-chip semiconductor package and forming method thereof | |
| CN118738033A (en) | A multi-die packaging structure and a method for forming the same | |
| CN111261527B (en) | Semiconductor packaging component and preparation method thereof | |
| JPH02102567A (en) | Manufacture of electronic device | |
| KR20130025643A (en) | Method of manufacturing chip package member | |
| US20250140573A1 (en) | Method of manufacturing pre-molded lead frame for packaging | |
| JP2010263137A (en) | Semiconductor device and manufacturing method thereof | |
| KR100234162B1 (en) | Heat treatment method of semiconductor lead frame | |
| CN119742241A (en) | A method for manufacturing a QFN chip including a flank structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |