CN118150972B - Clamping circuit with adjustable clamping voltage and semiconductor signal testing circuit - Google Patents
Clamping circuit with adjustable clamping voltage and semiconductor signal testing circuit Download PDFInfo
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- CN118150972B CN118150972B CN202410578353.3A CN202410578353A CN118150972B CN 118150972 B CN118150972 B CN 118150972B CN 202410578353 A CN202410578353 A CN 202410578353A CN 118150972 B CN118150972 B CN 118150972B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
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Abstract
The application provides a clamping circuit with adjustable clamping voltage and a semiconductor signal testing circuit, which are applied to the technical field of semiconductor testing. The clamping circuit with adjustable clamping voltage comprises a precision measurement unit, a first operational amplification circuit, a second operational amplification circuit, a first clamping diode, a second clamping diode, a first voltage division branch and a second voltage division branch; the precision measurement unit provides programmable programming voltage, the operational amplifier circuit forms stable output voltage, the voltage dividing branch circuit provides divided voltage, and the clamping diode forms clamping voltage from the output voltage and the divided voltage. The clamping circuit with adjustable clamping voltage is formed by utilizing the programming output characteristic of the precision measurement unit and the high-gain characteristic of the operational amplifier circuit, the voltage dividing characteristic of the voltage dividing branch circuit and the unidirectional conduction characteristic of the clamping diode, so that the clamping circuit can meet the requirements of various test signals on the clamping voltage under the support of adjustable clamping voltage, and the clamping reliability is ensured.
Description
Technical Field
The application relates to the technical field of semiconductor testing, in particular to a clamping circuit with adjustable clamping voltage and a semiconductor signal testing circuit.
Background
Currently, the communication industry and the consumer electronics industry develop rapidly, the market puts forward higher requirements on the related performance of products, and the development process of miniaturization and integration of semiconductor devices is greatly promoted.
Correspondingly, the testing technology of the semiconductor device also has higher requirements, and in the overall trend, the functions of the load are more and more, the current is more and more, and the functions are more and more complex.
In the test, once the short circuit occurs on the tested signal, other circuits may be damaged due to overvoltage, so that the tested signal needs to be clamped by using clamping voltage. However, the clamping voltage that the conventional clamping circuit can clamp can only be a fixed voltage, and cannot be dynamically matched with the test signal.
Based on this, a new signal testing circuit and clamping circuit scheme thereof are needed.
Disclosure of Invention
In view of this, the embodiment of the present disclosure provides a clamping circuit and a semiconductor signal testing circuit that can quickly adjust the clamping voltage for a test signal, so as to cope with the situation that the clamping circuit cannot be matched due to the variation of the test signal, improve the detection efficiency of the test signal, and improve the reliability of the system.
The embodiment of the specification provides the following technical scheme:
The embodiment of the specification provides a clamping circuit with adjustable clamping voltage, which comprises: the device comprises a precision measurement unit, a first operational amplifier circuit, a second operational amplifier circuit, a first clamping diode, a second clamping diode, a first voltage division branch and a second voltage division branch;
The precision measurement unit outputs a first programming voltage and a second programming voltage respectively, wherein the first programming voltage is a positive voltage, and the second programming voltage is a negative voltage;
The first voltage dividing branch comprises a first fixed resistor, a first rheostat and a second fixed resistor which are sequentially connected in series between a first programming voltage and ground;
the second voltage dividing branch circuit comprises a third fixed resistor, a second rheostat and a fourth fixed resistor which are sequentially connected in series between a second reference voltage and a second programming voltage;
The positive power end of the first operational amplifier circuit inputs a first programming voltage, the negative power end of the first operational amplifier circuit is grounded, the positive end of the first operational amplifier circuit inputs a first reference voltage, and the reverse end of the first operational amplifier circuit is connected with a sliding tap of the first rheostat;
The positive power end of the second operational amplifier circuit inputs a second power voltage, the negative power end of the second operational amplifier circuit inputs a second programming voltage, the positive phase end of the second operational amplifier circuit is grounded, and the reverse phase end of the second operational amplifier circuit is connected with a sliding tap of the second rheostat;
The output end of the first operational amplifier circuit is connected with the anode of the first clamping diode after being connected with the resistor in series, and the cathode of the first clamping diode inputs a first partial voltage;
The output end of the second operational amplifier circuit is connected with the cathode of the second clamping diode after being connected with the resistor in series, and the anode of the second clamping diode inputs a second partial voltage;
The first voltage division branch forms a first voltage division voltage, the second voltage division branch forms a second voltage division voltage, and the first voltage division voltage and the second voltage division voltage are correspondingly used as adjustable first clamping voltage and second clamping voltage under the action of programming voltage of the precision measurement unit;
The first divided voltage and the second divided voltage correspond to satisfy the following relation:
CLAMP_VOLTAGE1=VREF_AMP1*(R11+R10)/R10；
CLAMP_VOLTAGE2=VREF_AMP2*R22/R20；
Wherein clamp_voltage1 is denoted as a first VOLTAGE division VOLTAGE, R11 is denoted as a resistance value of the first varistor in the first VOLTAGE division branch, R10 is denoted as a resistance value of the second fixed resistor in the first VOLTAGE division branch, and vref_amp1 is denoted as a first reference VOLTAGE; clamp_voltage2 is denoted as the second divided VOLTAGE, R22 is denoted as the resistance of the second varistor in the second VOLTAGE dividing branch, R20 is denoted as the resistance of the third fixed resistor in the first VOLTAGE dividing branch, and vref_amp2 is denoted as the second reference VOLTAGE.
Preferably, the clamping circuit with adjustable clamping voltage further comprises: a microcontroller and an analog-to-digital conversion circuit; the analog-to-digital conversion circuit is used for performing analog-to-digital conversion on the programming output of the precision measurement unit; the microcontroller is used for responding to the detection instruction, and programming and controlling the precise measurement unit according to the detection instruction and the conversion result of the analog-to-digital conversion circuit, so that the precise measurement unit outputs corresponding first programming voltage and second programming voltage to meet the preset error requirement.
Preferably, the microcontroller is in communication with the analog-to-digital conversion circuit and the precision measurement unit through SPI interfaces, respectively.
Preferably, the clamp voltage adjustable circuit further includes: a first transistor and a second transistor; the grid electrode of the first transistor is connected with the anode of the first clamping diode, the source electrode of the first transistor is connected with the cathode of the first clamping diode, and the drain electrode of the first transistor is grounded; the grid of the second transistor is connected with the cathode of the second clamping diode, the source electrode of the second transistor is connected with the anode of the second clamping diode, and the drain electrode of the second transistor is grounded.
Preferably, the clamp voltage adjustable circuit further includes: a first capacitor and a second capacitor; the first capacitor is connected in series between the anode of the first clamping diode and the ground, and a resistor connected in series with the output end of the first operational amplifier forms a filter circuit; the second capacitor is connected in series between the cathode of the second clamping diode and the ground, and the second capacitor and a resistor connected in series with the output end of the second operational amplifier form a filter circuit.
Preferably, the clamp voltage adjustable circuit further includes: and the power supply circuit is used for respectively providing the working voltage required by the precision measurement unit, the first reference voltage, the second reference voltage and the second power supply voltage after stabilizing the input power supply.
Preferably, the power supply circuit includes a first voltage stabilizing circuit, a second voltage stabilizing circuit, and a third voltage stabilizing circuit;
the first voltage stabilizing circuit is used for stabilizing the voltage of the input power supply and providing analog positive voltages required by the operation of the analog circuits for the precision measuring unit, the second voltage stabilizing circuit and the third voltage stabilizing circuit respectively;
the second voltage stabilizing circuit is used for forming an analog negative voltage after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit so as to provide the required analog negative voltage for the precision measuring unit;
the third voltage stabilizing circuit is used for forming a reference voltage required by a reference standard after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit.
Preferably, the first voltage stabilizing circuit comprises a Boost circuit, wherein the Boost circuit is used for outputting a first positive voltage as an analog positive voltage after boosting and stabilizing according to an input power supply;
The second voltage stabilizing circuit comprises a Buck circuit, wherein the Buck circuit is used for stabilizing the first positive voltage and then outputting the first negative voltage as an analog negative voltage;
the third voltage stabilizing circuit comprises a reference voltage stabilizer, wherein the reference voltage stabilizer is used for carrying out voltage reduction and voltage stabilization on the first positive voltage.
Preferably, the power supply circuit comprises a DC-DC voltage stabilizer and a reference voltage stabilizer, wherein the DC-DC voltage stabilizer is used for respectively forming an analog positive voltage and an analog negative voltage after stabilizing the input power supply; the reference voltage stabilizer is used for carrying out voltage reduction and voltage stabilization on the analog positive voltage to form a reference standard.
The embodiment of the specification also provides a semiconductor signal test circuit, which comprises: a clamping circuit and a test interface; the clamping circuit is the clamping circuit with adjustable clamping voltage according to any one of the application; the clamping circuit is connected with the test interface to provide clamping protection for the test interface.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least:
By utilizing the programmable characteristic of the precise measurement unit and utilizing the operational amplifier circuit and the varistor voltage dividing circuit, when the required clamp is changed to be high or low, the output of the clamp voltage can be quickly adjusted to be matched with the tested signal, namely the clamp voltage which can be quickly adjusted is provided for the test signal, the problem that the range of the traditional clamp circuit design is fixed and cannot adapt to the requirement of the change of the test load is solved, the condition that the clamp circuit cannot be matched for coping with the change of the test signal can be protected, the detection efficiency of the test signal is improved, and the reliability of the system is improved. In addition, the clamping voltage of the clamping circuit can be programmed, the range of the clamping voltage obtained by programming is wide, and physical adjustment can be realized through sliding of a rheostat, so that the signal testing requirement is very convenient.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a circuit structure with adjustable clamp voltage according to the present application;
FIG. 2 is a schematic diagram of a 7V clamp voltage circuit according to the present application;
FIG. 3 is a schematic diagram of a circuit configuration of the clamping voltage of-2.5V in the present application;
FIG. 4 is a schematic diagram of a connection structure of a test signal and a clamp circuit according to the present application;
FIG. 5 is a schematic diagram of the interface structure of the clamping circuit and each internal circuit according to the present application;
FIG. 6 is a schematic diagram of the communication connection structure between the precision measurement unit and the microcontroller in the present application;
FIG. 7 is a schematic diagram showing the overall structure of a power supply circuit and a clamp circuit formed by a plurality of voltage stabilizing circuits according to the present application;
Fig. 8 is a schematic diagram of a power supply circuit configured by using a DC-DC power supply in the present application.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details.
In the conventional clamping circuit, the clamping voltage is designed fixedly, and when the clamping voltage is required to be higher or lower, the clamping circuit can only be redesigned. In addition, in the actual test, the load characteristic of the tested signal may change, and the clamping voltage is required to adapt to the test requirement of the actual signal.
Based on this, the embodiment of the specification proposes a clamp circuit scheme with adjustable clamp voltage.
As illustrated in fig. 1 to 3, the clamp circuit includes a precision measurement unit (PMU, precision Measurement Unit), a first operational amplifier circuit (OP 1, see U12 device illustrated in fig. 2), a second operational amplifier circuit (OP 2, see U13 device illustrated in fig. 3), a first clamp diode (see D5 device illustrated in fig. 2), a second clamp diode (see D7 device illustrated in fig. 3), a first voltage dividing branch (see a resistive voltage dividing branch constituted by an R64 fixed resistor and an R8 varistor or the like illustrated in fig. 2), and a second voltage dividing branch (see a resistive voltage dividing branch constituted by an R70 fixed resistor and an R72 varistor or the like illustrated in fig. 3).
The respective circuits are schematically described below:
The precision measurement element may be a circuit element using an integrated circuit having a precision measurement circuit (PMU) as a core, such as an integrated circuit including an AD5520, an AD5522, and the like, and the specific type is not limited. In practice, the programming function of the precision measurement unit is utilized to correspondingly OUTPUT a first programming voltage (such as pmu_output_1 illustrated in fig. 1) and a second programming voltage under programming control, wherein the first programming voltage is set to be a positive voltage, and the second programming voltage is set to be a negative voltage. It should be noted that, the range of the programming voltage may be determined according to the device type, for example, the selected device supports a wide range (for example, -20V to 20V), and then the programming voltage may be set in the wide range, and the specific setting value may also be a suitable programming voltage value according to the clamping requirement, which is not limited herein.
Referring to fig. 2, the first voltage dividing branch includes a first fixed resistor R64, a first varistor R8, and a second fixed resistor R66 connected in series in order between a first programming voltage (such as vcc_amp_20v_1 of fig. 2) and ground (such as UVSS of fig. 2). One end of the varistor is used as an output end of the divided voltage, and one end of a tap of the varistor is used as a resistor sampling end of the varistor for changing the resistance value of the branch circuit, so that the divided voltage changes along with the resistance value, and the change relation can be described with reference to the following schematic description.
Referring to fig. 2, a positive power supply terminal of the first operational amplifier circuit U12 inputs a first programming voltage, a negative power supply terminal of the first operational amplifier circuit is grounded, a non-inverting terminal of the first operational amplifier circuit inputs a first reference voltage (e.g., vref_amp_5v_1, labeled in fig. 2), and an inverting terminal of the first operational amplifier circuit is connected to one terminal of the second fixed resistor R66.
Therefore, based on the connection relationship between the voltage dividing branch and the operational amplifier, it can be known that the first divided voltage satisfies the following relationship: clamp_voltage 1=vref_amp 1 (r11+r10)/R10, the first divided VOLTAGE is denoted as clamp_voltage1, the resistance value of the first varistor in the first divided branch is denoted as R11, the resistance value of the second fixed resistor R66 in the first divided branch is denoted as R10, and the first reference VOLTAGE is denoted as vref_amp1.
For example, when vref_amp 1=5v, r11=3.3 kΩ, r10=10kΩ, the first divided voltage is about 7V (specifically, 6.68V).
Referring to fig. 3, the second voltage dividing branch has a circuit form similar to that of the first voltage dividing branch, and includes a third fixed resistor R70, a second varistor R72, and a fourth fixed resistor R71 sequentially connected in series between a second reference voltage (such as vref_amp_5v_1 of fig. 3) and a second programming voltage (such as vcc_amp_ -20v_1 of fig. 3).
Referring to FIG. 3, a positive power supply terminal of the second operational amplifier circuit inputs a second power supply voltage (e.g., UT4_P5V labeled in FIG. 3), a negative power supply terminal of the second operational amplifier circuit inputs a second programming voltage (e.g., VCC_AMP_ -20V_1 labeled in FIG. 3), a non-inverting terminal of the second operational amplifier circuit is grounded, and an inverting terminal of the second operational amplifier circuit is connected to the second varistor (i.e., a junction of the second varistor R72 and the third fixed resistor R70).
Therefore, based on the connection relationship between the voltage dividing branch and the operational amplifier, it can be known that the second voltage dividing voltage satisfies the following relationship: clamp_voltage 1=vref_amp 1R 22/R10, the second VOLTAGE division VOLTAGE is denoted clamp_voltage2, the resistance value of the second varistor R72 in the second VOLTAGE division branch is denoted R22, the resistance value of the third fixed resistor R70 in the second VOLTAGE division branch is denoted R20, and the second reference VOLTAGE is denoted vref_amp2.
For example, when vref_amp2 = 5V, r22 = 36kΩ, and r20 = 100kΩ, then the second voltage divider is about-2.5V (specifically, -1.8V).
In addition, the output end of the first operational amplifier circuit is connected in series with a resistor (such as R67 illustrated in fig. 2) and then connected with the anode of the first clamping diode D5, and the cathode of the first clamping diode D5 inputs a first divided voltage (such as +7v_clamp_1 illustrated in fig. 2); and, the output end of the second operational amplifier circuit is connected in series with the resistor and then connected to the cathode of the second clamping diode D7, and the anode of the second clamping diode D7 inputs the second divided voltage (for example, -2.5v_clamp_1 illustrated in fig. 3).
The operational amplifier has high amplification factor, can amplify the voltage, has the characteristics of strong load capacity and low output resistance, and the output end is very suitable for being connected with a load. In addition, the varistor may change its own resistance to function as a control circuit, and the sliding varistor may be used as a constant resistance or a variable resistance, or may be selected to be a type of physical sliding adjustment or a type of digital control adjustment, and is not limited herein. In addition, the precise measuring unit is a measuring unit with high performance, high integration and high precision, can output current and voltage through programming, can regulate output through programming, and has a very wide output range, such as a voltage range of-10V to +10V, and even wider.
The principle of operation of the above circuit, i.e., the schematic of the PMU regulating the clamp voltage, is as follows:
(1) Through the fixed resistor and the slide rheostat on the voltage dividing branch, a divided voltage is formed to supply power to an operational amplifier (OP amplifier) and input into an inverting terminal (IN-), so that stable output is formed by the operational amplifier;
(2) The input level of the amplifier is controlled by changing the value of the slide rheostat;
(3) The output of the clamping voltage is equal to the value of the resistor and sliding varistor partial voltage, and clamps the test signal (TEST SIGNAL) to a suitable range, such as-2.5 v-7 v as in the previous example, through a clamping diode (diode).
Therefore, based on the circuit characteristics, namely by utilizing the high gain characteristic of the operational amplifier, the potential of one end of the clamping diode is adjustable, namely the PMU can be controlled in a programming mode, and the range of the clamping voltage is adjustable under the action of the programming voltage of the precision measurement unit by utilizing the first voltage division voltage and the second voltage division voltage, so that the device can flexibly adapt to the actual signal testing requirement.
Referring to fig. 4, for the application of clamping protection for test connection of test signals (such as differential APT1_ A, APT2 _2_a, etc.), since the test signals may be connected to low-voltage boards such as digital boards and analog boards, the above-mentioned clamping circuit may be used to perform clamping protection on the group of signals, so as to avoid overvoltage impact caused by high voltage on the digital boards or analog boards for test. Specifically, referring to fig. 5, the test signal is respectively connected to the aforementioned CLAMP circuit through diodes, such as tc_apt1_a is connected to an upper limit terminal (i.e., PS1600_clamp_h illustrated in fig. 5) and a lower limit terminal (i.e., PS1600_clamp_l illustrated in fig. 5) of the CLAMP voltage through a CLAMP diode D01015, wherein the upper limit terminal may be +7v_clamp_1 illustrated in fig. 2, and the lower limit terminal may be-2.5v_clamp_1 illustrated in fig. 3. Therefore, the clamping circuit can effectively clamp the test signal, and the clamping voltage can be flexibly adjusted according to the clamping requirement of the test signal.
In some embodiments, a switch protection transistor is added at the clamping end, and the transistor is used for bearing the overshoot voltage instantaneously applied.
Referring to fig. 2 and 3, the clamp voltage adjustable circuit further includes: the first transistor and the second transistor, i.e. the Q1, Q2MOS switch transistors in the illustration. The Gate (Gate) of the first transistor Q1 is connected to the anode of the first clamp diode D5, the Source (Source) of the first transistor Q1 is connected to the cathode of the first clamp diode D5, and the Drain (Drain) of the first transistor D5 is grounded. Similarly, the gate of the second transistor Q2 is connected to the cathode of the second clamp diode D7, the source of the second transistor Q2 is connected to the anode of the second clamp diode D7, and the drain of the second transistor Q2 is grounded.
In some embodiments, an RC filter circuit may be utilized to improve circuit stability for the clamp. Specifically, the clamp voltage adjustable circuit further includes: a first capacitance (such as C562 illustrated in fig. 2) and a second capacitance (such as C68 illustrated in fig. 3); the first capacitor is connected in series between the anode of the first clamping diode and the ground, and a resistor connected in series with the output end of the first operational amplifier forms a filter circuit; the second capacitor is connected in series between the cathode of the second clamping diode and the ground, and the second capacitor and a resistor connected in series with the output end of the second operational amplifier form a filter circuit. The stability of the transistor grid electrode is further improved through the RC circuit, and the stability of the clamping circuit is guaranteed.
In some embodiments, the precision measurement unit can adopt a microcontroller to carry out closed-loop control, and flexible programming control is also convenient according to the requirement of an actual test signal on the clamping voltage.
In practice, a microcontroller and analog to digital conversion circuitry are employed for closed loop control of programming. Referring to fig. 6 or 7, the analog-to-digital conversion circuit is used for performing analog-to-digital conversion on the programming output of the precision measurement unit; when the microcontroller executes the detection instruction, such as when testing is performed on a certain signal, the corresponding clamping voltage needs to be specified, and at this time, the controller can instruct the precision measurement unit to output the corresponding programming voltage, so that an effective clamping voltage is formed according to the clamping circuit. Furthermore, the controller can also perform real-time programming closed-loop control on the precision measurement unit in the test according to the detection instruction and in combination with the conversion result of the analog-to-digital conversion circuit, so that the precision measurement unit outputs corresponding first programming voltage and second programming voltage, and the controller can meet the preset error requirement in the whole test, thereby providing more reliable clamping protection for the test circuit.
In some embodiments, the microcontroller is communicatively coupled to the analog-to-digital conversion circuit and the precision measurement unit via an SPI interface, respectively. Specifically, the microcontroller reads data of the analog-to-digital converter through the SPI protocol, and communicates with the PMU through the SPI protocol, so that the PMU outputs in real time according to programming control.
Referring to the connection schematic of fig. 6, a Microcontroller (MCU) programming controls the PMU as follows:
(1) When the SPI_CS signal of the MCU changes from high level to low level, the PMU equipment is enabled;
(2) The SPI_SCK of the MCU always transmits a square wave with a fixed period;
(3) The MCU transmits data to the PMU through SPI_MISO signals;
(4) The PMU transmits data to the MCU through the SPI_MOSI;
(5) The digital quantity corresponding to the voltage desired to be output by the PMU is sent to the PMU via MISO.
(6) In the test, the ADC is combined to carry out the conversion result of the analog-digital conversion, and whether the output value of the PMU is the same as the programmed value is judged. If the two types are the same, judging OK; if not, the PMU is calibrated so that the output voltage is the same as the programmed voltage. It should be noted that the calibration of the PMU may refer to the prior art, and is not limited herein.
In some embodiments, for the required operating power supply of each circuit in the clamping circuit, a voltage stabilizing circuit can be utilized to stabilize the input power supply to form the required operating voltage. In practice, the voltage stabilizing circuit may be in the form of a linear voltage stabilizing circuit, a DC-DC switching power supply, or the like.
The following is an example of a DC-DC switching power supply and a non-DC switching power supply, respectively.
Assuming an input power supply of 12V and pmu operating voltages including + 15V and 5V reference, these operating voltages may be formed using a plurality of voltage regulators, respectively.
In one example, multiple regulated power supplies may be used. The Power supply circuit comprises a first voltage stabilizing circuit (Power IC_1), a second voltage stabilizing circuit (Power IC_2) and a third voltage stabilizing circuit (REFERENCE VOLTAGE IC). Specifically, the first voltage stabilizing circuit is used for providing analog positive voltage required by the operation of the analog circuit to the precision measuring unit, the second voltage stabilizing circuit and the third voltage stabilizing circuit after stabilizing the voltage of the input power supply; the second voltage stabilizing circuit is used for forming an analog negative voltage after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit so as to provide the required analog negative voltage for the precision measuring unit; the third voltage stabilizing circuit is used for forming a reference voltage required by a reference standard after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit.
Referring to fig. 7, an example of a power supply circuit constituted by a plurality of voltage regulators is as follows: the input 12V power supply outputs a 15V voltage to supply power to the PMU and the OP amplifier-1 in a Boost mode through the power IC_1; power IC_2 outputs a voltage of-15V to supply Power to PMU and OP amplifier-2 by using BUCK to step down through a channel ①; ) Power IC_1 outputs a 5V reference (REFERENCE VOLTAGE) via path ② using BUCK BUCK to Power the PMU and ADC.
In one example, this may be accomplished using a single DC-DC power supply and a reference base power supply. Referring to fig. 8, an example of the power supply circuit is as follows: the input 5V power supply forms ±24v (pp_24v_clamp_sup, pn_24v_clamp_sup as illustrated in the drawing) by DC-DC power supply, and forms a 5V reference (pp5v0_clamp_ref as illustrated in the drawing) using a reference voltage regulator.
Based on the same inventive concept, the application also provides a semiconductor signal testing circuit. Wherein the test circuit comprises: clamp circuitry and test interface. Specifically, the clamping circuit is a clamping circuit with adjustable clamping voltage according to any implementation example of the application; the clamping circuit is connected with the test interface and can be illustrated by referring to the foregoing fig. 4 and 5, so that the clamping circuit provided by the application can carry out programming control through the precision measurement unit, and therefore, when different clamping voltages are needed for the test signal, the programming control can be flexibly carried out, so that the test signal is clamped in a safe voltage range, the test signal is prevented from generating signal short circuit to a low-voltage digital board card, an analog board card and the like, and the high-voltage board card and the digital board card or the analog board card are connected together to damage the digital board card and the analog board card, and the load and the test board card can be simultaneously protected from damage. Therefore, by providing clamping voltage adjustable characteristics, a wide variety of loads can be supported, and very effective clamping protection can be provided for the test interface.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the description is relatively simple for the embodiments described later, and reference is made to the description of the foregoing embodiments for relevant points.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A clamp circuit with an adjustable clamp voltage, comprising: the device comprises a precision measurement unit, a first operational amplifier circuit, a second operational amplifier circuit, a first clamping diode, a second clamping diode, a first voltage division branch and a second voltage division branch;
The precision measurement unit outputs a first programming voltage and a second programming voltage respectively, wherein the first programming voltage is a positive voltage, and the second programming voltage is a negative voltage;
The first voltage dividing branch comprises a first fixed resistor, a first rheostat and a second fixed resistor which are sequentially connected in series between a first programming voltage and ground;
the second voltage dividing branch circuit comprises a third fixed resistor, a second rheostat and a fourth fixed resistor which are sequentially connected in series between a second reference voltage and a second programming voltage;
The positive power end of the first operational amplifier circuit inputs a first programming voltage, the negative power end of the first operational amplifier circuit is grounded, the positive end of the first operational amplifier circuit inputs a first reference voltage, and the reverse end of the first operational amplifier circuit is connected with a sliding tap of the first rheostat;
The positive power end of the second operational amplifier circuit inputs a second power voltage, the negative power end of the second operational amplifier circuit inputs a second programming voltage, the positive phase end of the second operational amplifier circuit is grounded, and the reverse phase end of the second operational amplifier circuit is connected with a sliding tap of the second rheostat;
The output end of the first operational amplifier circuit is connected with the anode of the first clamping diode after being connected with the resistor in series, and the cathode of the first clamping diode inputs a first partial voltage;
The output end of the second operational amplifier circuit is connected with the cathode of the second clamping diode after being connected with the resistor in series, and the anode of the second clamping diode inputs a second partial voltage;
The first voltage division branch forms a first voltage division voltage, the second voltage division branch forms a second voltage division voltage, and the first voltage division voltage and the second voltage division voltage are correspondingly used as adjustable first clamping voltage and second clamping voltage under the action of programming voltage of the precision measurement unit; and the first divided voltage and the second divided voltage correspond to satisfy the following relation:
CLAMP_VOLTAGE1=VREF_AMP1*(R11+R10)/R10；
CLAMP_VOLTAGE2=VREF_AMP2*R22/R20；
Wherein clamp_voltage1 is denoted as a first VOLTAGE division VOLTAGE, R11 is denoted as a resistance value of the first varistor in the first VOLTAGE division branch, R10 is denoted as a resistance value of the second fixed resistor in the first VOLTAGE division branch, and vref_amp1 is denoted as a first reference VOLTAGE; clamp_voltage2 is denoted as the second divided VOLTAGE, R22 is denoted as the resistance of the second varistor in the second VOLTAGE dividing branch, R20 is denoted as the resistance of the third fixed resistor in the first VOLTAGE dividing branch, and vref_amp2 is denoted as the second reference VOLTAGE.
2. The clamp circuit of claim 1, wherein the clamp circuit further comprises: a microcontroller and an analog-to-digital conversion circuit; the analog-to-digital conversion circuit is used for performing analog-to-digital conversion on the programming output of the precision measurement unit; the microcontroller is used for responding to the detection instruction, and programming and controlling the precise measurement unit according to the detection instruction and the conversion result of the analog-to-digital conversion circuit, so that the precise measurement unit outputs corresponding first programming voltage and second programming voltage to meet the preset error requirement.
3. The clamp circuit with adjustable clamp voltage according to claim 2, wherein the microcontroller is in communication with the analog-to-digital conversion circuit and the precision measurement unit via SPI interfaces, respectively.
4. The clamp voltage adjustable clamp circuit of claim 1, wherein the clamp voltage adjustable circuit further comprises: a first transistor and a second transistor; the grid electrode of the first transistor is connected with the anode of the first clamping diode, the source electrode of the first transistor is connected with the cathode of the first clamping diode, and the drain electrode of the first transistor is grounded; the grid of the second transistor is connected with the cathode of the second clamping diode, the source electrode of the second transistor is connected with the anode of the second clamping diode, and the drain electrode of the second transistor is grounded.
5. The clamp voltage-adjustable clamp circuit of claim 4, further comprising: a first capacitor and a second capacitor; the first capacitor is connected in series between the anode of the first clamping diode and the ground, and a resistor connected in series with the output end of the first operational amplifier forms a filter circuit; the second capacitor is connected in series between the cathode of the second clamping diode and the ground, and the second capacitor and a resistor connected in series with the output end of the second operational amplifier form a filter circuit.
6. The clamp voltage adjustable clamp circuit of claim 1, wherein the clamp voltage adjustable circuit further comprises: and the power supply circuit is used for respectively providing the working voltage required by the precision measurement unit, the first reference voltage, the second reference voltage and the second power supply voltage after stabilizing the input power supply.
7. The clamp circuit of claim 6, wherein the power supply circuit comprises a first voltage regulator circuit, a second voltage regulator circuit, and a third voltage regulator circuit;
the first voltage stabilizing circuit is used for stabilizing the voltage of the input power supply and providing analog positive voltages required by the operation of the analog circuits for the precision measuring unit, the second voltage stabilizing circuit and the third voltage stabilizing circuit respectively;
the second voltage stabilizing circuit is used for forming an analog negative voltage after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit so as to provide the required analog negative voltage for the precision measuring unit;
the third voltage stabilizing circuit is used for forming a reference voltage required by a reference standard after stabilizing the voltage according to the analog positive voltage provided by the first voltage stabilizing circuit.
8. The clamp circuit of claim 7, wherein the first voltage regulator circuit comprises a Boost circuit, wherein the Boost circuit is configured to output a first positive voltage as an analog positive voltage after boosting and voltage stabilization according to an input power supply;
The second voltage stabilizing circuit comprises a Buck circuit, wherein the Buck circuit is used for stabilizing the first positive voltage and then outputting the first negative voltage as an analog negative voltage;
the third voltage stabilizing circuit comprises a reference voltage stabilizer, wherein the reference voltage stabilizer is used for carrying out voltage reduction and voltage stabilization on the first positive voltage.
9. The clamp circuit of claim 6, wherein the power supply circuit comprises a DC-DC voltage regulator and a reference voltage regulator, wherein the DC-DC voltage regulator is configured to respectively form an analog positive voltage and an analog negative voltage after the input power supply is regulated; the reference voltage stabilizer is used for carrying out voltage reduction and voltage stabilization on the analog positive voltage to form a reference standard.
10. A semiconductor signal testing circuit, comprising: a clamping circuit and a test interface; wherein the clamping circuit is the clamping circuit with adjustable clamping voltage as claimed in any one of claims 1-9; the clamping circuit is connected with the test interface to provide clamping protection for the test interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410578353.3A CN118150972B (en) | 2024-05-11 | 2024-05-11 | Clamping circuit with adjustable clamping voltage and semiconductor signal testing circuit |
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| CN202410578353.3A CN118150972B (en) | 2024-05-11 | 2024-05-11 | Clamping circuit with adjustable clamping voltage and semiconductor signal testing circuit |
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| CN118150972B true CN118150972B (en) | 2024-07-23 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147908A (en) * | 1997-11-03 | 2000-11-14 | Cypress Semiconductor Corp. | Stable adjustable programming voltage scheme |
| US6456557B1 (en) * | 2001-08-28 | 2002-09-24 | Tower Semiconductor Ltd | Voltage regulator for memory device |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139761A (en) * | 1984-12-12 | 1986-06-27 | Nec Corp | Voltage detection circuit |
| US5457621A (en) * | 1992-02-21 | 1995-10-10 | Abb Power T&D Company Inc. | Switching power supply having voltage blocking clamp |
| US6922346B2 (en) * | 2003-07-23 | 2005-07-26 | Texas Instruments Incorporated | System and method to limit maximum duty cycle and/or provide a maximum volt-second clamp |
| JP4589240B2 (en) * | 2006-01-13 | 2010-12-01 | 菊水電子工業株式会社 | Clamp circuit and test signal generator |
| JP5661231B2 (en) * | 2008-01-17 | 2015-01-28 | 中国電力株式会社 | Clamp meter and DC ground fault circuit search method |
| CN105092928B (en) * | 2015-07-23 | 2018-04-20 | 深圳市华谊智测科技股份有限公司 | Digital split-core type meter and its method for automatic measurement |
| CN108075750B (en) * | 2016-11-14 | 2023-06-30 | 恩智浦有限公司 | Current clamp circuit |
| CN116418207A (en) * | 2021-12-29 | 2023-07-11 | 圣邦微电子（北京）股份有限公司 | Circuit for keeping BOOST current limit value unchanged along with duty ratio by adopting dynamic clamping |
| CN217902333U (en) * | 2022-05-10 | 2022-11-25 | 深圳青铜剑技术有限公司 | Clamping circuit insensitive to temperature change and electronic equipment |
| CN115453305A (en) * | 2022-09-23 | 2022-12-09 | 重庆大学 | A voltage clamping circuit and its application |
| CN116413570A (en) * | 2023-04-17 | 2023-07-11 | 西安泽荃半导体科技有限公司 | Programming adjustment precision output circuit, load connection circuit and test substrate |
| CN116800212B (en) * | 2023-08-23 | 2023-11-03 | 中北大学 | Gain-adjustable non-contact ultrasonic receiving signal processing circuit with clamping function |
-
2024
- 2024-05-11 CN CN202410578353.3A patent/CN118150972B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147908A (en) * | 1997-11-03 | 2000-11-14 | Cypress Semiconductor Corp. | Stable adjustable programming voltage scheme |
| US6456557B1 (en) * | 2001-08-28 | 2002-09-24 | Tower Semiconductor Ltd | Voltage regulator for memory device |
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| CN118150972A (en) | 2024-06-07 |
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