CN118151710B - Capacitor-free voltage regulator circuit - Google Patents
Capacitor-free voltage regulator circuit Download PDFInfo
- Publication number
- CN118151710B CN118151710B CN202410585014.8A CN202410585014A CN118151710B CN 118151710 B CN118151710 B CN 118151710B CN 202410585014 A CN202410585014 A CN 202410585014A CN 118151710 B CN118151710 B CN 118151710B
- Authority
- CN
- China
- Prior art keywords
- driving
- tube
- constant current
- current source
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000001105 regulatory effect Effects 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 25
- 101000957559 Homo sapiens Matrin-3 Proteins 0.000 claims description 10
- 102100038645 Matrin-3 Human genes 0.000 claims description 10
- 230000004044 response Effects 0.000 abstract description 30
- 238000000034 method Methods 0.000 description 9
- 230000001276 controlling effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
The application relates to the technical field of integrated circuit design, and provides a capacitance-free voltage regulator circuit, which specifically comprises: a first driving circuit; the second driving circuit is connected with the first driving circuit; the third driving circuit is connected with the first driving circuit and the second driving circuit; wherein the first driving circuit, the second driving circuit and the third driving circuit are conducted when in a first driving mode; the first drive circuit is turned off and the second drive circuit and the third drive circuit are turned on when in the second drive mode. Different loops are connected in parallel, and voltage is regulated in one loop, so that good load response is achieved, the load response of the LDO in the second driving mode is improved, and reliability and stability are enhanced.
Description
Technical Field
The present application relates to the field of integrated circuit design, and more particularly, to a capacitor-less voltage regulator circuit.
Background
MCU, also called microcontroller or singlechip, is to reduce the frequency and specification of CPU properly, and integrate peripheral interfaces such as Memory, counter (Timer), USB, A/D conversion, UART, PLC, DMA, etc., even LCD driving circuit on a single chip to form chip level computer. Therefore, the terminal control function is realized, and the terminal control method has the advantages of high performance, low power consumption, programmability, high flexibility and the like.
Since in some MCU applications frequent switching to a low driving mode is required to save power consumption. There are also applications where low frequency operation in low drive mode is required, which requires a highly stable implementation of the CAPLAESS LDO switching.
In conventional CAPLAESS LDO circuits, the output stage is typically a FVF architecture, with a small drive loop to maintain the output voltage during low drive mode. But the load response of the LDO is poor due to the large compensation capacitance. Therefore, a high-stability and high-reliability CAPLAESS LDO circuit is needed, so that the LDO can obtain good load response in a low-driving mode, and the reliability and stability of the LDO are improved.
Disclosure of Invention
In order to solve the above problems, the present invention provides a capacitor-free voltage regulator circuit, which has the following specific technical scheme:
in some embodiments, the present invention provides a capacitance-free voltage regulator circuit comprising:
a first driving circuit;
the second driving circuit is connected with the first driving circuit;
the third driving circuit is connected with the first driving circuit and the second driving circuit;
Wherein the first driving circuit, the second driving circuit and the third driving circuit are conducted when in a first driving mode; the first drive circuit is turned off and the second drive circuit and the third drive circuit are turned on when in the second drive mode.
In some implementations, the first driving circuit includes: the device comprises a first constant current source, a second constant current source, a first NMOS tube, a first PMOS tube and a first driving tube;
The drain electrode of the first NMOS tube is connected with the first constant current source, the grid electrode of the first NMOS tube is connected with the fixed voltage input end, and the source electrode of the first NMOS tube and the second constant current source are connected to the ground;
The drain electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and the second constant current source, the grid electrode of the first PMOS tube is connected with the fixed voltage input end, and the source electrode of the first PMOS tube is connected with the drain electrode of the first driving tube;
The grid electrode of the first driving tube is connected with the output end of the first constant current source, and the source electrode of the first driving tube is connected with a power supply.
In some implementations, the second driving circuit includes: the third constant current source IP2, the fourth constant current source IN2, the second NMOS tube MN2, the second PMOS tube MP2 and the first driving tube MPD1;
the drain electrode of the second NMOS tube is connected with the third constant current source, the grid electrode of the second NMOS tube is connected with the fixed voltage input end, and the source electrode of the second NMOS tube and the fourth constant current source are connected to the ground;
The drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube and the fourth constant current source, the grid electrode of the second PMOS tube is connected with the fixed voltage input end, and the source electrode of the second PMOS tube is connected with the drain electrode of the first driving tube.
In some implementations, further comprising: the grid electrode of the first driving tube is connected with the output end of the third constant current source, the source electrode of the first driving tube is connected with the power supply voltage input end, and the drain electrode of the first driving tube is used as the output end of the first driving voltage.
In some implementations, further comprising: the first compensation circuit comprises a first capacitor and a first resistor;
The first end of the first capacitor is connected with the output end of the first constant current source, the output end of the third constant current source and the grid electrode of the first driving tube, and the second end of the first capacitor is connected with the first end of the first resistor;
the second end of the first resistor is connected with the power supply voltage input end.
In some implementations, the third driving circuit includes: the third constant current source, the fourth constant current source, the third NMOS tube, the third PMOS tube, the fourth PMOS tube, the first switch, the second switch and the second driving tube;
The drain electrode of the third NMOS tube is connected with the fifth constant current source, the grid electrode of the third NMOS tube is connected with the fixed voltage input end, the source electrode of the third NMOS tube and the sixth constant current source are connected to the ground, and the source electrode of the third NMOS tube is also connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube;
The drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and the sixth constant current source, the grid electrode of the third PMOS tube is connected with the fixed voltage input end, and the source electrode of the third PMOS tube is connected with the drain electrode of the second driving tube and the source electrode of the fourth PMOS tube;
The grid electrode of the fourth PMOS tube is connected with the first switch to a fixed voltage input end and is also connected with the second switch to a power supply voltage input end.
In some implementations, the method includes: the grid electrode of the second driving tube is connected with the output end of the fifth constant current source, the source electrode of the second driving tube is connected with the power supply voltage input end, and the drain electrode of the second driving tube is used as the output end of the second driving voltage.
In some implementations, further comprising: the second compensation circuit comprises a second capacitor and a second resistor;
The first end of the second capacitor is connected with the input end of the fifth constant current source and the grid electrode of the second driving tube, and the second end of the second capacitor is connected with the first end of the second resistor;
the second end of the second resistor is connected with the power supply voltage input end.
In some implementations, the method includes:
When the first driving mode is in the second driving mode, a fourth PMOS tube in the third driving circuit is regulated, and the first switch and the second switch in the third driving circuit are controlled so as to regulate the output voltage of the third driving circuit.
In some implementations, the method includes: when in the second driving mode, the first constant current source and the second constant current source are turned off, and the third driving circuit outputs a second driving voltage.
The capacitor-free voltage regulator circuit provided by the invention has at least the following beneficial effects:
The application provides a method for realizing switching of a high-stability CAPLAESS voltage regulator, which utilizes different loops to be connected in parallel and regulates voltage in one loop to achieve good load response, improves the load response in the LDO low-driving mode, and enhances the reliability and the stability.
Drawings
The above features, technical features, advantages and implementation thereof will be further described in the following detailed description of preferred embodiments with reference to the accompanying drawings in a clearly understandable manner.
FIG. 1 is a schematic diagram of one embodiment of a capacitance-free voltage regulator circuit of the present invention;
FIG. 2 is a schematic diagram of one embodiment of a capacitance-free voltage regulator circuit of the present invention;
FIG. 3 is a schematic diagram of an embodiment of a capacitance-free voltage regulator circuit according to the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
For the sake of simplicity of the drawing, the parts relevant to the present invention are shown only schematically in the figures, which do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
In conventional non-capacitive LDO (Low Dropout Regulaor, low dropout linear regulator) circuits, the output stage is typically FVF in which the output voltage is maintained by a small drive loop when in the second drive mode. But the load response of the LDO is poor due to the large compensation capacitance.
The application relates to the technical field of integrated circuit design and the field of single-chip computers, in particular to a capacitor-free voltage regulator of a single-chip computer chip, which is connected in parallel by utilizing different loops and regulates voltage in one loop so as to achieve high stability.
Referring to fig. 1, in one embodiment of the present application, in order to solve the problem of poor load response of the LDO circuit, the present application provides a capacitor-free voltage regulator circuit, which mainly includes:
A first driving circuit 100; a second driving circuit 200 connected to the first driving circuit 100; the third driving circuit 300 is connected to the first driving circuit 100 and the second driving circuit 200.
Wherein the first driving circuit 100, the second driving circuit 200, and the third driving circuit 300 are turned on when in the first driving mode; the first driving circuit 100 is turned off and the second driving circuit 200 and the third driving circuit 300 are turned on when in the second driving mode.
The first driving mode is a high driving mode, and the second driving mode is a low driving mode. The high driving mode is a mode in which the driving load current is large, and the low driving mode is a mode in which the driving load current is small. The first driving circuit 100 includes a large driving loop a, the second driving circuit 200 includes a small driving loop B, and the third driving circuit 300 includes a small driving loop C. The constant current source bias current of the large driving loop A is large, so that the response capability can be fast, the constant current source bias current of the small driving loop B is small, so that the response capability is poor, and the small driving loop C is provided with a small driving tube and a small compensation capacitor which are independent, so that the small constant current source bias can obtain a fast response speed. The high driving mode is mainly driven by a large driving loop A, wherein the large driving loop A and a small driving loop B share a large driving tube and have large compensation capacitance.
In this embodiment, a small driving loop C is added on the basis of the conventional capacitance-free LDO circuit, that is, a third driving circuit in this embodiment, and in the low driving mode, an additional small driving loop C is added to form a parallel connection with the original large driving loop a (the first driving circuit) and the small driving loop B (the second driving circuit), and in the low driving mode, the load current is smaller, so that the compensation capacitance C2 is correspondingly reduced in the additional small driving loop C.
Specifically, there are two modes when the whole capacitor-free voltage regulator regulating circuit works, and when the capacitor-free voltage regulator regulating circuit is in the first driving mode, the first driving circuit (a large driving loop A), the second driving circuit (a small driving loop B) and the third driving circuit (a small driving loop C) are all opened; when in the second drive mode, the large drive loop A is closed and the small drive loop B and the small drive loop C remain operational. Because the compensating capacitor C2 in the small driving loop C and the grid capacitance of the output tube MPD2 are smaller, the LDO can obtain better load response.
In some implementations, the first drive circuit includes: the first constant current source IP1, the second constant current source IN1, the first NMOS tube MN1, the first PMOS tube MP1 and the first driving tube MPD1.
The drain electrode of the first NMOS tube MN1 is connected with a first constant current source IP1, the grid electrode of the first NMOS tube MN1 is connected with a fixed voltage input end, and the source electrode of the first NMOS tube MN1 and a second constant current source IN1 are connected to the ground; the drain electrode of the first PMOS tube MP1 is connected with the source electrode of the first NMOS tube MN1 and the second constant current source IN1, the grid electrode of the first PMOS tube MP1 is connected with the fixed voltage input end, and the source electrode of the first PMOS tube MP1 is connected with the drain electrode of the first driving tube MPD 1; the grid of the first driving tube MPD1 is connected with the output end of the first constant current source IP1, and the source electrode of the first driving tube MPD1 is connected with a power supply.
A second driving circuit comprising: the third constant current source IP2, the fourth constant current source IN2, the second NMOS tube MN2, the second PMOS tube MP2 and the first driving tube MPD1; the drain electrode of the second NMOS tube MN2 is connected with a third constant current source IP2, the grid electrode of the second NMOS tube MN2 is connected with a fixed voltage input end, and the source electrode of the second NMOS tube MN2 and a fourth constant current source IN2 are connected to the ground; the drain electrode of the second PMOS tube MP2 is connected with the source electrode of the second NMOS tube MN2 and the fourth constant current source IN2, the grid electrode of the second PMOS tube MP2 is connected with the fixed voltage input end, and the source electrode of the second PMOS tube MP2 is connected with the drain electrode of the first driving tube MPD 1.
Specifically, the first NMOS transistor MN1 and the second NMOS transistor MN2 are NMOS transistors with fixed voltage bias, and the first PMOS transistor MP1 and the second PMOS transistor MP2 are PMOS transistors with negative feedback voltage bias (another fixed voltage bias).
Since the LDO needs to output a larger current, the first driving tube MPD1 has a larger size, and the first constant current source IP1 and the second constant current source IN1 have larger DC power consumption, and the first NMOS tube MN1 and the first PMOS tube MP1 have larger sizes IN order to improve the load response. In the first driving mode, the output pipe MPD1 is driven mainly by the large driving loop a. The current of the third constant current source IP2 is 1/N times the current of the first constant current source IP1, while the current of the fourth constant current source IN2 is 1/N times the current of IN 1. The second NMOS transistor MN2 and the second PMOS transistor MP2 are also respectively scaled down in size in proportion to the first NMOS transistor MN1 and the second NMOS transistor MN2 (the first PMOS transistor MP 1). When IN the second drive mode, both IP1 and IN1 are turned off, the output voltage is maintained by the small drive loop. However, since the compensation capacitor C1 is larger and the currents IP2 and IN2 are smaller, the gate response of MPD1 is slower, resulting IN poor load response of LDO.
Referring to fig. 2, the output stage generally has FVF structure, IP1, IN1, IP2, and IN2 are constant current sources, MN1 and MN2 are NMOS transistors biased by a fixed voltage, MP1 and MP2 are PMOS transistors biased by a negative feedback voltage, and MPD1 is a first driving transistor MPD 1. R1 and C1 are compensation circuits, wherein IP1, IN1, MN1, MP1 and MPD1 form a large driving loop A; wherein IP2, IN2, MN2, MP2 and MPD1 constitute a small driving loop B. Since the LDO needs to output a larger current, the first driving transistor MPD1 is larger IN size, and IP1 and IN1 have larger DC power consumption and MN1 and MP1 have larger size IN order to improve the load response.
When in the first drive mode, the output pipe MPD1 is driven mainly by the large drive loop. The current of IP2 is 1/N times the current of IP1, while the current of IN2 is 1/N times the current of IN 1. MN2, MP2 also reduces in size in proportion to MN1, MN2, respectively.
When IN the second drive mode, both IP1 and IN1 are turned off, maintaining the output voltage by the small drive loop B. However, since the compensation capacitor C1 is larger and the currents IP2 and IN2 are smaller, the gate response of MPD1 is slower, resulting IN poor load response of LDO.
In this embodiment, since the third driving loop is added, in the low driving mode, the additional small driving loop C is connected in parallel with the original large driving loop a and the small driving loop B, and in the low driving mode, the load current is smaller, so that the compensation capacitor C2 and the second driving tube MPD2 in the additional small driving loop C are correspondingly reduced. When the first driving mode is adopted, the large driving loop A, the small driving loop B and the small driving loop C are all opened; when in the second drive mode, the large drive loop A is closed, and the small drive loop B and the small drive loop C remain active. Because the compensating capacitor C2 in the small driving loop C and the grid capacitance of the output tube MPD2 are smaller, the LDO can obtain better load response.
In some implementations, further comprising: the grid of the first driving tube MPD1 is connected with the output end of the third constant current source IP2, the source electrode of the first driving tube MPD1 is connected with the power supply voltage input end, and the drain electrode of the first driving tube MPD1 serves as the output end of the first driving voltage.
The first compensation circuit (which can effectively increase loop stability of the first driving circuit and the second driving circuit) comprises a first capacitor C1 and a first resistor R1; the first end of the first capacitor C1 is connected with the output end of the first constant current source IP1, the output end of the third constant current source IP2 and the grid electrode of the first driving tube MPD1, and the second end of the first capacitor C1 is connected with the first end of the first resistor R1; the second end of the first resistor R1 is connected with the power supply voltage input end.
In some implementations, the third driving circuit includes: the third constant current source IP3, the sixth constant current source IN3, the third NMOS tube MN3, the third PMOS tube MP3, the fourth PMOS tube MP4, the first switch S1, the second switch S2 and the second driving tube MPD2;
the drain electrode of the third NMOS tube is connected with a fifth constant current source, the grid electrode of the third NMOS tube is connected with a fixed voltage input end, the source electrode of the third NMOS tube is connected with a sixth constant current source to be grounded, and the source electrode of the third NMOS tube is also connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube;
The drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and the sixth constant current source, the grid electrode of the third PMOS tube is connected with the fixed voltage input end, and the source electrode of the third PMOS tube is connected with the drain electrode of the second driving tube and the source electrode of the fourth PMOS tube;
The grid electrode of the fourth PMOS tube is connected with the first switch to the fixed voltage input end and is also connected with the second switch to the power supply voltage input end.
The grid electrode of the second driving tube is connected with the output end of the fifth constant current source, the source electrode of the second driving tube is connected with the power supply voltage input end, and the drain electrode of the second driving tube is used as the output end of the second driving voltage.
The output voltages VCORE of the large driving loop a, the small driving loop B and the additionally added small driving loop C are theoretically identical due to the same bias voltage, but in reality, the output voltages thereof may differ due to the process mismatch problem. In the first driving mode, the loops are all opened, and if the output voltage of the small driving loop C is higher than that of the large driving loop A and the small driving loop B, the output driving tubes of the large driving loop A and the small driving loop B are closed, so that the load response is poor in the first driving mode. By adjusting the size of the MP3 tube of the small driving loop C and controlling the switches S1 and S2 to control whether to connect the MP4 tube in parallel to the MP3 tube, the output voltage of the small driving loop C is adjusted, and the load response in the second driving mode can be effectively enhanced while the load response in the first driving mode is not changed.
In the first driving mode, the S1 is turned on, the S2 is turned off, the MP4 tube is connected to the MP3 tube in parallel, so that the direct current output voltage of the small driving loop C is lower, and after the outputs of the large driving loop A, the small driving loop B and the small driving loop C are short-circuited, the driving tube MPD2 of the small driving loop C is turned off due to the fact that the output voltages of the large driving loop A and the small driving loop B are higher, and therefore the LDO mainly provides current by the large driving loop A, the small driving loop B and the first driving tube MPD1 in the first driving mode.
In the second driving mode, the large driving loop A is closed, the small driving loop B and the small driving loop C keep working, S1 is disconnected, S2 is conducted, the direct current output voltage of the small driving loop C is higher than that of the small driving loop B, the driving pipes MPD1 of the large driving loop A and the small driving loop B are closed, the LDO mainly provides current by the small driving loop C and the driving pipe MPD2, and therefore the LDO can obtain good load response in the low driving mode, and reliability and stability of the LDO are improved.
In some implementations, further comprising: the second compensation circuit (which can effectively increase the loop stability of the third driving circuit) comprises a second capacitor C2 and a second resistor R2;
The first end of the second capacitor C2 is connected with the output end of the fifth constant current source and the grid electrode of the second driving tube, and the second end of the second capacitor C2 is connected with the first end of the second resistor R2;
the second end of the second resistor R2 is connected with the power supply voltage input end.
In some implementations, the method includes:
When the first driving mode is in the second driving mode, the first PMOS tube in the first driving circuit is regulated, and the first switch and the second switch in the first driving circuit are controlled, so that the output voltage of the first driving circuit is regulated.
Specifically, by adjusting (slightly reducing) the size of the MP3 tube of the small driving loop C and controlling the switches S1 and S2 to control whether to connect the MP4 tube in parallel to the MP3 tube, the output voltage of the small driving loop C is adjusted, and the load response in the second driving mode can be effectively enhanced while the load response in the first driving mode is not changed.
In some implementations, the method includes: when IN the second driving mode, the first constant current source IP1 and the second constant current source IN1 are turned off, and the third driving circuit outputs the second driving voltage.
As shown IN FIG. 3, IN the capless LDO circuit proposed by the present application, IP3, IN3, MN3, MP4, S1, S2 and MPD2 form a small driving loop C, and IN the low driving mode, an additional small driving loop C is added to form a parallel connection with the original large driving loop A and small driving loop B, and IN the low driving mode, the load current is smaller, so that the compensation capacitance C2 is correspondingly reduced IN the additional small driving loop C. When the first driving mode is adopted, the large driving loop A, the small driving loop B and the small driving loop C are all opened; when in the second drive mode, the large drive loop A is closed, and the small drive loop B and the small drive loop C remain active. Because the compensating capacitor C2 in the small driving loop C and the grid capacitance of the output tube MPD2 are smaller, the LDO can obtain better load response.
The output voltages VCORE of the large driving loop a, the small driving loop B and the additionally added small driving loop C are theoretically identical due to the same bias voltage, but there is a difference in the output voltages due to the process mismatch problem.
In the first driving mode, if the output voltage of the small driving loop C is higher than the output voltages of the large driving loop a and the small driving loop B, the output first driving tube MPD1 of the large driving loop A, B is turned off, resulting in poor load response in the first driving mode. By adjusting the size of the MP3 tube of the small driving loop C and controlling the switch S1 and the switch S2 to control whether the MP4 tube is connected in parallel to the MP3 tube or not, the output voltage of the small driving loop C is adjusted, and the load response in the second driving mode can be effectively enhanced while the load response in the first driving mode is not changed.
Under the first driving mode, S1 is conducted, S2 is disconnected, an MP4 pipe is connected to an MP3 pipe in parallel, so that the direct current output voltage of a small driving loop C is lower, after the outputs of a large driving loop A, a small driving loop B and the small driving loop C are short-circuited, the output voltage of the large driving loop A and the small driving loop B is higher, and a first driving pipe MPD1MPD2 of the small driving loop C is turned off, so that the LDO mainly provides current by the large driving loop A, the small driving loop B and the first driving pipe MPD1 under the first driving mode.
In the second driving mode, the large driving loop a is closed, the small driving loop B, C keeps working, the S1 is disconnected, and the S2 is conducted, so that the direct current output voltage of the small driving loop C is higher than that of the small driving loop B, the first driving tubes MPD1 of the large driving loop a and the small driving loop B are closed, and the LDO mainly provides current by the small driving loop C and the driving tube MPD2, so that the LDO can obtain good load response in the low driving mode, and the reliability and the stability of the LDO are improved.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.
It should be noted that the above embodiments can be freely combined as needed. The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (10)
1. A capacitance-free voltage regulator circuit, comprising:
the first driving circuit comprises a large driving loop;
the second driving circuit comprises a small driving loop, and is connected with the first driving circuit;
the third driving circuit comprises a small driving loop, and is connected with the first driving circuit and the second driving circuit; the constant current source bias current of the large driving loop is larger than that of the small driving loop; the large driving loop of the first driving circuit and the small driving loop of the second driving circuit share a large driving tube, and the small driving loop of the third driving circuit is provided with an independent small driving tube;
The first driving circuit, the second driving circuit and the third driving circuit are conducted when the first driving circuit is in a first driving mode, and the first driving mode is a high driving mode; the first driving circuit is turned off and the second driving circuit and the third driving circuit are turned on when in a second driving mode, the second driving mode being a low driving mode.
2. The capacitance-free voltage regulator circuit according to claim 1, wherein the first driving circuit comprises: the device comprises a first constant current source, a second constant current source, a first NMOS tube, a first PMOS tube and a first driving tube;
The drain electrode of the first NMOS tube is connected with the first constant current source, the grid electrode of the first NMOS tube is connected with the fixed voltage input end, and the source electrode of the first NMOS tube and the second constant current source are connected to the ground;
The drain electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and the second constant current source, the grid electrode of the first PMOS tube is connected with the fixed voltage input end, and the source electrode of the first PMOS tube is connected with the drain electrode of the first driving tube;
The grid electrode of the first driving tube is connected with the output end of the first constant current source, and the source electrode of the first driving tube is connected with a power supply.
3. The capacitor-less voltage regulator circuit of claim 2, wherein the second drive circuit comprises: the third constant current source, the fourth constant current source, the second NMOS tube, the second PMOS tube and the first driving tube;
the drain electrode of the second NMOS tube is connected with the third constant current source, the grid electrode of the second NMOS tube is connected with the fixed voltage input end, and the source electrode of the second NMOS tube and the fourth constant current source are connected to the ground;
The drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube and the fourth constant current source, the grid electrode of the second PMOS tube is connected with the fixed voltage input end, and the source electrode of the second PMOS tube is connected with the drain electrode of the first driving tube.
4. A capacitance-free voltage regulator circuit according to claim 3, further comprising: the grid electrode of the first driving tube is connected with the output end of the third constant current source, the source electrode of the first driving tube is connected with the power supply voltage input end, and the drain electrode of the first driving tube is used as the output end of the first driving voltage.
5. The capacitance-free voltage regulator circuit of claim 4, further comprising: the first compensation circuit comprises a first capacitor and a first resistor;
The first end of the first capacitor is connected with the output end of the first constant current source, the output end of the third constant current source and the grid electrode of the first driving tube, and the second end of the first capacitor is connected with the first end of the first resistor;
the second end of the first resistor is connected with the power supply voltage input end.
6. The capacitor-less voltage regulator circuit of claim 5, wherein the third drive circuit comprises: the third constant current source IP3, the sixth constant current source IN3, the third NMOS tube MN3, the third PMOS tube MP3, the fourth PMOS tube MP4, the first switch S1, the second switch S2 and the second driving tube MPD2;
The drain electrode of the third NMOS tube is connected with the fifth constant current source, the grid electrode of the third NMOS tube is connected with the fixed voltage input end, the source electrode of the third NMOS tube and the sixth constant current source are connected to the ground, and the source electrode of the third NMOS tube is also connected with the drain electrode of the third PMOS tube and the drain electrode of the fourth PMOS tube;
The drain electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube and the sixth constant current source, the grid electrode of the third PMOS tube is connected with the fixed voltage input end, and the source electrode of the third PMOS tube is connected with the drain electrode of the second driving tube and the source electrode of the fourth PMOS tube;
The grid electrode of the fourth PMOS tube is connected with the first switch to a fixed voltage input end and is also connected with the second switch to a power supply voltage input end.
7. The capacitance-free voltage regulator circuit of claim 6, comprising: the grid electrode of the second driving tube is connected with the output end of the fifth constant current source, the source electrode of the second driving tube is connected with the power supply voltage input end, and the drain electrode of the second driving tube is used as the output end of the second driving voltage.
8. The capacitance-free voltage regulator circuit of claim 7, further comprising: the second compensation circuit comprises a second capacitor and a second resistor;
The first end of the second capacitor is connected with the output end of the fifth constant current source, the grid electrode of the second driving tube and the drain electrode of the third NMOS tube, and the second end of the second capacitor is connected with the first end of the second resistor;
the second end of the second resistor is connected with the power supply voltage input end.
9. The capacitance-free voltage regulator circuit of claim 6, comprising:
When the first driving mode is in, a fourth PMOS tube in the third driving circuit is regulated, and the first switch and the second switch in the third driving circuit are controlled, so that the output voltage of the third driving circuit is regulated.
10. The capacitance-free voltage regulator circuit of claim 9, comprising: when in the first driving mode, the first constant current source and the second constant current source are turned off, and the third driving circuit outputs a second driving voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410585014.8A CN118151710B (en) | 2024-05-13 | 2024-05-13 | Capacitor-free voltage regulator circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410585014.8A CN118151710B (en) | 2024-05-13 | 2024-05-13 | Capacitor-free voltage regulator circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118151710A CN118151710A (en) | 2024-06-07 |
| CN118151710B true CN118151710B (en) | 2024-07-19 |
Family
ID=91287126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410585014.8A Active CN118151710B (en) | 2024-05-13 | 2024-05-13 | Capacitor-free voltage regulator circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118151710B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549672A (en) * | 2015-12-21 | 2016-05-04 | 豪威科技(上海)有限公司 | Low-dropout linear regulator |
| CN114647268A (en) * | 2022-03-24 | 2022-06-21 | 中国科学院微电子研究所 | A low-dropout linear voltage regulator circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12332674B2 (en) * | 2022-05-10 | 2025-06-17 | Texas Instruments Incorporated | Low-dropout voltage regulator with split-buffer stage |
| US20230409064A1 (en) * | 2022-06-16 | 2023-12-21 | Texas Instruments Incorporated | Pseudo esr technique in a multi-loop low-dropout regulator |
| CN115903984B (en) * | 2022-12-21 | 2023-08-04 | 桂林海纳德半导体科技有限公司 | Self-adaptive super source follower circuit and LDO voltage stabilizing chip |
-
2024
- 2024-05-13 CN CN202410585014.8A patent/CN118151710B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105549672A (en) * | 2015-12-21 | 2016-05-04 | 豪威科技(上海)有限公司 | Low-dropout linear regulator |
| CN114647268A (en) * | 2022-03-24 | 2022-06-21 | 中国科学院微电子研究所 | A low-dropout linear voltage regulator circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118151710A (en) | 2024-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10114399B2 (en) | Distributed power delivery scheme for on-die voltage scaling | |
| CN111367345B (en) | Compensation method for improving full load stability of low dropout linear regulator and circuit thereof | |
| US6765374B1 (en) | Low drop-out regulator and an pole-zero cancellation method for the same | |
| US8710811B2 (en) | Voltage regulator with improved voltage regulator response and reduced voltage drop | |
| US6653891B1 (en) | Voltage regulation | |
| CN108508951B (en) | LDO voltage regulator circuit without off-chip capacitor | |
| CN114167933B (en) | Low-power-consumption and fast-transient-response low-dropout linear voltage regulator circuit | |
| CN1989683A (en) | Low dropout voltage regulator providing adaptive compensation | |
| JPH04129264A (en) | Semiconductor integrated circuit | |
| CN102915063A (en) | Voltage regulator with charge pump | |
| US20190025861A1 (en) | Fast transient response voltage regulator with pre-boosting | |
| CN113760031B (en) | Low quiescent current NMOS type full-integrated LDO circuit | |
| CN114840051B (en) | Low power consumption, high transient response, capacitor-free low dropout linear regulator | |
| US20130002213A1 (en) | Voltage regulator structure | |
| US20240178753A1 (en) | Regulator with flipped voltage follower architecture | |
| US20030184268A1 (en) | Protection circuit for miller compensated voltage regulators | |
| US7843183B2 (en) | Real time clock (RTC) voltage regulator and method of regulating an RTC voltage | |
| CN118151710B (en) | Capacitor-free voltage regulator circuit | |
| Tseng et al. | An integrated linear regulator with fast output voltage transition for dual-supply SRAMs in DVFS systems | |
| US5506495A (en) | Step-down circuit with stabilized internal power-supply | |
| CN115276635A (en) | Enabling output control circuit of high-voltage chip | |
| US11841723B2 (en) | Distributed LDO structure without external capacitor | |
| Cheng et al. | A low power high area-efficiency NMOS LDO with fast adaptive bias | |
| CN116610180A (en) | Low-dropout linear voltage regulator circuit mutually started with band-gap reference circuit | |
| CN216248988U (en) | A Compact Adaptive Bias NMOS LDO Circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |