CN118164427A - Preparation method of template with micron-sized oxide insulating layer hole array - Google Patents
Preparation method of template with micron-sized oxide insulating layer hole array Download PDFInfo
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- CN118164427A CN118164427A CN202211536077.1A CN202211536077A CN118164427A CN 118164427 A CN118164427 A CN 118164427A CN 202211536077 A CN202211536077 A CN 202211536077A CN 118164427 A CN118164427 A CN 118164427A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 229910004298 SiO 2 Inorganic materials 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000001704 evaporation Methods 0.000 claims abstract description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims abstract description 8
- 238000004528 spin coating Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000005566 electron beam evaporation Methods 0.000 claims description 7
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 47
- 239000002346 layers by function Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00214—Processes for the simultaneaous manufacturing of a network or an array of similar microstructural devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00087—Holes
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The application discloses a preparation method of a template with a micron-sized oxide insulating layer hole array. Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, and then depositing a SiO 2 layer on the surface; then spin coating a layer of positive photoresist on the surface of the sample; after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of metal nickel on the surface of a sample, leaving the metal nickel deposited on the exposure area on the surface of the sample after the photoresist removing process is finished, carrying out dry etching on SiO 2 under the metal nickel and the sample, and preparing a micrometer-sized hole array on the SiO 2 layer, so that an n-GaN layer is completely exposed at the bottom of the micrometer holes, and finally, finishing the manufacture of a template for epitaxially growing the semi-polar micrometer column array.
Description
Technical Field
The invention relates to the technical field of masks, in particular to a preparation method of a template with a micron-sized oxide insulating layer hole array.
Background
In the field of flat panel display, a thin film transistor is a key device for manufacturing a display device, and a mask is an indispensable tool in the process of manufacturing the thin film transistor. The product is made of quartz glass as a substrate, a layer of metal chromium and photoresist are plated on the quartz glass to form a photosensitive material, a designed circuit pattern is exposed on the photoresist through an electronic laser device, an exposed area is developed, a circuit pattern is formed on the metal chromium to form a photomask which is similar to an exposed negative film, and then the photomask is applied to projection positioning of an integrated circuit, and the projected circuit is subjected to photoetching through an integrated circuit photoetching machine, so that the photomask is an indispensable tool in the IC manufacturing process.
In the patterning process of each functional layer on the array substrate, a mask is often used to form a corresponding pattern. In general, the pattern of the mask corresponds to the pattern of the functional layer to be formed, and the mask includes a light-transmitting region and a light-impermeable region, in which light can be totally transmitted for exposure, so that photoresist in the region is totally removed; and (3) reserving the photoresist in the opaque region, and etching to obtain the corresponding pattern of the functional layer.
Disclosure of Invention
The invention aims to: aiming at the defects in the prior art, the invention provides a preparation method of a template with a micron-sized oxide insulating layer hole array.
The technical scheme is as follows: the preparation method of the template with the micron-sized oxide insulating layer hole array provided by the invention comprises the following steps:
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, and then depositing a SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology; then spin coating a layer of positive photoresist on the surface of the sample;
step 2, after exposure by the mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of the sample by utilizing electron beam evaporation, and after the photoresist removing process is finished, leaving the metal nickel deposited in the exposure area on the surface of the sample and having the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, and preparing a micrometer-sized hole array on the SiO 2 layer, so that the n-GaN layer is completely exposed at the bottom of the micrometer holes, and thus, completing the manufacture of the template for epitaxially growing the semi-polar micrometer column array.
Specifically, in step 1, the thickness of the n-GaN layer is 0.8-1.2 μm.
Specifically, in step 1, the carrier concentration is about 3×10 18cm-3.
Specifically, in the step 1, the thickness of the SiO 2 layer is 450-550nm.
Specifically, in step 1, the positive photoresist has a thickness of 0.8 to 1.2 μm.
Specifically, in the step 2, the thickness of the metallic nickel is 45-55nm.
Specifically, the etching depth in the step 3 needs to be controlled to be 550-650nm.
Further, a typical scheme of the template preparation method with the micron-sized oxide insulating layer hole array of the invention is as follows:
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, wherein the thickness of the n-GaN layer is 1 mu m, the carrier concentration is about 3 multiplied by 10 18cm-3, then depositing an SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology, and the thickness of the SiO 2 layer is 500nm; then spin coating a layer of positive photoresist on the surface of the sample, wherein the thickness of the positive photoresist is 1 mu m;
Step 2, after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of a sample by utilizing electron beam evaporation, wherein the thickness of the metal nickel is 50nm, and after the photoresist removing process is finished, the metal nickel deposited in the exposure area is left on the surface of the sample and has the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, preparing a micrometer-sized hole array on the SiO 2 layer, controlling the etching depth to be 600nm, and enabling the n-GaN layer to be completely exposed at the bottom of the micrometer holes, so that the manufacture of the template for epitaxially growing the semi-polar micrometer-column array is completed.
The beneficial effects are that: the method provided by the invention can obtain the template with the micron-sized oxide insulating layer hole array, and has application prospect in the related field.
Drawings
FIG. 1 is a schematic diagram of the preparation process of the present invention.
1-Quantum wells in the figure; 2-GaN; 3-photoresist; 4-SiO 2.
FIG. 2 is a scanning electron microscope image of SiO 2 pores of about 2 μm size prepared in example 1.
Detailed Description
The following is a detailed description of the present invention, but the scope of the present invention is not limited to the examples.
Example 1
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, wherein the thickness of the n-GaN layer is 1 mu m, the carrier concentration is about 3 multiplied by 10 18cm-3, then depositing an SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology, and the thickness of the SiO 2 layer is 500nm; then spin coating a layer of positive photoresist on the surface of the sample, wherein the thickness of the positive photoresist is 1 mu m;
Step 2, after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of a sample by utilizing electron beam evaporation, wherein the thickness of the metal nickel is 50nm, and after the photoresist removing process is finished, the metal nickel deposited in the exposure area is left on the surface of the sample and has the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, preparing a micrometer-sized hole array on the SiO 2 layer, controlling the etching depth to be 600nm, and enabling the n-GaN layer to be completely exposed at the bottom of the micrometer holes, so that the manufacture of the template for epitaxially growing the semi-polar micrometer-column array is completed.
Example 2
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, wherein the thickness of the n-GaN layer is 0.8 mu m, the concentration of a carrier is about 3 multiplied by 10 18cm-3, then depositing an SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology, and the thickness of the SiO 2 layer is 450nm; then spin coating a layer of positive photoresist on the surface of the sample, wherein the thickness of the positive photoresist is 0.8 mu m;
Step 2, after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of a sample by utilizing electron beam evaporation, wherein the thickness of the metal nickel is 45nm, and after the photoresist removing process is finished, the metal nickel deposited in the exposure area is left on the surface of the sample and has the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, preparing a micrometer-sized hole array on the SiO 2 layer, controlling the etching depth to be 550nm, and enabling the n-GaN layer to be completely exposed at the bottom of the micrometer holes, so that the manufacture of the template for epitaxially growing the semi-polar micrometer-column array is completed.
Example 3
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, wherein the thickness of the n-GaN layer is 1.2 mu m, the concentration of a carrier is about 3 multiplied by 10 18cm-3, then depositing an SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology, and the thickness of the SiO 2 layer is 550nm; then spin coating a layer of positive photoresist on the surface of the sample, wherein the thickness of the positive photoresist is 1.2 mu m;
Step 2, after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of a sample by utilizing electron beam evaporation, wherein the thickness of the metal nickel is 55nm, and after the photoresist removing process is finished, the metal nickel deposited in the exposure area is left on the surface of the sample and has the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, preparing a micrometer-sized hole array on the SiO 2 layer, controlling the etching depth to 650nm, and enabling the n-GaN layer to be completely exposed at the bottom of the micrometer holes, so that the template manufacturing for epitaxially growing the semi-polar micrometer-column array is completed.
The foregoing description is only of the preferred embodiments of the application and is not intended to limit the application.
Claims (8)
1. The preparation method of the template with the micron-sized oxide insulating layer hole array is characterized by comprising the following steps of:
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, and then depositing a SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology; then spin coating a layer of positive photoresist on the surface of the sample;
step 2, after exposure by the mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of the sample by utilizing electron beam evaporation, and after the photoresist removing process is finished, leaving the metal nickel deposited in the exposure area on the surface of the sample and having the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, and preparing a micrometer-sized hole array on the SiO 2 layer, so that the n-GaN layer is completely exposed at the bottom of the micrometer holes, and thus, completing the manufacture of the template for epitaxially growing the semi-polar micrometer column array.
2. The method for preparing a template with a micro-scale oxide insulating layer hole array according to claim 1, wherein in the step 1, the thickness of the n-GaN layer is 0.8-1.2 μm.
3. The method of claim 1, wherein in step1, the carrier concentration is about 3 x 10 18cm-3.
4. The method for preparing a template with a micron-sized oxide insulating layer hole array according to claim 1, wherein in the step 1, the thickness of the SiO 2 layer is 450-550nm.
5. The method for preparing a template having an array of holes of a micron-sized oxide insulating layer according to claim 1, wherein in step 1, the positive photoresist has a thickness of 0.8-1.2 μm.
6. The method for preparing a template with a micron-sized oxide insulating layer hole array according to claim 1, wherein in the step 2, the thickness of the metallic nickel is 45-55nm.
7. The method for preparing the template with the micron-sized oxide insulating layer hole array according to claim 1, wherein the etching depth is controlled to be 550-650nm in the step 3.
8. The method for preparing the template with the micron-sized oxide insulating layer hole array according to claim 1, comprising the following steps:
Firstly, epitaxially growing an n-GaN layer on a GaN epitaxial wafer by using an MOCVD system, wherein the thickness of the n-GaN layer is 1 mu m, the carrier concentration is about 3 multiplied by 10 18cm-3, then depositing an SiO 2 layer on the surface by using a plasma enhanced chemical vapor deposition technology, and the thickness of the SiO 2 layer is 500nm; then spin coating a layer of positive photoresist on the surface of the sample, wherein the thickness of the positive photoresist is 1 mu m;
Step 2, after exposure by a mask plate, immersing the mask plate into a developing solution to remove photoresist in an exposure area, evaporating a layer of thick metal nickel on the surface of a sample by utilizing electron beam evaporation, wherein the thickness of the metal nickel is 50nm, and after the photoresist removing process is finished, the metal nickel deposited in the exposure area is left on the surface of the sample and has the same pattern as the mask plate;
And 3, taking the pattern as a mask plate, adopting reactive ion etching to carry out dry etching on SiO 2 and a sample under the metallic nickel, preparing a micrometer-sized hole array on the SiO 2 layer, controlling the etching depth to be 600nm, and enabling the n-GaN layer to be completely exposed at the bottom of the micrometer holes, so that the manufacture of the template for epitaxially growing the semi-polar micrometer-column array is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211536077.1A CN118164427A (en) | 2022-12-02 | 2022-12-02 | Preparation method of template with micron-sized oxide insulating layer hole array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211536077.1A CN118164427A (en) | 2022-12-02 | 2022-12-02 | Preparation method of template with micron-sized oxide insulating layer hole array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118164427A true CN118164427A (en) | 2024-06-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211536077.1A Pending CN118164427A (en) | 2022-12-02 | 2022-12-02 | Preparation method of template with micron-sized oxide insulating layer hole array |
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| Country | Link |
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| CN (1) | CN118164427A (en) |
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2022
- 2022-12-02 CN CN202211536077.1A patent/CN118164427A/en active Pending
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