CN118213311A - A method for preparing a semiconductor device, a wafer structure and a semiconductor device - Google Patents
A method for preparing a semiconductor device, a wafer structure and a semiconductor device Download PDFInfo
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- CN118213311A CN118213311A CN202410316160.0A CN202410316160A CN118213311A CN 118213311 A CN118213311 A CN 118213311A CN 202410316160 A CN202410316160 A CN 202410316160A CN 118213311 A CN118213311 A CN 118213311A
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
本发明公开了一种半导体器件的制备方法及半导体器件，应用于半导体器件制备技术领域，包括：获得正面用于形成有功能区及非功能区的晶圆；在非功能区刻蚀出预设深度的对位点；对位点的底面与晶圆背面的距离小于晶圆背面的减薄厚度；在设置对位点以及功能结构后，从晶圆的背面对晶圆进行减薄，暴露对位点；在晶圆的背面设置背面功能结构，完成半导体器件的制备。通过在晶圆的正面设置预设深度的对位点，此时晶圆的正面功能结构可以与该对位点相互对位。而在对晶圆背面进行减薄后，会在晶圆背面暴露该对位点，之后在设置背面功能结构时需要将背面功能结构与对位点相互对位，实现正面功能结构与背面功能结构的相互对位。
The present invention discloses a method for preparing a semiconductor device and a semiconductor device, which are applied to the technical field of semiconductor device preparation, including: obtaining a wafer with a functional area and a non-functional area formed on the front side; etching an alignment point of a preset depth in the non-functional area; the distance between the bottom surface of the alignment point and the back side of the wafer is less than the thinning thickness of the back side of the wafer; after setting the alignment point and the functional structure, thinning the wafer from the back side of the wafer to expose the alignment point; setting the back side functional structure on the back side of the wafer to complete the preparation of the semiconductor device. By setting the alignment point of a preset depth on the front side of the wafer, the front side functional structure of the wafer can be aligned with the alignment point. After thinning the back side of the wafer, the alignment point will be exposed on the back side of the wafer. After that, when setting the back side functional structure, the back side functional structure needs to be aligned with the alignment point to achieve mutual alignment between the front side functional structure and the back side functional structure.
Description
Technical Field
The present invention relates to the field of semiconductor device manufacturing technology, and in particular, to a method for manufacturing a semiconductor device, a wafer structure, and a semiconductor device.
Background
Photolithography is a process whereby specific portions of a thin film on the surface of a wafer are removed through a series of production steps. After this, the wafer surface will leave a film with the micropatterned structure. The photolithography process generally comprises the steps of cleaning and drying the surface of a wafer substrate, priming, spin coating photoresist, soft baking, aligning exposure, post baking, developing, hard baking, etching, detecting and the like.
Along with the diversification of the semiconductor device structure, functional structures are required to be arranged on the front surface and the back surface of the wafer at the present stage, and the functional structures on the front surface and the back surface are required to be mutually aligned. However, at the present stage, the existing exposure machine cannot realize the front and back alignment of the wafer, and has no such process capability. Therefore, how to realize the alignment of the functional structures on the front and back sides of the wafer is a urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which can realize the alignment of the functional structures on the front and back sides of a wafer; the invention also provides a wafer structure and a semiconductor device, which can realize the alignment of the functional structures on the front and back surfaces of the wafer.
In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, including:
Obtaining a wafer with a front surface for forming a functional area and a nonfunctional area, wherein the functional area is used for setting a functional structure of a chip;
Etching opposite sites with preset depth in the nonfunctional area; the distance between the bottom surface of the opposite point and the back surface of the wafer is smaller than the thickness of the back surface of the wafer; the position of the front functional structure can be mutually aligned with the position of the alignment point;
After the alignment points and the functional structures are arranged, thinning the wafer from the back surface of the wafer to expose the alignment points;
A back functional structure is arranged on the back of the wafer, so that the preparation of the semiconductor device is completed; the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
Optionally, etching the alignment point with the preset depth in the nonfunctional area includes:
Setting photoresist on the front surface of the wafer and exposing the photoresist to expose preset position points;
and etching opposite sites with preset depth at the opposite sites on the front surface of the wafer through a plasma etching process.
Optionally, setting photoresist on the front surface of the wafer and exposing the photoresist, and before exposing the preset position location, further including:
and arranging a front functional structure on the front surface of the wafer.
Optionally, before thinning the wafer from the back surface of the wafer to expose the alignment point, the method further includes:
and packaging the front surface of the wafer.
Optionally, encapsulating the front side of the wafer includes:
Filling PI glue on the front surface of the wafer;
gold is leached on the front side of the wafer based on the ENIG process.
Optionally, after packaging the front surface of the wafer, the method further includes:
And bonding a substrate on the front surface of the wafer.
Optionally, etching the alignment point with the preset depth on the front surface of the wafer provided with the front surface functional structure includes:
and etching a plurality of opposite sites with preset depth on the front surface of the wafer provided with the front functional structure.
Optionally, the distance between the plurality of pairs of points is not smaller than the radius of the wafer.
Optionally, disposing a back side functional structure on the back side of the wafer includes:
A back gold array is arranged on the back surface of the wafer; the back gold array comprises a plurality of back gold modules, and the back gold array and the alignment points are mutually aligned so that the back gold modules and the functional areas are mutually aligned.
Optionally, disposing a back gold array on the back side of the wafer includes:
setting a seed layer on the back surface of the wafer;
setting an isolation layer corresponding to the back cutting channel on the surface of the seed layer based on the position of the positioning point;
plating a back gold module on the area, which is not shielded by the isolating layer, of the surface of the seed layer to form a back gold array;
and removing the isolation layer after the back gold array is formed, and exposing the back cutting channel.
The invention also provides a wafer structure, wherein a functional area on the front side of the wafer is provided with a front functional structure, the back side of the wafer is provided with a back functional structure, a nonfunctional area of the wafer is provided with an alignment point extending from the front side to the back side, and the distance between the bottom surface of the alignment point and the initial back side of the wafer is smaller than the thickness of the back side of the wafer;
the positions of the front functional structures and the positions of the opposite sites are mutually aligned, and the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
Optionally, the wafer is provided with a plurality of the alignment sites.
Optionally, at least one layer of the back functional structure is a patterned structure, and the patterned structure and the alignment point are aligned with each other.
The invention also provides a semiconductor device, which comprises a substrate separated from a wafer, a front functional structure and a back functional structure, wherein the front functional structure and the back functional structure are mutually aligned based on alignment points, the alignment points are arranged in non-functional areas of the wafer before the wafer is separated, the alignment points extend from the front to the back, and the distance between the bottom surface of the alignment points and the initial back of the wafer is smaller than the thickness of the back of the wafer
Optionally, a step structure is formed between the edge of the back surface functional structure and the edge of the substrate, the step structure is formed by cutting the wafer based on a back surface dicing channel formed on the back surface of the wafer, and the back surface dicing channel is mutually aligned with the front surface dicing channel of the wafer through the alignment point.
The preparation method of the semiconductor device provided by the invention comprises the following steps: obtaining a wafer with a front surface for forming a functional area and a nonfunctional area, wherein the functional area is used for setting a functional structure of a chip; etching opposite sites with preset depth in the nonfunctional area; the distance between the bottom surface of the opposite site and the back surface of the wafer is smaller than the thickness of the back surface of the wafer; the position of the front functional structure can be mutually aligned with the position of the alignment point; thinning the wafer from the back surface of the wafer after setting the opposite sites and the functional structures to expose the opposite sites; setting a back functional structure on the back of the wafer to finish the preparation of the semiconductor device; the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
By arranging the alignment points with preset depth on the front surface of the wafer, the front functional structure of the wafer can be mutually aligned with the alignment points. After the back surface of the wafer is thinned, the alignment points are exposed on the back surface of the wafer, and then the back surface functional structure and the alignment points are required to be aligned with each other when the back surface functional structure is arranged. Because the positions of the alignment points are fixed, the mutual alignment of the front functional structure and the back functional structure can be realized.
The invention also provides a wafer structure and a semiconductor device, which have the same beneficial effects and are not described in detail herein.
Drawings
For a clearer description of embodiments of the invention or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
Fig. 1 to fig. 4 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
Fig. 5 to 12 are process flow diagrams of a specific method for manufacturing a semiconductor device according to an embodiment of the present invention.
In the figure: 1. wafer, 2, front functional structure, 3, opposite site, 4, back functional structure, 5, PI glue, 6, protective layer, 7, adhesive layer and 8, substrate.
Detailed Description
The core of the invention is to provide a method for manufacturing a semiconductor device. In the prior art, the existing exposure machine cannot realize the front and back alignment of the wafer, and has no such process capability.
The preparation method of the semiconductor device provided by the invention comprises the following steps: obtaining a wafer with a front surface for forming a functional area and a nonfunctional area, wherein the functional area is used for setting a functional structure of a chip; etching opposite sites with preset depth in the nonfunctional area; the distance between the bottom surface of the opposite site and the back surface of the wafer is smaller than the thickness of the back surface of the wafer; the position of the front functional structure can be mutually aligned with the position of the alignment point; thinning the wafer from the back surface of the wafer after setting the opposite sites and the functional structures to expose the opposite sites; setting a back functional structure on the back of the wafer to finish the preparation of the semiconductor device; the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
By arranging the alignment points with preset depth on the front surface of the wafer, the front functional structure of the wafer can be mutually aligned with the alignment points. After the back surface of the wafer is thinned, the alignment points are exposed on the back surface of the wafer, and then the back surface functional structure and the alignment points are required to be aligned with each other when the back surface functional structure is arranged. Because the positions of the alignment points are fixed, the mutual alignment of the front functional structure and the back functional structure can be realized.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 4, fig. 1 to 4 are process flow diagrams of a method for manufacturing a semiconductor device according to an embodiment of the invention.
Referring to fig. 1, in an embodiment of the present invention, a method for manufacturing a semiconductor device includes:
S101: a wafer is obtained with a front surface for forming functional and nonfunctional areas for providing functional structures of the chip.
The functional area is an area for forming various functional structures required by semiconductor devices such as chips or separation devices, namely an area for performing subsequent patterning; the nonfunctional area is an area that does not affect the function of the semiconductor device, such as a scribe line, PCM (process control monitor ) area, or the like, i.e., an area that does not require subsequent patterning.
S102: and etching the opposite sites with preset depth in the nonfunctional area.
Referring to fig. 2, in the embodiment of the present invention, the distance between the bottom surface of the pair of positioning points 3 and the back surface of the wafer 1 is smaller than the reduced thickness of the back surface of the wafer 1; the position of the front functional structure 2 can be mutually aligned with the position of the alignment point 3.
The present embodiment specifically refers to a step performed after the front side of the wafer 1 has been prepared to complete a FAB (semiconductor manufacturing) process, where the functional structure disposed on the front side of the wafer 1 in this embodiment is the front side functional structure 2, and the specific content of the front side functional structure 2 may be set by itself according to practical situations, which is not specifically limited herein, and may specifically be a related structure of a function required by a chip, a HEMT (high electron mobility transistor) structure, a related structure required for separating devices, and the like.
In this step, the alignment point 3 with a predetermined depth is etched on the front surface of the wafer 1, firstly, the alignment point 3 is exposed on the front surface of the wafer 1, and secondly, the alignment point 3 needs to have a certain depth, so that the distance between the bottom surface of the alignment point 3 and the back surface of the wafer 1 which is not thinned at this time is smaller than the thickness of the back surface of the wafer 1, that is, the alignment point 3 needs to be exposed after the back surface of the wafer 1 is thinned.
After the alignment points 3 are set, the positions of the entire front functional structure 2 and the alignment points 3 have a fixed corresponding relationship, and at this time, the positions of the front functional structure 2 and the alignment points 3 are aligned with each other. The specific etching process will be described in detail in the following embodiments of the present invention, and will not be described in detail herein.
S103: after the alignment sites and functional structures are provided, the wafer is thinned from the back side of the wafer, exposing the alignment sites.
Referring to fig. 3, the back surface of the wafer 1 is thinned in this step. Since the distance between the bottom surface of the alignment site 3 and the back surface of the wafer 1 before thinning in the above step is smaller than the thinned thickness of the back surface of the wafer 1, the alignment site 3 can be exposed at the back surface of the wafer 1 after this step.
The front side of the wafer 1 is typically encapsulated prior to this step to protect the front side functional structure 2. After packaging, the wafer 1 is also typically fixed. The details of the present invention will be described in the following embodiments of the present invention, and will not be described herein.
S104: and arranging a back functional structure on the back of the wafer to finish the preparation of the semiconductor device.
Referring to fig. 4, in the embodiment of the present invention, the position of the back surface functional structure 4 and the position of the alignment point 3 are aligned with each other. The back surface functional structure 4 is disposed on the back surface of the wafer 1 and has a certain function, and the back surface functional structure 4 is disposed on the basis of the exposed alignment points 3 in this step, so that the positions of the back surface functional structure 4 are aligned with the positions of the alignment points 3. Meanwhile, because the position of the alignment point 3 is fixed, in this embodiment, the back functional structure 4 and the front functional structure 2 are aligned with each other, so that the alignment of the front and back functional structures of the wafer 1 is realized. Similar to the front functional structure 2, the functional structure disposed on the back side of the wafer 1 in this embodiment, that is, the back functional structure 4, the specific content of the back functional structure 4 may be set according to the actual situation, and is not limited herein, the back functional structure 4 may be a structure formed by performing electroplating and/or etching processes after photolithography to form a certain pattern, and the above process may refer to the position of the alignment point 3, so as to implement alignment of the front and back functional structures of the wafer 1.
It should be emphasized that the layout of the back side photolithography used for preparing the back side functional structure 4 is a layout corresponding to the back side after the chip is turned 180 ° in the normal state. Namely, the design of the back photoetching plate needs to be turned by 180 degrees, so that the front and back of the wafer can be aligned.
According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the alignment point 3 with the preset depth is arranged on the front surface of the wafer 1, and at this time, the front functional structure 2 of the wafer 1 can be aligned with the alignment point 3. After the back surface of the wafer 1 is thinned, the alignment points 3 are exposed on the back surface of the wafer 1, and then the back surface functional structure 4 and the alignment points 3 need to be aligned when the back surface functional structure 4 is disposed. Since the position of the alignment site 3 is fixed, the mutual alignment of the front functional structure 2 and the back functional structure 4 can be achieved.
The specific details of the method for manufacturing a semiconductor device according to the present invention will be described in the following embodiments of the present invention.
Referring to fig. 5 to 12, fig. 5 to 12 are process flow diagrams of a specific method for manufacturing a semiconductor device according to an embodiment of the present invention.
Referring to fig. 5, in an embodiment of the present invention, a method for manufacturing a semiconductor device includes:
S201: and arranging a front functional structure on the front surface of the wafer.
Referring to fig. 6, in this step, the front functional structure 2 is first disposed on the front surface of the wafer 1, and details about the front functional structure 2 are described in detail in the above embodiment of the present invention, and the specific disposition process of the front functional structure 2 needs to be determined according to the structure thereof, so the present invention is not limited thereto specifically.
S202: and setting photoresist on the front surface of the wafer, and exposing the photoresist to expose the preset opposite site position.
The position of the alignment point 3 is a predetermined position of the alignment point 3 on the front surface of the wafer 1, for example, the front functional structure 2 generally includes functional modules corresponding to each chip, a scribe line is generally disposed between the functional modules, and the alignment point 3 is generally disposed in the scribe line, so as to avoid damage to the front functional structure 2 caused by the alignment point 3. The specific model of the photoresist and the specific morphology of the photoresist layer formed in this step can be set according to the actual situation, and are not particularly limited herein.
S203: and etching opposite sites with preset depth at the opposite sites on the front surface of the wafer through a plasma etching process.
In this step, the above-mentioned alignment point 3 is etched at the preset alignment point 3 position on the front surface of the wafer 1 based on the dry etching process, specifically, through the plasma etching process. Compared with wet etching, the anisotropy of dry etching is stronger, so that the opposite point 3 meeting the depth requirement can be etched in a small area, and the front functional structure 2 arranged on the front surface of the wafer 1 is not damaged in a large area.
Referring to fig. 7, in particular, in this embodiment, a plurality of pairs of sites 3 are disposed in a wafer 1, so this step may specifically include: a plurality of alignment points 3 with preset depth are etched on the front surface of the wafer 1, where the front surface functional structure 2 is arranged. At this time, a line may be formed between the pairs of sites 3. Compared with the structure that only one alignment point 3 is arranged, the connecting lines formed by the alignment points 3 can more accurately reflect the information such as the position, the azimuth and the like of the front functional structure 2, so that the back functional structure 4 and the front functional structure 2 are more accurately aligned.
It is apparent that in this embodiment, the further the distance between the two pairs of points 3 of the connection is, the longer the distance between the two pairs of points 3 of the connection is, the more accurate the position information reflected by the connection is, and the higher the accuracy is. Therefore, in this embodiment, it is generally necessary to ensure that the distance between the plurality of alignment points 3 is not smaller than the radius of the wafer 1, so as to ensure alignment accuracy. Of course, only one alignment point 3 or more than one alignment points 3 may be provided in the present embodiment. The more the number of the alignment sites 3 is set, the higher the alignment precision is, but the more the area of the wafer 1 is occupied, and meanwhile, the preparation cost is increased.
In this embodiment, the shape of the pair of positioning points 3 is not particularly limited, and the pair of positioning points 3 may be circular, rectangular, cross-shaped or any polygon, which is not particularly limited herein.
It should be noted that, the setting manner of the alignment point 3 provided in the present embodiment may be combined with other setting manners of the alignment point 3, that is, the alignment point 3 provided in the present embodiment and the alignment point 3 formed in other manners, including the alignment point 3 that is not finally exposed on the back of the wafer, may be mixed for use, and the present embodiment does not limit that only the alignment point 3 provided in the present embodiment can be used in the wafer 1, and its specific content may be set by itself according to the actual situation, and is not specifically limited herein.
S204: and filling PI glue on the front surface of the wafer.
S205: gold is leached on the front side of the wafer based on the ENIG process.
Referring to fig. 8 and 9, S203 to S204 are part of a wafer level advanced packaging process, wherein PI (polyimide) glue 5 is made of polyimide resin and filler, and in this step, non-metal structures in the front side functional structure 2 are covered by PI glue 5, and then metal nickel and metal mixture is electroplated on the front side of the wafer 1 to the metal structures by ENIG (electroless nickel gold) process to form the protection layer 6. For details of the PI glue 5 and ENIG process, reference may be made to the prior art, and details thereof will not be described herein.
S206: and bonding the substrate on the front surface of the wafer.
Referring to fig. 10, in this step, a substrate 8 is bonded to the front surface of the packaged wafer 1, and the substrate 8 may be used to provide a certain support for the wafer 1 when the back surface of the wafer 1 is thinned later. The specific material, specific thickness, etc. of the substrate 8 can be set according to the actual situation, and are not particularly limited. The bonding process may be performed by direct bonding or bonding by an adhesive layer 7 such as solder, and is not particularly limited herein.
S207: after the alignment sites and functional structures are provided, the wafer is thinned from the back side of the wafer, exposing the alignment sites.
S208: and setting a back functional structure on the back of the wafer based on the exposed alignment points, so as to complete the preparation of the semiconductor device.
Referring to fig. 11 and 12, the above-mentioned S207 to S208 are substantially identical to the above-mentioned S102 to S103 in the above-mentioned embodiment of the invention, and the detailed description will be omitted herein.
Specifically, the step of setting the other surface function structure in this step may include: a back gold array is arranged on the back surface of the wafer 1; the back gold array comprises a plurality of back gold modules, and the back gold array and the alignment points 3 are mutually aligned so that the back gold modules and the functional areas are mutually aligned.
The back gold modules are equivalent to small back gold blocks formed by patterning the whole back gold, and the back gold modules are distributed in an array to form a back gold array. At this time, back dicing channels corresponding to the nonfunctional areas may be formed between the adjacent back gold modules, and the back gold modules need to be aligned with the functional areas disposed on the front surface of the wafer 1. In this embodiment, the back gold modules specifically need to be aligned with the functional areas disposed on the front side of the wafer 1 through the alignment points 3 exposed on the back side of the wafer 1, and the corresponding back dicing streets between the back gold modules and the non-functional areas are also aligned with each other.
Specifically, the disposing a back gold array on the back surface of the wafer 1 may specifically include: setting a seed layer on the back surface of the wafer 1; setting an isolation layer corresponding to the back cutting channel on the surface of the seed layer based on the position of the positioning point 3; plating a back gold module on the area, which is not shielded by the isolating layer, of the surface of the seed layer to form a back gold array; and removing the isolation layer after the back gold array is formed, and exposing the back cutting channel.
In order to form the back gold array with the above structure, a seed layer with a relatively thin thickness may be first generated, and then an isolation layer is disposed on the surface of the seed layer, where the isolation layer is a patterned isolation layer, and the isolation layer is disposed corresponding to the scribe line. And then, plating a back gold module on the area, which is not shielded by the isolation layer, of the surface of the seed layer to form a back gold array. And the positions corresponding to the cutting channels are provided with isolating layers in advance, so that the isolating layers are not provided with back gold, and the back cutting channels are finally reserved. Finally, the isolation layer is required to be removed to expose the back dicing channels, so that the back gold patterning is realized. The thickness of the seed layer is generally thin, and does not affect dicing of the wafer 1.
Of course, other structures of the back surface functional structure 4 may be provided in the present embodiment, and the specific content thereof is not specifically limited herein as the case may be.
According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the alignment point 3 with the preset depth is arranged on the front surface of the wafer 1, and at this time, the front functional structure 2 of the wafer 1 can be aligned with the alignment point 3. After the back surface of the wafer 1 is thinned, the alignment points 3 are exposed on the back surface of the wafer 1, and then the back surface functional structure 4 and the alignment points 3 need to be aligned when the back surface functional structure 4 is disposed. Since the position of the alignment site 3 is fixed, the mutual alignment of the front functional structure 2 and the back functional structure 4 can be achieved.
The following describes a wafer structure provided by the embodiments of the present invention, and the wafer structure described below and the method for manufacturing a semiconductor device described above may be referred to correspondingly.
In this embodiment, the functional area on the front side of the wafer 1 is provided with a front functional structure 2, the back side of the wafer 1 is provided with a back functional structure 4, the nonfunctional area of the wafer 1 is provided with an alignment point 3 extending from the front side to the back side, the distance between the bottom surface of the alignment point 3 and the initial back side of the wafer is smaller than the thickness of the back side of the wafer 1, and the initial back side of the wafer is the back surface before the back side of the wafer 1 is thinned, that is, the opening of the alignment point 3 on the back side of the wafer 1 can be exposed by thinning the back side of the wafer 1; the position of the front functional structure 2 and the position of the alignment point 3 are aligned with each other, and the position of the back functional structure 4 and the position of the alignment point 3 are aligned with each other.
The wafer structure disclosed in this embodiment is an integral structure of a wafer 1 before dicing and separating, a front functional structure 2 is disposed on the front surface of the wafer 1, a back functional structure 4 is disposed on the back surface of the wafer 1, and a positioning point 3 extending from the front surface to the back surface is disposed at a preset position of the wafer 1, and an opening of the positioning point 3 on the back surface of the wafer 1 is specifically exposed by thinning the back surface of the wafer 1. In this embodiment, the front functional structure 2 and the back functional structure 4 are aligned specifically through the alignment point 3, and details of the front functional structure 2, the back functional structure 4, and the alignment point 3 may refer to the above embodiment of the present invention, and will not be described herein.
Specifically, in this embodiment, at least one layer of the back functional structure 4 is a patterned structure, and the patterned structure and the alignment points 3 are aligned with each other, so that the patterned structure on the back and the patterned structure on the front can be aligned with each other.
Specifically, in this embodiment, the wafer 1 may be provided with a plurality of the alignment points 3, and the distance between the corresponding plurality of the alignment points 3 may be not smaller than the radius of the wafer 1. The front surface of the wafer 1 may further be provided with an encapsulation layer covering the front surface functional structure 2, and the encapsulation layer may specifically be formed based on the PI glue 5 provided on the front surface of the wafer 1 and the metal protection layer 6 formed by the ENIG process. The specific structure of the encapsulation layer may refer to the prior art, and will not be described herein. Accordingly, after the encapsulation layer is provided, the substrate 8 may be further bonded to the surface of the encapsulation layer.
The wafer structure of the present embodiment is prepared based on the preparation method of the semiconductor device, so the specific implementation manner of the wafer structure can be seen from the foregoing example portions of the preparation method of the semiconductor device, so the specific implementation manner of the wafer structure can refer to the corresponding descriptions of the examples of the various portions, which are not repeated herein.
The following describes a semiconductor device provided in an embodiment of the present invention, and the semiconductor device described below and the method for manufacturing the semiconductor device described above may be referred to correspondingly.
In this embodiment, the semiconductor device includes a substrate, a front functional structure 2 and a back functional structure 4 separated from a wafer, the front functional structure 2 and the back functional structure 4 are aligned with each other based on an alignment point 3, the alignment point 3 is disposed in a nonfunctional area of the wafer 2 before the wafer 2 is separated, the alignment point 3 extends from the front surface to the back surface, and a distance between a bottom surface of the alignment point 3 and an initial back surface of the wafer is smaller than a reduced thickness of the back surface of the wafer 2.
The opening of the alignment point 3 at the back of the wafer 1 is exposed by thinning the back of the wafer 1. The semiconductor device disclosed in this embodiment is a device structure formed by dicing a separated wafer 1, at this time, the front surface of the substrate is provided with a front functional structure 2, the back surface of the substrate is provided with a back functional structure 4, and the front functional structure 2 and the back functional structure 4 are aligned with each other through an alignment point 3. The pair of sites 3 is not directly embodied in the semiconductor device at this time, but is provided in a nonfunctional area before dicing the wafer. For details of the front functional structure 2, the back functional structure 4, and the alignment point 3, reference should be made to the above embodiment of the present invention, and no further description is given here.
Specifically, in this embodiment, a step structure is formed between the edge of the back side functional structure 4 and the edge of the substrate, where the step structure is formed by cutting the wafer 1 based on a back side dicing lane formed on the back side of the wafer 1, and the back side dicing lane is aligned with the front side dicing lane of the wafer 1 through the alignment point 3.
Since the back side functional structure 4 is a patterned structure in this embodiment, the corresponding embodiment can specifically cut along the back side dicing streets formed by patterning the back side functional structure when dividing the wafer 1. It is apparent that the width of the dicing street is generally required to be larger than the width of the dicing tool, so that after dicing, a step structure is formed between the edge of the back side functional structure 4 and the edge of the substrate, which is a step structure formed by patterning the back side functional structure 4 while forming a back side dicing street and dicing the wafer 1 along the back side dicing street. The backside scribe line features are aligned with the scribe line of the wafer 1, i.e., with the nonfunctional area on the front side of the wafer 1, through the alignment points 3.
Similarly, in this embodiment, the edge of the front functional structure 2 and the edge of the substrate are also generally formed with a step structure, which is formed by cutting the wafer 1 based on the front dicing lane formed on the front side of the wafer 1.
The semiconductor device of this embodiment is manufactured based on the manufacturing method of the semiconductor device, so the detailed description of the semiconductor device can be found in the foregoing example portions of the manufacturing method of the semiconductor device, so the detailed description of the semiconductor device can be referred to the corresponding description of the examples of each portion, which is not repeated herein.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is provided for the preparation method of a semiconductor device, the wafer structure and the semiconductor device. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (15)
1. A method of manufacturing a semiconductor device, comprising:
Obtaining a wafer with a front surface for forming a functional area and a nonfunctional area, wherein the functional area is used for setting a functional structure of a chip;
Etching opposite sites with preset depth in the nonfunctional area; the distance between the bottom surface of the opposite point and the back surface of the wafer is smaller than the thickness of the back surface of the wafer; the position of the front functional structure can be mutually aligned with the position of the alignment point;
After the alignment points and the functional structures are arranged, thinning the wafer from the back surface of the wafer to expose the alignment points;
A back functional structure is arranged on the back of the wafer, so that the preparation of the semiconductor device is completed; the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
2. The method of claim 1, wherein etching alignment points of a predetermined depth in the nonfunctional area comprises:
Setting photoresist on the front surface of the wafer and exposing the photoresist to expose preset position points;
and etching opposite sites with preset depth at the opposite sites on the front surface of the wafer through a plasma etching process.
3. The method of claim 2, wherein disposing a photoresist on the front side of the wafer and exposing the photoresist to light, and before exposing the predetermined position location, further comprises:
and arranging a front functional structure on the front surface of the wafer.
4. The method of claim 1, further comprising, prior to thinning the wafer from its back side to expose the alignment points:
and packaging the front surface of the wafer.
5. The method of claim 4, wherein encapsulating the front side of the wafer comprises:
Filling PI glue on the front surface of the wafer;
gold is leached on the front side of the wafer based on the ENIG process.
6. The method of claim 4, further comprising, after encapsulating the front side of the wafer:
And bonding a substrate on the front surface of the wafer.
7. The method of claim 1, wherein etching alignment points of a predetermined depth in a front side of the wafer provided with the front side functional structure comprises:
and etching a plurality of opposite sites with preset depth on the front surface of the wafer provided with the front functional structure.
8. The method of claim 7, wherein a distance between a plurality of the pairs of sites is not less than a radius of the wafer.
9. The method of claim 1, wherein disposing a backside functional structure on the backside of the wafer comprises:
A back gold array is arranged on the back surface of the wafer; the back gold array comprises a plurality of back gold modules, and the back gold array and the alignment points are mutually aligned so that the back gold modules and the functional areas are mutually aligned.
10. The method of claim 9, wherein disposing a back gold array on the back side of the wafer comprises:
setting a seed layer on the back surface of the wafer;
setting an isolation layer corresponding to the back cutting channel on the surface of the seed layer based on the position of the positioning point;
plating a back gold module on the area, which is not shielded by the isolating layer, of the surface of the seed layer to form a back gold array;
and removing the isolation layer after the back gold array is formed, and exposing the back cutting channel.
11. The wafer structure is characterized in that a functional area on the front side of the wafer is provided with a front side functional structure, the back side of the wafer is provided with a back side functional structure, a nonfunctional area of the wafer is provided with an alignment point extending from the front side to the back side, and the distance between the bottom surface of the alignment point and the initial back side of the wafer is smaller than the thickness of the back side of the wafer;
the positions of the front functional structures and the positions of the opposite sites are mutually aligned, and the positions of the back functional structures and the positions of the opposite sites are mutually aligned.
12. The wafer structure of claim 11, wherein the wafer is provided with a plurality of the pair of sites.
13. The wafer structure of claim 11, wherein at least one layer of the backside functional structure is a patterned structure, the patterned structure being aligned with the alignment point.
14. The semiconductor device is characterized by comprising a substrate, a front functional structure and a back functional structure which are separated from a wafer, wherein the front functional structure and the back functional structure are mutually aligned based on alignment points, the alignment points are arranged in nonfunctional areas of the wafer before the wafer is separated, the alignment points extend from the front surface to the back surface, and the distance between the bottom surface of the alignment points and the initial back surface of the wafer is smaller than the thickness of the back surface of the wafer.
15. The semiconductor device of claim 14, wherein an edge of the back side functional structure and an edge of the substrate are formed with a step structure formed by dicing the wafer based on a back side dicing lane formed on a back side of the wafer, the back side dicing lane being aligned with a front side dicing lane of the wafer by the alignment point.
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| CN202410316160.0A CN118213311A (en) | 2024-03-19 | 2024-03-19 | A method for preparing a semiconductor device, a wafer structure and a semiconductor device |
| PCT/CN2024/126047 WO2025194764A1 (en) | 2024-03-19 | 2024-10-21 | Preparation method for semiconductor device, and wafer structure and semiconductor device |
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| CN202410316160.0A CN118213311A (en) | 2024-03-19 | 2024-03-19 | A method for preparing a semiconductor device, a wafer structure and a semiconductor device |
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| WO2025194764A1 (en) * | 2024-03-19 | 2025-09-25 | 达迩科技（成都）有限公司 | Preparation method for semiconductor device, and wafer structure and semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7588993B2 (en) * | 2007-12-06 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment for backside illumination sensor |
| CN103050480B (en) * | 2012-08-14 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The back-patterned process of silicon chip |
| US9105644B2 (en) * | 2013-07-23 | 2015-08-11 | Analog Devices, Inc. | Apparatus and method for forming alignment features for back side processing of a wafer |
| CN112530908B (en) * | 2019-09-18 | 2023-12-26 | 芯恩（青岛）集成电路有限公司 | Preparation method of semiconductor device and semiconductor device |
| CN118213311A (en) * | 2024-03-19 | 2024-06-18 | 达迩科技（成都）有限公司 | A method for preparing a semiconductor device, a wafer structure and a semiconductor device |
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| WO2025194764A1 (en) * | 2024-03-19 | 2025-09-25 | 达迩科技（成都）有限公司 | Preparation method for semiconductor device, and wafer structure and semiconductor device |
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