CN118232907B - Circuit for improving LVDS working frequency - Google Patents
Circuit for improving LVDS working frequency Download PDFInfo
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- CN118232907B CN118232907B CN202410650600.6A CN202410650600A CN118232907B CN 118232907 B CN118232907 B CN 118232907B CN 202410650600 A CN202410650600 A CN 202410650600A CN 118232907 B CN118232907 B CN 118232907B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 11
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- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 claims description 6
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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Abstract
The invention discloses a circuit for improving LVDS working frequency, which comprises a signal source and inverters E1 and E2, wherein the signal source is connected with a control circuit through a Vin input end, the control circuit is respectively connected with four groups of grid driving circuits in different modes, the four groups of grid driving circuits are respectively connected with switching tubes A1, A2, B1 and B2, the switching tubes A1, A2, B1 and B2 are respectively connected with four groups of substrate driving circuits, the corresponding switching tubes A1, A2, B1 and B2 are enabled to reach the conducting condition rapidly through the organic combination of the four groups of grid driving circuits and the four groups of substrate driving circuits, the influence of Miller effect is reduced, and therefore the working frequency of the LVDS circuit is improved through improving the conducting speed of an MOS tube, and the effect of improving the transmission rate is achieved.
Description
Technical Field
The invention relates to the technical field of LVDS circuits, in particular to a circuit for improving the working frequency of LVDS.
Background
LVDS (Low-Voltage DIFFERENTIAL SIGNALING) Low-Voltage differential signal is a differential signal technology with Low power consumption, low bit error rate, low crosstalk and Low radiation, the transmission technology can reach more than 155Mbps, the core of the LVDS technology is to adopt extremely Low Voltage swing high-speed differential transmission data, point-to-point or point-to-multipoint connection can be realized, and the transmission medium can be copper PCB connection or balanced cable. Because the LVDS adopts a differential signal transmission mode, common mode noise and other types of interference can be effectively restrained. This helps to improve the signal to noise ratio of the signal and reduce the bit error rate.
Fig. 1 is a block diagram of a related art LVDS circuit. LVDS is an interface technology widely applied to high-speed data transmission, and the improvement of the working frequency of the LVDS is significant for improving the data transmission rate. However, when the traditional LVDS circuit works, due to the influence of the Miller effect, the on-off times of the MOS tube in unit time are less, the working frequency of the LVDS circuit is greatly influenced, and the data transmission rate cannot be further improved.
Disclosure of Invention
The invention aims to provide a circuit for improving LVDS working frequency, which can increase the on-off times of an MOS tube in unit time, thereby improving the LVDS working frequency and further improving the data transmission rate.
In order to achieve the above purpose, the present invention provides the following technical solutions: the utility model provides a circuit for improving LVDS operating frequency, includes signal source and inverter E1, E2, and signal source passes through Vin input connection control circuit, and control circuit is connected with four groups of gate drive circuit through different modes respectively, four groups of gate drive circuit connect switch tube A1, A2, B1 and B2 respectively, and four groups of substrate drive circuit are connected respectively to switch tube A1, A2, B1 and B2, and control circuit's output and two of them two sets of direct connection of four groups of gate drive circuit pass through inverter E1, E2 indirect connection with other two sets.
Preferably, the switching transistors A1 and A2 are respectively a first PMOS transistor and a second PMOS transistor, the switching transistors B1 and B2 are respectively a first NMOS transistor and a second NMOS transistor, the drain interconnections of the switching transistors A1 and B1 are used as the in-phase output terminal Voutp, and the drain interconnections of the switching transistors A2 and B2 are used as the anti-phase output terminal Voutn.
Preferably, sources of the switching tubes A1 and A2 are connected with a signal source VDD, sources of the switching tubes B1 and B2 are grounded, the four groups of gate driving circuits are respectively a first gate driving circuit, a second gate driving circuit, a third gate driving circuit and a fourth gate driving circuit, and the first gate driving circuit, the second gate driving circuit, the third gate driving circuit and the fourth gate driving circuit are circuit modules formed by the same components.
Preferably, the first input end of the first gate driving circuit is connected to the signal source VDD1, the signal source VDD1 is connected to the input end of the first voltage regulator LDO1 and grounded, and the output end of the first voltage regulator LDO1 is connected to the left end of the first switch S1.
Preferably, the first gate driving circuit further includes a second switch S2 and a third switch S3, the right ends of the first switch S1, the second switch S2 and the third switch S3 are connected in parallel together to serve as an output end of the first gate driving circuit, the left end of the second switch S2 serves as a second input end of the first gate driving circuit, and the left end of the third switch S3 is grounded.
Preferably, the second input end of the first gate driving circuit is directly connected with the control circuit, the output end of the first gate driving circuit is connected with the gate of the first PMOS tube, the second input end of the second gate driving circuit is directly connected with the control circuit, and the output end of the second gate driving circuit is connected with the gate of the first NMOS tube.
Preferably, the second input end of the third gate driving circuit is connected with the control circuit through an inverter E1, the output end of the third gate driving circuit is connected with the gate of the second PMOS tube, the second input end of the fourth gate driving circuit is connected with the control circuit through an inverter E2, and the output end of the fourth gate driving circuit is connected with the gate of the second NMOS tube.
Preferably, the four groups of substrate driving circuits are respectively a first substrate driving circuit, a second substrate driving circuit, a third substrate driving circuit and a fourth substrate driving circuit, the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit are circuit modules formed by the same components, and substrates of the switching tubes A1, B1, A2 and B2 are respectively connected with output ends of the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit.
Preferably, the input end of the first substrate driving circuit is connected with a signal source VDD3, the signal source VDD3 is connected with the input end of the second voltage regulator LDO2 and grounded, and the output end of the second voltage regulator LDO2 is connected with the right end of the fourth switch S4.
Preferably, the first substrate driving circuit further includes a fifth switch S5, the left ends of the fourth switch S4 and the fifth switch S5 are connected in parallel as an output end of the first substrate driving circuit, and the right end of the fifth switch S5 is grounded.
Compared with the prior art, the invention has the following beneficial effects: the first, second, third and fourth gate driving circuits and the organic combination of the first, second, third and fourth substrate driving circuits enable the corresponding switching transistors A1, B1, A2 and B2 to quickly reach the conducting condition, thereby reducing the influence of the Miller effect. The invention increases the on-off times of the MOS tube in unit time on the premise of not changing the basic structure of the LVDS circuit, thereby realizing the improvement of the LVDS working frequency, further improving the data transmission rate and effectively solving the defects in the prior art.
Drawings
FIG. 1 is a schematic diagram of a conventional LDVS circuit;
FIG. 2 is a circuit block diagram of the present invention;
FIG. 3 is a schematic diagram of a first gate driving circuit according to the present invention;
FIG. 4 is a schematic diagram of a first substrate driving circuit according to the present invention;
FIG. 5 is a circuit diagram showing the connection between the gate of the switch B1 circuit and the substrate according to the present invention;
FIG. 6 is a diagram showing the waveform of the switch B1 in the conventional LDVS circuit;
fig. 7 is a waveform diagram of the operation of the switching tube B1 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2, a circuit for improving LVDS operating frequency includes a signal source and inverters E1 and E2, the signal source is connected to a control circuit through an input end of Vin, the control circuit is respectively connected to four groups of gate driving circuits in different manners, the four groups of gate driving circuits are respectively connected to switching tubes A1, A2, B1 and B2, the switching tubes A1, A2, B1 and B2 are respectively connected to four groups of substrate driving circuits, an output end of the control circuit is directly connected to two groups of the four groups of gate driving circuits, and is indirectly connected to the other two groups of the control circuit through inverters E1 and E2, the switching tubes A1 and A2 are respectively a first PMOS tube and a second PMOS tube, the switching tubes B1 and B2 are respectively a first NMOS tube and a second NMOS tube, drain interconnections of the switching tubes A1 and B1 are used as in-phase output ends Voutp, and drain interconnections of the switching tubes A2 and B2 are used as anti-phase output ends Voutn. The sources of the switch tubes A1 and A2 are connected with a signal source VDD, the sources of the switch tubes B1 and B2 are grounded, the four groups of grid driving circuits are respectively a first grid driving circuit, a second grid driving circuit, a third grid driving circuit and a fourth grid driving circuit, and the first grid driving circuit, the second grid driving circuit, the third grid driving circuit and the fourth grid driving circuit are circuit modules formed by the same components.
In the above, the control circuit is indirectly connected to the other two groups of four groups of gate driving circuits through the inverters E1 and E2, that is, the output ends of the control circuit are connected to the input ends of the inverters E1 and E2 respectively, and then the output ends of the inverters E1 and E2 are connected to the input ends of the other two groups of four groups of gate driving circuits respectively, referring to fig. 6, in the prior art, due to the structure and manufacturing process of the MOS transistor, the miller capacitance Cgd is inevitably generated between the gate and the drain of the MOS transistor, and the miller capacitance Cgd exists, after the time t0, that is, when Vgs > Vth0, id gradually increases, but as Vgs increases, vds does not decrease immediately, after t1, vgs does not continue to increase until Vds decreases to the minimum value, so that the turn-on time of the MOS transistor is prolonged, and the switching speed of the MOS transistor is reduced, so that the operating frequency of the LVDS circuit cannot be further improved, and the data transmission rate is required to be reduced by the design to reduce the corresponding switching speed of the MOS transistor.
Referring to fig. 5, the second input end of the first gate driving circuit is directly connected to the control circuit, the output end is connected to the gate of the first PMOS transistor, the second input end of the second gate driving circuit is directly connected to the control circuit, and the output end is connected to the gate of the first NMOS transistor. The second input end of the third grid driving circuit is connected with the control circuit through an inverter E1, the output end of the third grid driving circuit is connected with the grid electrode of the second PMOS tube, the second input end of the fourth grid driving circuit is connected with the control circuit through an inverter E2, and the output end of the fourth grid driving circuit is connected with the grid electrode of the second NMOS tube. The four groups of substrate driving circuits are respectively a first substrate driving circuit, a second substrate driving circuit, a third substrate driving circuit and a fourth substrate driving circuit, the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit are circuit modules formed by the same components, and substrates of the switching tubes A1, B1, A2 and B2 are respectively connected with output ends of the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit.
Referring to fig. 3, a first input terminal of the first gate driving circuit is connected to a signal source VDD1, the signal source VDD1 is connected to an input terminal of the first voltage regulator LDO1 and grounded, and an output terminal of the first voltage regulator LDO1 is connected to a left terminal of the first switch S1. The first gate driving circuit further comprises a second switch S2 and a third switch S3, the right ends of the first switch S1, the second switch S2 and the third switch S3 are connected in parallel to be used as an output end of the first gate driving circuit, the left end of the second switch S2 is used as a second input end of the first gate driving circuit, and the left end of the third switch S3 is grounded.
In the above, the first voltage regulator LDO1 is one of the existing LDO technologies, and the first, second, third and fourth gate driving circuits are circuits composed of LDO1, S2 and S3, and because Vgs is larger, the MOS transistor is faster to turn on, the operating states of S1, S2 and S3 can be controlled by the control signal, so that the gate driving voltage is as large as possible to increase Vgs, and the effect of fast turn-on and turn-off of the MOS transistor is achieved.
Referring to fig. 4, the input end of the first substrate driving circuit is connected to the signal source VDD3, the signal source VDD3 is connected to the input end of the second voltage regulator LDO2 and grounded, and the output end of the second voltage regulator LDO2 is connected to the right end of the fourth switch S4. The first substrate driving circuit further comprises a fifth switch S5, the left ends of the fourth switch S4 and the fifth switch S5 are connected in parallel to be used as an output end of the first substrate driving circuit, and the right end of the fifth switch S5 is grounded.
In the foregoing, the second voltage stabilizer LDO2 is also one of the existing LDO technologies, and the first, second, third and fourth substrate driving circuits are circuits formed by LDO2, S4 and S5, and according to the substrate bias effect, the greater the substrate voltage Vb, the greater the threshold voltage Vth of the MOS transistor, the higher the gate driving voltage required for the MOS transistor to be turned on, so the operating states of S4 and S5 can be controlled by the control signal to control the threshold voltage Vth of the MOS transistor, thereby providing a bias voltage for the on-off of the MOS transistor.
To sum up: referring to fig. 7, by the organic combination of the second gate driving circuit and the second substrate driving circuit, before the first NMOS transistor gate is powered on, the control S4 is closed, so that the substrate voltage Vb is raised to a high level, so that the threshold voltage of the first NMOS transistor is raised from the original Vth0 to Vth1, that is, vth1> Vth0, so that the closing of S1 and S2 can be controlled to increase the driving voltage of the first NMOS transistor gate, vgs is quickly raised from a lower level to a "miller plateau", vth1> Vgs is always present in the process of increasing Vgs, the first NMOS transistor is still not conducted, at this time (at time t1 in fig. 7), the control S5 is closed, S4 is opened, the substrate voltage Vb is lowered from a high level to a low level, so that the threshold voltage Vth1 of the first NMOS transistor is obviously lowered, at this time > Vth1, the condition that the first NMOS transistor is conducted is reached, the drain current Id is quickly raised, vds also quickly falls, so that the influence of the miller effect is reduced, the first NMOS transistor is quickly conducted, and the second NMOS transistor is correspondingly conducted by the first NMOS transistor, the fourth NMOS driving circuit and the fourth NMOS driving circuit, the second NMOS transistor is correspondingly conducted by the first NMOS transistor, and the second NMOS driving circuit, and the second NMOS transistor are quickly driven by the second NMOS circuit, and the first NMOS circuit, and the second NMOS transistor, and the first NMOS circuit, and the second driving circuit are quickly and the second driving circuit, and the fast.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The utility model provides a improve LVDS operating frequency's circuit, includes signal source and inverter E1, E2, and signal source passes through Vin input connection control circuit, and control circuit is connected with four groups grid drive circuit through different modes respectively, its characterized in that: the four groups of grid driving circuits are connected with the switching tubes A1, A2, B1 and B2 in one-to-one correspondence, the switching tubes A1, A2, B1 and B2 are connected with the four groups of substrate driving circuits in one-to-one correspondence, and the output end of the control circuit is directly connected with two groups of the four groups of grid driving circuits and indirectly connected with the other two groups of grid driving circuits through the inverters E1 and E2;
The first input end of the grid driving circuit is connected with a signal source VDD1, the signal source VDD1 is connected with the input end of a first voltage regulator LDO1 and grounded, and the output end of the first voltage regulator LDO1 is connected with the left end of a first switch S1; the grid driving circuit further comprises a second switch S2 and a third switch S3, the right ends of the first switch S1, the second switch S2 and the third switch S3 are connected in parallel to be used as an output end of the grid driving circuit, the left end of the second switch S2 is used as a second input end of the grid driving circuit, the second input end is directly connected with the control circuit, and the left end of the third switch S3 is grounded;
The input end of the substrate driving circuit is connected with a signal source VDD3, the signal source VDD3 is connected with the input end of a second voltage regulator LDO2 and grounded, and the output end of the second voltage regulator LDO2 is connected with the right end of a fourth switch S4; the substrate driving circuit further comprises a fifth switch S5, the left ends of the fourth switch S4 and the fifth switch S5 are connected in parallel and used as an output end of the first substrate driving circuit, and the right end of the fifth switch S5 is grounded;
Before the grid electrode of the switching tube is electrified, the fourth switch S4 is controlled to be closed, the substrate voltage Vb is raised to a high level, so that the threshold voltage of the switching tube is raised from the original Vth0 to Vth1, namely, vth1> Vth0;
controlling the closing of S1 and S2 to increase the driving voltage of the grid electrode of the switching tube, rapidly increasing Vgs from a lower level to a 'Miller platform period', wherein Vth1> Vgs exists all the time in the increasing process of the Vgs, and the switching tube is still not conducted;
By controlling S5 to be closed and S4 to be opened, the substrate voltage Vb is reduced from a high level to a low level, so that the threshold voltage Vth1 of the switching tube is obviously reduced, vgs > Vth1 at the moment reaches the condition that the switching tube is conducted, the drain current Id is rapidly increased, vds is rapidly reduced, the influence of the Miller effect is reduced, the switching tube is rapidly conducted, the working frequency of the LVDS circuit is improved, and the effect of improving the transmission rate is realized.
2. A circuit for increasing the operating frequency of LVDS as claimed in claim 1, wherein: the switching tubes A1 and A2 are respectively a first PMOS tube and a second PMOS tube, the switching tubes B1 and B2 are respectively a first NMOS tube and a second NMOS tube, drain electrode interconnection of the switching tubes A1 and B1 is used as an in-phase output end Voutp, and drain electrode interconnection of the switching tubes A2 and B2 is used as an anti-phase output end Voutn.
3. A circuit for increasing the operating frequency of LVDS as claimed in claim 2, wherein: the source electrodes of the switch tubes A1 and A2 are connected with a signal source VDD, the source electrodes of the switch tubes B1 and B2 are grounded, the four groups of grid driving circuits are respectively a first grid driving circuit, a second grid driving circuit, a third grid driving circuit and a fourth grid driving circuit, and the first grid driving circuit, the second grid driving circuit, the third grid driving circuit and the fourth grid driving circuit are circuit modules formed by the same components.
4. A circuit for increasing the operating frequency of LVDS as claimed in claim 1, wherein: the second input end of the first grid driving circuit is directly connected with the control circuit, the output end of the first grid driving circuit is connected with the grid electrode of the first PMOS tube, the second input end of the second grid driving circuit is directly connected with the control circuit, and the output end of the second grid driving circuit is connected with the grid electrode of the first NMOS tube.
5. A circuit for increasing the operating frequency of LVDS as claimed in claim 2, wherein: the second input end of the third grid driving circuit is connected with the control circuit through an inverter E1, the output end of the third grid driving circuit is connected with the grid electrode of the second PMOS tube, the second input end of the fourth grid driving circuit is connected with the control circuit through an inverter E2, and the output end of the fourth grid driving circuit is connected with the grid electrode of the second NMOS tube.
6. A circuit for increasing the operating frequency of LVDS as claimed in claim 2, wherein: the four groups of substrate driving circuits are respectively a first substrate driving circuit, a second substrate driving circuit, a third substrate driving circuit and a fourth substrate driving circuit, the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit are circuit modules formed by the same components, and substrates of the switch tubes A1, B1, A2 and B2 are respectively connected with output ends of the first substrate driving circuit, the second substrate driving circuit, the third substrate driving circuit and the fourth substrate driving circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410650600.6A CN118232907B (en) | 2024-05-24 | 2024-05-24 | Circuit for improving LVDS working frequency |
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| CN202410650600.6A CN118232907B (en) | 2024-05-24 | 2024-05-24 | Circuit for improving LVDS working frequency |
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| CN118232907B true CN118232907B (en) | 2024-08-20 |
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| CN119727699A (en) * | 2024-11-25 | 2025-03-28 | 圣邦微电子（北京）股份有限公司 | Low voltage differential signaling devices and their drivers |
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| CN116662236A (en) * | 2022-02-28 | 2023-08-29 | 意法半导体国际有限公司 | Low Voltage Differential Signaling Transmitter Circuit |
| CN117296250A (en) * | 2021-05-14 | 2023-12-26 | 派赛公司 | Bulk resistor bypass for RF FET switch stack |
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| WO2011079879A1 (en) * | 2009-12-30 | 2011-07-07 | Stmicroelectronics S.R.L. | Low voltage isolation switch, in particular for a transmission channel for ultrasound applications |
| JP5581913B2 (en) * | 2010-09-06 | 2014-09-03 | ソニー株式会社 | Driver amplifier circuit and communication system |
| CN204481788U (en) * | 2015-04-07 | 2015-07-15 | 电子科技大学 | A kind of LVDS drive circuit suppressing output common mode to fluctuate |
| CN109683836B (en) * | 2018-12-04 | 2022-04-19 | 珠海妙存科技有限公司 | Driving device compatible with hardware interfaces of various display protocols |
| CN210629440U (en) * | 2019-09-17 | 2020-05-26 | 圣邦微电子（北京）股份有限公司 | Power tube grid driving circuit and integrated circuit |
| CN111371443B (en) * | 2020-05-28 | 2020-08-28 | 上海南麟电子股份有限公司 | Active rectifier bridge circuit and on-chip integrated system |
| CN114268080B (en) * | 2021-12-17 | 2024-03-26 | 中国电子科技集团公司第五十八研究所 | An M-LVDS drive circuit to prevent bus leakage |
| US12047038B2 (en) * | 2022-06-01 | 2024-07-23 | Mediatek Inc. | Reconfigurable crystal oscillator and method for reconfiguring crystal oscillator |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117296250A (en) * | 2021-05-14 | 2023-12-26 | 派赛公司 | Bulk resistor bypass for RF FET switch stack |
| CN116662236A (en) * | 2022-02-28 | 2023-08-29 | 意法半导体国际有限公司 | Low Voltage Differential Signaling Transmitter Circuit |
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