CN118244876A

CN118244876A - Processor power consumption control method, processor and electronic equipment

Info

Publication number: CN118244876A
Application number: CN202410323452.7A
Authority: CN
Inventors: 石英正; 刘恒
Original assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Current assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Priority date: 2024-03-20
Filing date: 2024-03-20
Publication date: 2024-06-25

Abstract

The application provides a power consumption control method of a processor, the processor and electronic equipment, wherein the processor comprises a power consumption detection unit, a processor core unit and a clock reset generation unit, the input end of the power consumption detection unit is connected with the output end of the processor core unit, and the output end of the power consumption detection unit is connected with the input end of the clock reset generation unit; the output end of the clock reset generating unit is connected with the input end of the processor core unit; the power consumption detection unit is used for detecting the corresponding first instruction completion times of the processor core unit in a first preset statistical period, and sending a high-level low-activity signal to the clock reset generation unit when the first instruction completion times are smaller than a first preset times threshold; the clock reset generation unit is used for reducing the clock frequency of the processor core unit according to the high-level low-activity signal. According to the scheme provided by the application, the power consumption of the processor core unit can be reduced more quickly, and the power consumption control effect of the processor is improved.

Description

Processor power consumption control method, processor and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method for controlling power consumption of a processor, and an electronic device.

Background

With the development of technology, the power consumption of today's processors is higher and higher while higher and higher performance is achieved, so how to optimize the power consumption of the processors is an important research direction at present.

The existing power consumption optimization strategies have a plurality of types, such as power consumption reduction through a physical heat dissipation mode, power consumption reduction through a software management mode and the like. The software management mode uses a PMC (Power Management Controller, power consumption management controller) unit built in the computer, which can switch the processor CPU into a low power consumption mode when the device is in an idle state for a period of time (e.g., the mouse is not clicked or moved for a long time, the keyboard is not typed in for a long time). However, this solution has the disadvantage that the PMC needs to wait for a period of time when all relevant devices remain idle, and then enter the low power mode, which results in a short time when the computer is actually in the low power state, and the power control effect is general.

Therefore, the power consumption control effect of the current power consumption optimization strategy needs to be further improved.

Disclosure of Invention

The application provides a power consumption control method of a processor, the processor and electronic equipment, which are used for solving the problem that the power consumption control effect of the current power consumption optimization strategy needs to be further improved.

A first aspect of the present application provides a processor comprising: the device comprises a power consumption detection unit, a processor core unit and a clock reset generation unit;

the input end of the power consumption detection unit is connected with the output end of the processor core unit, and the output end of the power consumption detection unit is connected with the input end of the clock reset generation unit;

The output end of the clock reset generating unit is connected with the input end of the processor core unit;

The power consumption detection unit is used for detecting the corresponding first instruction completion times of the processor core unit in a first preset statistical period, and sending a high-level low-activity signal to the clock reset generation unit when the first instruction completion times are smaller than a first preset times threshold;

the clock reset generation unit is used for reducing the clock frequency of the processor core unit according to the high-level low-activity signal.

A second aspect of the present application provides a method for controlling power consumption of a processor, applied to a processor of the first aspect, the method comprising:

When the task processing signal is at a high level, determining the corresponding first instruction completion times of the processor core unit in a first preset statistical period by adopting a power consumption detection unit; the task processing signal is generated by a processor core unit;

Judging whether the first instruction completion times are smaller than a first preset times threshold value or not;

And if the first instruction completion times are smaller than a first preset times threshold, sending a high-level low-activity signal to a clock reset generating unit through a power consumption detecting unit so that the clock reset generating unit reduces the clock frequency of a processor core unit according to the high-level low-activity signal.

Further, as described above, the power consumption detecting unit includes: a first counter and a second counter;

the determining, by using the power consumption detecting unit, a corresponding first instruction completion number of the processor core unit in a first preset statistical period includes:

starting the first counter, and accumulating and counting from zero according to a first preset statistical period;

counting the times of the high level of the instruction execution completion signal by adopting a second counter; the instruction execution completion signal is generated for the processor core unit and sent to the power consumption detection unit;

And when the first counter counts up to a first preset counting period, determining the counted times of the high level of the instruction execution completion signal as the first instruction completion times.

Further, in the method as described above, the power consumption detecting unit further includes: a first comparator;

the judging whether the first instruction completion times are smaller than a first preset times threshold value comprises the following steps:

Reading the first preset times threshold value from a preset register;

and comparing the first instruction completion times with the first preset times threshold by adopting a first comparator so as to judge whether the first instruction completion times are smaller than the first preset times threshold.

Further, in the method as described above, the power consumption detecting unit further includes: a third counter and a second comparator;

the method includes the steps that the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal, and then the method further includes the steps of:

calculating the corresponding second instruction completion times of the processor core unit in a second preset statistical period by adopting a third counter;

comparing the second instruction completion times with a second preset times threshold by adopting a second comparator so as to judge whether the second instruction completion times are smaller than the second preset times threshold;

If the second instruction completion times are smaller than a second preset times threshold, sending a high-level low-activity signal to a clock reset generating unit through a power consumption detecting unit, so that the clock reset generating unit adjusts the clock frequency of a processor core unit according to the high-level low-activity signal;

And if the second instruction completion times are greater than or equal to a second preset times threshold, sending a low-level low-activity signal to a clock reset generating unit through a power consumption detecting unit so that the clock reset generating unit increases the clock frequency of a processor core unit according to the low-level low-activity signal.

Further, in the method as described above, the power consumption detecting unit further includes: a fourth counter;

the calculating, by using a third counter, the number of times of completion of the second instruction corresponding to the processor core unit in the second preset statistical period includes:

adopting the fourth counter to count up from zero according to a second preset statistical period;

counting the times of the high level of the instruction execution completion signal by adopting a third counter;

And when the fourth counter counts up to a second preset counting period, determining the counted times of the high level instruction execution completion signal as second instruction completion times.

Further, the method as described above, the method further comprising:

determining a total duration when the low active signal is high;

Judging whether the total duration is greater than a preset time threshold;

and if the total duration is determined to be greater than the preset time threshold, sending a sleep instruction to the processor core unit.

Further, in the method as described above, after the sending, by the power consumption detecting unit, the high-level low-activity signal to the clock reset generating unit, so that the clock reset generating unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal, the method further includes:

allocating new data processing tasks to the processor core unit or controlling the clock reset generation unit to increase the clock frequency of the processor core unit.

Further, in the method as described above, the processor core unit is a plurality of processor core units, and one of the processor core units is a monitor core unit;

redistributing data processing tasks corresponding to the processor core units according to the interrupt signals of the monitoring core units; and the interrupt signal is generated by the processor core unit and sent to the monitoring core unit when the first instruction completion times are smaller than a first preset times threshold value.

A third aspect of the present application provides a processor power consumption control apparatus, in a processor of the first aspect, the apparatus comprising:

The determining module is used for determining the corresponding first instruction completion times of the processor core unit in a first preset statistical period by adopting the power consumption detecting unit when the task processing signal is at a high level; the task processing signal is generated by a processor core unit;

The judging module is used for judging whether the first instruction completion times are smaller than a first preset times threshold value or not;

And the adjusting module is used for sending a high-level low-activity signal to the clock reset generating unit through the power consumption detecting unit if the first instruction completion times are smaller than a first preset times threshold value, so that the clock reset generating unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

Further, in the apparatus as described above, the power consumption detecting unit includes: a first counter and a second counter;

The determining module is specifically configured to, when determining, by using the power consumption detecting unit, a first instruction completion number corresponding to the processor core unit in a first preset statistical period:

starting the first counter, and accumulating and counting from zero according to a first preset statistical period; counting the times of the high level of the instruction execution completion signal by adopting a second counter; the instruction execution completion signal is generated for the processor core unit and sent to the power consumption detection unit; and when the first counter counts up to a first preset counting period, determining the counted times of the high level of the instruction execution completion signal as the first instruction completion times.

Further, in the apparatus as described above, the power consumption detecting unit further includes: a first comparator;

The judging module is specifically configured to:

Reading the first preset times threshold value from a preset register; and comparing the first instruction completion times with the first preset times threshold by adopting a first comparator so as to judge whether the first instruction completion times are smaller than the first preset times threshold.

Further, in the apparatus as described above, the power consumption detecting unit further includes: a third counter and a second comparator;

The apparatus further comprises:

The control module is used for calculating the corresponding second instruction completion times of the processor core unit in a second preset statistical period by adopting a third counter; comparing the second instruction completion times with a second preset times threshold by adopting a second comparator so as to judge whether the second instruction completion times are smaller than the second preset times threshold; if the second instruction completion times are smaller than a second preset times threshold, sending a high-level low-activity signal to a clock reset generating unit through a power consumption detecting unit, so that the clock reset generating unit adjusts the clock frequency of a processor core unit according to the high-level low-activity signal; and if the second instruction completion times are greater than or equal to a second preset times threshold, sending a low-level low-activity signal to a clock reset generating unit through a power consumption detecting unit so that the clock reset generating unit increases the clock frequency of a processor core unit according to the low-level low-activity signal.

Further, in the apparatus as described above, the power consumption detecting unit further includes: a fourth counter;

The control module is specifically configured to, when calculating the number of times of completion of the second instruction corresponding to the processor core unit in the second preset statistical period by using the third counter:

Adopting the fourth counter to count up from zero according to a second preset statistical period; counting the times of the high level of the instruction execution completion signal by adopting a third counter; and when the fourth counter counts up to a second preset counting period, determining the counted times of the high level instruction execution completion signal as second instruction completion times.

Further, the apparatus as described above, further comprising:

A sleep module for determining a total duration when the low active signal is high; judging whether the total duration is greater than a preset time threshold; and if the total duration is determined to be greater than the preset time threshold, sending a sleep instruction to the processor core unit.

Further, the apparatus as described above, further comprising:

And the first distribution module is used for distributing new data processing tasks to the processor core unit or controlling the clock reset generation unit to adjust the clock frequency of the processor core unit.

Further, in the apparatus as described above, the processor core unit is a plurality of processor core units, and one of the processor core units is a monitor core unit;

The apparatus further comprises:

The second distribution module is used for redistributing the data processing tasks corresponding to the processor core units according to the interrupt signals of the monitoring core units; and the interrupt signal is generated by the processor core unit and sent to the monitoring core unit when the first instruction completion times are smaller than a first preset times threshold value.

A fourth aspect of the present application provides an electronic device, comprising: a processor and a memory; the processor comprises a power consumption detection unit, a processor core unit and a clock reset generation unit;

the processors and the memory circuits are interconnected;

the memory stores computer-executable instructions;

the processor executes computer-executable instructions stored in the memory to implement the method of controlling processor power consumption according to any one of the second aspects.

A fifth aspect of the present application provides a computer-readable storage medium having stored therein computer-executable instructions for implementing the processor power consumption control method of any of the second aspects when executed by a processor.

A sixth aspect of the application provides a computer program product comprising a computer program which, when executed by a processor, implements the method of controlling power consumption of a processor according to any of the second aspects.

The application provides a power consumption control method of a processor, the processor and electronic equipment, wherein the processor comprises the following steps: the power consumption detection unit is connected with the output end of the processor core unit, and the output end of the power consumption detection unit is connected with the input end of the clock reset generation unit; the output end of the clock reset generating unit is connected with the input end of the processor core unit; the power consumption detection unit is used for detecting the corresponding first instruction completion times of the processor core unit in a first preset statistical period, and sending a high-level low-activity signal to the clock reset generation unit when the first instruction completion times are smaller than a first preset times threshold; the clock reset generation unit is used for reducing the clock frequency of the processor core unit according to the high-level low-activity signal. When the processor core unit processes tasks, the power consumption detection unit can be used for detecting the corresponding first instruction completion times of the processor core unit in the first preset statistical period, and whether the current tasks of the processor core unit are less or not is determined by judging whether the first instruction completion times are smaller than a first preset times threshold value or not. If the first instruction completion times are smaller than the first preset times threshold, the clock reset generating unit can reduce the clock frequency of the processor core unit in a mode that the power consumption detecting unit sends a high-level low-activity signal to the clock reset generating unit, so that the power consumption of the processor core unit is reduced more quickly, and the power consumption control effect of the processor is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a scenario diagram of a processor power consumption control method in which embodiments of the present application may be implemented;

FIG. 2 is a flow chart illustrating a method for controlling power consumption of a processor according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating a method for controlling power consumption of a processor according to another embodiment of the present application;

FIG. 4 is a schematic diagram illustrating connection of a power consumption detection unit according to an embodiment of the present application;

FIG. 5 is a flowchart illustrating a method for controlling power consumption of a processor according to another embodiment of the present application;

FIG. 6 is a flowchart illustrating a method for controlling power consumption of a processor according to another embodiment of the present application;

FIG. 7 is a schematic diagram illustrating a power consumption control apparatus of a processor according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device provided by the present application.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The technical scheme of the application is described in detail below by specific examples. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

In order to clearly understand the technical scheme of the present application, the conception process of the inventor is first described. With the development of technology, the CPU design of the processor today becomes more and more complex, and while achieving higher and higher performance, more power is consumed and more heat is generated. Strategies for power consumption optimization are becoming increasingly important for all CPU-containing devices (e.g., desktop computers, tablet computers, notebook computers, cell phones, etc.).

The current power consumption optimization strategies are various, such as power consumption reduction through a physical heat dissipation mode, power consumption reduction through a software management mode and the like. The software may be configured to monitor, in real time, whether the device is in an idle state by using the power management controller, and if so, enter a low power consumption mode. It may also be a way to predict the processor power consumption situation by collecting performance data and a prediction algorithm.

The mode managed by the power consumption management controller needs to wait for a period of time when all related devices are kept in an idle state, and then the computer can enter a low power consumption mode, so that the time when the computer is in the low power consumption state is very short, and the power consumption control effect is general. Prediction accuracy by prediction is generally and hardware implementation is costly. Therefore, the power consumption control effect of the current power consumption optimization strategy needs to be further improved.

Therefore, the inventor finds in the research that in order to solve the problem that the power consumption control effect of the power consumption optimization strategy in the prior art needs to be further improved, a power consumption detection unit can be preset in the processor, and whether the processor core unit is in a low active state or not is determined based on the instruction completion times by detecting the instruction completion times corresponding to the processor core unit in a preset period, if the processor core unit is in the low active state, the clock frequency of the processor core unit is reduced by a clock reset generation unit, the power consumption of the processor is reduced more quickly, and the power consumption control effect of the processor is improved.

Specifically, the processor includes: the device comprises a power consumption detection unit, a processor core unit and a clock reset generation unit. When the task processing signal is at a high level, a power consumption detection unit is adopted to determine the corresponding first instruction completion times of the processor core unit in a first preset statistical period. The task processing signals are generated for the processor core unit. Judging whether the first instruction completion times are smaller than a first preset times threshold. If the first instruction completion times are smaller than the first preset times threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

In the method for controlling power consumption of the processor, when the task processing signal is at a high level, the task processing signal represents that the processor core unit is processing tasks, at this time, the power consumption detection unit can be adopted to determine the corresponding first instruction completion times of the processor core unit in a first preset statistical period, and whether the current tasks of the processor core unit are less or not is determined by judging whether the first instruction completion times are smaller than the first preset times threshold value or not. If the first instruction completion times are smaller than the first preset times threshold, the clock reset generating unit can reduce the clock frequency of the processor core unit in a mode that the power consumption detecting unit sends a high-level low-activity signal to the clock reset generating unit, so that the power consumption of the processor core unit is reduced more quickly, and the power consumption control effect of the processor is improved.

The inventor proposes the technical scheme of the application based on the creative discovery.

The application scenario of the processor power consumption control method provided by the embodiment of the application is described below. As shown in fig. 1, the internal structure of the processor is exemplarily shown, where 1 is a power consumption detection unit, 2 is a processor core unit, and 3 is a clock reset generation unit (Clock and Reset Generation, CRG). The number of the processor core units 2 may be plural, and this embodiment only exemplifies the case of one processor core unit. The power consumption detection unit 1 is configured to detect the number of times of instruction completion of the processor core unit 2 in a preset statistical period, and determine whether the processor core unit 2 is in a low active state according to the number of times of instruction completion. The clock reset generation unit 3 is used for controlling the clock frequency of the processor core unit 2.

Illustratively, when the processor core unit 2 is processing a task, the task processing signal is at a high level, and the power consumption detection unit 1 starts a detection flow, specifically as follows:

Determining the corresponding first instruction completion times of the processor core unit 2 in a first preset statistical period, wherein the task processing signal is generated by the processor core unit 2.

Judging whether the first instruction completion times are smaller than a first preset times threshold.

If the first instruction completion number is determined to be smaller than the first preset number threshold, a high-level low-activity signal is sent to the clock reset generation unit 3.

The clock reset generation unit 3 reduces the clock frequency of the processor core unit 2 according to the low active signal of the high level, thereby reducing the power consumption of the processor core unit 2.

Embodiments of the present application will now be described with reference to the accompanying drawings.

As shown in fig. 1, the present embodiment provides a processor, including: a power consumption detection unit 1, a processor core unit 2, and a clock reset generation unit 3.

The input end of the power consumption detection unit 1 is connected with the output end of the processor core unit 2, and the output end of the power consumption detection unit 1 is connected with the input end of the clock reset generation unit 3. The output end of the clock reset generating unit 3 is connected with the input end of the processor core unit 2.

The power consumption detection unit 1 is configured to detect a first instruction completion number corresponding to the processor core unit 2 in a first preset statistics period, and send a high-level low-activity signal to the clock reset generation unit 3 when the first instruction completion number is less than a first preset number threshold.

The clock reset generation unit 3 is configured to reduce the clock frequency of the processor core unit 2 according to the low active signal of the high level.

In this embodiment, the power consumption detecting unit 1 includes a plurality of comparators and a counter, the counter is used for determining the corresponding first instruction completion times or performing other counts in the first preset counting period, and the comparators are used for comparing the sizes of the data, such as the first instruction completion times and the first preset times threshold. The first preset time threshold may be set to a clock period, for example, may be set to 256 clock periods, or may be set correspondingly according to practical applications. The power consumption detection unit 1 may be provided in a control logic module responsible for maintenance of a CPU core, power consumption management, error reporting/processing, and the like.

Fig. 2 is a flow chart of a method for controlling power consumption of a processor according to an embodiment of the present application, as shown in fig. 2, in this embodiment, the number of the processor core units may be one or more, and the number of the power consumption detecting units may correspond to the number of the processor core units or may be only one.

The power consumption detection unit belongs to a combined module comprising a processor core unit and peripheral control logic in the processor, the power consumption detection unit is used for detecting whether the processor core unit is in a low active state, the clock reset generation unit belongs to a collective control logic module in the processor, and the collective control logic module is responsible for generating logic such as clock, reset, power-on and power-off and the like. The method for controlling the power consumption of the processor provided by the embodiment comprises the following steps:

in step S101, when the task processing signal is at a high level, the power consumption detection unit is used to determine the number of times of completion of the first instruction corresponding to the processor core unit in the first preset statistical period. The task processing signals are generated for the processor core unit.

In this embodiment, the task processing signal is a signal generated by the processor core unit, and when the task processing signal is at a high level, it indicates that the processor core unit is processing a task. The power consumption detection unit may automatically execute a subsequent flow of determining the number of times the first instruction is completed when the task processing signal is detected to be at a high level.

Optionally, when the processor core unit generates the task processing signal, the processor may control the power consumption detection unit to start according to the task processing signal, and execute a subsequent process of determining the number of times the first instruction is completed. The specific way may be to configure an enable register associated with the power consumption detection unit to enable the power consumption detection unit to start and execute a subsequent flow when the task processing signal is generated by the processor core unit.

The processor core unit may further generate a signal for completing execution of the instruction when performing task processing, and the power consumption detecting unit may determine the number of times of completing the first instruction according to the number of times the signal is at a high level.

In this embodiment, the first preset statistical period is a clock period, which may be set to 256 clock periods, or may be set correspondingly according to practical applications, which is not limited in this embodiment.

Step S102, judging whether the first instruction completion times are smaller than a first preset times threshold.

In this embodiment, the first preset number of times threshold may be set according to practical applications, for example, may be set according to IPCs (Instruction Per Clock, instruction number per clock cycle) of the processor, and the first preset number of times threshold may be set to 20 IPCs, 10 IPCs, and so on.

Step S103, if it is determined that the first instruction completion count is less than the first preset count threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

In this embodiment, the low active signal is used to indicate whether the processor core unit is in a low active state, and if it is determined that the processor core unit is in the low active state (may also be referred to as an idle state), a high low active signal is sent to the clock reset generation unit. The clock reset generation unit may reduce the clock frequency of the processor core unit in accordance with the low activity signal.

The embodiment of the application provides a method for controlling power consumption of a processor, which comprises the following steps: when the task processing signal is at a high level, a power consumption detection unit is adopted to determine the corresponding first instruction completion times of the processor core unit in a first preset statistical period. The task processing signals are generated for the processor core unit. Judging whether the first instruction completion times are smaller than a first preset times threshold. If the first instruction completion times are smaller than the first preset times threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

Fig. 3 is a flowchart of a method for controlling power consumption of a processor according to another embodiment of the present application, as shown in fig. 3, where the method for controlling power consumption of a processor according to the present application is further refined based on the method for controlling power consumption of a processor according to the previous embodiment of the present application, and the power consumption detecting unit includes: the first counter, the second counter and the first comparator. The method for controlling power consumption of a processor provided in this embodiment includes the following steps.

In step S201, when the task processing signal is at a high level, a first counter is started, and counts up from zero according to a first preset statistical period.

In this embodiment, the first counter is configured to calculate a counted period time, where the counted period time is set as a first preset counted period. And stopping counting the times of the high level of the instruction execution completion signal when the first counter counts up to the value of the first preset counting period.

In step S202, the second counter is used to count the number of times the instruction execution completion signal is at the high level. An instruction execution completion signal is generated for the processor core unit and sent to the power consumption detection unit.

In this embodiment, the second counter is configured to count the number of times the instruction execution completion signal is at a high level, and indicate that a certain instruction of the processor core unit has been executed when the instruction execution completion signal is at the high level.

In step S203, when the first counter counts up to the first preset counting period, the counted number of times the instruction execution completion signal is at the high level is determined as the first instruction completion number.

And when the first counter counts up to a first preset counting period, the counting period is ended, and the counted times of the command execution completion signal being at a high level are the times of the first command completion signal to be determined.

In step S204, a first preset number of times threshold is read from a preset register.

In this embodiment, the preset register stores a first preset frequency threshold, and the first preset frequency threshold may be directly obtained from the preset register.

In step S205, a first comparator is used to compare the number of times the first instruction is completed with a first preset number of times threshold to determine whether the number of times the first instruction is completed is smaller than the first preset number of times threshold.

In step S206, if the first instruction completion count is determined to be less than the first preset count threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

In this embodiment, the implementation manner of S206 is similar to that of the above-mentioned embodiment S103, and will not be described here again.

Optionally, the power consumption detection unit further includes: the third counter and the second comparator may further perform the exit detection process after S206, which is specifically as follows:

And calculating the corresponding second instruction completion times of the processor core unit in a second preset statistical period by adopting a third counter.

And comparing the second instruction completion times with a second preset times threshold by adopting a second comparator so as to judge whether the second instruction completion times are smaller than the second preset times threshold.

If the second instruction completion times are smaller than the second preset times threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit adjusts the clock frequency of the processor core unit according to the high-level low-activity signal.

If the second instruction completion times are greater than or equal to the second preset times threshold, the power consumption detection unit sends a low-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit increases the clock frequency of the processor core unit according to the low-level low-activity signal.

In this embodiment, the second preset statistical period may be the same as or different from the first preset statistical period. The second preset number of times threshold may be the same as or different from the first preset number of times threshold.

If the second instruction completion count is less than the second preset count threshold during the second preset count period detection, the processor core unit is still in a low active state, the detection is not required to be exited, and the current clock frequency of the processor core unit can be maintained or the clock frequency of the processor core unit can be further reduced.

If the second instruction completion number is greater than or equal to the second preset number threshold when the second preset statistic period is detected, the processor core unit is not in the low active state, so that the clock frequency of the processor core unit can be increased, for example, the clock frequency can be directly adjusted to be the previous high clock frequency, thereby improving the task processing efficiency of the processor core unit.

Optionally, in this embodiment, the power consumption detecting unit further includes: and a fourth counter.

The process of calculating the number of times of completion of the second instruction corresponding to the processor core unit in the second preset statistical period by using the third counter may be specifically as follows:

and accumulating the count from zero by using a fourth counter according to a second preset statistical period.

And counting the times of the high level of the instruction execution completion signal by adopting a third counter.

And when the fourth counter counts up to a second preset counting period, determining the counted times of the high level of the instruction execution completion signal as the second instruction completion times.

Optionally, in this embodiment, a process flow when the low active state is maintained for too long may be further added, which is specifically as follows:

the total duration when the low active signal is high is determined.

And judging whether the total duration is greater than a preset time threshold.

In this embodiment, if the low active state is maintained for too long, the sleep instruction may be directly sent to the processor core unit, so that the processor core unit enters a sleep state, and the clock frequency is turned off, so as to further reduce the power consumption of the processor core unit.

Optionally, in this embodiment, after S206 or after exiting the detecting process, the data task allocation situation of the processor core unit may be further adjusted, which is specifically as follows:

The new data processing task is distributed to the processor core unit or the clock reset generation unit is controlled to increase the clock frequency of the processor core unit.

The clock frequency of the processor core unit is controlled to be increased by controlling the clock reset generation unit, so that the task processing efficiency of the processor core unit can be improved, the efficiency requirement of a user on task processing is met, and meanwhile, the processor core unit can be enabled to enter a low-activity state more quickly.

Alternatively, in this embodiment, the number of the processor core units may be plural, and when the number of the processor core units is plural, the number of the power consumption detecting units may be plural, and each power consumption detecting unit corresponds to the processor core unit, and each power consumption detecting unit detects the power consumption condition of the corresponding processor core unit.

Optionally, when there are multiple processor core units, one of the processor core units is a monitoring core unit, after S206 or after exiting the detecting process, the data processing tasks corresponding to all the processor core units may be redistributed, which is specifically as follows:

and reallocating the data processing tasks corresponding to the processor core units according to the interrupt signals of the monitoring core units. The interrupt signal is generated and sent to the monitoring core unit by the processor core unit when the first instruction completion time is smaller than a first preset time threshold or generated and sent to the monitoring core unit by the processor core unit when the second instruction completion time is smaller than a second preset time threshold.

The redistribution of the data tasks may be that the processor core unit in the low active state distributes more tasks, and the processor core unit in the high active state distributes fewer tasks, thereby improving the overall data processing efficiency of the processor.

In order to describe the processor power consumption control method of the present embodiment in detail, the power consumption detection unit of the present embodiment will be further described below.

The processor power consumption control method of the present embodiment reduces power consumption by monitoring the number of times of CPU core IPC. The CPU component related to the scheme comprises two parts: the combination module comprises a CPU core unit and peripheral control logic. The collective control logic module is responsible for generating logic such as clock, reset, power-on and power-off and the like. The combination module includes a real core processing unit of the CPU and a power consumption detection unit of the embodiment. And the collective control logic module comprises a clock reset generation unit.

As shown in fig. 4, in this embodiment, the hardware interface of the power consumption detection unit is associated with the processor core unit and is used for transmitting a task processing signal instr_running, which indicates that the processor core unit is processing a task, and an instruction execution completion signal instr_cnt_inc, which is a flag indicating that the instruction execution is completed.

The software interface is mainly an interface of registers, which can be configured by software as follows: the power consumption detection unit starts to detect an enable register enable_low_activity_detect. A time window timer_select_for_entry into a low activity detection period (i.e., the first preset count period) and a threshold_for_entry into a low activity detection threshold (i.e., the first preset count threshold).

A time window timer_select_for_exit that exits the low activity detection period (i.e., the second predetermined count period) and a threshold_for_exit that exits the low activity detection threshold (i.e., the second predetermined count threshold). The output signal of the power consumption detection unit is a low active signal lad _ detected, which is directly connected to the clock reset generation unit for frequency modulation, and can be made into a readable register so that software can monitor the running condition of the processor core unit in real time.

The power consumption detection unit may obtain the first preset statistical period, the first preset frequency threshold, the second preset statistical period and the second preset frequency threshold through the data stored in the register, where the data may be configured correspondingly by the user in advance. The power consumption detection unit may also be configured with a readable register to facilitate a user's inquiry or monitoring of the low activity signal by a software program.

In this embodiment, the power consumption detection and exit detection processes may be automatically completed by the power consumption detection unit, and the user only needs to configure the period, the threshold data, and the configuration enable register, without performing additional interference and configuration in the detection process.

As shown in fig. 5, the detection flow is specifically as follows:

And (3) configuring a register.

When the CPU core is in the process of processing tasks, i.e. the signal instr_running is 1, the first counter starts to accumulate and enters the low activity detection period (i.e. the first preset statistical period)

After the time window configured by the timer_select_for_entry, a flag bit for starting detection is generated, and the detection flow is entered.

At this point the second counter (for counting the number of IPC) is cleared and starts counting the number of times the signal instr_cnt_inc is 1 during the low liveness detection period.

When the counting period is over, if the counted number of instructions is greater than the threshold for entering the low activity detection threshold (i.e. the first preset number of times threshold), the first counter is cleared.

If the counted number of instructions is smaller than threshold_for_entry, a level signal lad _ detected =1 is generated indicating that low liveness has been detected. And transmits lad _ detected to the clock reset generation unit CRG. At this time, the CRG dynamically reduces the clock frequency to the CPU core, so as to achieve the effect of saving power consumption.

As shown in fig. 6, the flow of determining whether to exit the low liveness detection is as follows:

when the low activity signal lad _ detected is 1, the fourth counter starts to count up, and generates a flag bit for exiting detection after exiting the low activity detection period (i.e. the second preset statistics period) timer_select_for_exit, and the exiting detection flow is started.

At this time, the counter of the third counter (for counting the number of IPC) is cleared, and counting of the number of times the signal instr_cnt_inc is 1 in the cycle is restarted.

When the counting period is over, if the counted number of instructions is smaller than the exit low liveness detection threshold (i.e. the second preset number of times threshold), the low liveness signal lad _ detected remains 1 and the clock frequency remains low.

If the counted number of instructions is greater than the second preset number of times threshold, the low liveness signal lad _ detected =0, and the CRG unit will readjust the output clock frequency back to the high frequency.

The power consumption control method of the processor of the embodiment has the following advantages:

1. The hardware cost of the scheme is lower: compared with other power consumption management schemes, the whole process can be completed by only realizing a very simple power consumption detection unit in each CPU core unit. The power consumption detection unit is mainly realized by a plurality of counters and comparators, and compared with other hardware schemes, the power consumption detection unit has very small resource occupation.

2. The physical expansion of the scheme is simple: in the multi-core CPU, each core can independently integrate the power consumption detection unit, regulate and control the clock frequency of each core respectively, and the cores are not affected by each other and do not need inter-core communication. In addition, because the hardware logic is simpler, and the physical distances between the power consumption detection unit and the CPU core unit and between the power consumption detection unit and the clock reset generation unit CRG are relatively close, the hardware processing delay for completing the whole power consumption management flow is also very low.

3. The real-time performance and the accuracy of the scheme are high: the parameter which is easy to calculate and can reflect the CPU state in real time is selected as the standard of low-power consumption regulation, and whether the CPU state is in the low-activity state or not can be accurately calculated through the real-time IPC value, so that the related module can perform necessary regulation in the low-activity state. In other schemes, parameters like a throttle value are often adopted, and although more power consumption information can be comprehensively reflected, the calculation is complex, and a large number of profiling (performance analysis) are often required to give accurate parameters so as to make accurate prediction of the throttle value.

4. The software intervention degree of the scheme is very low: only a few registers are required to be configured in advance, and the effects of dynamic frequency modulation and power consumption saving can be automatically realized by hardware.

5. The hardware frequency modulation component is realized in the unit for controlling the clock and resetting the clock, and the clock frequency can be automatically adjusted according to the signal feedback of the power consumption detection unit.

6. The scheme realizes the automatic linkage among the CPU core unit, the power consumption detection unit and the clock reset generation unit, and does not need software participation: the CPU core unit outputs a key signal to the power consumption detection unit, the power consumption detection unit obtains a result through statistics and calculation and sends the result to the clock reset generation unit, and finally the clock reset generation unit feeds back the adjusted clock to the CPU core unit, so that the power consumption of the CPU is reduced, and the complete flow of the scheme is completed.

7. In addition to hardware-adaptive frequency adjustment, the power consumption detection unit also provides a software readable register interface. When the software reads that the low activity signal is high for a long time, other power consumption management methods can be realized according to the software requirement, such as executing a sleep instruction, and completely closing the clock of the CPU core so as to realize higher power consumption saving.

Fig. 7 is a schematic structural diagram of a processor power consumption control device according to an embodiment of the present application, as shown in fig. 7, in this embodiment, the processor power consumption control device 300 may be disposed in an electronic apparatus. The electronic device comprises a processor and a memory, wherein the processor comprises a power consumption detection unit, a processor core unit and a clock reset generation unit. The processor power consumption control apparatus 300 includes:

The determining module 301 is configured to determine, when the task processing signal is at a high level, a first instruction completion number corresponding to the processor core unit in a first preset statistical period by using the power consumption detecting unit. The task processing signals are generated for the processor core unit.

The determining module 302 is configured to determine whether the first instruction completion count is less than a first preset count threshold.

And the adjusting module 303 is configured to send, if it is determined that the number of times of completion of the first instruction is less than the first preset number of times threshold, a high-level low-activity signal to the clock reset generating unit through the power consumption detecting unit, so that the clock reset generating unit reduces the clock frequency of the processor core unit according to the high-level low-activity signal.

The power consumption control device of the processor provided in this embodiment may execute the technical scheme of the method embodiment shown in fig. 2, and its implementation principle and technical effects are similar to those of the method embodiment shown in fig. 2, and are not described in detail herein.

The processor power consumption control device provided by the present application further refines the processor power consumption control device based on the processor power consumption control device provided in the previous embodiment, and the processor power consumption control device 300 includes:

optionally, in this embodiment, the power consumption detecting unit includes: a first counter and a second counter.

The determining module 301 is specifically configured to, when determining, by using the power consumption detecting unit, a first instruction completion number corresponding to the processor core unit in a first preset statistical period:

The first counter is started, and the count is accumulated from zero according to a first preset statistical period. And counting the times of the high level of the instruction execution completion signal by adopting a second counter. An instruction execution completion signal is generated for the processor core unit and sent to the power consumption detection unit. And when the first counter counts up to a first preset counting period, determining the counted times of the high level of the instruction execution completion signal as the first instruction completion times.

Optionally, in this embodiment, the power consumption detecting unit further includes: a first comparator.

The judging module 302 is specifically configured to:

the first preset number of times threshold is read from a preset register. And comparing the first instruction completion times with a first preset times threshold by adopting a first comparator so as to judge whether the first instruction completion times are smaller than the first preset times threshold.

Optionally, in this embodiment, the power consumption detecting unit further includes: a third counter and a second comparator.

The processor power consumption control apparatus 300 further includes:

The control module is used for calculating the corresponding second instruction completion times of the processor core unit in a second preset statistical period by adopting a third counter. And comparing the second instruction completion times with a second preset times threshold by adopting a second comparator so as to judge whether the second instruction completion times are smaller than the second preset times threshold. If the second instruction completion times are smaller than the second preset times threshold, the power consumption detection unit sends a high-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit adjusts the clock frequency of the processor core unit according to the high-level low-activity signal. If the second instruction completion times are greater than or equal to the second preset times threshold, the power consumption detection unit sends a low-level low-activity signal to the clock reset generation unit, so that the clock reset generation unit increases the clock frequency of the processor core unit according to the low-level low-activity signal.

And accumulating the count from zero by using a fourth counter according to a second preset statistical period. And counting the times of the high level of the instruction execution completion signal by adopting a third counter. And when the fourth counter counts up to a second preset counting period, determining the counted times of the high level of the instruction execution completion signal as the second instruction completion times.

Optionally, in this embodiment, the processor power consumption control apparatus 300 further includes:

And the sleep module is used for determining the total duration time when the low active signal is in a high level. And judging whether the total duration is greater than a preset time threshold. And if the total duration is determined to be greater than the preset time threshold, sending a sleep instruction to the processor core unit.

the first allocation module is used for allocating new data processing tasks to the processor core unit or controlling the clock reset generation unit to increase the clock frequency of the processor core unit.

Optionally, in this embodiment, the plurality of processor core units is a plurality of processor core units, and one of the plurality of processor core units is a monitor core unit.

The processor power consumption control apparatus 300 further includes:

And the second distribution module is used for redistributing the data processing tasks corresponding to the processor core units according to the interrupt signals of the monitoring core units. The interrupt signal is generated by the processor core unit and sent to the monitoring core unit when the first instruction completion number is smaller than a first preset number threshold.

The power consumption control device for a processor provided in this embodiment may execute the technical scheme of the method embodiment shown in fig. 2 to 6, and its implementation principle and technical effects are similar to those of the method embodiment shown in fig. 2 to 6, and are not described in detail herein.

According to embodiments of the present application, the present application also provides an electronic device, a computer-readable storage medium, and a computer program product.

As shown in fig. 8, fig. 8 is a schematic structural diagram of an electronic device provided by the present application. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the applications described and/or claimed herein.

As shown in fig. 8, the electronic device includes: a processor 401 and a memory 402. The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions for execution at the electronic device. The processor 401 includes a power consumption detection unit, a processor core unit, and a clock reset generation unit (not shown in the figure). The power consumption detection unit is used for detecting the power consumption condition of the processor core unit, and the clock reset generation unit is used for controlling the clock frequency of the processor core unit.

Memory 402 is a non-transitory computer readable storage medium provided by the present application. The memory stores instructions executable by the at least one processor to cause the at least one processor to perform the processor power consumption control method provided by the application. The non-transitory computer readable storage medium of the present application stores computer instructions for causing a computer to execute the processor power consumption control method provided by the present application.

The memory 402 is used as a non-transitory computer readable storage medium, and may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules (e.g., the determining module 301, the determining module 302, and the adjusting module 303 shown in fig. 7) corresponding to the processor power consumption control method according to the embodiments of the present application. The processor 401 executes various functional applications of the electronic device and processor power consumption control by running non-transitory software programs, instructions, and modules stored in the memory 402, i.e., implements the processor power consumption control method in the above-described method embodiments.

Meanwhile, the present embodiment also provides a computer product which, when instructions in the computer product are executed by a processor, enables execution of the processor power consumption control method of the above-described embodiment.

Other implementations of the examples of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of embodiments of the application following, in general, the principles of the embodiments of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the embodiments of the application pertains.

It is to be understood that the embodiments of the application are not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof. The scope of embodiments of the application is limited only by the appended claims.

Claims

1. A processor, comprising: the device comprises a power consumption detection unit, a processor core unit and a clock reset generation unit;

2. A method of controlling power consumption of a processor, applied to the processor of claim 1, the method comprising:

3. The method of claim 2, wherein the power consumption detection unit comprises: a first counter and a second counter;

4. The method of claim 3, wherein the power consumption detection unit further comprises: a first comparator;

Reading the first preset times threshold value from a preset register;

5. The method of claim 4, wherein the power consumption detection unit further comprises: a third counter and a second comparator;

6. The method of claim 5, wherein the power consumption detection unit further comprises: a fourth counter;

7. The method according to any one of claims 2 to 6, further comprising:

determining a total duration when the low active signal is high;

Judging whether the total duration is greater than a preset time threshold;

8. The method according to any one of claims 2 to 4, wherein after the transmitting, by the power consumption detecting unit, the high-level low-activity signal to the clock reset generating unit to cause the clock reset generating unit to decrease the clock frequency of the processor core unit according to the high-level low-activity signal, further comprising:

9. The method of any one of claims 2 to 4, wherein the processor core unit is a plurality of processor core units, and wherein one processor core unit is a monitor core unit;

10. An electronic device, comprising: a processor and a memory; the processor comprises a power consumption detection unit, a processor core unit and a clock reset generation unit;

the processors and the memory circuits are interconnected;

the memory stores computer-executable instructions;

The processor executes computer-executable instructions stored in the memory to implement the processor power consumption control method of any one of claims 2 to 9.