CN118248098B

CN118248098B - Multistage source driving circuit

Info

Publication number: CN118248098B
Application number: CN202410359678.2A
Authority: CN
Inventors: 张灵逸; 王硕
Original assignee: Shanghai Bailian Intelligent Technology Co ltd
Current assignee: Shanghai Bailian Intelligent Technology Co ltd
Priority date: 2024-03-27
Filing date: 2024-03-27
Publication date: 2024-12-31
Anticipated expiration: 2044-03-27
Also published as: CN118248098A

Abstract

The invention relates to the technical field of power supply driving, and discloses a multistage source driving circuit which comprises a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitance multiplexing and level, a tertiary generating circuit based on a buffer of double-bit interpolation, and a power supply module for supplying power to the primary generating circuit, wherein the power supply module comprises a power supply VDD end and a GND end, the highest voltage of the primary generating circuit is VDD, the lowest voltage of the primary generating circuit is 0, and 15 resistors are connected in series between the VDD and the 0. The multi-stage source driving circuit is used for completing the generation of the display gray scale of the high-definition pixel based on the 12-bit gray scale generation of the three-stage DAC source stage, can solve the problems that the driving area of a driving IC is large, the use power consumption of an actual product is high and the space utilization is not facilitated when the interpolation output of the second stage is used as the generation mode of the second stage gray scale, can effectively reduce the power consumption and heat dissipation of the driving circuit, and is environment-friendly and energy-saving.

Description

Multistage source driving circuit

Technical Field

The invention relates to the technical field of power supply driving, in particular to a multistage source driving circuit.

Background

The OLED-oriented driving IC is an integrated circuit chip and is used for controlling the switching and display modes of the AMOLED panel. As panel display resolution and data transfer speed increase, the requirements for driver ICs are also increasing.

The driving ICs of the AMOLED are classified into a source driving IC and a row selecting IC. The Source driving IC controls brightness, gray scale and color by line, and the control voltage enters pixels of Panel through channels formed by Source end and Drain end of the transistor. The current OLED-oriented display is basically based on the generation of gray scales by a two-level DAC. The structure of the DAC generally adopts a resistor string-based mode to generate corresponding first-stage gray scales, and interpolation output of a second stage is connected in series to generate the second-stage gray scales. The single-channel driving area of the driving IC designed in the source driving mode is large, and the miniaturization design of the source driving IC with low power consumption is not easy to carry out.

Disclosure of Invention

The present invention is directed to a multi-stage source driving circuit for solving the above-mentioned problems.

The multi-stage source driving circuit comprises a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitance multiplexing and level, a tertiary generating circuit based on a double-bit interpolation buffer, and a power supply module for supplying power to the primary generating circuit, wherein the power supply module comprises a power supply VDD end and a GND end.

Optionally, the highest voltage of the first-stage generating circuit is VDD, the lowest voltage is 0, and 15 resistors are connected in series between VDD and 0, and DATA [9:6] is input as a switch to select different voltages.

Optionally, the second-level generating circuit includes five groups of sampling capacitors and five groups of latch circuits, and the second-level generating circuit adopts a capacitor approximation and level latching mode to complete the generation of 4bit/16 gray scale.

Optionally, the two-stage generation circuit first feeds the [6:2] bit wide DATA into the second stage DAC of the DAC.

Optionally, each set of the sampling capacitors includes a capacitor 1, a capacitor 2 and a capacitor 3, and each set of the latch circuits includes a transistor 1, a transistor 2, a transistor 3, a transistor 4, a transistor 5 and a transistor 6, where the capacitor 1, the capacitor 2 and the capacitor 3 are used to generate different voltages to accept the voltage output from the resistor string.

Optionally, the latch circuit includes a capacitor SEL1, a capacitor SEL2, a capacitor SEL3, a capacitor SEL4, a capacitor SEL5, and a capacitor SEL6, and the capacitor SEL3, the capacitor SEL4, the capacitor SEL5, and the capacitor SEL6 are used to select output voltages of the transistors 3, 4, 5, and 6, respectively, the output voltages including two voltages m3_6_1h and m3_6_1l.

Optionally, the three stage generation circuit inputs the [1:0] bit wide DATA into a third stage DAC of the DAC, the three stage generation circuit comprising a bit interpolation buffer comprising a rail-to-rail input stage, a programmable current source, and a summing output unit.

Optionally, the rail-to-rail input stage includes a VH module electrically connected to the m3_6_1h voltage and a VL module electrically connected to the m3_6_1l voltage;

the programmable current source comprises D0, D1, D2 and D3 ends, and is compatible with 4bit gray scale voltage generation;

the summing output unit outputs a voltage.

Compared with the prior art, the invention provides a multi-stage source driving circuit, which has the following beneficial effects:

The multi-stage source driving circuit is used for completing the generation of the display gray scale of the high-definition pixel based on the 12-bit gray scale generation of the three-stage DAC source stage, can solve the problems that the driving area of a driving IC is large, the use power consumption of an actual product is high and the space utilization is not facilitated when the interpolation output of the second stage is used as the generation mode of the second stage gray scale in series connection, and can effectively reduce the power consumption and heat dissipation of the driving circuit, thereby being more environment-friendly and energy-saving.

Drawings

FIG. 1 is a schematic diagram of an overall driving circuit according to the present invention;

FIG. 2 is a schematic diagram of a power module according to the present invention;

FIG. 3 is a schematic diagram of a sampling capacitor and latch circuit according to the present invention;

FIG. 4 is a schematic diagram of a three stage generating circuit according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in figures 1-4, the invention provides a technical scheme that the multi-stage source driving circuit comprises a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitance multiplexing and level, a tertiary generating circuit based on a buffer of double-bit interpolation, and a power supply module for supplying power to the primary generating circuit, wherein the power supply module comprises a power supply VDD end and a GND end.

In this embodiment, the highest voltage of the primary generating circuit is VDD, the lowest voltage is 0, and 15 resistors are serially connected between VDD and 0 to input 10-bit pixel gray scale, and the input DATA is DATA [9:0], so that DATA [9:6] bit wide can be first sent to the first stage resistor string of the DAC, and DATA [9:6] is input as a switch to select different voltages, and the primary generating circuit encodes each stage voltage based on 4-bit/16-gray scale bits of the resistor string to obtain the encoded DATA with the following encoding forms of 0, v1, v2, v3, v4, v5, v6, v7, v8, b9, v10, v11, v12, v13, v14, VDD, see the following table:

The secondary generation circuit comprises five groups of sampling capacitors and five groups of latch circuits, and the secondary generation circuit adopts a capacitor approximation and level latching mode to finish the generation of 4bit/16 gray scale. The two-stage generation circuit first feeds the [6:2] bit wide DATA into the second stage DAC of the DAC.

In addition, each set of sampling capacitors includes a capacitor 1, a capacitor 2 and a capacitor 3, and each set of latch circuits includes a transistor 1, a transistor 2, a transistor 3, a transistor 4, a transistor 5 and a transistor 6, and the capacitors 1, 2 and 3 are used for generating different voltages to receive voltage outputs from the resistor string. The latch circuit includes a capacitor SEL1, a capacitor SEL2, a capacitor SEL3, a capacitor SEL4, a capacitor SEL5, and a capacitor SEL6, and the capacitor SEL3, the capacitor SEL4, the capacitor SEL5, and the capacitor SEL6 are used to select output voltages of the transistors 3, 4, 5, and 6, respectively, the output voltages including m3_6_1h and m3_6_1l.

Notably, the three stage generation circuit inputs the [1:0] bit wide DATA into the third stage DAC of the DAC, and the three stage generation circuit includes a bit interpolation buffer comprising a rail-to-rail input stage, a programmable current source, and a summing output unit. The rail-to-rail input stage comprises a VH module and a VL module, wherein the VH module is electrically connected with M3_6_1H voltage, the VL module is electrically connected with M3_6_1L voltage, the programmable current source comprises D0, D1, D2 and a D3 end, the programmable current source is compatible with 4bit gray scale voltage generation, and the summation output unit outputs the voltage.

As one implementation of the present embodiment:

The first stage inputs VOUT1 and VOUT2, and 10pf for capacitors 1, 2 and 3, and if the capacitors SEL1 and SEL2 are high, then transistors 1 and 2 are on at the same time. Because of the voltage division of the capacitors 1, 2 and 3, the voltages of P1 and P4 are respectively:

the voltages to obtain P2 and P3 are then respectively:

the voltages of transistor 3, transistor 4, transistor 5 and transistor 6 are then respectively:

The voltage values of the four types of levels are obtained through the switch of 4 selection 2, namely M3_6_1H and M3_6_1L respectively.

The voltage values of the other stages can be deduced in the same way.

The foregoing invention has been generally described in great detail, but it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, it is intended to cover modifications or improvements within the spirit of the inventive concepts.

Claims

1. A multi-level source driving circuit, characterized in that: it includes a primary generating circuit based on a resistor string, a secondary generating circuit based on capacitor multiplexing and level, and a tertiary generating circuit based on a double-bit interpolation buffer; it also includes a power supply module for supplying power to the primary generating circuit, the power supply module includes a power supply VDD terminal and a GND terminal;

The secondary generation circuit includes five groups of sampling capacitors and five groups of latch circuits. The secondary generation circuit uses capacitor approximation and level latching to complete the generation of 4bit/16 grayscales.

The secondary generation circuit first sends the [6:2]-bit-width DATA to the second-stage DAC of the DAC;

Each group of the sampling capacitors includes capacitor 1, capacitor 2 and capacitor 3, each group of the latch circuits includes transistor 1, transistor 2, transistor 3, transistor 4, transistor 5 and transistor 6, and the capacitors 1, capacitor 2 and capacitor 3 are used to generate different voltages to receive the voltage output from the resistor string;

The latch circuit includes capacitors SEL1, SEL2, SEL3, SEL4, SEL5 and SEL6, and capacitors SEL3, SEL4, SEL5 and SEL6 are used to select output voltages of transistors 3, 4, 5 and 6 respectively, and the output voltages include two voltages M3_6_1H and M3_6_1L.

2. A multi-level source driving circuit according to claim 1, characterized in that: the highest voltage of the first-level generating circuit is VDD, the lowest voltage is 0, and 15 resistors are connected in series between VDD and 0, and input DATA[9:6] is used as a switch to select different voltages.

3. A multi-stage source driving circuit according to claim 2, characterized in that: the three-stage generating circuit inputs the DATA with a bit width of [1:0] into the third-stage DAC of the DAC, the three-stage generating circuit includes a bit interpolation buffer, and the bit interpolation buffer includes: a rail-to-rail input stage, a programmable current source and a summing output unit.

4. A multi-stage source driver circuit according to claim 3, characterized in that: the rail-to-rail input stage comprises a VH module and a VL module, the VH module is electrically connected to the M3_6_1H voltage, and the VL module is electrically connected to the M3_6_1L voltage;

The programmable current source includes terminals D0, D1, D2 and D3, and the programmable current source is compatible with 4-bit grayscale voltage generation;

The summing output unit outputs a voltage.