CN118260236B - Data access request sending method, device and equipment for multi-core processor - Google Patents
Data access request sending method, device and equipment for multi-core processor Download PDFInfo
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Abstract
The disclosure provides a data access request sending method, device and equipment for a multi-core processor. The method is executed by a master node of the multi-core processor and comprises the steps of determining a first quantity of data access requests which can be processed by a management queue of the master node at a first time, determining a target request node for sending the first data access requests to a routing node of the multi-core processor after the first time under the condition that the first quantity is smaller than a first quantity threshold or the first quantity is equal to a second quantity threshold, wherein the first quantity threshold is the maximum receiving quantity of the data access requests which can be received by the master node at the first time, the second quantity threshold is zero, and sending a first signal to the target request node, so that the time when the master node cannot continue to process the data access requests can be timely determined, congestion of a network on chip caused by waiting for the data access requests in the network on chip due to the fact that the data access requests continue to be sent to the target request node is avoided, and further improving the performance of the multi-core processor.
Description
Technical Field
The disclosure relates to the technical field of processors, and in particular relates to a data access request sending method and device for a multi-core processor, electronic equipment and a storage medium.
Background
The rapid development of semiconductor technology has led to an increasing speed and integration of microprocessors, and the number and variety of transistor resources that processor designers can utilize to implement a chip have increased, and single-chip multiprocessors (Chip Multiprocessors, CMP), also known as multi-core processors, have become the mainstay of high-performance general-purpose processors, in which CMP network-on-chip data transmission strategies are aimed at meeting the requirements of processor-core data access and Cache Coherence (Cache Coherence) maintenance at relatively low communication overhead, power consumption, response delay, etc., with high bandwidth, and reducing network-on-chip congestion.
In the related art, a data access request that a master node cannot process in time in CMP will wait on a network-on-chip, occupy Buffer (Buffer) resources of each routing node (Router) of the network-on-chip, and cause blocking of the network-on-chip.
Disclosure of Invention
The present disclosure aims to solve, at least to some extent, one of the technical problems in the related art.
Therefore, an object of the present disclosure is to provide a method, an apparatus, an electronic device, and a storage medium for sending a data access request for a multi-core processor, so that a timing when a master node management queue cannot continue to process the data access request can be determined in time, and congestion of a network on chip caused by waiting for the data access request in the network on chip due to the fact that the data access request is continuously sent to a target request node can be avoided based on a first signal, and performance of the multi-core processor is further improved.
The data access request sending method for the multi-core processor provided by the embodiment of the first aspect of the disclosure is executed by a master node of the multi-core processor, and the method comprises the steps of determining a first quantity of data access requests which can be processed by a management queue of the master node at a first time, determining a target request node for sending the first data access requests to a routing node of the multi-core processor after the first time if the first quantity is smaller than a first quantity threshold or equal to a second quantity threshold, wherein the first quantity threshold is the maximum receiving quantity of the data access requests which can be received by the master node at the first time, and sending a first signal to the target request node, wherein the first signal is used for indicating the target request node to stop sending the first data access requests.
The data access request sending method for the multi-core processor provided by the embodiment of the second aspect of the disclosure is executed by a target request node of the multi-core processor, and the method comprises the steps of receiving a first signal sent by a main node of the multi-core processor, and suspending sending of the first data access request according to the first signal.
The data access request sending device for the multi-core processor provided by the embodiment of the third aspect of the disclosure is executed by a master node of the multi-core processor, and the device comprises a first determining module, a second determining module and a sending module, wherein the first determining module is used for determining a first quantity of data access requests which can be processed by a management queue of the master node at a first time, the second determining module is used for determining a target request node which sends the first data access requests to a routing node of the multi-core processor after the first time if the first quantity is smaller than a first quantity threshold or equal to a second quantity threshold, the first quantity threshold is the maximum receiving quantity of the data access requests which can be received by the master node at the first time, the second quantity threshold is zero, and the sending module is used for sending a first signal to the target request node, wherein the first signal is used for indicating the target request node to stop sending the first data access requests.
The data access request sending device for the multi-core processor provided by the embodiment of the fourth aspect of the disclosure is executed by a target request node of the multi-core processor, and the device comprises a receiving module, a sending module and a sending module, wherein the receiving module is used for receiving a first signal sent by a main node of the multi-core processor and suspending sending of a first data access request according to the first signal.
An embodiment of a fifth aspect of the present disclosure provides an electronic device, including a memory, and a computer program stored on the memory and capable of running on the memory, where the memory implements a data access request sending method for a multi-core processor as set forth in the embodiment of the first aspect of the present disclosure, or implements a data access request sending method for a multi-core processor as set forth in the embodiment of the second aspect of the present disclosure when the memory executes the program.
A sixth aspect of the present disclosure proposes a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a memory, implements a data access request transmission method for a multi-core processor as proposed by the first aspect of the present disclosure, or implements a data access request transmission method for a multi-core processor as proposed by the second aspect of the present disclosure.
An embodiment of a seventh aspect of the present disclosure proposes a computer program product, which when executed by an instruction memory in the computer program product, performs a data access request sending method for a multi-core processor as proposed by an embodiment of the first aspect of the present disclosure, or implements a data access request sending method for a multi-core processor as proposed by an embodiment of the second aspect of the present disclosure.
The data access request sending method, the device, the electronic equipment and the storage medium for the multi-core processor have the advantages that at least the first quantity of the data access requests which can be processed by the management queue of the main node at the first time is determined, the target request node which sends the first data access requests to the routing node of the multi-core processor after the first time is determined under the condition that the first quantity is smaller than a first quantity threshold value or the first quantity is equal to a second quantity threshold value, the first quantity threshold value is the maximum receiving quantity of the data access requests which can be received by the main node at the first time, the second quantity threshold value is zero, and the first signal is sent to the target request node, so that the moment that the management queue of the main node cannot continue to process the data access requests can be timely determined, congestion of on-chip networks caused by waiting for the data access requests in the on-chip networks due to the fact that the data access requests are continuously sent to the target request nodes can be avoided based on the first signal, and the performance of the multi-core processor is further improved.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
The foregoing and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a flow chart of a method for sending a data access request for a multi-core processor according to an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a multi-core processor architecture according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of a method for sending a data access request for a multi-core processor according to another embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for sending a data access request for a multi-core processor according to another embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a data access request sending device for a multi-core processor according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of a data access request sending device for a multi-core processor according to an embodiment of the disclosure;
fig. 7 illustrates a block diagram of an exemplary electronic device suitable for use in implementing embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present disclosure and are not to be construed as limiting the present disclosure. On the contrary, the embodiments of the disclosure include all alternatives, modifications, and equivalents as may be included within the spirit and scope of the appended claims.
Fig. 1 is a flowchart of a data access request sending method for a multi-core processor according to an embodiment of the present disclosure.
It should be noted that, the execution body of the data access request sending method for a multi-core processor in this embodiment is a data access request sending device for a multi-core processor, where the device may be implemented by software and/or hardware, and the device may be configured in an electronic device, and the electronic device may include, but is not limited to, a terminal, a server, and so on.
As shown in fig. 1, the data access request sending method for the multi-core processor includes:
S101, determining a first number of management queues of the master node capable of processing data access requests at a first time.
The data access request sending method for the multi-core processor described in the embodiments of the present disclosure is executed by a master node of the multi-core processor.
The multi-core processor is also called a single-Chip multiprocessor (Chip Multiprocessors, CMP), the number of processor cores integrated on a Chip reaches 32 cores, 64 cores, 128 cores or even more cores, and the inter-core interconnection adopts a Network on Chip (NoC), and the Network on Chip of the multi-core processor adopts a Mesh (Mesh) topology structure or a topology structure such as Torus (3-dimensional cube) which is expanded on the basis of the Mesh from the aspect of expandability.
Under the multi-level cache hierarchy and the network-on-chip architecture, the system level cache is shared by all processor cores and is addressed uniformly, and cache consistency is maintained among on-chip multi-cores of the multi-core processor. In the case of last level Cache sharing, each Cache block has a fixed Home node as a hierarchy for coherency maintenance. The memory address distribution is consistent with the address distribution of the last level cache. Each Home node maintains a directory that records the Cache nodes on which each Cache block in the processor core is owned, and the state in the processor core Cache.
In an embodiment of the present disclosure, referring to fig. 2, fig. 2 is a schematic architecture diagram of a multi-core processor according to an embodiment of the present disclosure, where a processor core includes a processor core execution unit and a multi-level cache hierarchy, and a network-on-chip routing node is responsible for transmitting a request from the processor core to a Home node, where the Home node includes a management queue, a record queue, a threshold determination unit, a system-level cache (SYSTEM CACHE), and a Directory (Directory).
Each Home node is provided with a management Queue (management Queue), and the management Queue is a control Core among a processor Core (CPU Core), a Directory (Directory), a system level cache (SYSTEM CACHE) and a memory controller (Memory Controller), wherein the management Queue (management Queue) is used for uniformly processing access requests sent to the system level cache of the corresponding Home node by a processing Core and consistency requests sent to the Directory and returning data. The management queue is responsible for receiving and sending cache miss (CACHE MISS) access requests from the processor core to the directory and system level caches, sending access memory requests to the memory controller for system level cache miss (SYSTEM CACHE MISS), returning replies to the processor core for invalidating accesses, sending coherency maintenance related operations to the processor core, receiving replies from the memory controller, etc.
The first time may be a current time, which is not limited.
The data access request may be, for example, information for requesting access to the master node directly sent by the processor core related to the master node, or information for requesting access to the master node sent by other processor cores to the master node via the request node related to the master node, which is not limited.
Wherein the management queue of the master node has a corresponding first number threshold of data access requests when processing the data access requests, whereby the first number of data access requests that the management queue is capable of processing at a first time may be a number difference between the processing data threshold and the number of data access requests that the management queue is processing at the first time.
That is, in the embodiment of the present disclosure, the first number of data access requests that can be processed by the management queue of the master node at the first time is determined, which may be a first number threshold value of the data access requests corresponding to the management queue, and the number of data access requests that are being processed by the management queue at the first time is determined, and then a number difference between the first number threshold value and the number of data access requests that are being processed by the management queue at the first time is taken as the first number.
S102, determining a target request node for sending a first data access request to a routing node of the multi-core processor after a first time in the case that the first number is smaller than a first number threshold or the first number is equal to a second number threshold.
Wherein the first number threshold is the maximum number of received data access requests that the master node can receive at the first time, or the second number threshold is the management queue full, i.e. the second number threshold is zero.
It will be appreciated that when the number of data access requests being processed in the management queue is less than the first number threshold, or the first number is equal to the second number threshold, the Home node cannot continue to receive the data access requests from the network on chip, so that the data access requests sent by the requesting node occupy Buffer resources of each routing node (Router) of the network on chip due to the fact that the Home node cannot receive the data access requests which would wait on the network on chip, thereby causing blocking of the network on chip.
The first data access request refers to a request node which communicates with the master node after a first time, and the data access request is to be sent.
Therefore, the embodiment of the disclosure aims to solve the technical problems, so as to determine the first number of the management queues of the master node capable of processing the data access requests at the first time, and timely determine the time when the management queues cannot continue to process the data access requests by combining the first number threshold and the second number threshold, thereby taking corresponding measures to avoid the problems.
Optionally, in some embodiments, the first number threshold is determined based on determining a third number of initial requesting nodes in communication with the master node, determining a fourth number of data access requests each of which can be sent in parallel, and determining a fifth number of data access requests each of which can be sent in parallel by a local processor core associated with the master node, determining a product between the third number and the fourth number, and taking a sum between the product and the fifth number as the first number threshold.
That is, in the embodiment of the present disclosure, referring to fig. 2, the request of the Home node of the multicore processor may come from the third number (four directions of north and south of east and west) of initial request nodes, and the direction of the local processor core is added, and if the directions of the third number (4) of initial request nodes are the largest, the fourth number (M) of data access requests may be sent in parallel, and the local processor core may send the fifth number (N) of requests in parallel, it may be determined that the first number threshold of the management queue is 4×m+n.
For example, when the four directions of north and south and the local processor core can only send one request at most, the first number threshold of the management queue is 5, the four directions of north and south of act as host can only send one request at most, and the local processor core can only send a plurality of parallel access Home node requests at most, the threshold of the management queue is set to be the four directions of north and south of east plus the maximum number of requests of the local maximum parallel access Home node, for example, the four directions of north and south of west can only send one data access request for accessing the Home node, the local processor core can only send 2 data access requests of parallel access Home node at most, the first number threshold of the management queue is 4+2=6, which is not limited.
Alternatively, in some embodiments, the second number of thresholds is determined based on, for example, the Home node managing the queue full, when all items of the managing queue are occupied, there are no empty items available, and thus it is determined that the first number of data access requests that the managing queue of the master node can handle at the first time is equal to 0, i.e., the second number of thresholds is set to 0.
It should be noted that the above manner of determining the number threshold is merely an example, and the number threshold of the management queue may be dynamically adjusted according to analysis of congestion situations of the network on chip, which is not limited.
Optionally, in some embodiments, in a case that the first number is smaller than the first number threshold, or the first number is equal to the second number threshold, node identification information and request priority corresponding to each first data access request are acquired, and then the node identification information and the request priority are stored in a record queue of the master node.
The request priority corresponding to the first data access request refers to a request priority of a processor core corresponding to the first data access request, and may be classified into different levels of priority, for example, 4 levels, and the like, and different request requirements or quality of service (QoS) corresponding to the processor core may be given different priorities, or the request priority corresponding to each first data access request may be determined according to information such as delay or bandwidth of a processor core requirement corresponding to the first data access request, which is not limited.
In this embodiment of the present disclosure, the node identification information corresponding to the first data access request may be, for example, the number of the target request node that directly sends the first data access request, or may be, for example, the number of the processor core corresponding to the first data access request, where the number of bits of the processor core number is determined according to the number of processor cores, if the number of processor cores is 128 cores, the number of processor cores is 7 bits, the number of processor cores is 256 cores, and the number of processor cores is 8 bits, which is not limited.
The number of entries of the record queue may be set to be the sum of the maximum number of requests that all processor cores may issue, thereby ensuring that the record queue is not full.
Alternatively, in some embodiments, the determining the target request node for sending the first data access request to the routing node of the network-on-chip after the first time if the first number is less than the first number threshold, or the first number is equal to the second number threshold may determine the node identification information from the record queue if the first number is less than the first number threshold, or the first number is equal to the second number threshold, and then determine the target request node from a plurality of initial request nodes of the multi-core processor according to the node identification information.
That is, in the embodiment of the present disclosure, the node identification information may be determined from the record queue when the first number is less than the first number threshold, or the first number is equal to the second number threshold, and then the initial request node corresponding to the node identification information is taken as the target node.
And S103, sending a first signal to the target request node.
In the embodiment of the disclosure, after determining that the target request node of the first data access request is sent to the routing node of the multi-core processor after the first time, the first signal may be sent to the target request node if the first number is smaller than the first number threshold or the first number is equal to the second number threshold, so that congestion of the network on chip caused by waiting for the data access request in the network on chip due to the fact that the data access request is continuously sent to the target request node can be avoided based on the first signal, and performance of the multi-core processor can be effectively improved.
In this embodiment, by determining the first number of data access requests that can be processed by the management queue of the master node at the first time, and determining the target request node that sends the first data access request to the routing node of the multi-core processor after the first time if the first number is less than the first number threshold or the first number is equal to the second number threshold, and then sending the first signal to the target request node, the first number threshold is the maximum number of data access requests that can be received by the master node at the first time, so that the time when the master node management queue cannot continue to process the data access requests can be determined in time, and therefore congestion of the network on chip caused by waiting for the data access requests in the network on chip due to the fact that the data access requests continue to be sent to the target request node can be avoided based on the first signal, and performance of the multi-core processor is further improved.
Fig. 3 is a flowchart of a data access request sending method for a multi-core processor according to another embodiment of the present disclosure.
As shown in fig. 3, the data access request sending method for the multi-core processor includes:
s301, determining a first number of management queues of the master node capable of processing data access requests at a first time.
S302, determining a target request node for sending a first data access request to a routing node of the multi-core processor after a first time if the first number is less than a first number threshold or the first number is equal to a second number threshold.
The descriptions of S301 to S302 may be specifically referred to the above embodiments, and are not repeated herein.
And S303, sending a third signal to the initial request node under the condition that the first number is larger than or equal to a first number threshold value, wherein the third signal is used for indicating the initial request node to continuously send a second data access request to the master node.
And the second data access request is a data access request which is continuously sent to the master node by the initial request node under the condition that the first number is larger than or equal to a first number threshold value, and the first data access request and the second data access request are different.
That is, in the embodiment of the present disclosure, it may be determined that, if the first number is greater than or equal to the first number threshold, the number of data access requests that can be currently processed by the management queue is not up to the first number threshold, that is, the management queue can continue to process the data access requests at this time, so the target node may send a third signal to the initial request node to instruct the initial request node to continue to send the second data access request to the master node, thereby avoiding wasting resources of the management queue and not delaying the processing opportunity of the data access request.
S304, determining a second number of data access requests that can be processed by the management queue at a second time.
Wherein the second time is after the first time.
That is, in the embodiment of the present disclosure, the determining the second number of data access requests that can be processed by the management queue of the master node at the second time may be determining a second number threshold of data access requests corresponding to the management queue, determining the number of data access requests that are being processed by the management queue at the second time, and taking a difference between the second number threshold and the number of data access requests that are being processed by the management queue at the second time as the second number.
And S305, sending a second signal to the target request node when the second number is greater than or equal to the first number threshold, wherein the second signal is used for indicating the target request node to resend the first data access request to the master node.
In the embodiment of the disclosure, when the second number is determined to be greater than or equal to the first number threshold, it may be determined that the number of data access requests that can be processed by the management queue at the second time reaches the first number threshold, that is, the management queue can continue to process the data access requests at this time, so that the master node may send a second signal to the target request node at the second time to instruct the second signal to resend the first data access request to the master node, thereby, while avoiding network-on-chip blocking at the first time, resending the first data access request by the target request node at the second time is promoted, thereby avoiding omission of the data access request, and thus effectively guaranteeing the data access effect of the processor core.
Optionally, in some embodiments, the second signal is sent to the target request node, where the priorities of the plurality of requests in the record queue may be ordered from low to high, so as to obtain an ordering result, and then the second signal is sequentially sent to the plurality of target request nodes according to the ordering result.
That is, in the embodiment of the present disclosure, when the second number is greater than or equal to the first number threshold, the priorities of the plurality of requests in the record queue may be sorted from low to high, so as to obtain a sorting result, and then, according to the sorting result, the second signal is sent to the target request node corresponding to the request priority with the higher priority.
In the embodiment of the disclosure, after the second signal is sent to the target request node, an item can be reserved in the management queue to the local processor core related to the master node, so that the first data access request retransmitted by the local processor core can be processed by the management queue.
In the embodiment of the disclosure, by determining the first number of the management queues of the master node capable of processing the data access requests at the first time, determining the target request node for transmitting the first data access requests to the routing node of the multi-core processor after the first time when the first number is smaller than the first number threshold or the first number is equal to the second number threshold, transmitting the third signal to the initial request node when the first number is larger than or equal to the first number threshold, and transmitting the third signal to the initial request node by the target node to instruct the initial request node to continue transmitting the second data access requests to the master node, thereby avoiding resource waste of the management queues, avoiding delay of processing time of the data access requests, determining the second number of the management queues capable of processing the data access requests at the second time, and transmitting the second signal to the target request node when the second number is larger than or equal to the first number threshold.
Fig. 4 is a flowchart of a data access request sending method for a multi-core processor according to an embodiment of the present disclosure.
It should be noted that, the execution body of the data access request sending method for a multi-core processor in this embodiment is a data access request sending device for a multi-core processor, where the device may be implemented by software and/or hardware, and the device may be configured in an electronic device, and the electronic device may include, but is not limited to, a terminal, a server, and so on.
As shown in fig. 4, the data access request sending method for the multi-core processor includes:
s401, receiving a first signal sent by a main node of a multi-core processor.
In the embodiments of the present disclosure, the explanation of the same terms in the above embodiments may be specifically referred to the above embodiments, and will not be repeated herein.
In the embodiment of the disclosure, the target request node may receive a first signal sent by a master node of the multi-core processor.
And S402, suspending sending the first data access request according to the first signal.
In the embodiment of the disclosure, after receiving the first signal, the target request node may suspend sending the first data access request to the master node, so that it can be avoided that the data access request cannot be processed in time, and the data access request waits in the network-on-chip to cause network-on-chip congestion, and the target request node may send indication information to the processor core corresponding to the first data access request, where the indication information is used to indicate that the processor core is to reserve the request, and wait for future retransmission.
Optionally, in some embodiments, the target requesting node may further receive a second signal sent by the master node, and resend the first data access request to the master node according to the second signal.
Specifically, after receiving the second signal, the target requesting node may determine that the master node management queue may continue to process the data access request at this time, and thus, the target requesting node may resend the first data access request to the master node.
In the embodiment of the disclosure, the target request node of the multi-core processor receives the first signal sent by the master node of the multi-core processor, so that when the first data access request can be sent to the target request node in a suspension mode based on the first signal, the situation that the data access request cannot be processed in time, and the network on chip is blocked due to waiting of the data access request in the network on chip can be avoided, and the overall performance of the multi-core processor is improved.
Fig. 5 is a schematic structural diagram of a data access request sending device for a multi-core processor according to an embodiment of the present disclosure.
As shown in fig. 5, the data access request sending apparatus 50 for a multi-core processor is characterized in that it is executed by a master node of the multi-core processor, and the apparatus includes:
A first determining module 501, configured to determine a first number of management queues of a master node that can process a data access request at a first time;
A second determining module 502, configured to determine a target request node that sends a first data access request to a routing node of a multicore processor after a first time, where the first number is less than a first number threshold, or the first number is equal to a second number threshold, and the first number threshold is equal to zero, and the first number threshold is the maximum number of receptions that a master node can receive the data access request at the first time;
A sending module 503, configured to send a first signal to the target request node, where the first signal is used to instruct the target request node to suspend sending the first data access request.
In some embodiments of the present disclosure, the data access request transmitting apparatus 50 for a multicore processor further includes:
The acquisition module is used for acquiring node identification information and request priority corresponding to each first data access request under the condition that the first number is smaller than a first number threshold value or the first number is equal to a second number threshold value;
and the storage module is used for storing the node identification information and the request priority in a record queue of the master node.
In some embodiments of the present disclosure, the second determining module 502 is further configured to:
Determining node identification information from the record queue if the first number is less than the first number threshold, or the first number is equal to the second number threshold;
And determining a target request node from a plurality of initial request nodes of the multi-core processor according to the node identification information.
In some embodiments of the present disclosure, the data access request transmitting apparatus 50 for a multicore processor further includes:
A third determining module configured to determine a second number of data access requests that the management queue is capable of handling at a second time, wherein the second time is subsequent to the first time;
And the first sending module is used for sending a second signal to the target request node under the condition that the second number is larger than or equal to the first number threshold value, wherein the second signal is used for indicating the target request node to send the first data access request to the master node again.
In some embodiments of the present disclosure, the first transmitting module is further configured to:
sorting the priorities of the requests in the record queue from low to high to obtain a sorting result;
and sequentially sending second signals to the target request nodes according to the sequencing result.
In some embodiments of the present disclosure, the first number threshold is determined based on:
Determining a third number of initial requesting nodes in communication with the master node;
Determining a fourth number of data access requests which can be transmitted in parallel by each initial requesting node, and determining a fifth number of data access requests which can be transmitted in parallel by local processor cores related to the main node;
determining a product between the third number and the fourth number;
the sum between the product and the fifth number is taken as a first number threshold.
In some embodiments of the present disclosure, the data access request transmitting apparatus 50 for a multicore processor further includes:
And the second sending module is used for sending a third signal to the initial request node under the condition that the first number is larger than or equal to the first number threshold value, wherein the third signal is used for indicating the initial request node to continue sending the second data access request to the master node.
The present disclosure also provides a data access request transmitting apparatus for a multi-core processor, corresponding to the data access request transmitting method for a multi-core processor provided in the embodiments of fig. 1 to 3 described above, and since the data access request transmitting apparatus for a multi-core processor provided in the embodiments of the present disclosure corresponds to the data access request transmitting method for a multi-core processor provided in the embodiments of fig. 1 to 3 described above, implementation of the data access request transmitting method for a multi-core processor is also applicable to the data access request transmitting apparatus for a multi-core processor provided in the embodiments of the present disclosure, which will not be described in detail in the embodiments of the present disclosure.
In this embodiment, by determining the first number of data access requests that can be processed by the management queue of the master node at the first time, and determining the target request node that sends the first data access request to the routing node of the multi-core processor after the first time if the first number is less than the first number threshold or the first number is equal to the second number threshold, the first number threshold is the maximum receiving number of the data access requests that can be received by the master node at the first time, and the second number threshold is zero, the first signal is sent to the target request node, thereby determining the time when the master node management queue cannot continue to process the data access requests in time, avoiding congestion of the network on chip caused by waiting for the data access requests in the network on chip due to the continuous sending of the data access requests to the target request node, and further improving performance of the multi-core processor.
Fig. 6 is a schematic structural diagram of a data access request sending device for a multi-core processor according to an embodiment of the present disclosure.
As shown in fig. 6, the data access request transmitting apparatus 60 for a multi-core processor is executed by a target requesting node of the multi-core processor, and the apparatus includes:
and the receiving module 601 is configured to receive a first signal sent by a master node of the multi-core processor, and suspend sending the first data access request according to the first signal.
In some embodiments of the present disclosure, the receiving module 601 is further configured to:
receiving a second signal sent by a master node;
and retransmitting the first data access request to the master node according to the second signal.
Corresponding to the data access request sending method for a multi-core processor provided by the embodiment of fig. 4, the present disclosure further provides a data access request sending device for a multi-core processor, and since the data access request sending device for a multi-core processor provided by the embodiment of the present disclosure corresponds to the data access request sending method for a multi-core processor provided by the embodiment of fig. 4, implementation of the data access request sending method for a multi-core processor is also applicable to the data access request sending device for a multi-core processor provided by the embodiment of the present disclosure, which is not described in detail in the embodiment of the present disclosure.
In the embodiment of the disclosure, the target request node of the multi-core processor receives the first signal sent by the master node of the multi-core processor, so that when the first data access request can be sent to the target request node in a suspension mode based on the first signal, the situation that the data access request cannot be processed in time, and the network on chip is blocked due to waiting of the data access request in the network on chip can be avoided, and the overall performance of the multi-core processor is improved.
In order to realize the embodiment, the disclosure further provides electronic equipment, which comprises a memory, a memory and a computer program stored on the memory and capable of running on the memory, wherein the memory realizes the data access request sending method for the multi-core processor according to the embodiment of the disclosure when executing the program.
In order to implement the above-described embodiments, the present disclosure also proposes a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a memory, implements a data access request transmission method for a multicore processor as proposed in the foregoing embodiments of the present disclosure.
In order to implement the above-described embodiments, the present disclosure also proposes a computer program product which, when executed by an instruction memory in the computer program product, performs a data access request transmission method for a multicore processor as proposed in the foregoing embodiments of the present disclosure.
Fig. 7 illustrates a block diagram of an exemplary electronic device suitable for use in implementing embodiments of the present disclosure. The electronic device 12 shown in fig. 7 is merely an example and should not be construed as limiting the functionality and scope of use of the disclosed embodiments.
As shown in fig. 7, the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to, one or more memories or processing units 16, a system memory 28, and a bus 18 that connects the various system components, including the system memory 28 and the processing units 16.
Bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a memory, or a local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include industry Standard architecture (Industry Standard Architecture; hereinafter ISA) bus, micro channel architecture (Micro Channel Architecture; hereinafter MAC) bus, enhanced ISA bus, video electronics standards Association (Video Electronics Standards Association; hereinafter VESA) local bus, and peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECTION; hereinafter PCI) bus.
Electronic device 12 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by electronic device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
Memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (Random Access Memory; hereinafter: RAM) 30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 7, commonly referred to as a "hard disk drive").
Although not shown in fig. 7, a disk drive for reading from and writing to a removable nonvolatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable nonvolatile optical disk (e.g., a compact disk read only memory (Compact Disc Read Only Memory; hereinafter CD-ROM), digital versatile read only optical disk (Digital Video Disc Read Only Memory; hereinafter DVD-ROM), or other optical media) may be provided. In such cases, each drive may be coupled to bus 18 through one or more data medium interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the various embodiments of the disclosure.
A program/utility 40 having a set (at least one) of program modules 42 may be stored in, for example, memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 42 generally perform the functions and/or methods in the embodiments described in this disclosure.
The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), one or more devices that enable a user to interact with the electronic device 12, and/or any devices (e.g., network card, modem, etc.) that enable the electronic device 12 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 22. Also, the electronic device 12 may communicate with one or more networks, such as a local area network (Local Area Network; hereinafter: LAN), a wide area network (Wide Area Network; hereinafter: WAN), and/or a public network, such as the Internet, through the network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 over the bus 18. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 12, including, but not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, for example, implementing the data access request transmission method for a multi-core processor mentioned in the foregoing embodiment.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
It should be noted that in the description of the present disclosure, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present disclosure in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present disclosure.
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of techniques known in the art, discrete logic circuits with logic gates for implementing logic functions on data signals, application specific integrated circuits with appropriate combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or part of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, and the program may be stored in a computer readable storage medium, where the program when executed includes one or a combination of the steps of the method embodiments.
Furthermore, each functional unit in the embodiments of the present disclosure may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented as software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present disclosure have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the present disclosure.
Claims (12)
1. A data access request transmission method for a multi-core processor, characterized by being executed by a master node of the multi-core processor, the method comprising:
determining a first number of management queues of the master node that can process data access requests at a first time;
Determining a target request node for sending a first data access request to a routing node of the multi-core processor after the first time if the first number is less than a first number threshold or the first number is equal to a second number threshold, wherein the second number threshold is zero;
Transmitting a first signal to the target request node, wherein the first signal is used for indicating the target request node to suspend transmitting the first data access request;
wherein the method further comprises:
determining a third number of initial requesting nodes in communication with the master node;
determining a fourth number of data access requests that each of the initial requesting nodes can send in parallel, and determining a fifth number of data access requests that the local processor cores associated with the master node can send in parallel;
determining a product between the third number and the fourth number;
and taking the sum value between the product and the fifth number as the first number threshold.
2. The method of claim 1, wherein the method further comprises:
Acquiring node identification information and request priority corresponding to each first data access request when the first number is smaller than the first number threshold or the first number is equal to the second number threshold;
storing the node identification information and the request priority in a record queue of the master node.
3. The method of claim 2, wherein the determining a target requesting node to send a first data access request to a routing node of the multi-core processor after the first time if the first number is less than a first number threshold or the first number is equal to a second number threshold comprises:
Determining the node identification information from the record queue if the first number is less than the first number threshold or the first number is equal to the second number threshold;
And determining the target request node from a plurality of initial request nodes of the multi-core processor according to the node identification information.
4. A method according to claim 2 or 3, wherein the method further comprises:
determining a second number of data access requests that the management queue is capable of handling at a second time, wherein the second time is subsequent to the first time;
And if the second number is greater than or equal to the first number threshold, sending a second signal to the target request node, wherein the second signal is used for indicating the target request node to resend the first data access request to the master node.
5. The method of claim 4, wherein the sending the second signal to the target requesting node comprises:
Sorting a plurality of request priorities in the record queue from low to high to obtain a sorting result;
And sequentially sending the second signals to a plurality of target request nodes according to the sequencing result.
6. The method of claim 1, wherein the method further comprises:
And sending a third signal to the initial request node when the first number is greater than or equal to the first number threshold, wherein the third signal is used for indicating the initial request node to continuously send a second data access request to the master node.
7. A data access request sending method for a multi-core processor, wherein the method is performed by a target request node of the multi-core processor, wherein the target request node is a request node that sends a first data access request to a routing node of the multi-core processor after a first time, the method comprising:
Receiving a first signal sent by a main node of the multi-core processor;
Suspending sending the first data access request according to the first signal;
The method comprises the steps of determining a first quantity of initial request nodes communicated with a master node, determining a fourth quantity of data access requests which can be sent in parallel by each initial request node, determining a fifth quantity of data access requests which can be sent in parallel by local processor cores related to the master node, determining a product between the third quantity and the fourth quantity, and taking the sum value between the product and the fifth quantity as the first quantity threshold.
8. The method of claim 7, wherein the method further comprises:
receiving a second signal sent by the master node;
and retransmitting the first data access request to the master node according to the second signal.
9. A data access request transmitting apparatus for a multi-core processor, characterized by being executed by a master node of the multi-core processor, the apparatus comprising:
a first determining module, configured to determine a first number of management queues of the master node that can process data access requests at a first time;
A second determining module, configured to determine a target request node that sends a first data access request to a routing node of the multi-core processor after the first time if the first number is less than a first number threshold, or the first number is equal to a second number threshold, where the second number threshold is zero;
A sending module, configured to send a first signal to the target request node, where the first signal is used to instruct the target request node to suspend sending the first data access request;
Wherein, the device is further used for:
determining a third number of initial requesting nodes in communication with the master node;
determining a fourth number of data access requests that each of the initial requesting nodes can send in parallel, and determining a fifth number of data access requests that the local processor cores associated with the master node can send in parallel;
determining a product between the third number and the fourth number;
and taking the sum value between the product and the fifth number as the first number threshold.
10. A data access request transmitting apparatus for a multi-core processor, characterized by being executed by a target request node of the multi-core processor, wherein the target request node transmits a request node of a first data access request to a routing node of the multi-core processor after a first time, the apparatus comprising:
The receiving module is used for receiving a first signal sent by a main node of the multi-core processor and suspending sending the first data access request according to the first signal;
The method comprises the steps of determining a first quantity of initial request nodes communicated with a master node, determining a fourth quantity of data access requests which can be sent in parallel by each initial request node, determining a fifth quantity of data access requests which can be sent in parallel by local processor cores related to the master node, determining a product between the third quantity and the fourth quantity, and taking the sum value between the product and the fifth quantity as the first quantity threshold.
11. An electronic device, comprising:
At least one memory, and
A memory communicatively coupled to the at least one memory, wherein,
The memory stores instructions executable by the at least one memory to enable the at least one memory to perform the method of any one of claims 1-8.
12. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-8.
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