CN118261113A - Method for setting and managing shared memory, electronic device and medium - Google Patents
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Abstract
The present invention relates to the field of chip technologies, and in particular, to a method for setting and managing a shared memory, an electronic device, and a medium, where the method includes: s1, acquiring a chip composition module corresponding to a chip design and a shared memory corresponding to the chip design; step S2, setting a region division table G m for each E m; step S3, setting a region access list F m for each E m; steps S4, D n perform a preset memory operation on G i m of at least one E j m that is accessible based on the corresponding H i m, and synchronously update the storage states of the other E j m in E m. The invention reduces the setting quantity of the memories and improves the efficiency of chip development.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method for setting and managing a shared memory, an electronic device, and a medium.
Background
In the chip development process, different operations of different layers and different chip composition modules aiming at memories are generally involved, in the chip verification process, different language processing is also involved, and the association synchronization between the different language processing is also involved. If corresponding memories are respectively set for different layers and different composition modules, and the memories are respectively set for processing of different languages, the number of the memories is huge, and the management difficulty is high. In addition, the memories of different languages need to be synchronized by additional processing, which takes a lot of time, thereby reducing the efficiency of chip development. Therefore, how to reasonably arrange and manage the memory is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a setting and managing method of a shared memory, electronic equipment and a medium, which reduce the setting quantity of the memory and improve the efficiency of chip development.
According to a first aspect of the present invention, there is provided a method for setting and managing a shared memory, including:
Step S1, obtaining a chip composition module { D 1,D2,...,Dn,...,DN } corresponding to a chip design and a shared memory { E 1,E2,...,Em,...,EM } corresponding to the chip design, wherein D n is an nth chip composition module, D n is a minimum composition unit or a module formed by interconnecting the minimum composition units, D 1,D2,...,Dn,...,DN is arranged in a level, the value range of N is 1 to N, and N is the total number of chip composition modules; e m is the M-th shared memory, the value range of M is 1 to M, M is the total number ,Em={E1 m,E2 m,...,Ej m,...,Ef(m) m},E1 m of shared memories and is the physical memory corresponding to E m, E j m is the memory model generated by the j-th language corresponding to E m, the value range of j is 1 to f (M), and f (M) is the total number of memory forms corresponding to E m;
Step S2, setting a region division table Gm,Gm={G1 m,G2 m,...,Gi m,...,Gg(m) m},Gi m for each E m as an ith storage region of E m, wherein each E j m executes region division according to G m, the value range of i is 1 to G (m), and G (m) is the total number of the regions divided by E m;
Step S3, setting a region access list Fm,Fm={H1 m,H2 m,...,Hi m,...,Hg(m) m},Hi m for each E m to be an i-th chip composition module list capable of accessing G i m, setting an accessible chip composition module for each E j m according to F m, and setting at least one D n for each H i m;
Steps S4, D n perform a preset memory operation on G i m of at least one E j m that is accessible based on the corresponding H i m, and synchronously update the storage states of the other E j m in E m.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the setting and managing method of the shared memory, the electronic equipment and the medium can achieve quite technical progress and practicality, and have wide industrial utilization value, and the setting and managing method of the shared memory has at least the following beneficial effects:
According to the invention, the memory models with different languages can be set for the same memory, the corresponding region division table is set for each memory based on different application scenes, and the corresponding access rights are set for different chip composition modules, so that flexible sharing of the memory is realized, the setting quantity of the memory is reduced, and the efficiency of chip development is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for setting and managing a shared memory according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a method for setting and managing a shared memory, as shown in fig. 1, comprising the following steps:
Step S1, obtaining a chip composition module { D 1,D2,...,Dn,...,DN } corresponding to a chip design and a shared memory { E 1,E2,...,Em,...,EM } corresponding to the chip design, wherein D n is an nth chip composition module, D n is a minimum composition unit or a module formed by interconnecting the minimum composition units, D 1,D2,...,Dn,...,DN is arranged in a level, the value range of N is 1 to N, and N is the total number of chip composition modules; e m is the M-th shared memory, the value range of M is 1 to M, M is the total number ,Em={E1 m,E2 m,...,Ej m,...,Ef(m) m},E1 m of shared memories and is the physical memory corresponding to E m, E j m is the memory model generated by the j-th language corresponding to E m, the value range of j is 1 to f (M), f (M) is the total number of memory forms corresponding to E m, and f (M) is more than or equal to 1.
The minimum composition unit is a unit preset with a corresponding RTL (Register Transfer Level) code. There is one top module in { D 1,D2,...,Dn,...,DN }, the top module has no parent module, the smallest constituent unit has no child module, and all logical layer interconnect modules in { D 1,D2,...,Dn,...,DN } except the top module have only one parent module.
It should be noted that, the memory shared by the plurality of chip composition modules and/or having the memory model is a shared memory. The jth language of the generated memory model may be SystemVerilog, C ++, systemC, python, or the like.
In step S2, the region division table Gm,Gm={G1 m,G2 m,...,Gi m,...,Gg(m) m},Gi m is set for each E m to be the i-th storage region of E m, each E j m performs region division according to G m, the value range of i is 1 to G (m), and G (m) is the total number of regions divided by E m.
It should be noted that, each memory model and the corresponding physical memory are set with the same memory address, and each E j m performs region division according to G m, which means that all E j m corresponding to E m have the same rule of region division, and follow the same region division table G m.
Step S3, a region access list Fm,Fm={H1 m,H2 m,...,Hi m,...,Hg(m) m},Hi m is set for each E m to be an i-th chip component module list capable of accessing G i m, each E j m sets an accessible chip component module according to F m, and each H i m includes at least one D n.
It should be noted that the same physical memory can be shared by a plurality of chip constituent modules, and by setting the region access list F m, the access authority of each chip constituent module to the storage region can be finely controlled, so that the access requirements of a plurality of chip constituent modules can be flexibly satisfied.
Steps S4, D n perform a preset memory operation on G i m of at least one E j m that is accessible based on the corresponding H i m, and synchronously update the storage states of the other E j m in E m.
The storage area that can be accessed by D n can be determined based on H i m corresponding to D n, when the memory model is shared, D n may directly perform an operation on the corresponding physical memory or may perform an operation on one of the memory models, but since the physical memory and the corresponding memory model are in a mirror image relationship, after any one E j m performs a preset memory operation, the storage states of other E j m in E m need to be synchronously updated, so as to maintain consistency of the data stored by the physical memory and the corresponding memory model.
It should be noted that, there are multiple area dividing methods in the same memory, and in different application examples, different area dividing methods may be selected, so all possible area dividing tables may be generated in advance based on all possible area dividing methods, and then the corresponding area dividing tables are directly selected according to specific application scenarios, as an embodiment, the step S2 includes:
Step S21, at least one alternative area division table is set for E m based on a preset chip design scene.
The candidate region division table is all possible region division tables which are generated in advance based on all possible region division methods.
Step S22, selecting one setting G m from the alternative area division table corresponding to E m based on the example of the shared memory.
As an embodiment, the preset memory operation includes applying for a reserved memory space, applying for an allocated memory space, applying for a released memory space, and the like. Correspondingly, each E j m sets a corresponding first application programming interface a 1 jm, second application programming interface a 2 jm, and third application programming interface a 3 jm,A1 jm for applying for reserving a memory space from E j m, a 2 jm for applying for allocating a memory space from E j m, and a 3 jm for releasing a memory space of E j m.
The storage space in the memory is initially in an idle state, if the storage space is set in a reserved state, the storage space can only be used by a component module with the reserved state, the storage space is set in a use state after being used, and the storage space is reset in the idle state after being released.
As an embodiment, the step S4 includes:
step S41, D n sends an apply for reserve storage instruction to the first target G i m of the first target E j m, the first target E j m is one E j m set in H i m corresponding to D n, The first target G i m is one G i m of the first targets E j m that can be accessed by D n set in H i m corresponding to D n.
And S42, analyzing the reserved storage space instruction to acquire the target reserved space address.
Step S43, judging whether the reserved space address is in an idle state, if so, calling A 1 jm of the first target E j m to set the target reserved space address in the first target G i m to be in a reserved state.
Step S44, call a 1 jm of each E j m except the first target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m }, and set the corresponding target headspace address to the reserved state.
It should be noted that, after the space address of the memory is set to the reserved state, in the reserved state, the space address of the memory can only be used by the constituent modules that set the reserved state, and other modules cannot apply for use.
In the chip random verification process, a random allocation of memory space is required, and as an embodiment, the step S4 includes:
And C1, D n sends an instruction for applying to randomly allocate the storage space to a second target E j m, wherein the second target E j m is one E j m set in H i m corresponding to D n.
And C2, analyzing the application random allocation storage space instruction, and obtaining the size of the target allocation storage space and the target random parameter.
As an example, the target random parameter includes an alignment identifier random allocation space size and a random allocation space amount. It should be noted that, in the process of chip design, data processing for aligned addresses is generally not easy to make mistakes, and data processing for non-aligned addresses is easy to make mistakes, but the random verification process is not easy to randomly generate non-aligned addresses. According to the invention, on the basis of setting the shared memory and the region division list, the alignment mark is set as non-alignment, so that the randomization of non-alignment addresses can be realized, the excitation that chip design is easy to make mistakes is generated, the coverage rate is ensured to be more complete, and the chip verification is more sufficient. The embodiment of the invention can also set the size of the random allocation space and the number of the random allocation spaces according to specific randomization requirements to control the randomization degree.
And C3, determining available candidate G i m with allocatable space currently exists based on H i m corresponding to the second target E j m.
Step C4, invoking A 2 jm of the second target E j m, and randomly distributing target random distribution space with the size of the target distribution storage space from at least one candidate G i m based on the target random parameters.
Wherein the randomness in one candidate G i m can be achieved based on the target randomness parameter, and the randomness across multiple candidates G i m can also be achieved.
Step C5, call a 2 jm of each E j m except the second target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m }, and set the corresponding target random allocation space address to the use state.
It should be noted that, if no corresponding random storage space is returned after the step C1-step C5, it is indicated that randomization fails, and the step C1-step C5 is performed by readjusting the target random parameters until the corresponding random storage space is obtained.
After the chip composition module finishes using the shared memory, the corresponding memory space can be released through the A 3 jm in time, so that other chip composition modules can be used continuously, and the memory space utilization rate of the shared memory is improved. As an embodiment, the step S4 includes:
Step D1, D n sends an instruction for applying to release the storage space to at least one third target G i m of the third targets E j m, where the third target G i m is a reserved storage space or an allocated storage space corresponding to D n, and the third target E j m is a physical memory or a memory model where the third target G i m is located.
And D2, analyzing an instruction for applying to release the storage space, and obtaining a target release address.
And D3, calling A 3 jm of the third target E j m to release the corresponding target release address in the third target G i m.
Step D4, call A 3 jm of each E j m except the third target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m } and release the corresponding target release address.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the memory models of different languages can be set for the same memory, the corresponding region division table is set for each memory based on different application scenes, and the corresponding access rights are set for different chip composition modules, so that flexible sharing of the memory is realized, the setting quantity of the memory is reduced, and the efficiency of chip development is improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. A method for setting and managing a shared memory, comprising:
Step S1, obtaining a chip composition module { D 1,D2,...,Dn,...,DN } corresponding to a chip design and a shared memory { E 1,E2,...,Em,...,EM } corresponding to the chip design, wherein D n is an nth chip composition module, D n is a minimum composition unit or a module formed by interconnecting the minimum composition units, D 1,D2,...,Dn,...,DN is arranged in a level, the value range of N is 1 to N, and N is the total number of chip composition modules; e m is the M-th shared memory, the value range of M is 1 to M, M is the total number ,Em={E1 m,E2 m,...,Ej m,...,Ef(m) m},E1 m of shared memories and is the physical memory corresponding to E m, E j m is the memory model generated by the j-th language corresponding to E m, the value range of j is 1 to f (M), and f (M) is the total number of memory forms corresponding to E m;
Step S2, setting a region division table Gm,Gm={G1 m,G2 m,...,Gi m,...,Gg(m) m},Gi m for each E m as an ith storage region of E m, wherein each E j m executes region division according to G m, the value range of i is 1 to G (m), and G (m) is the total number of the regions divided by E m;
Step S3, setting a region access list Fm,Fm={H1 m,H2 m,...,Hi m,...,Hg(m) m},Hi m for each E m to be an i-th chip composition module list capable of accessing G i m, setting an accessible chip composition module for each E j m according to F m, and setting at least one D n for each H i m;
Steps S4, D n perform a preset memory operation on G i m of at least one E j m that is accessible based on the corresponding H i m, and synchronously update the storage states of the other E j m in E m.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The step S2 includes:
Step S21, setting at least one alternative area division table for E m based on a preset chip design scene;
Step S22, selecting one setting G m from the alternative area division table corresponding to E m based on the example of the shared memory.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
The preset memory operation comprises the steps of applying for reserved memory space, applying for allocated memory space and applying for released memory space.
4. The method of claim 3, wherein the step of,
Each E j m sets a corresponding first application programming interface a 1 jm, second application programming interface a 2 jm, and third application programming interface a 3 jm,A1 jm for applying for a reserved storage space to E j m, a 2 jm for applying for allocating a storage space to E j m, and a 3 jm for releasing a storage space of E j m.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
The step S4 includes:
step S41, D n sends an apply for reserve storage instruction to the first target G i m of the first target E j m, the first target E j m is one E j m set in H i m corresponding to D n, The first target G i m is one G i m in a first target E j m which can be accessed by D n set in H i m corresponding to D n;
S42, analyzing the reserved storage space instruction to acquire a target reserved space address;
Step S43, judging whether the reserved space address is in an idle state, if so, calling A 1 jm of the first target E j m to set the target reserved space address in the first target G i m to be in a reserved state;
Step S44, call a 1 jm of each E j m except the first target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m }, and set the corresponding target headspace address to the reserved state.
6. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
The step S4 includes:
Step C1, D n sends an instruction for applying to randomly allocate a storage space to a second target E j m, where the second target E j m is one E j m set in H i m corresponding to D n;
step C2, analyzing an application random allocation storage space instruction, and obtaining the size of the target allocation storage space and a target random parameter;
Step C3, determining available candidate G i m with allocatable space currently existing based on H i m corresponding to the second target E j m;
Step C4, invoking A 2 jm of the second target E j m, and randomly distributing target random distribution space with the size of target distribution storage space from at least one candidate G i m based on the target random parameters;
Step C5, call a 2 jm of each E j m except the second target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m }, and set the corresponding target random allocation space address to the use state.
7. The method of claim 6, wherein the step of providing the first layer comprises,
The target random parameter includes an alignment identifier random allocation space size and a random allocation space amount.
8. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
The step S4 includes:
Step D1, D n sends an instruction for applying to release the storage space to at least one third target G i m of the third targets E j m, where the third target G i m is a reserved storage space or an allocated storage space corresponding to D n, and the third target E j m is a physical memory or a memory model where the third target G i m is located;
step D2, analyzing an instruction for applying to release the storage space, and obtaining a target release address;
Step D3, calling A 3 jm of the third target E j m to release the corresponding target release address in the third target G i m;
Step D4, call A 3 jm of each E j m except the third target E j m in { E 1 m,E2 m,...,Ej m,...,Ef(m) m } and release the corresponding target release address.
9. An electronic device, comprising:
At least one processor;
and a memory communicatively coupled to the at least one processor;
Wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-8.
10. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-8.
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