CN118280952A - Chip packaging structure and manufacturing method thereof - Google Patents

Abstract

The application discloses a chip packaging structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The chip packaging structure comprises a lead frame, a first chip, a substrate, a second chip and a plastic package body. The first chip is attached to the lead frame and is electrically connected with the lead frame through a first wire. The substrate is provided with an avoidance cavity, the substrate is attached to the lead frame, the first chip is accommodated in the avoidance cavity, a circuit is arranged on the substrate, and the circuit is electrically connected with the lead frame through a second wire. The second chip is attached to one side of the substrate, which is away from the lead frame, and the second chip is electrically connected with the circuit of the substrate. The chip packaging structure provided by the embodiment of the application has the characteristic of good heat dissipation effect of the lead frame, realizes high routing density through the substrate, stacks the first chip and the second chip and saves plane space. The manufacturing method of the chip packaging structure provided by the embodiment of the application can be used for manufacturing the chip packaging structure.

Description

Chip packaging structure and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a manufacturing method thereof.

Background technique

The lead frame is an alloy frame with extended leads. It has the following functions in chip packaging: 1) Provide mechanical support for the chip, which plays a supporting role in plastic packaging and subsequent use; 2) Provide electrical connection, connecting the chip and the external circuit; 3) Provide a heat dissipation path. The pins have lower thermal resistance than the plastic package and are the main heat dissipation channel. When packaging chips, such as the Quad Flat No-leads Package (QFN), the electrical connection between the chip and the lead frame is achieved by wire bonding.

However, with the development of integrated circuit technology, the functions of a single chip are increasing day by day, and the internal rewiring has no pins or interconnected nodes, which makes it difficult to implement the traditional lead frame. Although the traditional QFN package with lead frame has the advantages of good heat dissipation and high mechanical strength, the lead frame used has a limited number of pins and a large volume, making it difficult to achieve a high internal line interconnection density and meet more and more complex functional requirements.

Summary of the invention

The purpose of the present application includes providing a chip packaging structure and a manufacturing method thereof, which can take into account better heat dissipation performance, structural strength and high-density circuit interconnection.

The embodiments of the present application can be implemented as follows:

In a first aspect, the present application provides a chip packaging structure, including:

Lead frame;

A first chip, the first chip is mounted on a lead frame and is electrically connected to the lead frame through a first wire;

A substrate, wherein the substrate has an avoidance cavity, the substrate is mounted on the lead frame, and the first chip is accommodated in the avoidance cavity, a circuit is arranged on the substrate, and the circuit is electrically connected to the lead frame through a second wire;

A second chip, the second chip is mounted on a side of the substrate away from the lead frame, and the second chip is electrically connected to a circuit of the substrate;

The plastic package wraps the substrate and the second chip.

In an optional embodiment, the lead frame includes a heat sink located in the middle, and the first chip is connected to the heat sink by a thermally conductive adhesive.

In an optional embodiment, the substrate and the lead frame are bonded together by a DAF film.

In an optional embodiment, the second chip is mounted on the substrate, and the second chip is electrically connected to the circuit of the substrate through a third wire.

In an optional embodiment, the second chip is bonded to the substrate via a DAF film.

In an optional embodiment, the second chip is flipped on the substrate, and the second chip is electrically connected to the circuit of the substrate through metal bumps.

In an optional implementation, the avoidance cavity penetrates the substrate along the thickness direction of the substrate, and the second chip covers an opening of the avoidance cavity on a side away from the lead frame.

In an optional embodiment, the substrate is a resin substrate or a ceramic substrate.

In an optional implementation, the first chip is a logic chip, and the second chip is a memory chip.

In a second aspect, the present application provides a method for manufacturing a chip packaging structure, comprising:

Obtain a lead frame, mount a first chip on the lead frame, and make a first wire to electrically connect the first chip to the lead frame;

Obtain a substrate with a circuit, a avoidance cavity is opened on the substrate, the substrate is mounted on a lead frame, and a first chip is accommodated in the avoidance cavity;

Mounting a second chip on the substrate and electrically connecting the second chip to the substrate;

Making a second wire to electrically connect the circuit of the substrate with the lead frame;

A plastic package is manufactured on the lead frame to encapsulate the substrate and the second chip.

The beneficial effects of the embodiments of the present application include, for example:

The chip packaging structure provided in the present application includes a lead frame, a first chip, a substrate, a second chip and a plastic package. The first chip is mounted on the lead frame and electrically connected to the lead frame through a first wire. The substrate has an avoidance cavity, the substrate is mounted on the lead frame, and the first chip is accommodated in the avoidance cavity. A circuit is arranged on the substrate, and the circuit is electrically connected to the lead frame through a second wire. The second chip is mounted on the side of the substrate away from the lead frame, and the second chip is electrically connected to the circuit of the substrate. The plastic package wraps the substrate and the second chip. In this embodiment, since a lead frame is used, it has good mechanical strength and can ensure that the first chip has good heat dissipation. At the same time, a second chip is also arranged in the chip packaging structure, enriching the function of the entire chip packaging structure. By arranging a substrate with an avoidance cavity, the structure of the first chip, the substrate and the second chip can be stacked more compactly. The circuit of the substrate can be arranged as needed, such as arranging a multi-layer or single-layer wiring layer, so as to meet the needs of signal transmission. Therefore, the chip packaging structure provided in the embodiment of the present application has the characteristics of good heat dissipation effect of the lead frame, and also realizes high wiring density through the substrate, and stacking the first chip and the second chip also saves plane space. The manufacturing method of the chip packaging structure provided in the embodiment of the present application can be used to manufacture the above-mentioned chip packaging structure, thereby achieving the above-mentioned beneficial effects.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of a chip packaging structure in an embodiment of the present application;

FIG2 is a schematic diagram of the arrangement of a lead frame, a substrate and a first chip in one embodiment of the present application;

FIG3 is a schematic diagram of a chip packaging structure in another embodiment of the present application;

FIG4 is a flow chart of a method for manufacturing a chip packaging structure in one embodiment of the present application;

5 to 8 are schematic diagrams of different states of a chip packaging structure during a manufacturing process in an embodiment of the present application.

Icon: 010 - chip packaging structure; 100 - lead frame; 110 - heat sink; 200 - first chip; 210 - first wire; 300 - substrate; 301 - avoidance cavity; 310 - second wire; 400 - second chip; 410 - third wire; 420 - metal bump; 500 - plastic package.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition and explanation in the subsequent drawings.

In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the invention is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

In the prior art, although the traditional QFN package with lead frame has advantages such as good heat dissipation and high mechanical strength, the lead frame used has a limited number of pins and a large volume, so it is difficult to achieve a high wiring density. With the development of integrated circuit technology, the functions of a single chip are increasing, and the traditional method of using lead frame is difficult to meet more functional requirements in a smaller volume.

To this end, an embodiment of the present application provides a chip packaging structure, which achieves better heat dissipation and higher wiring density by mounting a substrate with a circuit on a lead frame with a first chip mounted on it, and stacking a second chip on the substrate, thereby meeting more functional requirements in a small volume.

FIG. 1 is a schematic diagram of a chip packaging structure 010 in an embodiment of the present application. As shown in FIG. 1 , the chip packaging structure 010 provided in the embodiment of the present application includes a lead frame 100, a first chip 200, a substrate 300, a second chip 400, and a plastic package 500. The first chip 200 is mounted on the lead frame 100 and is electrically connected to the lead frame 100 through a first wire 210. The substrate 300 has an avoidance cavity 301, the substrate 300 is mounted on the lead frame 100, and the first chip 200 is accommodated in the avoidance cavity 301. A circuit is provided on the substrate 300, and the circuit is electrically connected to the lead frame 100 through a second wire 310. The second chip 400 is mounted on a side of the substrate 300 away from the lead frame 100, and the second chip 400 is electrically connected to the circuit of the substrate 300. The plastic package 500 is arranged on one side of the lead frame 100 and wraps the substrate 300 and the second chip 400.

In this embodiment, the lead frame 100 is made of alloy material, which has good strength, good thermal conductivity and electrical signal transmission function. The lead frame 100 provides support for the first chip 200, the substrate 300 and the plastic package 500, ensuring that the entire chip packaging structure 010 has good mechanical strength. The first chip 200 is mounted on the lead frame 100, so the heat emitted by the first chip 200 can be efficiently transmitted to the surface of the chip packaging structure 010 (the lower surface in Figure 1) through the lead frame 100, thereby achieving better heat dissipation for the first chip 200. In addition, the lead frame 100 can also realize electrical connection between the first chip 200 and the second chip 400, and between the chip packaging structure 010 and external devices (such as circuit boards).

In the embodiment of the present application, the outer contour of the lead frame 100 is a rectangle, a heat sink 110 is disposed in the middle thereof, and the first chip 200 is mounted on the heat sink 110 .

Furthermore, the first chip 200 is mounted on the lead frame 100, that is, the pin of the first chip 200 is located on the side away from the lead frame 100. One end of the first wire 210 is connected to the pin of the first chip 200, and the other end is connected to the lead frame 100, so as to realize the electrical interconnection between the first chip 200 and the lead frame 100. The first wire 210 can be formed by a wire bonding process (i.e., wire bonding). The first chip 200 and the lead frame 100 (specifically the heat sink 110 in this embodiment) are connected by thermal conductive adhesive. The thermal conductive adhesive can ensure better connection strength and also has a higher thermal conductivity. The thermal conductive adhesive can eliminate the air gap between the first chip 200 and the heat sink 110, and can better conduct the heat emitted by the first chip 200 to the heat sink 110, thereby reducing the risk of overheating of the first chip 200 and ensuring the stability of its performance during operation.

In the embodiment of the present application, a circuit for signal transmission is provided on the substrate 300. The substrate 300 may be provided with one or more wiring layers including the circuit as required, and the wiring layer may be located inside the substrate 300. In the present embodiment, the surface of the substrate 300 has a pad, and the pad is connected to the circuit on the substrate 300 and the wire outside the substrate 300.

Specifically, in this embodiment, a first pad and a second pad (not shown) are provided on the surface of the substrate 300, the first pad is electrically connected to the lead frame 100 via a second wire 310, and the second pad is electrically connected to the second chip 400 via a third wire 410. In this connection mode, the second chip 400 is indirectly connected to the lead frame 100. The second wire 310 can be manufactured by a wire bonding process.

Furthermore, the substrate 300 and the lead frame 100 are bonded together by a DAF film. DAF film (Die Attach Film) is a special wafer bonding film. Optionally, the structure of the DAF film includes a first adhesive surface, a second adhesive surface, and an intermediate layer. The first adhesive surface can be used to bond with the substrate 300, and the second adhesive surface can be used to bond with the lead frame 100. The intermediate layer is located between the first adhesive surface and the second adhesive surface, and is a high thermal conductivity resin layer, which has the functions of supporting, filling, and conducting heat. Compared with glue, DAF film will not overflow during mounting, is smoother, and has an optional thickness. Of course, in other optional embodiments, the substrate 300 and the lead frame 100 can also be bonded together by glue.

FIG. 2 is a schematic diagram of the arrangement of the lead frame 100, the substrate 300 and the first chip 200 in one embodiment of the present application. As shown in FIG. 1 and FIG. 2, in the present embodiment, the substrate 300 is in the shape of a rectangle, and its outer contour is smaller than that of the lead frame 100, and its four sides are parallel to the four sides of the lead frame 100. The avoidance cavity 301 on the substrate 300 is used to avoid and accommodate the first chip 200 and the first wire 210, so as to avoid interference with the first chip 200 and the first wire 210 after the substrate 300 is mounted on the lead frame 100. By accommodating the first chip 200 in the avoidance cavity 301 of the substrate 300, the packaging structure can be made more compact, and the increase in size caused by the horizontal side-by-side arrangement or the vertical stacking can be avoided. In the present embodiment, the shape of the avoidance cavity 301 is also a rectangle, and its four sides are parallel to the four sides of the outer contour of the substrate 300.

In this embodiment, the avoidance cavity 301 penetrates the substrate 300 along the thickness direction of the substrate 300, and the second chip 400 covers the opening of the avoidance cavity 301 on the side away from the lead frame 100, so that the second chip 400 and the first chip 200 are spaced and opposite to each other in the thickness direction of the substrate 300. In other optional embodiments, the avoidance cavity 301 can be a groove body with an opening toward the lead frame 100, that is, the avoidance cavity 301 does not penetrate the substrate 300, and has only one opening toward the lead frame 100.

In this embodiment, the second chip 400 is mounted on the substrate 300, that is, the pins of the second chip 400 are located on the side away from the substrate 300. The pins of the second chip 400 are connected to the second pads on the substrate 300 through the third wires 410. The third wires 410 can be made by wire bonding process. Further, the second chip 400 and the substrate 300 are bonded by DAF film.

In this embodiment, the materials of the first conductive wire 210 , the second conductive wire 310 , and the third conductive wire 410 may be metal materials with good conductivity, such as gold, silver, and copper.

Optionally, the substrate 300 is a resin substrate, which is easy to design and low in cost, and can form several wiring layers inside. When cross wiring is required, the wires can be cross-deployed to another metal layer to achieve high internal line interconnection density. In other embodiments, the substrate 300 can also be a ceramic substrate, which has the characteristics of high thermal conductivity, high voltage resistance, high temperature resistance, corrosion resistance, and low dielectric loss.

The first chip 200 and the second chip 400 may be chips with different functions. Since the first chip 200 is mounted on the lead frame 100, the first chip 200 has a better heat dissipation environment than the second chip 400. Therefore, optionally, the heat generation of the first chip 200 is higher than that of the second chip 400. For example, the first chip 200 is a logic chip and the second chip 400 is a memory chip. Compared with the logic chip, the memory chip has a relatively small amount of computation and heat generation. The second chip 400 may specifically be a memory chip with a high lead density.

It should be understood that in other optional embodiments, the first chip 200 and the second chip 400 may also be chips of other types, or chips of the same type.

FIG3 is a schematic diagram of a chip packaging structure 010 in another embodiment of the present application. As shown in FIG3, in an optional embodiment, the second chip 400 is flipped on the substrate 300, and the second chip 400 is electrically connected to the circuit of the substrate 300 (specifically, the pad on the substrate 300) through the metal bump 420. Compared with the embodiment of FIG1, this arrangement omits the third wire 410, which can save a certain amount of space in the thickness direction.

FIG4 is a flow chart of a method for manufacturing a chip packaging structure in an embodiment of the present application; FIG5 to FIG8 are schematic diagrams of different states of a chip packaging structure 010 in an embodiment of the present application during the manufacturing process. As shown in FIG4 to FIG8, the method for manufacturing a chip packaging structure provided in an embodiment of the present application can be used to manufacture the chip packaging structure 010 provided in the above embodiment, and specifically includes the following steps:

Step S100 , obtaining a lead frame 100 , mounting a first chip 200 on the lead frame 100 , and making a first wire 210 to electrically connect the first chip 200 to the lead frame 100 .

Taking the chip packaging structure 010 of the embodiment of FIG. 1 as an example, the first chip 200 is mounted on the heat sink 110 of the lead frame 100 through a thermally conductive adhesive, and the first wire 210 is made through a wire bonding process to electrically connect the first chip 200 to the lead frame 100, as shown in FIG. 5. The thermally conductive adhesive has a high thermal conductivity and can meet the heat dissipation requirements of the first chip 200 with a high heat generation. In other optional embodiments, the first chip 200 can also be mounted in other ways, such as by a DAF film.

Step S200 , obtaining a substrate 300 with circuits, the substrate 300 is provided with an escape cavity 301 , mounting the substrate 300 on the lead frame 100 , and accommodating the first chip 200 in the escape cavity 301 .

Taking the chip packaging structure 010 of the embodiment of Figure 1 as an example, the substrate 300 can be mounted on the lead frame 100 using a DAF film, and the first chip 200 and the first wire 210 are placed in the avoidance cavity 301. The height of the first wire 210 and the first chip 200 is not greater than the thickness of the substrate 300, as shown in Figure 6.

Step S300 , mounting the second chip 400 on the substrate 300 , and electrically connecting the second chip 400 to the substrate 300 .

Taking the chip packaging structure 010 of the embodiment of FIG. 1 as an example, the second chip 400 generates relatively little heat, so it can be mounted on the substrate 300 using a DAF film, thereby avoiding the problem of glue overflow that may be caused by using glue. The second chip 400 covers the opening of the avoidance cavity 301 away from the lead frame 100.

Furthermore, the second chip 400 is mounted on the substrate 300 , and a third wire 410 is formed by a wire bonding process. The third wire 410 connects the pin of the second chip 400 and the second pad on the substrate 300 , as shown in FIG. 7 .

If the chip package structure 010 of the embodiment of FIG. 3 is manufactured, the third wire 410 may not be manufactured, but the metal bump 420 may be manufactured, and the second chip 400 is flipped onto the substrate 300 to connect the metal bump 420 to the second pad on the substrate 300 .

Step S400 , manufacturing a second wire 310 to electrically connect the circuit of the substrate 300 with the lead frame 100 .

Taking the chip package structure 010 of the embodiment of FIG1 as an example, the second wire 310 can be formed by a wire bonding process, and the second wire 310 connects the first pad on the substrate 300 to the lead frame 100, as shown in FIG8. It should be understood that the order of step S400 and step S300 can be reversed.

Step S500 , manufacturing a plastic package 500 on the lead frame 100 to encapsulate the substrate 300 and the second chip 400 .

Taking the chip packaging structure 010 of the embodiment of FIG. 1 as an example, a plastic package 500 is manufactured on the side of the lead frame 100 where the substrate 300 is provided, so that the plastic package 500 wraps the substrate 300 and the second chip 400, thereby protecting the substrate 300 and the second chip 400. Finally, the chip packaging structure 010 shown in FIG. 1 is obtained.

In summary, the embodiment of the present application provides a chip packaging structure 010 and a manufacturing method thereof. The chip packaging structure 010 provided in the present application includes a lead frame 100, a first chip 200, a substrate 300, a second chip 400 and a plastic package 500. The first chip 200 is mounted on the lead frame 100 and is electrically connected to the lead frame 100 through a first wire 210. The substrate 300 has an avoidance cavity 301, the substrate 300 is mounted on the lead frame 100, and the first chip 200 is accommodated in the avoidance cavity 301. A circuit is provided on the substrate 300, and the circuit is electrically connected to the lead frame 100 through a second wire 310. The second chip 400 is mounted on the side of the substrate 300 away from the lead frame 100, and the second chip 400 is electrically connected to the circuit of the substrate 300. The plastic package 500 wraps the substrate 300 and the second chip 400. In this embodiment, due to the use of the lead frame 100, it has good mechanical strength and can ensure that the first chip 200 has good heat dissipation. At the same time, the second chip 400 is also provided in the chip packaging structure 010, enriching the function of the entire chip packaging structure 010. By providing a substrate 300 with an avoidance cavity 301, the structure of the first chip 200, the substrate 300 and the second chip 400 can be stacked more compactly. The circuit of the substrate 300 can be set as needed, such as setting a multi-layer or single-layer wiring layer, so as to meet the needs of signal transmission. Therefore, the chip packaging structure 010 provided in the embodiment of the present application not only has the characteristics of good heat dissipation effect of the lead frame 100, but also realizes high wiring density through the substrate 300, and stacking the first chip 200 and the second chip 400 also saves plane space. The manufacturing method of the chip packaging structure provided in the embodiment of the present application can be used to manufacture the above-mentioned chip packaging structure 010, so as to achieve the above-mentioned beneficial effects.

The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims (10)

1. A chip packaging structure, comprising: Lead frame (100); A first chip (200), the first chip (200) being mounted on the lead frame (100) and electrically connected to the lead frame (100) via a first wire (210); A substrate (300), the substrate (300) having an avoidance cavity (301), the substrate (300) being mounted on the lead frame (100), and the first chip (200) being accommodated in the avoidance cavity (301), a circuit being arranged on the substrate (300), and the circuit being electrically connected to the lead frame (100) via a second wire (310); a second chip (400), the second chip (400) being mounted on a side of the substrate (300) facing away from the lead frame (100), the second chip (400) being electrically connected to the circuit of the substrate (300); A plastic package (500), wherein the plastic package (500) wraps the substrate (300) and the second chip (400). 2. The chip packaging structure according to claim 1, characterized in that the lead frame (100) comprises a heat sink (110) located in the middle, and the first chip (200) and the heat sink (110) are connected by thermal conductive adhesive. 3. The chip packaging structure according to claim 1, characterized in that the substrate (300) and the lead frame (100) are bonded together by a DAF film. 4. The chip packaging structure according to claim 1, characterized in that the second chip (400) is mounted on the substrate (300), and the second chip (400) is electrically connected to the circuit of the substrate (300) through a third wire (410). 5. The chip packaging structure according to claim 4, characterized in that the second chip (400) and the substrate (300) are bonded together by a DAF film. 6. The chip packaging structure according to claim 1, characterized in that the second chip (400) is flip-chip mounted on the substrate (300), and the second chip (400) is electrically connected to the circuit of the substrate (300) through metal bumps (420). 7. The chip packaging structure according to claim 1, characterized in that the avoidance cavity (301) penetrates the substrate (300) along the thickness direction of the substrate (300), and the second chip (400) covers an opening of the avoidance cavity (301) away from the lead frame (100). 8. The chip packaging structure according to any one of claims 1 to 7, characterized in that the substrate (300) is a resin substrate or a ceramic substrate. 9. The chip packaging structure according to any one of claims 1 to 7, characterized in that the first chip (200) is a logic chip, and the second chip (400) is a memory chip. 10. A method for manufacturing a chip packaging structure, characterized by comprising: Obtaining a lead frame (100), mounting a first chip (200) on the lead frame (100), and making a first wire (210) to electrically connect the first chip (200) to the lead frame (100); Obtaining a substrate (300) having a circuit, wherein a avoidance cavity (301) is provided on the substrate (300), mounting the substrate (300) on the lead frame (100), and accommodating the first chip (200) in the avoidance cavity (301); Mounting a second chip (400) on the substrate (300), and electrically connecting the second chip (400) to the substrate (300); Making a second wire (310) to electrically connect the circuit of the substrate (300) and the lead frame (100); A plastic package (500) is manufactured on the lead frame (100) to encapsulate the substrate (300) and the second chip (400).