CN118295496A - A computing device and a control method - Google Patents

Abstract

The embodiment of the present application provides a computing device and method, the computing device comprising: a first card slot, a first circuit board and a mainboard; the first card slot is used to plug the first circuit board; the first circuit board comprises: an M.2 connector; the M.2 connector is used to connect a solid-state drive (SSD); the mainboard comprises a baseboard management controller (BMC); the presence pin of the first circuit board is connected to the BMC; the presence pin of the M.2 connector and the SSD type pin are connected to the serial bus interface of the BMC; the BMC is used to detect the state of the presence pin of the first circuit board to determine whether the first circuit board is in place; when the first circuit board is in place, whether the SSD is in place is determined according to the level of the presence pin of the M.2 connector; when the SSD is in place, the type of the SSD is determined according to the level of the SSD type pin, which can save space inside the chassis, facilitate maintenance, and is compatible with the SATA M.2 interface and the NVMe M.2 interface.

Description

A computing device and a control method

Technical Field

The embodiments of the present application relate to the field of server technology, and in particular to a computing device and a control method.

Background technique

At present, servers need solid state drives (SSDs) to store documents, videos and other files. SSDs are connected to the server's motherboard through the M.2 interface (Next Generation Form Factor, NGFF), and the motherboard reads and writes data in the SSD. The M.2 interface is a new interface specification that replaces the mini-Serial Advanced Technology Attachment (mSATA) interface and is compatible with SATA and the high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIE).

The M.2 interface is mainly compatible with Socket 2 and Socket 3. Socket 2 can support M.2 SSDs compatible with SATA and PCIe x2 channel interfaces, and the corresponding key is B Key, while Socket 3 supports M.2 SSDs compatible with PCIex4 channel interfaces, and the corresponding key is M Key. Currently, SSD interfaces include SATA M.2 and Non-Volatile Memory express (NVMe) M.2. SATA M.2 can be plugged with both M Key and B Key SSDs, but NVMe M.2 can only be plugged with M Key SSDs.

In the prior art, the M.2 interface and the SSD are both set on a carrier board, and the carrier board is set inside the chassis of the server, occupying the space inside the chassis. When the SSD has a problem, the chassis must be disassembled, which makes maintenance difficult. Moreover, the current M.2 interface is not compatible with the SATA M.2 interface and the NVMe M.2 interface.

Summary of the invention

The embodiments of the present application provide a computing device and a control method, which can save space inside a chassis, facilitate maintenance, and be compatible with a SATA M.2 interface and an NVMe M.2 interface.

An embodiment of the present application provides a computing device, including: a first card slot, a first circuit board and a mainboard; the first card slot is used to plug in the first circuit board; the first circuit board includes: an M.2 connector; the M.2 connector is used to connect a solid-state drive (SSD); the mainboard includes a baseboard management controller (BMC); the presence pin of the first circuit board is connected to the BMC; the presence pin and the SSD type pin of the M.2 connector are connected to the serial bus interface of the BMC; the BMC is used to detect the state of the presence pin of the first circuit board to determine whether the first circuit board is in place; when the first circuit board is in place, whether the SSD is in place is determined according to the level of the presence pin of the M.2 connector, and when the SSD is in place, the type of the SSD is determined according to the level of the SSD type pin.

In order to save the internal space of the chassis and facilitate the maintenance of the SSD and the M.2 connector, and the M.2 connector can be compatible with both SATA and NVMe types of interfaces, the embodiment of the present application inserts a newly designed first circuit board into the first card slot, and an M.2 connector and a serial bus expansion device are designed on the first circuit board. The in-position pin of the first circuit board is connected to the BMC on the server motherboard; the in-position pin and the SSD type pin of the M.2 connector are connected to the serial bus interface of the BMC through the serial bus expansion device; the BMC determines whether the SSD on the first circuit board is in place by detecting the state of the in-position pin, and when the SSD is in place, continues to determine whether the type of the SSD is SATA or NVMe, and can be compatible with two types of SSDs, thereby expanding the application scenarios and being more flexible to use.

In a possible implementation, the mainboard further includes: a central processing unit; the M.2 connector is connected to the central processing unit; the BMC is further used to inform the central processing unit of the SSD type; the central processing unit is used to determine a protocol matching the SSD type according to the SSD type, the protocol including a Serial Advanced Technology Attachment Interface (SATA) protocol and a Non-Volatile Memory Host Controller Interface (NVMe) protocol.

Since the first circuit board can be replaced without unpacking the box, if an M.2 SSD fails, the first circuit board can be removed to replace the M.2 SSD without opening the chassis when the power of the entire machine is disconnected, eliminating the need to plug and unplug cables and move the entire computing device out of the cabinet and disassemble the machine. Especially when the computing device is very heavy, the pluggable maintenance method of the present application brings great convenience to operation and maintenance. The M.2 SSD carrier board in the form of an OCP card provided in the embodiment of the present application only occupies the space of an OCP card in size, and there is no need to reserve a dedicated space for the M.2 SSD carrier board in the chassis of the computing device in advance. At the same time, the M.2 SSD carrier board can be easily removed without opening the chassis of the computing device, so that the M.2 SSD can be maintained without unpacking the box.

In a possible implementation, the M.2 connector includes a first M.2 connector and a second M.2 connector, and the first circuit board also includes a serial bus expander; the first M.2 connector is used to connect a first SSD, and the second M.2 connector is used to connect a second SSD; the first SSD and the second SSD are backed up for each other; the in-position pin and the SSD type pin of the first M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; the in-position pin and the SSD type pin of the second M.2 connector are both connected to the serial bus interface of the BMC through the serial bus expander; the first M.2 connector includes a PCIE X4 pin, the PCIE X3 pin of the first M.2 connector is connected to the central processor, and the remaining PCIE X1 pin of the first M.2 connector is connected to the central processor as a SATA pin; the second M.2 connector includes a PCIE X4 pin, the PCIE X3 pin of the second M.2 connector is connected to the central processor, and the remaining PCIE X1 pin of the second M.2 connector is connected to the central processor as a SATA pin.

Generally, in order to achieve data backup, two M.2 connectors are set on the OCP card to connect two SSDs. The following describes how the OCP card can connect two SSDs. The M.2 connector provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, which expands the application scenarios and brings great convenience to actual use.

In a possible implementation, a first on-position pin and a second on-position pin of the first circuit board are respectively connected to two IO pins of the BMC, and the first on-position pin and the second on-position pin are both grounded on the first circuit board; a third on-position pin and a fourth on-position pin of the first circuit board are respectively connected to another two IO pins of the BMC; the third on-position pin and the fourth on-position pin of the first circuit board are both suspended on the first circuit board; and the BMC is used to determine that the first circuit board is in place when it is detected that the levels of the two IO pins connected to the first on-position pin and the second on-position pin are low.

The embodiments of the present application do not specifically limit the high and low level states of the in-position pin. For example, in one possible implementation, when the level of the in-position pin is high, the SSD is judged to be in position; otherwise, when the level of the in-position pin is low, the SSD is judged to be not in position. Similarly, the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin. For example, in one possible implementation, when the level of the SSD type pin is low, the SSD type is judged to be a SATA type; otherwise, when the level of the SSD type pin is high, the SSD type is judged to be an NVMe type.

In a possible implementation, a board ID is also stored on the first circuit board; the BMC is also used to read the board ID, and determine whether the first circuit board is an M.2 carrier board through the board ID. If it is not the M.2 carrier board, the central processor configures the first circuit board according to the bandwidth requirements of the standard OCP card.

The BMC can determine the function of the inserted OCP card by reading the Board ID information. Specifically, the BMC determines whether the first circuit board 100 is an M.2 carrier board through the Board ID, and if it is not an M.2 carrier board, it is configured according to the standard OCP card.

In a possible implementation, the BMC is specifically used to determine that the SSD type is NVMe when it is detected that the level of the SSD type pin is high; and to determine that the SSD type is SATA when it is detected that the level of the SSD type pin is low.

The embodiment of the present application does not specifically limit the high and low levels of the SSD type pins and can be set according to actual needs.

Based on a computing device provided in the above embodiment, an embodiment of the present application further provides a control method for a computing device, wherein the computing device comprises: a first card slot, a first circuit board and a mainboard; the first card slot is used to plug in the first circuit board; the first circuit board comprises: an M.2 connector; the M.2 connector is used to connect a solid-state drive SSD; the mainboard comprises a baseboard management controller BMC; the presence pin of the first circuit board is connected to the BMC; the presence pin of the M.2 connector and the SSD type pin of the M.2 connector are both connected to a serial bus interface of the BMC; the method comprises: judging whether the first circuit board is in place according to the level of the presence pin of the first circuit board; if the first circuit board is in place, judging whether the SSD is in place according to the level of the presence pin of the M.2 connector; if the SSD is in place, determining the type of the SSD according to the level of the SSD type pin.

In a possible implementation manner, the method provided in an embodiment of the present application further includes: determining a protocol matching the SSD type according to the SSD type; the protocol includes a Serial Advanced Technology Attachment interface SATA protocol and a Non-Volatile Memory Host Controller Interface NVMe protocol.

A possible implementation method is provided in an embodiment of the present application, wherein a board ID is also stored on the first circuit board, and the method further includes: reading the board ID, determining whether the first circuit board is an M.2 carrier board through the board ID, and if it is not the M.2 carrier board, causing the central processor to configure the first circuit board according to the bandwidth requirements of the standard OCP card.

A possible implementation method is the method provided in an embodiment of the present application, wherein the type of the SSD is determined by the level of the SSD type pin, specifically including: when the level of the SSD type pin is detected to be a high level, determining that the SSD type is NVMe; when the level of the SSD type pin is detected to be a low level, determining that the SSD type is SATA.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1A is a schematic diagram of a computing device provided in an embodiment of the present application;

FIG1B is a schematic diagram of another computing device provided in an embodiment of the present application;

FIG1C is a schematic diagram of another computing device provided in an embodiment of the present application;

FIG2 is a schematic diagram of a SATA M.2 provided in an embodiment of the present application;

FIG3 is a schematic diagram of an NVMe M.2 provided in an embodiment of the present application;

FIG4 is a schematic diagram of another computing device provided in an embodiment of the present application;

FIG5 is a flow chart of a method for controlling a computing device provided in an embodiment of the present application;

FIG6 is a flowchart of another method for controlling a computing device provided in an embodiment of the present application.

Detailed ways

The computing device provided in the embodiment of the present application does not specifically limit the application scenario. For example, the computing device is introduced by taking a server as an example, and the type of the server is not specifically limited. For example, the computing device can be a server. The server can be located in a data center or in other areas, and the embodiment of the present application does not make specific limitations.

A server is a computing device that runs faster and has a higher load than an ordinary computer. A server provides computing or application services to other clients (such as PCs, smartphones and other devices) in the network. The server has high-speed CPU computing power, long-term reliable operation, strong external data throughput and better scalability. Servers are divided into rack-mounted, blade-mounted, tower-mounted and cabinet-mounted in appearance; servers can also include AI servers, such as GPU servers, etc. in terms of function.

Single board is a common component in servers. Single board can be understood as a general term for circuit boards, which can be in various forms such as main board, power management board, network data exchange board, etc. Single board can be provided with other components, such as controller, processor, or other chips, to realize the computing function of the server. Single board can also be provided with electrical connector, through which single board can be plugged into other electrical components, or electrically connected to another single board through the electrical connector.

The server may include a single board and a power supply, wherein the power supply is used to supply power to various loads on the single board; the loads may be a central processing unit, a memory, a baseboard management controller, etc., which are arranged on the single board.

The embodiment of the present application does not specifically limit the type of single board, and the single board may be a main board or other single board.

The motherboard is a circuit board in the server. The motherboard can be equipped with controllers, memory sticks, electrical connectors and other components. The controller may include a central processing unit (CPU), a south bridge chip PCH, a microcontroller unit (MCU), a complex programming logic device (CPLD), a field programmable gate array (FPGA), etc. Among them, the CPU can be electrically connected to peripheral devices through the internal wiring and electrical connectors on the motherboard. For example, the CPU is electrically connected to network cards, graphics cards and other devices through electrical connectors. The CPU, PCH and CPLD can be set on the motherboard of a general server, and the CPU can be one or more.

The embodiments of the present application do not specifically limit the specific types of memory sticks. For example, memory sticks include but are not limited to the following types: dual-inline-memory-modules (DIMMs) and single inline memory modules (SIMMs). The memory chips on the DIMMs may be synchronous dynamic random access memory (SDRAM), fourth-generation double data rate synchronous dynamic random access memory (DDR4), and fifth-generation double data rate synchronous dynamic random access memory (DDR5).

A baseboard management controller (BMC) may be disposed on the mainboard.

BMC is an essential component of the server, used to monitor the operating status of the server, such as temperature, fan speed, power supply status, operating system status, etc. BMC operates independently of the server and is not affected by the server. It can perform some operations such as upgrading the server firmware, checking machine equipment, and remotely controlling the machine startup when the server is not turned on in the standby state. It can also record key logs when the server is down.

SSD, solid-state drive, also known as solid-state drive, is a hard disk made of an array of solid-state electronic storage chips.

The Open Compute Project (OCP) card is a hardware design specification customized for data centers, including customized design specifications for computer rooms, cabinets, servers, storage, network equipment, and management specifications for cloud hardware. The OCP card is a network interface card for the Open Compute Project. The side of the server chassis generally includes multiple first card slots, but generally some of the first card slots are vacant and no OCP card is inserted.

In order to save the internal space of the chassis and facilitate the maintenance of the SSD and M.2 connector, the embodiment of the present application is compatible with both SATA and NVMe interfaces. A newly designed first circuit board is inserted into the first card slot. The first circuit board has the same size and interface shape as the existing OCP card, and can also be an M.2 carrier board. An M.2 connector and a serial bus expander are designed on the first circuit board. The in-position pin of the first circuit board is connected to the BMC on the server motherboard; the in-position pin and the SSD type pin of the M.2 connector are connected to the serial bus interface of the BMC through the serial bus expander; the BMC determines whether the SSD on the first circuit board is in place by detecting the state of the in-position pin. When the SSD is in place, it continues to determine whether the type of the SSD is SATA or NVMe.

In order to enable those skilled in the art to better understand the technical solution provided by the embodiments of the present application, a detailed description is given below in conjunction with the accompanying drawings.

Refer to Figure 1A, which is a schematic diagram of a computing device provided in an embodiment of the present application.

The side of the server 1000 chassis generally includes a plurality of first card slots. For example, the first card slot can be used to insert an OCP card. However, the first card slot of the server 1000 is generally vacant and no OCP card is inserted. The present application can use the vacant first card slot to insert the first circuit board 100 provided in the embodiment of the present application. The first circuit board 100 has the same size and interface shape as the existing OCP card, and can also be an M.2 carrier board.

See FIG. 1B , which is a schematic diagram of another computing device provided in an embodiment of the present application.

The computing device provided in the embodiment of the present application includes a first circuit board 100 and a mainboard 200. The mainboard 200 is provided with a first card slot 300. For example, the first card slot can be an OCP slot, which can be plugged with an OCP card or the first circuit board 100 in the embodiment of the present application. The first circuit board 100 provided in the embodiment of the present application can be used as an M.2 carrier board. The embodiment of the present application does not specifically limit the number of M.2 connectors provided thereon. One M.2 connector can be provided, or multiple M.2 connectors can be provided. The M.2 connector can be inserted into SATA or NVMe. See Figure 1C, which is a schematic diagram of another computing device provided in the embodiment of the present application.

The computing device provided in the embodiment of the present application includes: a first card slot (not shown), a first circuit board 100 and a mainboard (MB) 200; the computing device is described below by taking a server as an example.

The OCP card slot is used to plug in the first circuit board 100; it should be understood that the first card slot is located on the side of the chassis of the server, which is not shown in Figure 1C. The first circuit board 100 can be directly inserted into the first card slot. Generally, a chassis is provided with multiple first card slots, and there will be idle first card slots. Therefore, the embodiment of the present application utilizes the idle first card slot to plug in the OCP card designed in the embodiment of the present application. It should be understood that the first circuit board 100 involved in the embodiment of the present application is different from the traditional OCP card. The first circuit board 100 provided in the embodiment of the present application is used as an M.2 carrier board, and an M.2 connector is provided on the M.2 carrier board. The M.2 carrier board can be connected to the motherboard to expand the storage device. For example, at least one M.2 SSD can be installed on the M.2 carrier board, for example, one M.2 SSD can be installed, or multiple M.2 SSDs can be installed. SATA type SSDs and NVMe type SSDs can be installed on the carrier board.

As shown in FIG1C , the OCP card provided in the embodiment of the present application includes: a first M.2 connector 101 and a serial bus expander 103; the first M.2 connector 101 is used to connect a solid-state drive SSD (not shown in the figure); the first M.2 connector 101 provided in the embodiment of the present application can be connected to a SATA type SSD, and can also be connected to an NVMe type SSD, that is, it is compatible with a SATA type SSD and an NVMe type SSD.

The main board 200 includes a BMC 202 .

The on-position pin of the first circuit board 100 is connected to BMC202; it should be understood that the on-position pin of the first circuit board 100 provided in the embodiment of the present application complies with the standard protocol of the OCP card, and the first circuit board 100 includes four on-position pins, namely the first on-position pin PRSNTB3#, the second on-position pin PRSNTB2#, the third on-position pin PRSNTB1# and the fourth on-position pin PRSNTB0#.

In a possible implementation, the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are respectively connected to the two IO pins of the BMC 202, and the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are both grounded on the first circuit board 100; the third in-position pin PRSNTB1# and the fourth in-position pin PRSNTB0# of the first circuit board 100 are respectively connected to the other two IO pins of the BMC 202, that is, the other two IO pins inside the BMC are connected to a high potential through a resistor, or directly connected to a high potential. The third in-position pin PRSNTB1# and the fourth in-position pin PRSNTB0# of the first circuit board 100 are both suspended on the first circuit board 100.

The serial bus expander 103 is generally an expansion interface of an integrated circuit bus (Inter-Integrated Circuit, I2C), which is used for serial communication between the first circuit board 100 and the BMC202. I2C is a serial communication bus that uses a multi-master-slave architecture. The I2C serial communication bus generally includes two signal lines, one is a bidirectional data line SDA, and the other is a clock line SCL. All serial data SDA connected to the I2C bus device is connected to the SDA of the bus, and the clock line SCL of each device is connected to the SCL of the bus.

The position pin M2_PRSNT1# and the SSD type pin PEDET1 of the first M.2 connector 101 are both connected to the serial bus interface Searial Bus of the BMC through the serial bus expander 103 .

BMC202 is used to determine whether the first circuit board 100 is in place by detecting the state of the in-place pin of the first circuit board 100. When the first circuit board 100 is in place, the state of the in-place pin of the M.2 connector is detected to determine whether the SSD is in place. When the SSD is in place, the type of the SSD is obtained through the SSD type pin.

BMC202 is used to determine that the first circuit board 100 is in place when the levels of the two IO pins are low, that is, when the two IO pins connected to the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are both low. Because the first in-position pin PRSNTB3# and the second in-position pin PRSNTB2# are both grounded on the first circuit board 100, the level states of the two IO pins identified by BMC202 are both low.

The above four in-position pins are compatible with the in-position detection of the standard OCP card. And the BMC can allocate PCIE bandwidth to the first circuit board 100 according to the detection of the four in-position pins.

The above describes the situation where the BMC determines that the first circuit board 100 is in place. The following describes the situation where the SSD is still in place when the first circuit board 100 is in place. Since the first circuit board 100 provided in the embodiment of the present application includes an M.2 connector for connecting an SSD, when the first circuit board 100 is in place, it includes an M.2 connector, and it is only necessary to further determine whether an SSD is connected to the M.2 connector.

The BMC 202 on the mainboard can automatically identify whether the first M.2 connector 101 on the first circuit board 100 is connected to a SATA SSD or an NVMe SSD disk, and configure the interface to enable the server to be compatible with the two types of SSDs.

Specifically, when determining whether an SSD is plugged into the first M.2 connector 101 and the type of the plugged SSD, BMC202 reads the level of the in-position pin M2_PRSNT1# of the first M.2 connector 101 through the serial bus expander 103 to determine whether the SSD is in position. In addition, BMC202 reads the SSD type pin PEDET1 through the serial bus expander 103 to determine whether the type of the SSD is SATA or NVMe. The embodiment of the present application does not specifically limit the high and low level states of the in-position pin. For example, in one possible implementation, when the level of the in-position pin M2_PRSNT1# is high, it is determined that the SSD is in position; conversely, when the level of the in-position pin M2_PRSNT1# is low, it is determined that the SSD is not in position. Similarly, the embodiments of the present application do not specifically limit the high and low level states of the SSD type pin PEDET1. For example, in one possible implementation, when the level of the SSD type pin PEDET1 is low, the SSD type is judged to be a SATA type; conversely, when the level of the SSD type pin PEDET1 is high, the SSD type is judged to be an NVMe type.

Since the first circuit board 100 is structurally replaceable without opening the case, if an M.2 SSD fails, the first circuit board 100 can be removed and the M.2 SSD can be replaced without opening the case when the power of the entire machine is disconnected, eliminating the need to plug and unplug cables and move the entire computing device out of the cabinet and disassemble the machine. Especially when the computing device is heavy, the pluggable maintenance method of the present application brings great convenience to operation and maintenance.

The M.2 SSD carrier board in the form of an OCP card provided in the embodiment of the present application only occupies the space of an OCP card in size, and there is no need to reserve a dedicated space for the M.2 SSD carrier board in the chassis of the computing device in advance. At the same time, the M.2 SSD carrier board can be easily removed without opening the chassis of the computing device, thereby realizing maintenance of the M.2 SSD without opening the box.

In addition, the motherboard 200 also includes a processor CPU and an integrated south bridge (Platform Controller Hub, PCH) 201. In the embodiment of the present application, the first M.2 connector 101 is connected to the processor CPU 201 as an example. The CPU 201 has IO expansion capabilities, and these IO expansion ports are usually compatible with multiple protocols. For example, the same IO port can support both PCIE and SATA protocols at the same time, and can be configured according to actual needs to implement different functions.

The CPU 201 also runs a Basic Input Output System (BIOS), which is responsible for self-checking and parameter configuration during the startup of the computing device business system. During the startup process, the BIOS can also obtain information from the BMC 202 and flexibly configure the parameters in the business system based on the information obtained.

The PCIE interface of the first M.2 connector 101 is connected to the CPU 201 .

BMC 202 is also used to inform CPU 201 of the SSD type.

CPU201 is used to determine the protocol that matches the SSD type according to the SSD type, and the SSD types include SATA and NVMe. SATA type SSD only needs one pin of PCIE, such as PCIE X1/SATA0 as shown in FIG1 . NVMe uses 4 pins of PCIE, so CPU201 configures a 4-pin PCIE interface to connect the first M.2 connector 101. Generally, SATA type SSD and NVMe type SSD will not exist at the same time, so CPU201 only needs to configure 4 PCIE pins in total, as shown in FIG1C , where SATA uses one pin PCIE X1/SATA0, and NVMe uses four pins, that is, in addition to using PCIE X3, NVMe also shares PCIE X1/SATA0 with SATA.

The computing device provided in the embodiment of the present application utilizes an OCP card as a carrier board of M.2. An M.2 connector is provided on the OCP card, and the M.2 connector can be used to plug in an SSD. Since the OCP card is located on the side of the chassis of the computing device, it can be directly plugged in and out. When the SSD or the M.2 connector fails, it can be directly plugged in and out for maintenance without disassembling the chassis. Moreover, the computing device provided in the embodiment of the present application utilizes the idle slot of the OCP card, so there is no need to reserve space inside the chassis of the computing device to set up an M.2 carrier board, thereby saving the internal space of the chassis. Moreover, the M.2 connector on the OCP card provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, and has universal applicability.

If the M.2 connector is only compatible with NVMe SSDs and not SATA SSDs, the actual application scenarios will be limited. Since M.2 is mostly used for system disks in the industry, SATA SSDs are widely used because of their strong software compatibility and ease of use. If it is only compatible with NVMe SSDs, there will be great limitations in its application. The M.2 connector provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, which expands the application scenarios and brings great convenience to actual use.

In addition, compared with the traditional PCIE M.2 adapter card, the OCP card provided in the embodiment of the present application is different from the traditional PCIE M.2 adapter card. Since the PCIE slot is expanded from the motherboard through the PCIE M.2 adapter card, and the OCP card is directly inserted into the motherboard, in comparison, the M.2 carrier board in the form of an OCP card provided in the embodiment of the present application uses one less PCIE M.2 adapter card, which can save costs.

For ease of understanding, the following describes the differences between SATA key positions and NVMe key positions with reference to the accompanying drawings.

See FIG. 2 , which is a schematic diagram of a SATA M.2 provided in an embodiment of the present application.

SATA M.2 includes two key positions, namely B Key and M Key. SATA M.2 can be applied to both Socket 2 and Socket 3 slots.

See Figure 3, which is a schematic diagram of an NVMe M.2 provided in an embodiment of the present application.

NVMe M.2 includes a key position, namely, M Key. NVMe M.2 is only applicable to Socket 3 slots.

The M.2 connector on the OCP card provided in the embodiment of the present application can be connected to both the SATA key position and the NVMe key position.

Generally, in order to achieve data backup, two M.2 connectors are set on the OCP card to connect two SSDs. The following describes how to connect two SSDs to the OCP card.

See FIG. 4 , which is a schematic diagram of another computing device provided in an embodiment of the present application.

By comparing FIG. 4 with FIG. 1 , it can be found that the first circuit board 100 shown in FIG. 4 is further provided with a second M.2 connector 102 compared with the first circuit board 100 shown in FIG. 1 . The second M.2 connector 102 includes a position pin M2_PRSNT2# and an SSD type pin PEDET2.

The computing device provided in the embodiment of the present application, the OCP card includes a first M.2 connector 101 and a second M.2 connector 102; the first M.2 connector 101 is used to connect the first SSD, and the second M.2 connector 102 is used to connect the second SSD; the first SSD and the second SSD are backed up for each other; the in-position pin M2_PRSNT2# and the SSD type pin PEDET1 of the first M.2 connector are both connected to the serial bus interface Searial Bus of the BMC202 through the serial bus expander 103. The in-position pin M2_PRSNT2# and the SSD type pin PEDET2 of the second M.2 connector 102 are both connected to the serial bus interface Searial Bus of the BMC through the serial bus expander 103;

The first M.2 connector 101 includes a PCIE X4 pin, a PCIE X3 pin of the first M.2 connector 101 is connected to CPU201, and the remaining PCIE X1 pin of the first M.2 connector 101 is used as SATA pin 0 to connect to CPU201; the second M.2 connector 102 includes a PCIE X4 pin, a PCIE X3 pin of the second M.2 connector 102 is connected to CPU201, and the remaining PCIE X1 pin of the second M.2 connector 102 is used as SATA pin 1 to connect to CPU201.

BMC202 reads the level of the in-position pin M2_PRSNT2# of the second M.2 connector 101 through the serial bus expander 103 to determine whether the SSD is in position. In addition, BMC202 reads the SSD type pin PEDET2 through the serial bus expander 103 to determine whether the type of the SSD is SATA or NVMe.

The embodiment of the present application does not specifically limit the high and low level states of the in-position pin. For example, in one possible implementation, when the level of the in-position pin M2_PRSNT2# is high, it is judged that the SSD is in position; otherwise, when the level of the in-position pin M2_PRSNT2# is low, it is judged that the SSD is not in position. Similarly, the embodiment of the present application does not specifically limit the high and low level states of the SSD type pin PEDET2. For example, in one possible implementation, when the level of the SSD type pin PEDET2 is low, it is judged that the SSD type is SATA type; otherwise, when the level of the SSD type pin PEDET2 is high, it is judged that the SSD type is NVMe type.

In addition, the second M.2 connector 102 is also connected to the CPU 201 via a PCIE interface.

CPU201 is used to determine the protocol that matches the SSD type according to the SSD type, and the SSD types include SATA and NVMe. SATA type SSD only needs one pin of PCIE, such as PCIE X1/SATA1 as shown in FIG4. NVMe uses 4 pins of PCIE, so CPU201 configures a 4-pin PCIE interface to connect the second M.2 connector 102. Generally, SATA type SSD and NVMe type SSD will not exist at the same time, so CPU201 only needs to configure 4 PCIE pins, as shown in FIG4, where SATA uses one pin PCIE X1/SATA1, and NVMe uses PCIE X1/SATA1 in addition to PCIE X3.

In the computing device provided in the embodiment of the present application, the first circuit board 100 stores a board identification (Board Identity, Board ID). For example, the first circuit board 100 includes a memory chip, and the memory chip stores the Board ID.

BMC202 is also used to read the Board ID through the serial bus expander 103. BMC202 can determine the function of the inserted OCP card by reading the Board ID information. Specifically, BMC202 determines whether the first circuit board 100 is an M.2 carrier board through the Board ID. If it is not an M.2 carrier board, it is configured according to the standard OCP card.

BMC202 determines whether an OCP card is installed in the OCP slot through the four in-place signals PRSNTB0#-PRSNTB3# of the first circuit board 100, and then determines the type of the installed OCP card according to the Board ID on the OCP card. If the OCP card is a standard universal OCP card, the PCIE bandwidth can be allocated according to the signal combination of PRSNTB0#-PRSNTB3#.

If BMC202 determines that an M.2 carrier board is installed based on the Board ID, BMC202 will continue to determine whether an M.2 SSD card is installed on the M.2 carrier board, and whether a SATA M.2 SSD or an NVMe M.2 SSD is installed based on the above M2_PRSNT# and PEDET signals. If a SATA M.2 SSD is installed on the M.2 carrier board, BMC202 needs to notify the BIOS in CPU201 to configure the M.2 connector as a SATA interface. If an NVMe M.2 SSD is installed on the M.2 carrier board, BMC202 notifies the BIOS in CPU201 to configure the M.2 connector as a PCIE interface, thereby achieving compatibility with different types of M.2 SSDs.

In the computing device provided in the embodiment of the present application, two M.2 connectors can be set on the OCP card, and the BMC can automatically identify whether the M.2 connector of the OCP card is connected to a SATA SSD or an NVMe SSD disk, and configure the PCIE interface of the CPU accordingly, thereby achieving the motherboard's compatibility with the two types of SSDs.

It should be understood that the embodiment of the present application does not specifically limit the number of M.2 connectors provided on the OCP card, and may be one, two, or more. The above only introduces one M.2 connector and two M.2 connectors as examples. The working principle is similar when more connectors are included, and will not be repeated here.

Based on a computing device provided in the above embodiment, an embodiment of the present application further provides a clock configuration method for a computing device, which is described in detail below in conjunction with the accompanying drawings.

Refer to FIG. 5 , which is a flow chart of a method for controlling a computing device provided in an embodiment of the present application.

The control method of a computing device provided in an embodiment of the present application, the computing device comprises: a first card slot, a first circuit board and a mainboard; the first card slot is used to plug an OCP card; the OCP card comprises: an M.2 connector; the M.2 connector is used to connect a solid-state hard disk SSD; the mainboard comprises a baseboard management controller BMC; the in-position pin of the OCP card is connected to the BMC; the in-position pin and the SSD type pin of the M.2 connector are both connected to the serial bus interface of the BMC;

The method includes:

S501: The BMC determines whether the first circuit board is in place according to the state of the in-place pin of the first circuit board;

The in-position pin of the OCP card 100 is connected to the BMC; it should be understood that the in-position pin of the OCP card provided in the embodiment of the present application complies with the standard protocol of the OCP card, and the OCP card 100 includes four in-position pins. Two in-position pins are both grounded on the OCP card; the pins are suspended on the OCP card. When the BMC detects that the level of the two IO pins is low, it determines that the OCP card is in position.

S502: When the first circuit board is in place, the BMC determines whether the SSD is in place according to the state of the in-place pin of the M.2 connector;

The BMC reads the level of the presence pin of the M.2 connector through the serial bus expander to determine whether the SSD is in place.

S503: When the SSD is in place, the BMC obtains the type of the SSD through the SSD type pin.

For example, when the level of the SSD type pin read by the BMC through the serial bus expander is low, the SSD type is determined to be a SATA type; conversely, when the level of the SSD type pin PEDET1 is high, the SSD type is determined to be an NVMe type.

The control method of the computing device provided in the embodiment of the present application can determine whether the OCP card is in place through the in-place pin of the BMC. When the OCP card is in place, it can determine whether the SSD is in place by detecting the state of the in-place pin of the M.2 connector; when the SSD is in place, the BMC obtains the type of the SSD through the SSD type pin. The M.2 connector on the OCP card is compatible with SATA type SSDs and NVMe type SSDs, has universality, expands the application scenarios of SSDs, and brings great convenience to actual use.

The central processing unit CPU may determine a protocol matching the SSD type according to the SSD type; for example, the SSD types include SATA and NVMe.

In a possible implementation manner, the control method provided in the embodiment of the present application, after the above step S501, the above control method further includes:

The board ID is read through the serial bus expander, and the board ID is used to determine whether the OCP card is an M.2 carrier board. If it is not an M.2 carrier board, it is configured according to the standard OCP card.

In order for those skilled in the art to better understand and implement the technical solution provided in the embodiments of the present application, a complete process of BMC identifying OCP card is introduced below in conjunction with the accompanying drawings.

Refer to FIG. 6 , which is a flow chart of another method for controlling a computing device provided in an embodiment of the present application.

The control method of a computing device provided in an embodiment of the present application includes:

S601: The BMC determines whether the first circuit board is in place according to the in-place pin signal of the first circuit board.

After the hardware system of the computing device is deployed, the power is turned on, the AC is powered on and the BMC is started. It should be understood that the side of the server chassis is provided with a first card slot, and judging whether the first circuit board is in place means judging whether the first card slot has the first circuit board inserted.

If there is no first circuit board, the server will start according to the default logic, ignoring the PCIE bandwidth configuration on the first card slot. The first card slot can be an OCP card slot located on the rear side of the server.

For example, a serial bus expander expands the I2C bus.

S602: When the first circuit board is in place, the BMC reads the Board ID of the first circuit board through the serial bus expander to determine whether the first circuit board is an M.2 adapter card.

S603: When the first circuit board is an M.2 adapter card, the BMC reads the in-position pin of the M.2 connector through the serial bus expander to determine whether the SSD is in position.

S604: When the SSD is in place, the BMC reads the SSD type pin through the serial bus expander to determine whether the SSD type is SATA or NVMe. If the SSD is not in place, the BIOS in the CPU configures the bandwidth according to the two X4 PCIE interfaces.

If the BMC determines that the SSD is not inserted into the M.2 connector, the BMC transmits the information that the SSD is not in place to the BIOS of the CPU.

S605: When it is determined that the SSD is a SATA M.2 SSD, the BIOS in the CPU configures bandwidth according to the two SATA interfaces to ensure that the SATA M.2 SSD is available.

S606: When it is determined that the SSD is an NVMe M.2 SSD, the BIOS in the CPU configures the bandwidth according to the two X4 PCIE interfaces to ensure that the NVMe M.2 SSD is available.

In the control method of the computing device provided in the embodiment of the present application, multiple M.2 connectors can be set on the first circuit board, and the BMC can automatically identify whether the M.2 connector of the first circuit board is connected to a SATA SSD or an NVMe SSD disk, and configure the PCIE interface of the CPU accordingly, so as to achieve the compatibility of the motherboard with the two types of SSDs.

The control method of the computing device provided in the embodiment of the present application is designed to have an M.2 carrier board that is the same as the OCP card (including the size and the physical size of the gold finger/connector connected to the motherboard is the same as the OCP card), and the M.2 carrier board is provided with an M.2 connector, and the M.2 connector can be used to plug in the SSD. Since the OCP card slot is located on the side of the chassis of the computing device, it can be directly plugged in and out. When the SSD or the M.2 connector fails, it can be directly plugged in and out for maintenance without disassembling the chassis. Moreover, the computing device provided in the embodiment of the present application utilizes the idle slot of the OCP card, so there is no need to reserve space inside the chassis of the computing device to set up the M.2 carrier board, thereby saving the internal space of the chassis. Moreover, the M.2 connector on the OCP card provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, and has universal applicability.

Since M.2 is mostly used for system disks in the industry, SATA SSDs are widely used due to their strong software compatibility and ease of use. If they are only compatible with NVMe SSDs, there will be great limitations in their application. The M.2 connector provided in the embodiment of the present application is compatible with SATA type SSDs and NVMe type SSDs, which expands the application scenarios and brings great convenience to actual use.

In addition, compared with the traditional PCIE M.2 adapter card, the first circuit board provided in the embodiment of the present application has a PCIE slot that is extended from the motherboard through the PCIE M.2 adapter card, while the OCP card is directly inserted into the motherboard. In comparison, the OCP card-shaped M.2 carrier board provided in the embodiment of the present application uses one less PCIE M.2 adapter card, which can save costs.

The above is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can make many possible changes and modifications to the technical solution of the present application using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims (10)

1. A computing device, comprising: the first clamping groove, the first circuit board and the main board;

the first clamping groove is used for being inserted into the first circuit board;

the first circuit board includes: an M.2 connector; the M.2 connector is used for connecting a solid state disk SSD;

The main board comprises a baseboard management controller BMC;

the in-place pin of the first circuit board is connected with the BMC;

the in-place pin of the M.2 connector and the SSD type pin of the M.2 connector are connected with a serial bus interface of the BMC;

The BMC is used for detecting the state of the in-place pin of the first circuit board and judging whether the first circuit board is in place or not; and judging whether the SSD is in place according to the level of an in-place pin of the M.2 connector under the condition that the first circuit board is in place, and determining the type of the SSD according to the level of the SSD type pin under the condition that the SSD is in place.

2. The computing device of claim 1, wherein the motherboard further comprises: a central processing unit;

the M.2 connector is connected with the central processing unit;

The BMC is also used for informing the CPU of the SSD type;

The central processing unit is configured to determine, according to the SSD type, a protocol that matches the SSD type, where the protocol includes a serial advanced technology attachment interface SATA protocol and a nonvolatile memory host controller interface NVMe protocol.

3. The computing device of claim 1, wherein the m.2 connector comprises a first m.2 connector and a second m.2 connector, the first circuit board further comprising a serial bus extender;

The first M.2 connector is used for connecting a first SSD, and the second M.2 connector is used for connecting a second SSD;

The first SSD and the second SSD are mutually backed up;

The bit pin and the SSD type pin of the first M.2 connector are connected with a serial bus interface of the BMC through the serial bus expander;

The bit pin and the SSD type pin of the second M.2 connector are connected with a serial bus interface of the BMC through the serial bus expander;

The first m.2 connector comprises a PCIE X4 pin, a PCIE X3 pin of the first m.2 connector is connected to the central processor, and the remaining PCIE X1 pin of the first m.2 connector is used as a SATA pin to be connected to the central processor;

the second m.2 connector includes a PCIE X4 pin, a PCIE X3 pin of the second m.2 connector is connected to the central processor, and a remaining PCIE X1 pin of the second m.2 connector is connected to the central processor as a SATA pin.

4. The computing device of claim 1, wherein a first in-place pin and a second in-place pin of the first circuit board are respectively connected to two IO pins of the BMC, the first in-place pin and the second in-place pin being both grounded on the first circuit board; the third in-place pin and the fourth in-place pin of the first circuit board are respectively connected with the other two IO pins of the BMC; the third in-place pin and the fourth in-place pin of the first circuit board are suspended on the first circuit board;

And the BMC is used for determining that the first circuit board is in place when the level of the two IO pins connected with the first in-place pin and the second in-place pin is detected to be low.

5. The computing device of any of claims 1-4, wherein the first circuit board further has a board ID stored thereon;

And the BMC is also used for reading the board ID, judging whether the first circuit board is an M.2 carrier board or not through the board ID, and if the first circuit board is not the M.2 carrier board, configuring the first circuit board by the central processing unit according to the bandwidth requirement of a standard OCP card.

6. The computing device of any of claims 1-4, wherein the BMC is specifically configured to determine that the SSD type is NVMe when the level of the SSD type pin is detected to be high; and when the level of the SSD type pin is detected to be low, determining that the SSD type is SATA.

7. A control method of a computing device, the computing device comprising: the first clamping groove, the first circuit board and the main board; the first clamping groove is used for being inserted into the first circuit board; the first circuit board includes: an M.2 connector; the M.2 connector is used for connecting a solid state disk SSD; the main board comprises a baseboard management controller BMC; the in-place pin of the first circuit board is connected with the BMC; the in-place pin of the M.2 connector and the SSD type pin of the M.2 connector are both connected with a serial bus interface of the BMC;

The method comprises the following steps:

Judging whether the first circuit board is in place or not according to the level of the in-place pin of the first circuit board;

Judging whether the SSD is in place or not according to the level of an in-place pin of the M.2 connector under the condition that the first circuit board is in place;

And determining the type of the SSD through the level of the SSD type pin under the condition that the SSD is in place.

8. The control method according to claim 7, characterized by further comprising:

Determining a protocol matched with the SSD type according to the SSD type; the protocol includes a serial advanced technology attachment interface SATA protocol and a non-volatile memory host controller interface NVMe protocol.

9. The control method of claim 7, wherein the first circuit board further has a board ID stored thereon, the method further comprising:

And reading the board ID, judging whether the first circuit board is an M.2 carrier board or not through the board ID, and if the first circuit board is not the M.2 carrier board, configuring the first circuit board by the central processing unit according to the bandwidth requirement of a standard OCP card.

10. The computing device of claim 1, wherein the determining the type of the SSD by the level of the SSD type pin, in particular comprises:

when the level of the SSD type pin is detected to be high, determining that the SSD type is NVMe; and when the level of the SSD type pin is detected to be low, determining that the SSD type is SATA.