CN118295709A - Instruction processing method, chip, electronic equipment and storage medium - Google Patents

Abstract

The present application relates to the technical field of instruction processing, and in particular to an instruction processing method, chip, electronic device and storage medium. In the method, a first prefetch instruction is inserted into the function entry of a sub-function that cannot be inlined, and a first label corresponding to the first prefetch instruction is inserted into the function end of the sub-function that cannot be inlined, a second prefetch instruction is inserted into the function entry of a main function adjusted to the beginning of a compilation unit, and a second label corresponding to the second prefetch instruction is inserted into the end of the compilation unit. Based on the first prefetch instruction, the first label, the second prefetch instruction and the second label, the number of instructions of the sub-function that cannot be inlined and the compilation unit is determined respectively, so that the number of prefetch instructions can be determined in combination with the remaining storage space corresponding to the cache. In this way, the accuracy of the determined number of prefetch instructions can be improved, so that functions with a suitable number of loading instructions can be stored in the cache to reduce the situation of instruction missing.

Description

Instruction processing method, chip, electronic device and storage medium

Technical Field

The present application relates to the technical field of instruction processing, and in particular to an instruction processing method, a chip, an electronic device and a storage medium.

Background technique

In the process of the central processing unit (CPU) executing instructions, it usually reads the instructions from the memory first and stores the instructions in the cache. When the instructions need to be executed again, it directly checks whether there are relevant instructions in the cache. If there are relevant instructions in the cache, that is, the instruction cache hits, the central processing unit can read the instructions directly from the cache. If there are no relevant instructions in the cache, that is, the instruction cache misses, the central processing unit needs to read the instructions from the memory again and store the instructions in the cache. In this way, in the case of an instruction cache miss, the processing efficiency of the central processing unit will be reduced.

Summary of the invention

In order to solve the problem that the processing efficiency of the central processing unit will be reduced when the instruction cache is missed, the embodiments of the present application provide an instruction processing method, a chip, an electronic device and a storage medium.

In a first aspect, an embodiment of the present application provides an instruction processing method, which is applied to an electronic device, wherein the electronic device includes a processor and a memory, and the processor includes a cache, the method comprising: detecting an execution instruction of a compilation unit, wherein the compilation unit includes a target instruction; based on the number of target instructions and the remaining storage space of the cache, determining the number of prefetch instructions of the corresponding compilation unit; reading the target instructions of the number of prefetch instructions from the instructions of the corresponding compilation unit stored in the memory, and storing them in the cache.

Based on the above scheme, the accuracy of the determined number of pre-fetch instructions can be improved, so that functions with an appropriate number of loading instructions can be stored in the cache to reduce instruction misses, thereby improving the processing efficiency of the processor.

It can be understood that the cache may refer to the target cache mentioned below. Different processors have different target caches. Since different processors have different hierarchical storage architectures, for example, a general-purpose memory may include a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), and a third-level cache (L3 I-cache). A dedicated memory (such as a GPU, an NPU, etc.) may include a primary cache (L0 I-cache) and a first-level cache (L1 I-cache). Therefore, in the process of executing instructions in a general-purpose memory, the target cache may be a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), and a third-level cache (L3 I-cache). In the process of executing instructions in a dedicated memory, the target cache may be a primary cache (L0 I-cache) and a first-level cache (L1 I-cache).

In some optional implementations of the first aspect, the target instruction includes a first instruction and a second instruction, the first instruction is an instruction of a first sub-function, the second instruction is an instruction of a first function and the first sub-function, wherein the first function calls the first sub-function, and the first sub-function is a sub-function that cannot be inlined.

In some optional implementations of the first aspect, the number of target instructions is determined in the following manner: inserting a first label group in a first sub-function, and inserting a second label group in a compilation unit, wherein the first label group and the second label group are different; based on the first label group, determining a first number of first instructions; based on the second label group, determining a second number of second instructions; based on the first number and the second number, determining the number of target instructions.

In some optional implementations of the first aspect, the first label group includes a first prefetch instruction and a first label, and inserting the first label group in the first sub-function includes: when compiling the first sub-function, inserting the first prefetch instruction at the function entry of the first sub-function, and inserting the first label at the function end of the first sub-function.

For example, a first prefetch instruction, such as "prefetch__func1_end", is inserted into the function entry of the first sub-function, and a first label, such as "__func1_end", is inserted into the function end of the first sub-function.

In some optional implementations of the first aspect, the second label group includes a second prefetch instruction and a second label, and inserting the second label group in the compilation unit includes: when compiling the compilation unit, adjusting the first function to the beginning of the compilation unit, inserting the second prefetch instruction at the function entry of the first function, and inserting the second label at the end of the compilation unit.

For example, a second prefetch instruction, such as "prefetch__dummy", is inserted into the function entry of the first function (i.e., the main function mentioned below), and a second label, such as "__dummy", is inserted into the end of the compilation unit. It can be understood that "__dummy" can be an empty function or a non-empty function, which is a sub-function that cannot be inlined.

In some optional implementations of the first aspect, the number of prefetched instructions is any one of a first number of first instructions or a second number of second instructions.

In some optional implementations of the first aspect, the number of prefetch instructions of the corresponding compilation unit is determined based on the number of target instructions and the remaining storage space of the cache, including: corresponding to the remaining storage space of the cache being greater than a second number, the number of prefetch instructions is determined according to the second number; or corresponding to the remaining storage space of the cache being less than or equal to the second number and greater than the first number, the number of prefetch instructions is determined according to the first number; or corresponding to the remaining storage space of the cache being less than the first number, the number of prefetch instructions is determined according to the remaining storage space of the cache.

In some optional implementations, if the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined can be used as the number of pre-fetched instructions. If the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is greater than the remaining storage space corresponding to the target cache, and the number of instructions of the sub-functions that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the number of instructions of the sub-functions that cannot be inlined can be used as the number of pre-fetched instructions. If the number of instructions of the sub-functions that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

In some optional implementations of the first aspect, a request to store in the cache may be split by hardware into N cache requests according to the size of data processed by the bus, and the N cache requests may include a first cache request and a second cache request; storing in the cache may include: sending a first cache request to the cache; before receiving a return result from the cache, sending a second cache request to the cache, and the instruction requested by the first cache request may be different from the instruction requested by the second cache request.

It can be understood that the first cache request and the second cache request, until the Nth cache request can form a pipeline.

It can be understood that for prefetch instructions, the hardware needs to form a pipeline for prefetch operations, that is, the hardware needs to execute prefetch instructions quickly, so as to improve the processing efficiency of the processor. Forming a pipeline for prefetch operations can mean, for example, that a prefetch instruction needs to prefetch 10 cache lines. When sending the first cache request to the target cache, the second cache request can be sent without waiting for the return result, and so on. In this way, compared with sending the second cache request after sending the first cache request and receiving the return result, the processing efficiency of the processor can be improved.

In a second aspect, an embodiment of the present application provides a chip comprising a processor and a memory, and the processor comprises a cache and a processing unit, the processing unit being used to read a target instruction of a pre-fetch instruction quantity from the instructions of the corresponding compilation unit stored in the memory, and store them in the cache, wherein the number of pre-fetch instructions is determined based on the number of target instructions and the remaining storage space of the cache.

In a third aspect, an embodiment of the present application provides an electronic device, including: the above-mentioned chip.

It can be understood that the chip may include a processor and a memory, and the processor includes a cache and a processing unit, the processing unit is used to read the target instructions of the pre-fetch instruction quantity from the instructions of the corresponding compilation unit stored in the memory, and store them in the cache, wherein the pre-fetch instruction quantity is determined based on the number of target instructions and the remaining storage space of the cache.

In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which instructions are stored. When the instructions are executed on an electronic device, the electronic device executes the above-mentioned instruction processing method.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing a computer structure according to some examples of the present application;

FIG2 is a schematic diagram showing a function of reading a number of prefetch instructions from a memory and storing it in a cache according to some examples of the present application;

FIG3 is a flow chart showing a method for processing instructions according to some examples of the present application;

FIG4 is a schematic diagram showing a main function after inserting a main tag at the function entry and inserting a sub-tag corresponding to the main tag at the end of the function according to some examples of the present application;

FIG5 is a schematic diagram showing a method of inserting a main label at a function entry and a sub-label corresponding to the main label at the end of a function, according to some examples of the present application;

FIG6 shows a schematic structural diagram of an electronic device according to some examples of the present application.

Detailed ways

The illustrative embodiments of the present application include but are not limited to an instruction processing method, a chip, an electronic device, and a storage medium.

It can be understood that the solutions mentioned in the embodiments of the present application can be applicable to any processor (central processing unit, CPU), such as a general-purpose processor, a graphics processing unit (graphic processing unit, GPU), a neural network processing unit (neural network processing unit, NPU), etc.

Before introducing the technical solution implemented in the present application, the professional terms involved in the embodiments of the present application are first explained.

(1) Function: A code segment that implements a specific function by combining multiple instructions. Functions can include main functions and sub-functions, where sub-functions can contain attributes such as inline and non-inline. Generally speaking, a program that can run on an operating system requires a main function. The main function means establishing an independent process, and this process is the program entry point to call other sub-functions. Inlineable sub-functions are usually defined using the modifier "inline". Non-inline functions are sub-functions that are not called frequently, that is, sub-functions that are not defined using the modifier "inline".

(2) Multi-level storage architecture: In computers, a multi-level storage architecture is usually used. Referring to the computer structure shown in FIG1 , the computer 100 may include a processor 110 and a memory 120, and the processor 110 may be provided with a cache 130 and a processing unit 140. The cache 130 may be a multi-level cache, such as a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), a third-level cache (L3 I-cache) ... an N-level cache (Ln I-cahce).

It can be understood that in some examples, the size of the storage space corresponding to the cache 130 is smaller than the size of the storage space corresponding to the memory 120, the size of the storage space corresponding to the primary cache is smaller than the size of the storage space corresponding to the first-level cache, the size of the storage space corresponding to the first-level cache is smaller than the size of the storage space corresponding to the second-level cache, and so on. In addition, since the cache 130 is in the processor 110, the distance between the processing unit 140 and the cache 130 is smaller than the distance between the processing unit 140 and the memory 120, and therefore, the speed at which the processing unit 140 reads instructions from the cache 130 is higher than the speed at which it reads instructions from the memory 120.

(3) Cache line: The smallest cache unit in cache 130 is called a cache line, and the size of a cache line can be determined based on the size of cache 130. For example, if the size of cache 130 is 64 bytes, cache 130 can be evenly divided into 8 cache lines of 8 bytes, or cache 130 can be evenly divided into 16 cache lines of 4 bytes. In practical applications, the size of a cache line is usually between 4 bytes and 128 bytes, such as 4 bytes, 8 bytes, 16 bytes, 64 bytes, 128 bytes, etc.

(4) Inlineable sub-functions: Usually, inlineable sub-functions can be defined using the modifier "inline".

When the processor 110 needs to execute an instruction, it will first check whether there is a related instruction in the cache 130. For example, it will first check whether there is a related instruction in the primary cache. If there is no related instruction in the primary cache, it can check whether there is a related instruction in the first-level cache. If there is no related instruction in the first-level cache, it will check whether there is a related instruction in the second-level cache. If there is no related instruction in the second-level cache, it will check whether there is a related instruction in the third-level cache, and so on.

If there are relevant instructions in the cache 130, that is, an instruction cache hit, the processor 110 can directly read the instructions from the cache 130. If there are no relevant instructions in the cache 130, that is, an instruction cache miss, the processor 110 can read the instructions from the memory 120. Since the distance between the cache 130 and the processor 110 is smaller than the distance between the memory 120 and the processor 110, the speed at which the processor 110 accesses the cache 130 is higher than the speed at which the processor 110 accesses the memory 120. In this way, in the case of an instruction cache miss, the processing efficiency of the processor 110 will be reduced.

In general, an instruction prefetch mechanism can be used to alleviate instruction missing. For example, by analyzing the law of instruction execution by the processor 110, the instructions of the preset number of bytes or preset cache lines that may need to be executed again are stored in the cache 130 in advance. However, when the preset number of bytes or the preset cache lines are set to be large, due to the small size of the storage space corresponding to the cache 130, it may not be possible to store all the prefetched instructions in the cache 130. When the preset number of bytes or the preset cache lines are set to be small, the instructions obtained may not be enough to alleviate the situation of instruction missing. Therefore, it can be understood that the existing instruction prefetch mechanism cannot accurately determine the instruction number of the prefetched instructions.

In order to solve the above problems, the embodiment of the present application provides an instruction processing method. In this method, since the compiler will automatically embed the frequently called inline sub-functions into the main function during the compilation process, the first prefetch instruction can be inserted into the function entry of the sub-function that cannot be inlined, and the first label corresponding to the first prefetch instruction can be inserted at the end of the function of the sub-function that cannot be inlined, and the second prefetch instruction can be inserted into the function entry of the main function adjusted to the beginning of the compilation unit, and the second label corresponding to the second prefetch instruction can be inserted at the end of the compilation unit. Based on the first prefetch instruction, the first label, the second prefetch instruction and the second label, the number of instructions of the sub-function and the compilation unit that cannot be inlined is determined respectively, and the number of instructions of the sub-function and the compilation unit that cannot be inlined and the size of the storage space corresponding to the target cache in the multi-level cache is determined. During the operation process, based on the execution time sequence of the function and the number of prefetch instructions, the function of the number of prefetch instructions is read from the memory and stored in the cache. In this way, the accuracy of the determined number of prefetch instructions can be improved, so that the function with the appropriate number of loading instructions can be stored in the cache to reduce the situation of instruction missing, and then the processing efficiency of the processor can be improved.

In some specific implementations, the main function may be referred to as a first function, the sub-function that cannot be inlined may be referred to as a first sub-function, and the instructions of the main function and the instructions of the sub-function that cannot be inlined may be collectively referred to as target instructions.

In some specific implementations, during the linking process, if the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined can be used as the number of pre-fetched instructions. If the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

If the number of instructions of the sub-function that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the number of instructions of the sub-function that cannot be inlined can be used as the number of pre-fetched instructions. If the number of instructions of the sub-function that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

It is understandable that different processors have different target caches. Since different processors have different hierarchical storage architectures, for example, a general-purpose memory may include a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), and a third-level cache (L3 I-cache). A dedicated memory (such as a GPU, an NPU, etc.) may include a primary cache (L0 I-cache) and a first-level cache (L1 I-cache). Therefore, in the process of executing instructions in a general-purpose memory, the target cache may be a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), and a third-level cache (L3 I-cache). In the process of executing instructions in a dedicated memory, the target cache may be a primary cache (L0 I-cache) and a first-level cache (L1 I-cache).

In some specific implementations, as shown in FIG2 , a schematic diagram of a function of reading the number of pre-fetched instructions from the memory and storing it in the cache is shown. If the execution order of multiple functions in the memory 120 is to execute function 1, function 2 ... function n in sequence, wherein the execution time sequence of function 1 takes precedence over the execution time sequence of function 2, and function 2 includes instruction 1, instruction 2, and instruction 3, the storage space corresponding to the primary cache in the cache 130 is greater than the instruction number of instruction 1, and less than the sum of the instruction numbers of instruction 1, instruction 2, and instruction 3, and the storage space corresponding to the first-level cache in the cache 130 is greater than the sum of the instruction numbers of instruction 1, instruction 2, and instruction 3.

When function 1 is executed and function 2 is executed, instruction 1, instruction 2 and instruction 3 can be read from memory 120 and stored in the first-level cache of cache 130. In addition, instruction 1 can also be read from memory 120A and stored in the primary cache of cache 130.

It can be understood that for frequently called sub-functions, if the inline attribute is set, the compiler will automatically embed the sub-function into the main function during the compilation process, which can reduce the function call overhead and improve the processor processing efficiency.

The instruction processing method mentioned in the embodiment of the present application is introduced below. FIG3 shows a flowchart of an instruction processing method. As shown in FIG3, the instruction processing method may include:

301: When an execution instruction of a compilation unit is detected, the number of pre-fetch instructions of the corresponding compilation unit is determined according to the number of target instructions in the compilation unit and the remaining storage space of the cache.

It can be understood that the target instructions may include instructions of the main function and instructions of the sub-function that cannot be inlined.

In some optional instances, since the compiler will automatically embed frequently called inlineable sub-functions into the main function during the compilation process, a first prefetch instruction, such as "prefetch__func1_end", can be inserted at the function entry of the non-inlineable sub-function, and a first label, such as "__func1_end", can be inserted at the function end of the non-inlineable sub-function. In this way, the number of instructions in the non-inlineable sub-function, i.e., the first number, can be determined based on the first prefetch instruction and the first label.

Furthermore, the compiler may first traverse all functions in the compilation unit, identify the main function in the compilation unit through features, and adjust the main function to the beginning of the compilation unit, and then insert a second prefetch instruction, such as "prefetch__dummy", at the function entry of the main function, and insert a second label, such as "__dummy", at the end of the compilation unit. In this way, the number of instructions in the compilation unit, i.e., the second number, may be determined based on the second prefetch instruction and the second label.

Thus, the number of target instructions may be determined based on the first number and the second number.

302: Read target instructions of the pre-fetched instruction quantity from the instructions of the corresponding compilation unit stored in the memory, and store them in the cache.

In some optional instances, when the remaining storage space of the cache is greater than the second number, the number of prefetch instructions is determined based on the second candidate number.

In some optional instances, when the remaining storage space of the cache is less than or equal to the second quantity and greater than the first quantity, the number of prefetch instructions is determined based on the first quantity.

In some optional instances, when the remaining storage space of the cache is less than the first candidate quantity, the number of pre-fetch instructions is determined according to the remaining storage space of the cache.

Based on the embodiments of the present application, the accuracy of the determined number of pre-fetch instructions can be improved, so that functions with an appropriate number of loading instructions can be stored in the cache to reduce instruction missing situations, thereby improving the processing efficiency of the processor.

It is understood that the process in which the compiler translates the source file into an executable file may include a compile phase and a link phase. After the link is completed, the run phase may be entered, i.e. the executable file may be executed to implement the functions of the software in the executable file.

During the compilation phase, the compiler can automatically insert the prefetch instruction provided by the hardware at the function entry of the sub-function that cannot be inlined, and insert a label at the end of the function of the sub-function that cannot be inlined. The prefetch instruction can include information such as the opcode, offset, cache type, and cache length.

For example, a prefetch instruction with a length of 32 bits may be in the following form:

prefetch|opcode|offest|mode|size|

Among them, opcode can represent the operation code, offest can represent the offset, and mode can represent the cache type (i.e., the target cache mentioned above). For example, if mode is 2 bits, such as mode is b00-b11, the four codes b00-b11 can represent the primary cache (L0 I-cache), the first-level cache (L1 I-cache), the second-level cache (L2 I-cache), and the third-level cache (L3 I-cache), among which 00 can represent the primary cache (L0 I-cache), 01 can represent the first-level cache (L1 I-cache), 10 can represent the second-level cache (L2I-cache), and 11 can represent the third-level cache (L3 I-cache). Size can represent the length of the prefetch instruction, or the number of cache lines, wherein the length of the prefetch instruction and the number of cache lines can be the number of prefetch instructions mentioned above.

During the compilation phase, the compiler first traverses all functions in the compilation unit, identifies the main function in the compilation unit through features, and adjusts the main function to the beginning of the compilation unit. Main function features include but are not limited to: main function, functions modified by kernel modifier, etc.

During the compilation phase, the compiler may insert a prefetch instruction provided by the hardware, namely, the first prefetch instruction, at the function entry of all sub-functions that cannot be inlined, and insert a label, namely, the first label corresponding to the first prefetch instruction, at the function end of each sub-function that cannot be inlined.

During the compilation phase, the compiler may insert a second prefetch instruction, such as "prefetch__dummy", at the function entry of the main function that is automatically adjusted to the beginning of the compilation unit, and insert an empty function, such as "__dummy", at the end of the compilation unit (i.e., a unit formed by the main function and the non-inline function). It is understood that the empty function may be an empty function or a non-empty function, which is a sub-function that cannot be inlined.

In the linking stage, the compiler can determine the number of pre-fetched instructions based on the number of instructions of the sub-functions and compilation units that cannot be inlined and the size of the storage space corresponding to the target cache in the multi-level cache. Then, in the running stage, the executable file can be loaded into the memory 120 and jump to the first instruction to start running.

In some optional examples, if the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined can be used as the number of pre-fetched instructions. If the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

If the number of instructions of the sub-function that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the number of instructions of the sub-function that cannot be inlined can be used as the number of pre-fetched instructions. If the number of instructions of the sub-function that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

In the running stage, based on the execution time sequence of the function and the number of pre-fetched instructions, the function with the number of pre-fetched instructions can be read from the memory 120 and stored in the cache 130. In this way, the accuracy of the determined number of pre-fetched instructions can be improved, so that the function with the appropriate number of loading instructions can be stored in the cache to reduce the situation of instruction missing, thereby improving the processing efficiency of the processor 110.

The following describes the automatic insertion of the second prefetch instruction at the entry of the compilation unit (ie, the unit formed by the main function and the non-inlineable function) and the insertion of the second label at the end of the compilation unit.

In some specific implementations, as shown in FIG4 , a pseudo code is shown for inserting a second prefetch instruction at the function entry of the main function adjusted to the beginning of the compilation unit, and inserting a second label at the end of the compilation unit. The second prefetch instruction may be "prefetch__dummy" and the second label may be "__dummy". "__dummy" may be an empty function. In this way, the functions of the entire compilation unit may be rearranged, with the main function placed at the front and the empty function inserted by the compiler placed at the back, generating a final function sorting order of main-func1-func2-dummy.

It can be understood that, for the main function shown in FIG. 4 , bl may represent a function call instruction, that is, the main function calls func1 and func2.

It can be understood that the main function may include a main function, a kernel function in OpenCL, a kernel function in CUDA, etc., and the embodiment of the present application does not make specific limitations.

The following describes how to insert a prefetch instruction provided by the hardware into the function entry of a sub-function that cannot be inlined, and how to insert a label into the function end of a sub-function that cannot be inlined.

In some specific implementations, as shown in FIG5 , a pseudo code for inserting a prefetch instruction at the function entry of a sub-function that cannot be inlined and inserting a label at the function end of the sub-function that cannot be inlined is shown, wherein the main label may be “prefetch__func1_end” and the label may be “__func1_end”.

It can be understood that in the linking stage, the length of the prefetch instruction can be obtained based on the distance between the prefetch instruction and the tag, or it can be converted into the number of cache lines, where the length of the prefetch instruction and the number of cache lines can be the number of prefetch instructions mentioned above.

In some optional examples, if the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined can be used as the number of pre-fetched instructions. If the sum of the number of instructions of the main function and the number of instructions of the sub-functions that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

If the number of instructions of the sub-function that cannot be inlined is less than or equal to the remaining storage space corresponding to the target cache, the number of instructions of the sub-function that cannot be inlined can be used as the number of pre-fetched instructions. If the number of instructions of the sub-function that cannot be inlined is greater than the remaining storage space corresponding to the target cache, the size of the storage space corresponding to the target cache can be used as the number of pre-fetched instructions.

It can be understood that the prefetch instructions "prefetch__dummy", "prefetch__func1_end", and labels "__dummy", "__func1_end" listed in the embodiments of the present application are only some examples and do not represent all examples.

It can be understood that for prefetch instructions, the hardware needs to form a pipeline for prefetch operations, that is, the hardware needs to execute prefetch instructions quickly, so as to improve the processing efficiency of the processor. Forming a pipeline for prefetch operations can mean, for example, that a prefetch instruction needs to prefetch 10 cache lines. When sending the first cache request to the target cache, the second cache request can be sent without waiting for the return result, and so on. The instructions requested by the first cache request and the instructions requested by the second cache request are different. In this way, compared with sending the second cache request after sending the first cache request and receiving the return result, the processing efficiency of the processor can be improved.

In an embodiment of the present application, by determining the number of prefetch instructions based on the main tag and the sub-tag corresponding to the main tag, the accuracy of the determined number of prefetch instructions can be improved, so that a function with a suitable number of loading instructions can be stored in the cache. For example, the entire function to be executed can be read at one time and stored in the cache to reduce the situation of missing instructions, thereby improving the processing efficiency of the processor. In addition, by setting an offset in the prefetch instruction, prefetching can be started a certain distance forward or backward, and the mechanism of the hardware general cache can be reused. Moreover, by completing instruction prefetching during the compilation process by the compiler, user-unaware prefetching can be achieved, improving the convenience of programming.

It is understandable that the instruction processing method mentioned in the embodiment of the present application can be applied to electronic devices, and the hardware structure of the electronic device is introduced below. The hardware structure of the electronic device is introduced below. As shown in Figure 6, Figure 6 shows a schematic diagram of the hardware structure of an electronic device. It is understandable that the electronic device of the present application can be an electronic device, a desktop computer (desktop computer), a handheld computer, a notebook computer (laptop) and other electronic devices. The structure of the electronic device is introduced below by taking the electronic device as an example of an electronic device.

In one embodiment, the electronic device may include one or more processors 601, a system control logic 602 connected to at least one of the processors 601, a system memory 603 connected to the system control logic 602, a non-volatile memory (NVM) 604 connected to the system control logic 602, and an input/output (I/O) device 605 and a network interface 606 connected to the system control logic 602.

In some embodiments, the processor 601 may include one or more single-core or multi-core processors. In some embodiments, the processor 601 may include any combination of a general-purpose processor and a dedicated processor (e.g., a graphics processor, an application processor, a baseband processor, etc.). In an embodiment where the electronic device uses an eNB (Evolved Node B, enhanced base station) or a RAN (Radio Access Network, wireless access network) controller, the processor 601 may be configured to execute various compliant embodiments.

In some examples, a cache 607 may be provided in the processor 601. The cache 607 may be a multi-level cache, such as a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache), a third-level cache (L3 I-cache) ... N-level cache (Ln I-cahce). For example, a primary cache (L0 I-cache), a first-level cache (L1 I-cache), a second-level cache (L2 I-cache) and a third-level cache (L3 I-cache) may be provided in a general memory. A primary cache (L0 I-cache) and a first-level cache (L1 I-cache) may be provided in a dedicated memory.

In some embodiments, system control logic 602 may include any suitable interface controller to provide any suitable interface to at least one of processors 601 and/or any suitable device or component in communication with system control logic 602 .

In some embodiments, the system control logic 602 may include one or more memory controllers to provide an interface to the system memory 603. The system memory 603 may be used to load and store data and/or instructions 6031. In some embodiments, the memory of the electronic device may include any suitable volatile memory, such as a suitable dynamic random access memory (DRAM).

The non-volatile memory (NVM) 604 may include one or more tangible, non-transitory computer-readable media for storing data and/or instructions. In some embodiments, the non-volatile memory (NVM) 604 may include any suitable non-volatile memory such as flash memory and/or any suitable non-volatile storage device, such as at least one of a HDD (Hard Disk Drive), a CD (Compact Disc) drive, and a DVD (Digital Versatile Disc) drive.

The non-volatile memory (NVM) 604 may include a portion of storage resources on a device on which the electronic device is installed, or it may be accessible by the device but is not necessarily a portion of the device. For example, the non-volatile memory (NVM) 604 may be accessed over a network via the network interface 606 .

In particular, the system memory 603 and the non-volatile memory (NVM) 604 may include: a temporary copy and a permanent copy of the instruction, respectively. The instruction may include: an instruction that causes the electronic device to implement the instruction processing method mentioned in the embodiment of the present application when executed by at least one of the processors 601. In some embodiments, the instruction, hardware, firmware and/or its software components may be placed in the system control logic 602, the network interface 606 and/or the processor 601 in addition or alternatively.

The network interface 606 may include a transceiver for providing a radio interface for the electronic device, and then communicating with any other suitable device (such as a front-end module, an antenna, etc.) through one or more networks. In some embodiments, the network interface 606 can be integrated with other components of the electronic device. For example, the network interface 606 can be integrated with at least one of the processor 601, the system memory 603, the non-volatile memory (NVM) 604, and a firmware device (not shown) with instructions. When at least one of the processors 601 executes the instructions, the electronic device implements the instruction processing method mentioned in the embodiments of the present application.

The network interface 606 may further include any suitable hardware and/or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 606 may be a network adapter, a wireless network adapter, a telephone modem and/or a wireless modem.

In one embodiment, at least one of the processors 601 may be packaged together with logic for one or more controllers of the system control logic 602 to form a system in package (SiP). In one embodiment, at least one of the processors 601 may be integrated on the same die with logic for one or more controllers of the system control logic 602 to form a system on chip (SoC).

The electronic device may further include: an input/output (I/O) device 605. The I/O device 605 may include a user interface to enable a user to interact with the electronic device; the design of the peripheral component interface enables the peripheral component to also interact with the electronic device. In some embodiments, the electronic device further includes a sensor for determining at least one of an environmental condition and location information related to the electronic device.

In some embodiments, the user interface may include, but is not limited to, a display (e.g., an LCD display, a touch screen display, etc.), a speaker, a microphone, one or more cameras (e.g., a still image camera and/or a video camera), a flashlight (e.g., an LED flash), and a keyboard.

In some embodiments, the peripheral component interface may include, but is not limited to, a non-volatile memory port, an audio jack, and a power interface.

In some embodiments, the sensors may include, but are not limited to, gyroscope sensors, accelerometers, proximity sensors, ambient light sensors, and positioning units. The positioning unit may also be part of or interact with the network interface 606 to communicate with components of a positioning network (e.g., global positioning system (GPS) satellites).

The above describes the hardware structure that the electronic device may have. It is understood that the structure illustrated in the embodiments of the present application does not constitute a specific limitation on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

In the accompanying drawings, some structural or method features may be shown in a specific arrangement and/or order. However, it should be understood that such a specific arrangement and/or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and/or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

The embodiments disclosed in the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application may be implemented as a computer program or program code executed on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.

Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit, or a microprocessor.

Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

It should be noted that the units/modules mentioned in the various device embodiments of the present application are all logical units/modules. Physically, a logical unit/module can be a physical unit/module, or a part of a physical unit/module, or can be implemented as a combination of multiple physical units/modules. The physical implementation method of these logical units/modules themselves is not the most important. The combination of functions implemented by these logical units/modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units/modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units/modules in the above-mentioned device embodiments.

It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Although the present application has been illustrated and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the present application.

Claims (11)

1. An instruction processing method, applied to an electronic device, wherein the electronic device comprises a processor and a memory, and the processor comprises a cache, wherein the method comprises: detecting an execution instruction of a compilation unit, wherein the compilation unit includes a target instruction; Determining the number of prefetch instructions corresponding to the compilation unit based on the number of the target instructions and the remaining storage space of the cache; The target instructions of the pre-fetched instruction quantity are read from the instructions corresponding to the compilation unit stored in the memory, and stored in the cache. 2. The method according to claim 1, wherein the target instruction comprises a first instruction and a second instruction, The first instruction is an instruction of a first sub-function, and the second instruction is an instruction of a first function and the first sub-function. The first function calls the first sub-function, and the first sub-function is a sub-function that cannot be inlined. 3. The method according to claim 2, characterized in that the number of the target instructions is determined by: Inserting a first label group into the first sub-function, and inserting a second label group into the compilation unit, wherein the first label group and the second label group are different; Based on the first tag group, determining a first quantity of the first instructions; Based on the second tag group, determining a second number of the second instructions; Based on the first number and the second number, the number of the target instructions is determined. 4. The method according to claim 3, wherein the first tag group includes a first prefetch instruction and a first tag, The inserting the first tag group into the first sub-function comprises: When compiling the first sub-function, the first prefetch instruction is inserted into the function entry of the first sub-function, and the first label is inserted into the function end of the first sub-function. 5. The method according to claim 3, wherein the second tag group includes a second prefetch instruction and a second tag, The inserting the second tag group into the compilation unit comprises: When compiling the compilation unit, the first function is adjusted to the beginning of the compilation unit, the second prefetch instruction is inserted at the function entry of the first function, and the second label is inserted at the end of the compilation unit. 6 . The method according to claim 2 , wherein the number of pre-fetched instructions is any one of a first number of the first instructions or a second number of the second instructions. 7. The method according to claim 6, wherein determining the number of prefetch instructions corresponding to the compilation unit based on the number of the target instructions and the remaining storage space of the cache comprises: Corresponding to the remaining storage space of the cache being greater than the second number, the number of prefetch instructions is determined according to the second number; or The remaining storage space corresponding to the cache is less than or equal to the second number and greater than the first number, and the number of prefetch instructions is determined according to the first number; or Corresponding to the remaining storage space of the cache being less than the first number, the number of pre-fetch instructions is determined according to the remaining storage space of the cache. 8. The method according to any one of claims 1 to 7, characterized in that the request stored in the cache is split into N cache requests by hardware according to the bus processing data size, and the N cache requests include a first cache request and a second cache request; The storing in the cache comprises: Sending the first cache request to the cache; Before receiving the return result of the cache, the second cache request is sent to the cache, and the instruction requested by the first cache request is different from the instruction requested by the second cache request. 9. A chip, comprising a processor and a memory, wherein the processor comprises a cache and a processing unit, wherein: The processing unit is used to read target instructions of the pre-fetched instruction quantity from the instructions of the corresponding compilation unit stored in the memory, and store them in the cache, wherein The number of pre-fetched instructions is determined based on the number of target instructions and the remaining storage space of the cache. 10. An electronic device, comprising: the chip according to claim 9. 11. A readable storage medium, characterized in that instructions are stored on the readable storage medium, and when the instructions are executed on an electronic device, the electronic device executes the instruction processing method according to any one of claims 1 to 8.