CN118295859A - Chip peripheral interface testing device - Google Patents
Chip peripheral interface testing device Download PDFInfo
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- CN118295859A CN118295859A CN202311608666.0A CN202311608666A CN118295859A CN 118295859 A CN118295859 A CN 118295859A CN 202311608666 A CN202311608666 A CN 202311608666A CN 118295859 A CN118295859 A CN 118295859A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2268—Logging of test results
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- General Physics & Mathematics (AREA)
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Abstract
The invention provides a chip peripheral interface testing device, which comprises: the chip to be tested comprises a plurality of peripheral interfaces; the test chip comprises a plurality of peripheral interfaces, wherein the peripheral interfaces of the tested chip are respectively connected with peripheral interfaces of corresponding types of the test chip, the test chip is used as a plurality of peripheral devices connected with the peripheral interfaces of the tested chip, and the peripheral interfaces of the tested chip are tested. In this way, the cost of peripheral circuit construction and testing can be reduced.
Description
[ Field of technology ]
The invention relates to the field of chip design, in particular to a chip peripheral interface testing device.
[ Background Art ]
When testing the peripheral (i.e., external device) interface of the newly designed chip, a peripheral is required to be matched for each peripheral interface, for example, an I2C interface is matched with an EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, electrically erasable programmable read-only memory), and an ETH (Ethernet) interface is matched with a network and an upper computer for interconnection test.
As shown in fig. 1, it is a structural diagram of a conventional chip peripheral interface test device. As shown in fig. 1, one peripheral circuit is matched for each peripheral interface of a newly designed chip running an own program test. For the peripheral A (such as the matched peripheral of the I2C interface), the chip communicates with the peripheral A, the self-program test determines a test result according to the communication data, and the test result can be locally or printed in the serial terminal. For the peripheral equipment N (such as the matching peripheral equipment of the ETH interface), the chip is communicated with the peripheral equipment N, the peripheral equipment N can communicate with an upper computer, and the result is stored in the upper computer or is judged manually through other instruments.
First, all peripheral interfaces need to match peripheral circuits, which requires more board-level resources and is more complex. In addition, the corresponding test results are scattered in different places and different channels, and are difficult to arrange and inquire. Especially, batch and aging tests are troublesome in test result data arrangement. In addition, the manual operation and the confirmation of the test result are more, and particularly, when the aging and batch test are involved, the workload is very large, and the data arrangement of the test result is difficult.
Therefore, a new solution is needed to solve the above problems.
[ Invention ]
One of the objectives of the present invention is to provide a chip peripheral interface testing device, which can reduce the cost of peripheral circuit construction and testing.
According to one aspect of the present invention, there is provided a chip peripheral interface test apparatus comprising: the chip to be tested comprises a plurality of peripheral interfaces; the test chip comprises a plurality of peripheral interfaces, wherein the peripheral interfaces of the tested chip are respectively connected with peripheral interfaces of corresponding types of the test chip, the test chip is used as a plurality of peripheral devices connected with the peripheral interfaces of the tested chip, and the peripheral interfaces of the tested chip are tested.
In a further embodiment, the chip peripheral interface test apparatus further includes: peripheral circuits of the chip to be tested; testing peripheral circuits of the chip; the memory is connected with the test chip and used for storing test results; and the test control end is connected with the test chip and used for controlling the test chip to start and stop testing, and the test chip is a verified chip which can be used.
In a further embodiment, a test program is set in the test chip, the test control end controls the test chip to start the test program, the test chip tests a plurality of peripheral interfaces of the tested chip in turn according to the test program, and test results of each peripheral interface are sent to the memory or/and the test control end.
In a further embodiment, the test control end outputs a single-step control instruction to the test chip, and controls the test program in the test chip to perform a single-step test on the peripheral interface.
In a further embodiment, the chip under test includes a communication interface, the test chip includes a communication interface, the communication interface of the test chip is connected with the communication interface of the chip under test, and the test chip informs the peripheral interface of the chip under test that needs to be tested currently through the communication interface.
In a further embodiment, when testing a peripheral interface of the chip under test, the test chip performs data interaction with the peripheral interface under test of the chip under test according to the test program, the test program determines a test result based on the interaction data, and sends the test result to the memory and/or the test control terminal.
In a further embodiment, the peripheral interface of the tested chip includes an I2C interface and an ETH interface, the peripheral interface of the tested chip also includes an I2C interface and an ETH interface, the I2C interface of the tested chip is connected with the I2C interface of the tested chip, the ETH interface of the tested chip is connected with the ETH interface of the tested chip, the communication interface of the tested chip is a UART interface, and the UART interface of the tested chip is connected with the UART interface of the tested chip.
In a further embodiment, the test chip informs the tested chip to perform an I2C interface test through a UART interface, the I2C interface of the test chip and the I2C interface of the tested chip perform data interaction according to the test program, the test program determines a test result based on interaction data and sends the test result to the memory and/or the test control end, the test chip informs the tested chip to perform an ETH interface test through the UART interface, the ETH interface of the test chip and the ETH interface of the tested chip perform data interaction according to the test program, the test program determines the test result based on interaction data and sends the test result to the memory and/or the test control end.
In a further embodiment, a master-slave mode of the test chip and the chip under test is established when testing the I2C interface of the chip under test.
Compared with the prior art, the invention uses the verified usable test chip as a plurality of peripheral devices connected with a plurality of peripheral device interfaces of the tested chip to test the plurality of peripheral device interfaces of the tested chip, thereby reducing the construction and test cost of peripheral circuits.
[ Description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a block diagram of a conventional chip peripheral interface test apparatus;
FIG. 2 is a block diagram of a chip peripheral interface test apparatus in accordance with one embodiment of the present invention;
fig. 3 is a schematic diagram of a testing principle of the chip peripheral interface testing device in the present invention.
[ Detailed description ] of the invention
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless specifically stated otherwise, the terms coupled, connected, or connected, as used herein, mean either direct or indirect connection, such as a and B, and include both direct electrical connection of a and B, and connection of a to B through electrical components or circuitry.
In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
The invention provides a chip peripheral interface testing device, which tests a plurality of peripheral interfaces of a tested chip by taking a verified chip capable of being used as a plurality of peripheral interfaces connected with the peripheral interfaces of the tested chip, so that the construction and testing cost of a peripheral circuit can be reduced.
FIG. 2 is a block diagram of a chip peripheral interface test apparatus in accordance with one embodiment of the present invention; fig. 3 is a schematic diagram of a testing principle of the chip peripheral interface testing device in the present invention. As shown in fig. 2-3, the chip peripheral interface test apparatus includes a chip under test 110, a test chip 120, a memory 130, and a test control terminal 140.
The chip under test 110 is a newly designed chip, which needs to be tested, and may also be referred to as a chip under test. The chip under test 110 includes a communication interface and a plurality of peripheral interfaces. The peripheral interfaces may be peripheral interfaces a-N. The peripheral interface of the chip under test 110 needs to be tested.
The test chip 120 is a validated usable chip such as a mature MCU (e.g., STM 32) that has been marketed. The well-established MCU (micro control unit) typically includes various peripheral interfaces, such as UART (Universal Asynchronous Receiver/transceiver) interface, I2C interface, I2S interface, SPI (serial peripheral interface ), QSPI (Quad SPI) interface, ETH interface, SD (Secure Digital) interface, and the like. The mature MCU is thus well suited for testing the chip under test 110. In the present invention, the test chip 120 also includes a communication interface and a plurality of peripheral interfaces. The peripheral interfaces may be peripheral interfaces a-N.
The plurality of peripheral interfaces of the chip under test 110 are respectively connected with the peripheral interfaces of the corresponding types of the test chip 120. Specifically, the peripheral interface a of the chip under test 110 is connected to the peripheral interface a of the test chip 120. The peripheral interface N of the chip under test 110 is connected to the peripheral interface N of the test chip 120.
In one example, the peripheral interfaces of the chip under test 110 include an I2C interface and an ETH interface, and the peripheral interfaces of the test chip 120 also include an I2C interface and an ETH interface. The communication interface of the tested chip 110 is a UART interface, and the communication interface of the test chip 120 is a UART interface. The I2C interface of the tested chip 110 is connected to the I2C interface of the test chip 120, the ETH interface of the tested chip 110 is connected to the ETH interface of the test chip 120, and the UART interface of the tested chip 110 is connected to the UART interface of the test chip 120.
In the present invention, the test chip 120 is used as a plurality of peripherals connected to a plurality of peripheral interfaces of the chip under test 110, and the plurality of peripheral interfaces of the chip under test 110 are tested. The test chip 120 informs the peripheral interface to be tested of the tested chip 110 through the communication interface. In this way, the plurality of peripheral interfaces of the chip under test 110 may be tested sequentially.
The memory 130 is connected to the test chip 120. The test control terminal 140 is connected to the test chip 120. The test control terminal 140 may be a PC (personal computer) control terminal, and the test control terminal 140 may be integrated with the memory 130 or may be separately provided. The memory 130 may be used to store test results. The test control terminal 140 may control the test chip 120 to start and terminate a test, and may also be used to store and display the test result.
The chip peripheral interface test device further comprises: peripheral circuitry of the chip under test 110; the peripheral circuits of the chip 120 are tested. The peripheral circuits may include circuits such as a power supply to ensure that the chip under test 110 and the test chip 120 operate normally.
In one embodiment, a test program is set in the test chip 120, the test control end 140 controls the test chip 120 to start the test program, the test chip 120 sequentially tests a plurality of peripheral interfaces of the tested chip 110 according to the test program, and sends a test result of each peripheral interface to the memory 130 or/and the test control end 140. After the test of one peripheral interface of the tested chip 110 is completed, the test of the next peripheral interface of the tested chip 110 is automatically started, and no engineer is needed to participate in the test process of each peripheral interface of the tested chip 110, so that the whole test process does not need to be manually participated, the time of the engineer is greatly saved, and the full-automatic test of a plurality of peripheral interfaces of the tested chip 110 can be realized.
In another example, as shown in fig. 3, the test control terminal may output a single-step control instruction to the test chip 120, and control the test program in the test chip 120 to perform a single-step test on the peripheral interface, so that the peripheral interface may be subjected to a fine test to understand each step of the test.
In one embodiment, when testing one peripheral interface of the tested chip 110, the test chip 120 performs data interaction with the tested peripheral interface of the tested chip 110 according to the test program, and the test program determines a test result based on the interaction data and sends the test result to the memory 130 and/or the test control terminal 140.
Since the present invention uses the test chip 120 that has been put into use as the peripheral of the chip under test 110 to test the peripheral interfaces of the chip under test 110, and the test chip 120 has multiple peripheral interfaces of the same type as the chip under test 110, there is no need to build multiple different peripheral circuits as in the prior art, and there is no need to collect test results from multiple devices, so that the cost of peripheral circuit building and testing can be greatly reduced. The test results are stored in the memory 130 and/or the test control terminal 140 in a unified manner, which facilitates subsequent queries. Particularly, when the aging and batch test of the tested chips are performed, an unattended mode can be realized.
In a specific test example, the test chip 120 informs the tested chip 110 to perform an I2C interface test through a UART interface, the I2C interface of the test chip 120 and the I2C interface of the tested chip 110 perform data interaction according to the test program, and the test program determines a test result based on the interaction data and sends the test result to the memory 130 and/or the test control terminal 140. The test chip 120 informs the tested chip 110 to perform an ETH interface test through a UART interface, the ETH interface of the test chip 120 and the ETH interface of the tested chip 110 perform data interaction according to the test program, the test program determines a test result based on the interaction data, and sends the test result to the memory 130 and/or the test control end 140.
Specifically, when testing the I2C interface of the chip under test 110, a master-slave mode of the test chip 120 and the chip under test 110 is defined, for example, the test chip 120 is defined as a master device, and the chip under test 110 is defined as a slave device. After the test chip 120 sends a string of data through the I2C interface, the tested chip 110 receives and parses the string of data, and then sends parsed data back to the test chip 120 through the communication interface, the test chip 120 compares the sent string of data with the received parsed data, if the string of data is consistent with the received parsed data, the test is considered to be successful, otherwise, the test fails, a test result is sent to the memory 130 and/or the test control end 140, and the test result may include the sent string of data, the received parsed data and the comparison result. And otherwise, the test chip 120 is agreed to be a slave device, the tested chip 110 is a master device, the tested chip 110 sends a series of predetermined data through the I2C interface, the test chip 120 analyzes the received data, compares the analyzed data with the predetermined data, judges whether the test is successful, and sends the test result to the memory 130 and/or the test control end 140. The scene can be interacted and tested for multiple times according to different peripheral interfaces and testing requirements, and different conditions are built in a testing program without manual operation.
Taking the ETH interface test as an example, the ETH interface of the tested chip 110 and the ETH interface of the test chip 120 are directly interconnected, and the two parties send packets to each other, and confirm whether the data is correct, and the test result is output to the memory 130 and/or the test control end 140 by the test chip 120.
In the present invention, the test chip 120 may be fully automated unless the test control terminal has a single step test instruction or terminates an automated test instruction.
In the present invention, the test chip 120 may output the test result of each step to the memory 130 and/or the test control terminal 140. The user can find out where the problem has occurred by retrieving the log keywords, such as TEST FAILED. The labor saving is particularly obvious in the scenes of batch test and aging test.
The invention has the following advantages: 1) The automation program is higher, so that the labor cost of manual operation is reduced; 2) The test results are all on the same terminal, so that the search and arrangement are convenient; 3) The test system is suitable for batch test and aging test, and can be unattended; 4) The peripheral interface of the tested chip is automatically tested by utilizing the mature chip, so that the construction and testing cost of a peripheral circuit is reduced.
It should be noted that any modifications to the specific embodiments of the invention may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims. Accordingly, the scope of the claims of the present invention is not limited to the foregoing detailed description.
Claims (9)
1. A chip peripheral interface test device, comprising:
the chip to be tested comprises a plurality of peripheral interfaces;
The test chip comprises a plurality of peripheral interfaces, wherein the peripheral interfaces of the tested chip are respectively connected with peripheral interfaces of corresponding types of the test chip, the test chip is used as a plurality of peripheral devices connected with the peripheral interfaces of the tested chip, and the peripheral interfaces of the tested chip are tested.
2. The chip peripheral interface test device according to claim 1, further comprising:
Peripheral circuits of the chip to be tested;
testing peripheral circuits of the chip;
the memory is connected with the test chip and used for storing test results;
And the test control end is connected with the test chip and used for controlling the test chip to start and stop testing, and the test chip is a verified chip which can be used.
3. The device for testing the peripheral interfaces of the chip according to claim 2, wherein a test program is arranged in the test chip, the test control end controls the test chip to start the test program, the test chip sequentially tests a plurality of peripheral interfaces of the tested chip according to the test program, and the test result of each peripheral interface is sent to the memory or/and the test control end.
4. The device according to claim 3, wherein the test control terminal outputs a single-step control instruction to the test chip to control a test program in the test chip to perform a single-step test on the peripheral interface.
5. The device for testing a peripheral interface of a chip according to claim 3, wherein,
The chip to be tested comprises a communication interface,
The test chip comprises a communication interface, the communication interface of the test chip is connected with the communication interface of the tested chip,
And the test chip informs the peripheral interface which is required to be tested currently of the tested chip through the communication interface.
6. The device according to claim 5, wherein when a peripheral interface of the chip under test is tested, the test chip performs data interaction with the peripheral interface under test of the chip under test according to the test program, the test program determines a test result based on the interaction data, and sends the test result to the memory and/or the test control terminal.
7. The device for testing a peripheral interface of a chip as claimed in claim 5, wherein,
The peripheral interfaces of the tested chip comprise an I2C interface and an ETH interface,
The peripheral interfaces of the test chip also comprise an I2C interface and an ETH interface,
The I2C interface of the tested chip is connected with the I2C interface of the tested chip,
The ETH interface of the tested chip is connected with the ETH interface of the tested chip,
The communication interface of the chip to be tested is a UART interface, the communication interface of the test chip is a UART interface, and the UART interface of the chip to be tested is connected with the UART interface of the test chip.
8. The device for testing a peripheral interface of a chip as claimed in claim 7, wherein,
The test chip informs the tested chip to perform I2C interface test through UART interface, the I2C interface of the test chip and the I2C interface of the tested chip perform data interaction according to the test program, the test program determines test results based on the interaction data and sends the test results to the memory and/or the test control end,
The test chip informs the tested chip of carrying out ETH interface test through the UART interface, the ETH interface of the test chip and the ETH interface of the tested chip carry out data interaction according to the test program, the test program determines a test result based on the interaction data, and the test result is sent to the memory and/or the test control end.
9. The device for testing a peripheral interface of a chip as claimed in claim 8, wherein,
When the I2C interface of the tested chip is tested, a master-slave mode of the tested chip and the tested chip is well defined.
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| CN202311608666.0A CN118295859A (en) | 2023-11-28 | 2023-11-28 | Chip peripheral interface testing device |
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| CN202311608666.0A CN118295859A (en) | 2023-11-28 | 2023-11-28 | Chip peripheral interface testing device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119512844A (en) * | 2024-11-25 | 2025-02-25 | 上海芯钛信息科技有限公司 | Method and device for automated testing of I2C peripherals |
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- 2023-11-28 CN CN202311608666.0A patent/CN118295859A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119512844A (en) * | 2024-11-25 | 2025-02-25 | 上海芯钛信息科技有限公司 | Method and device for automated testing of I2C peripherals |
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