CN118316443B - Low-phase-noise fractional frequency-division phase-locked loop, chip and electronic equipment - Google Patents

Abstract

The invention discloses a decimal frequency division phase-locked loop with low phase noise, a chip and electronic equipment, wherein the phase-locked loop comprises: the phase-locked loop comprises a first oscillator for outputting a first intermediate output clock, a first frequency divider for dividing the first intermediate output clock by an integer, a first phase detector, a feedforward phase noise canceling circuit, a second oscillator for outputting an output clock of the phase-locked loop, a second frequency divider for dividing the output clock of the phase-locked loop by a decimal, and a second phase detector, wherein the second intermediate output clock output by the feedforward phase noise canceling circuit is used as a reference clock of the second phase detector. The phase-locked loop provided by the invention has low phase noise and can realize fractional frequency division, so that the phase noise performance of the phase-locked loop can be improved and the application range of the phase-locked loop can be increased.

Description

Low-phase-noise fractional frequency-division phase-locked loop, chip and electronic equipment

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a fractional frequency pll, a chip, and an electronic device.

Background

A phase locked loop (Phase Locked Loop, PLL) is mainly used to keep the phases of the reference signal and the output signal constant. The method is widely applied to circuits such as filtering, frequency synthesis, modulation and demodulation, signal detection and the like. In modern communication circuits, the importance of the clock is more ubiquitous. In radio frequency communications, radio signals are transmitted strictly according to a specific frequency. Thus in both radio frequency receiver and transmitter systems, a phase locked loop circuit is required to generate an accurate clock signal. Also in wired communication systems, such as optical fiber communication, and in communication systems with metallic conductors as carriers, digital signals are modulated to a frequency, and accurate clock generation and recovery circuits are very important components in such systems.

Because the integer division ratio phase-locked loop can only realize the output clock frequency which is an integer multiple of the reference clock frequency, the application range of the integer division ratio phase-locked loop is severely limited, and thus, a fractional division ratio phase-locked loop is needed to realize that the frequency of the output clock is a fractional multiple of the reference clock frequency. The main indexes of the phase-locked loop include phase noise, spurious, power consumption, area, frequency locking range, phase margin and the like. The phase noise is a key index for measuring the phase-locked loop. Therefore, a fractional-n pll with low phase noise is needed to improve the phase noise performance and the application range of the pll.

Disclosure of Invention

An aspect of the present invention provides a fractional-n pll with low phase noise to improve the phase noise performance of the fractional-n pll.

The fractional frequency phase-locked loop provided by the invention comprises: a first oscillator outputting a first intermediate output clock of the phase-locked loop according to a first control voltage; the first frequency divider is used for carrying out integer frequency division on the first intermediate output clock to obtain a first clock, and the frequency of the first intermediate output clock is an integer multiple of the frequency of the first clock; a first phase detector for detecting a first phase difference between the first clock and a reference clock of a phase-locked loop and converting the first phase difference into a first control voltage to control the first oscillator; the feedforward phase noise cancellation circuit comprises a phase difference voltage converter and a voltage-controlled cancellation sub-circuit; the phase difference voltage converter is used for converting a first phase difference between the first clock and a reference clock of the phase-locked loop into a voltage; the voltage-controlled cancellation sub-circuit is configured to control and generate a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter and the first intermediate output clock, and enable the first intermediate output clock to superimpose the delay signal so as to cancel the first phase difference and output a second intermediate output clock, where the second intermediate output clock is a reference clock of a second phase discriminator; a second oscillator for outputting an output clock of the phase-locked loop according to a second control voltage; the second frequency divider is used for performing fractional frequency division on the output clock to obtain a second clock, and the frequency of the output clock is fractional times of the frequency of the second clock; and the second phase discriminator is used for detecting a second phase difference between the second clock and the second intermediate output clock and converting the second phase difference into a second control voltage so as to control the second oscillator.

In a preferred embodiment of the present invention, the voltage-controlled cancellation sub-circuit comprises: the operational amplifier, the switch, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer; the positive phase input end of the operational amplifier is connected with the output end of the phase difference voltage converter, the reverse input end of the operational amplifier is connected with one end of the switch, and the output end of the operational amplifier is connected with the other end of the switch; the input end of the buffer is grounded after sequentially passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4, the input end of the buffer is connected with one end of the third capacitor and one end of the switch, the output end of the buffer outputs the second intermediate output clock, the grid/base electrode of the fifth N-type switching tube N5 is connected with the first intermediate output clock, and the other end of the third capacitor is grounded.

In a preferred embodiment of the present invention, the phase difference voltage converter includes a first capacitor, and the phase difference voltage converter is configured to control a power supply voltage to charge the first capacitor until a voltage value on the first capacitor is the voltage value of the power supply voltage, and control the first capacitor to discharge according to the first phase difference to convert the first phase difference into a voltage, and store the converted voltage in the first capacitor.

In a preferred embodiment of the present invention, the phase difference voltage converter includes: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1; the gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the first phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through a second N-type switch tube.

In a preferred embodiment of the present invention, the phase difference voltage converter further includes: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor.

In a preferred embodiment of the present invention, the reset signal controls the first P-type switching tube to be closed, so that the switch S1 is opened when the first capacitor is charged; after the first capacitor is discharged, the switch S1 is closed, so that the first voltage on the first capacitor is transmitted to the second capacitor.

In a preferred embodiment of the present invention, the generating a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter and the first intermediate output clock control, and the superimposing the delay signal by the first intermediate output clock, includes: controlling the third capacitor to be charged until the voltage on the third capacitor is equal to the voltage output by the phase difference voltage converter and the voltage on the third capacitor is enabled to follow the voltage output by the phase difference voltage converter; the voltage-controlled cancellation sub-circuit receives the first intermediate output clock and discharges the third capacitor when the first intermediate output clock is at a high level, so that the delay time of the buffer is reversely changed, and the voltage on the third capacitor is connected to the buffer, so that the first intermediate output clock is overlapped with the delay signal.

In a preferred embodiment of the present invention, the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed.

In a preferred embodiment of the present invention, the ratio of the discharge current of the first capacitor to the discharge current of the third capacitor is a fixed value.

In a preferred embodiment of the present invention, further comprising: the current source and the first N-type switch tube N1, one end of the current source is connected with the power supply voltage, the other end of the current source is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1, the discharging current of the first capacitor and the discharging current of the third capacitor form mirror currents.

In a preferred embodiment of the present invention, further comprising: a first charge pump and a first low-pass filter connected in sequence between the first phase detector and the first oscillator; and/or a second charge pump and a second low pass filter connected in sequence between the second phase detector and the second oscillator.

In a preferred embodiment of the present invention, the feedforward phase noise canceling circuit further includes a first phase difference sampler for acquiring a first phase difference between the first clock and a reference clock of a phase locked loop and outputting the first phase difference to the phase difference voltage converter.

The invention also provides a chip comprising a phase locked loop as claimed in any one of the preceding claims.

The invention also provides an electronic device comprising a phase locked loop as claimed in any one of the preceding claims.

The phase-locked loop provided by the invention outputs a second intermediate output clock with low phase noise to the second phase detector as a reference clock after being matched with a first oscillator, a first frequency divider, a first phase detector and a feedforward phase noise cancellation circuit, and the second frequency divider is combined to carry out fractional frequency division on the output clock output by the second oscillator, and then the second phase detector is combined with the phase difference (namely the second phase difference) between the second clock after fractional frequency division and the second intermediate output clock to control the second oscillator to oscillate so as to generate the output clock of the phase-locked loop, so that the phase-locked loop can realize fractional frequency division and also has extremely low phase noise. The feedforward phase noise cancellation circuit enables the reference clock output to the second phase detector to have low noise in a feedforward mode. Namely: the phase difference voltage converter and the voltage-controlled cancellation sub-circuit form a phase noise cancellation circuit, and further the first phase difference between the first intermediate output clock of the phase-locked loop and the reference clock is converted into a voltage through the phase difference voltage converter. The voltage-controlled cancellation sub-circuit controls and generates a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter and the first intermediate output clock, and enables the first intermediate output clock of the phase-locked loop to superimpose the delay signal, so that the first intermediate output clock of the phase-locked loop can cancel the first phase difference and output a high-frequency second intermediate output clock as a reference clock of the second phase discriminator after the first intermediate output clock of the phase-locked loop superimposes the delay signal. Therefore, after the first intermediate output clock output by the first oscillator of the phase-locked loop enters the voltage-controlled cancellation sub-circuit, the first phase difference can be cancelled, and further the phase noise performance of the phase-locked loop is greatly improved. After passing through the first phase discriminator, the first oscillator, the first frequency divider and the feedforward phase noise cancellation circuit, the voltage-controlled cancellation sub-circuit can output a high-frequency second intermediate output clock which is used as a reference clock of a second phase discriminator in a later stage of the phase-locked loop, so that the phase noise performance of the fractional frequency division phase-locked loop can be further improved. Therefore, the phase-locked loop provided by the invention can realize fractional frequency division, and can also have low phase noise, so that the phase-locked loop provided by the invention has wider application range and good phase noise performance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a fractional-n pll according to an embodiment of the present invention;

Fig. 2 is a schematic diagram of a fractional-n pll according to another embodiment of the present invention;

Fig. 3 is a circuit diagram of a voltage-controlled cancellation sub-circuit of a phase-locked loop according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a feedforward phase noise cancellation circuit of the phase-locked loop provided by the embodiment of FIG. 3;

Fig. 5 is a phase noise diagram of a fractional-n pll;

fig. 6 is a waveform diagram of the fractional-n pll provided by the embodiment shown in fig. 4.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention can be applied to high-speed interface chips, wireless communication chips, wired communication chips, wearable main control chips, mobile phone main control chips, AR/VR main control chips and the like.

In the following description, for the purpose of providing a thorough understanding of the present invention, detailed structures and steps are presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Referring to fig. 1, the phase-locked loop provided by the present invention includes: the phase detector comprises a first phase detector 10, a first oscillator 20, a first frequency divider, a feedforward phase noise cancellation circuit for canceling phase noise of a phase locked loop, a second oscillator, a second frequency divider, and a second phase detector. The first phase detector 10 is configured to detect a first phase difference between a first clock div_out1 of the phase-locked loop and a reference clock clk_ref and convert the first phase difference into a first control voltage to control the operation of the first oscillator; a first oscillator 20, typically a voltage controlled oscillator, which outputs a first intermediate output clock pll_out1 of the phase locked loop according to the first control voltage; and the first frequency divider is used for carrying OUT integer frequency division on the first intermediate output clock PLL_OUT1 to obtain a first clock DIV_OUT1, wherein the frequency of the first intermediate output clock is an integer multiple of the frequency of the first clock. Therefore, the first intermediate output clock pll_out1 of high frequency can be output through the first oscillator, the first frequency divider, and the first phase detector. The feedforward phase noise cancellation circuit includes: the voltage-controlled cancellation sub-circuit 32 and the phase difference voltage converter 31. A phase difference voltage converter 31 for converting a phase difference (i.e., a first phase difference) between the first clock and a reference clock of the phase-locked loop into a voltage. The reference clock of the phase-locked loop generally refers to the clock generated by the crystal oscillator, and the clock generated by the crystal oscillator is generally low frequency; the voltage-controlled cancellation sub-circuit 32 is configured to generate a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter 31 and the first intermediate output clock pll_out1, and superimpose the delay signal on the first intermediate output clock to cancel the first phase difference and output a second intermediate output clock FFPNC _out, where the second intermediate output clock FFPNC _out is a high-frequency clock, and the second intermediate output clock FFPNC _out is used as a reference clock for the second phase detector 50. A second frequency divider 70, configured to divide the output clock pll_out2 by a fractional number to obtain a second clock div_out2, where the frequency of the output clock is a fractional multiple of the frequency of the second clock; the second phase detector 50 is configured to detect a phase difference (i.e., a second phase difference) between the second clock div_out2 and the second intermediate output clock FFPNC _out and convert the second phase difference into a second control voltage to control the second oscillator 60. The second oscillator 60 outputs an output clock pll_out2 of the phase locked loop, which is typically a voltage controlled oscillator, according to a second control voltage. the present invention may form a conventional integer division phase locked loop by the first phase detector 10, the first oscillator 20, and the first frequency divider. The phase noise of the phase-locked loop can be reduced or even removed by the feedforward phase noise cancellation circuit. The voltage-controlled cancellation sub-circuit 32 superimposes the delay signals on the first intermediate output clock to cancel the first phase difference and output a second intermediate output clock, which is used as a reference clock for the second phase detector 50 and is a high-frequency reference clock, so as to further improve the phase noise performance of the fractional-n pll provided by the present invention. Therefore, the invention can solve the contradiction problem of high loop bandwidth, low reference clock spurious and DSM quantization noise of the traditional fractional frequency division phase-locked loop, realize the fractional frequency division PLL of high loop bandwidth, low reference clock spurious and low DSM quantization noise, and finally realize the fractional frequency division phase-locked loop of low phase noise.

Each module of the phase locked loop typically produces noise, with Voltage controlled oscillators (Voltage-controlled oscillator VCO) often being the largest source of noise and consuming the greatest power consumption. Phase noise of a signal loop of a phase-locked loop on a voltage-controlled oscillator is generally equivalent to high-pass filtering, so in order to obtain better phase noise filtering effect, the loop bandwidth of the phase-locked loop needs to be improved. However, the increase in bandwidth deteriorates reference clock spurs and DSM (delta-sigma modulation) quantization noise performance, reduces the phase margin of the loop, and even destabilizes the phase locked loop. Therefore, the phase-locked loop needs to achieve high phase-locked loop bandwidth while reducing reference clock spurs and DSM quantization noise. However, the reference clock frequency generated by the crystal oscillator is generally smaller than 100MHz, in order to obtain a higher reference clock frequency, the present invention can first multiply the reference clock clk_ref generated by the crystal oscillator to a high frequency by combining the first phase detector 10, the first oscillator 20, the first frequency divider 40, and the feedforward phase noise cancellation circuit, so as to output a high-frequency clock FFPNC _out with low phase noise to the second phase detector 50 as the reference clock, and further, the second phase detector 50, the second oscillator 60, and the second frequency divider 70 can realize high loop bandwidth to filter the oscillator low frequency noise, and can reduce the reference clock spurious and the DSM quantization noise, thereby realizing a fractional division phase-locked loop with low phase noise. Therefore, the phase-locked loop provided by the invention can improve the phase-noise performance and the application range of the phase-locked loop, and the phase-locked loop provided by the invention adopts an open loop feedforward phase-noise counteracting mode, so that the corresponding phase-locked loop provided by the invention can not introduce clock spurious, and can avoid the problems of clock spurious and loop stability.

A frequency divider is an important part of a phase locked loop circuit that can adjust the frequency of an input signal to a frequency range that the phase locked loop can handle. For example, the frequency of the input signal may be reduced by a frequency divider so that it can be correctly received and processed by the phase locked loop. In addition, the frequency divider can also provide phase information of the input signal, so that the phase-locked loop can accurately lock the frequency and the phase of the input signal. By comparing the input signal with a reference signal, the phase locked loop can achieve accurate control of the frequency and phase of the input signal. In one embodiment, the first phase difference obtained by the first phase detector 10 is a first phase difference between the divided clock (i.e., the first clock) div_out1 output by the first frequency divider and the reference clock ref_clk. The phase noise cancellation circuit further comprises a first phase difference sampler 30 for acquiring a first phase difference between the divided clock and a reference clock and outputting the first phase difference to the phase difference voltage converter 31. Therefore, the first phase difference obtained by the phase difference voltage converter 31 in the phase-locked loop provided by the invention may be the first phase difference obtained by the first phase detector 10, or may be the first phase difference obtained by the first phase difference sampler 30 in the phase noise cancellation circuit. The noise cancellation circuit is provided with the first phase difference sampler 30, so that the circuit structure of the phase-locked loop can be more flexible, and the noise cancellation circuit is suitable for more types of phase-locked loops and can be suitable for more electronic circuits and electronic devices. In a preferred embodiment provided by the present invention, it further comprises a DSM (Delta-sigma modulator) connected to the second frequency divider 70 for dynamically adjusting the frequency division ratio of the second frequency divider 70. The DSM can accurately and stably control the frequency division ratio of the frequency divider to accurately and stably realize fractional frequency division. Referring to fig. 1, 2, and 5, the DSM dynamically adjusts the frequency division ratio of the second frequency divider 70 to achieve the fractional frequency division function. For example, when the DSM controls the frequency division ratio of the second frequency divider 70 to be N and n+1, the frequency division ratio N is D, the frequency division ratio n+1 is 1-D, the average frequency division ratio n+d+ (n+1) ×1-D, different fractional frequency division ratios between N and n+1 can be obtained by selecting different frequency division ratios N and different duty ratios D, and since the output frequency is the product of the reference clock frequency and the average frequency division ratio, the output clock pll_out2 of the frequency of the reference clock (FFPNC _out) of the second phase detector 50 can be obtained, thereby realizing the function of the fractional frequency division phase-locked loop. The reference clock generated by the crystal oscillator and the first clock are usually low frequency, and the first intermediate output clock provided by the invention is high frequency, for example, the frequency of the first intermediate output clock is 4 times that of the first clock, so that the first intermediate output clock and the second intermediate output clock are high frequency clocks, thereby providing the high frequency reference clock for the second phase detector 50.

The phase noise of the phase locked loop is mainly derived from the DSM quantization noise and the oscillator, see also fig. 5, which illustrates the phase noise corresponding to the phase locked loop in case the reference clocks are at different frequencies. In the figure, the phase noise diagram corresponding to the thin line is a relation diagram of phase noise of the phase-locked loop and frequency of the phase-locked loop in the prior art, and the phase noise diagram corresponding to the thick line is a relation diagram of phase noise of the phase-locked loop and frequency of the phase-locked loop. As can be seen from fig. 5: when the reference clock is at low frequency, the DSM quantization noise accounts for a major part of the noise of the phase locked loop; when the reference clock is at high frequency, the oscillator phase noise accounts for a major portion of the noise of the phase locked loop. As the DSM operating frequency changes from low to high frequency, the DSM quantization noise is substantially reduced, thereby substantially reducing the overall phase noise of the phase locked loop. The invention multiplies the reference clock clk_ref from the crystal oscillator to a high frequency by a technique with feedforward phase noise cancellation (FFPNC) to obtain a low phase noise and high frequency clock FFPNC _out as the reference clock for the second phase detector 50. Specifically, the phase difference voltage converter 31 and the voltage-controlled cancellation sub-circuit 32 form a phase noise cancellation circuit, and further the first phase difference between the first intermediate output clock of the phase-locked loop and the reference clock is converted into a voltage by the phase difference voltage converter 31. The voltage-controlled cancellation sub-circuit 32 controls and generates a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter 31 and the first intermediate output clock, and superimposes the delay signal on the first intermediate output clock of the phase-locked loop, so that the first intermediate output clock of the phase-locked loop can cancel the first phase difference and output the second intermediate output clock as the reference clock of the second phase discriminator 50 after superimposing the delay signal, thereby greatly improving the phase noise performance of the fractional frequency phase-locked loop.

In a preferred embodiment of the present invention, the phase difference voltage converter 31 includes a first capacitor. The phase difference voltage converter 31 is configured to control the power supply voltage VDD to charge the first capacitor until the voltage value on the first capacitor is the voltage value of the power supply voltage, and control the first capacitor to discharge according to the first phase difference, so as to convert the first phase difference into a voltage, and store the converted voltage on the capacitor (i.e., the first capacitor). The voltage output by the phase difference voltage converter 31 is the voltage on the first capacitor. Therefore, the output voltage of the phase difference voltage converter 31 includes the first phase difference information, and the output voltage including the first phase difference information is transmitted to the voltage-controlled cancellation sub-circuit 32 to control the operation of the voltage-controlled cancellation sub-circuit 32. The voltage-controlled cancellation sub-circuit 32 generates a signal opposite to the above-described first phase difference based on the output voltage of the phase difference voltage converter 31, and generates a delayed signal opposite to the first phase difference in conjunction with the first intermediate output clock control. That is, the voltage-controlled cancellation sub-circuit 32 may combine the voltage stored on the first capacitor and including the first phase difference, and the first intermediate output clock output by the first oscillator 20 to generate a delayed signal opposite to the first phase difference. Therefore, the first intermediate output clock output from the first oscillator 20 enters the voltage-controlled cancellation sub-circuit 32 to superimpose the delay signals, and the first phase difference can be cancelled. In summary, the present invention converts the first phase difference between the sampled reference clock and the first clock into a voltage signal, stores the voltage signal in a capacitor, and outputs the voltage signal, and then the voltage signal controls the voltage-controlled cancellation sub-circuit 32 to generate a delay signal opposite to the first phase difference. When the first intermediate output clock of the pll passes through the voltage-controlled cancellation sub-circuit 32, the first phase difference is reduced, thereby greatly improving the phase noise performance of the pll.

In one embodiment of the present invention, the phase difference voltage converter 31 includes: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1; the gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the first phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through a second N-type switch tube. Therefore, the first capacitor can be controlled to be charged by controlling the on-off state of the first P-type switching tube P1. The third N-type switching tube N3 is grounded through the second N-type switching tube N2, one end of the first capacitor is connected with the third N-type switching tube N3, and the other end of the first capacitor is grounded, so that the on-off of the third N-type switching tube N3 can be controlled through the first phase difference, the first capacitor can be further controlled to be discharged, and then the voltage on the first capacitor can contain the information of the first phase difference. Therefore, the output voltage including the first phase difference information can be led out to the voltage-controlled cancellation sub-circuit 32 by taking one end of the first capacitor as the output terminal of the phase difference voltage converter 31, so as to control the operation of the voltage-controlled cancellation sub-circuit 32. The phase difference voltage converter 31 with the structure has a simple circuit structure and can quickly and accurately convert the first phase difference of the phase-locked loop into voltage information. The power supply used for charging the first capacitor is preferably the power supply voltage VDD of the phase-locked loop, and the existing resources of the phase-locked loop can be further multiplexed, so that the circuit structure is further simplified, and the interference and the error are reduced. The voltage converted by the first phase difference is stored in the first capacitor, and the voltage-controlled cancellation sub-circuit 32 can be controlled continuously by the voltage on the first capacitor to generate a delay signal, so that the first phase difference can be cancelled when the delay signal is superimposed by the first intermediate output clock.

Referring to fig. 3, 4, and 5, the phase difference voltage converter 31 further includes: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor. By adding S1 and the second capacitor CS2, the interference of the phase difference voltage converter 31 to the voltage-controlled cancellation sub-circuit 32 during sampling can be reduced, and jitter can be further reduced. Preferably, when the reset signal controls the first P-type switching tube to be closed to charge the first capacitor, the switch S1 is opened; after the first capacitor is discharged, the switch S1 is closed, so that the first voltage on the first capacitor is transmitted to the second capacitor, and further, phase errors can be counteracted by continuous sampling and continuous and stable sampling according to the condition of sampling of the phase-locked loop, signals with low phase noise can be stably output, and interference and jitter can be better reduced.

The voltage-controlled cancellation sub-circuit 32 includes: the operational amplifier, the switch S2, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer INV1. Wherein, the non-inverting input end of the operational amplifier is connected with the output end of the phase difference voltage converter 31, the inverting input end thereof is connected with one end of the switch S2, and the output end thereof is connected with the other end of the switch S2; the input end of the buffer is grounded after sequentially passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4, the input end of the buffer is connected with one end of the third capacitor and one end of the switch, the output end of the buffer outputs the second intermediate output clock, the grid/base electrode of the fifth N-type switching tube N5 is connected with the first intermediate output clock, and the other end of the third capacitor is grounded. When the control signal op_en is at a high level, the switch S2 is closed, the operational amplifier charges the third capacitor CPNC, and the voltage VCPNC on the third capacitor is equal to the voltage output by the phase-difference voltage converter 31 due to the negative feedback effect of the operational amplifier, i.e. the voltage output by the phase-difference voltage converter 31 is copied to the third capacitor CPNC. By combining the voltage-controlled cancellation sub-circuit 32 with the structure, the over-charge can be avoided, the wanted voltage can be obtained, and further the phase error cancellation is more accurate, so that the phase noise performance of the phase-locked loop provided by the invention is better.

The feedforward phase noise cancellation effect is obviously reduced along with the influence of factors such as process manufacturing, temperature change, power supply voltage change and the like. Therefore, to achieve better open loop feedforward cancellation of phase noise, it is often necessary to calibrate the gain of the phase noise cancellation. Preferably, the phase-locked loop provided by the present invention further includes: the current source and the first N-type switch tube N1, one end of the current source is connected with the power supply voltage, the other end of the current source is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1, the discharging current of the first capacitor and the discharging current of the third capacitor form mirror currents. In this way, the gain of the phase noise cancellation circuit in the phase-locked loop can be more stable within a fixed range, and the gain of the phase noise cancellation circuit does not need to be calibrated, or the process of calibrating the gain is reduced. Further preferably, the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed. The gain of the phase noise cancellation circuit in the phase-locked loop can be completely fixed, and the gain of the phase noise cancellation circuit is not required to be calibrated at all. (for specific reasons, see the following detailed description of the working principle and working procedure of the phase-locked loop), the phase-locked loop provided by the invention may have at least the following advantages: the gain calibration algorithm is reduced or even avoided from being added, so that a series of negative effects are brought to the phase-locked loop, a chip where the phase-locked loop is located, an electronic device where the phase-locked loop is located and the like (for example, the complexity of design is increased, the area and the power consumption of the chip are increased, the convergence of the complex calibration algorithm brings about the reduction of the robustness of the system, the calibration algorithm needs longer calibration time, and the fast-changing power supply voltage interference cannot be dealt with). Therefore, the phase-locked loop provided by the invention can realize constant gain without calibrating gain, so as to realize better phase noise cancellation, and further improve the phase noise performance of the phase-locked loop.

Further preferably, the phase-locked loop provided by the present invention further includes: a first charge pump 80 and a first low-pass filter 90 connected in sequence between the first phase detector 10 and the first oscillator 20; and/or a second charge pump and a second low pass filter connected in series between the second phase detector 50 and the second oscillator 60. The method can perform better filtering on the signals in the phase-locked loop, so that the noise of the phase-locked loop is smaller, and the performance is better.

The following describes the working principle and working procedure of the phase-locked loop according to the present invention in detail with reference to fig. 2 to 6 as follows:

The first phase detector 10 of the phase-locked loop collects a first phase difference between the first clock div_out1 output by the first frequency divider and the reference clock clk_ref, and converts the first phase difference into a first control voltage to control the operation of the first oscillator 20, and the first oscillator 20 outputs a first intermediate output clock pll_out1 of the phase-locked loop according to the first control voltage. The first phase difference between the first clock and the reference clock, and the first phase difference between the first intermediate output clock output by the first oscillator 20 and the reference clock are substantially the same, and are all within the scope of the present invention. The first intermediate output clock pll_out1 has a frequency M times the first clock div_out, M being the frequency division ratio of the first frequency divider.

The first phase difference sampler 30 in the feedforward phase noise canceling circuit is implemented by an and gate to compare the phases of the reference clock and the divided clock output by the divider, so as to obtain a first phase difference between the reference clock and the divided clock, where the first phase difference is output in the form of a pulse signal (i.e., a pulse signal sam_out in the figure). On the one hand, when the reset signal connected to the control end of the first P-type switching tube P1 is enabled, the first P-type switching tube P1 is turned on, and then the power supply voltage VDD charges the first capacitor CS1 until the voltage value on the first capacitor CS1 is VDD, and since the lower electrode plate of the first capacitor is grounded, that is, the voltage of the upper electrode plate of the first capacitor is VDD, the reset signal turns off the first P-type switching tube. Then, when the rising edge of the pulse signal sam_out corresponding to the first phase difference comes, the third N-type switching tube and the second N-type switching tube are triggered to be turned on, and the first capacitor CS1 discharges. The first phase difference sampler 30 controls the on time of the third N-type switching tube N3 through the pulse width of the pulse signal sam_out, thereby controlling the discharging of the first capacitor CS1 and controlling the voltage on the first capacitor CS 1. Therefore, the voltage information on the first capacitor includes the information of the first phase difference and is stored on the first capacitor. When the switch S1 is turned on by the control signal ph_sam1 of the switch S1, the voltage information on the first capacitor is transmitted to the second capacitor CS2 by the charge sharing principle, and the second voltage VCS2 on the second capacitor is used as the output voltage of the phase difference voltage converter 31 to control the voltage-controlled cancellation sub-circuit 32. when the control signal op_en in the voltage-controlled cancellation sub-circuit 32 is at a high level, the switch in the voltage-controlled cancellation sub-circuit 32 is closed, the operational amplifier charges the third capacitor CPNC, and due to the negative feedback effect of the operational amplifier, the voltage VCPNC on the third capacitor is equal to the voltage output by the phase-difference voltage converter 31, i.e. the voltage output by the phase-difference voltage converter 31 is copied to the third capacitor CPNC. When the rising edge of the first intermediate output clock pll_out1 passes through the voltage-controlled cancellation sub-circuit 32, its rising edge triggers the fifth N-type switching transistor N5 to turn on, and the current i_pnc discharges the third capacitor CPNC. When the voltage VCPNC on the third capacitor is lower than the reverse Voltage (VTRIG) of the buffer, the buffer outputs a high level, and if the voltage on the third capacitor is higher than the reverse voltage of the buffer, the buffer outputs a low level. Thus, the voltage-controlled cancellation sub-circuit 32 can control generation of a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter 31 and the intermediate output clock, and superimpose the delay signal on the intermediate output clock to cancel the first phase difference. Wherein the phase difference voltage converter 31 converts the first phase difference into a voltage and outputs a corresponding voltage to control the voltage-controlled cancellation sub-circuit 32 to generate a signal opposite to the first phase difference, and generates a delayed signal opposite to the first phase difference in combination with the first intermediate output clock control. The buffer output signal FFPNC OUT is a low phase noise high frequency signal and is input to the second phase detector 50 as a reference clock for the second phase detector 50. The second phase detector 50 detects a phase difference (i.e., a second phase difference) between the second clock div_out2 and the second intermediate output clock FFPNC _out and converts the second phase difference into a second control voltage to control the second oscillator 60. The second clock is obtained by dividing the signal pll_out2 output by the second oscillator 60 by a fraction by the second frequency divider 70, and the second oscillator 60 outputs the output clock pll_out2 of the phase-locked loop according to the second control voltage. therefore, the phase-locked loop provided by the invention can realize fractional frequency division with low phase noise.

The gain calibration method and the gain calibration device can realize constant gain of the phase noise cancellation circuit without calibrating the gain, thereby avoiding a series of problems brought by introducing a gain calibration algorithm. The reason for this is roughly described as follows: after the phase-locked loop is locked, the first phase difference sampler 30 performs phase sampling on the divided clock div_out1 output by the first frequency divider, and the output pulse of the first phase difference sampler 30 is sam_out. The pulse width of sam_out (tSAM OUT) at this time includes a fixed delay time tdc and a random time error terr introduced by device noise or interference of the phase locked loop circuit. The formula for tSAM _OUT is as follows:

∆tSAM_OUT=∆tdc+∆terr （1）；

the first clock div_out1 is directly driven and divided by the first intermediate output clock pll_out1. Thus, the phase error of pll_out1 is directly transmitted to div_out1. The first phase difference sampling of div_out1 is equivalent to the phase difference sampling of pll_out1. Alternatively, the phase error may be obtained by dividing the time error by the period of the first intermediate output clock of the phase locked loop and multiplying by 2pi. Since the locked output clock period and pi are constants and the phase error and the time error are equivalent, canceling the time error is equivalent to canceling the phase error. The phase error is equivalent to the time error.

When the reset signal RSTB is at a low level, the first P-type switching transistor P1 is turned on, and the upper plate voltage of the capacitor CS1 is further charged to be equal to the power supply voltage VDD. After that, the output pulse sam_out containing the first phase difference discharges the first capacitor CS1 by controlling the switching time of the third N-type switching transistor N3, and the sampled voltage value after the first capacitor CS1 is discharged is VCS1, which has the following calculation formula:

VCS1=VDD-（∆tSAM_OUT×I_SAM）/CS1 （2）；

When op_en is high, the negative feedback of the OP-amp makes VCPNC equal to VCS2, namely:

VCPNC= VCS2（3）

When the pll_out1 has a time error fater with respect to the reference clock ref_clk, the same time error fater will occur at the rising edge of div_out1 because div_out1 is triggered and divided by pll_out1. When the rising edge of pll_out1 passes through voltage-controlled cancellation subcircuit 32, its rising edge triggers transistor N5 to turn on, at which point current i_pnc discharges capacitor CPNC.

Assuming that the rising edge of the phase-noise-free PLL output signal occurs at times T1, T2, and T3, the actual pll_out1 rising edge occurs at times t1+ster1, t2+ster2, t3+ster3, where ster1, terr2, terr3 are the temporal noise of pll_out1 at times T1, T2, and T3, respectively. The first FFPNC _out output rising edge time (TPNC 2) after time T2 is calculated as follows:

TPNC2_err= ∆terr1×I_SAM×CS1/(CS1+CS2)/I_PNC-∆terr2（4）

for the low frequency part noise of the output clock pll_out11, terr1≡terr2. The gain of the feedforward phase noise cancellation circuit is defined as:

PNC_GAIN= I_SAM×CS1/(CS1+CS2)/I_PNC（5）

When PNC _ gain=1, at time TPNC,

TPNC2_err=∆terr1-∆terr2（6）

At time TPNC2, the pll_out1 original noise fatr 2 is subtracted from fatr 1. Similarly, at time TPNC, pll_out1 original noise terr3 is subtracted. By subtracting the term "ter 1" in the time domain, the feedforward phase noise cancellation circuit performs high-pass filtering on the phase noise of the output clock pll_out1.

Wherein CS1 is the capacitance of the first capacitor, CS2 is the capacitance of the second capacitor, I_SAM is the discharge current of the first capacitor, and I_PNC is the discharge current of the third capacitor.

As can be seen from the formula (5), the gain of the feedforward phase noise canceling circuit is related to the ratio i_sam/i_pnc of the two discharge currents and the ratio CS 1/(cs1+cs2) of the capacitance values. Preferably, the ratio of the discharge current of the first capacitor to the discharge current of the third capacitor is a fixed value, which can fix the gain within a desired range. Referring to fig. 3 and 4, since the first, second, and fourth N-type switching transistors N1, N2, and N4 form a current mirror circuit, the ratio i_sam/i_pnc of the two discharge currents is fixed in this embodiment. The first capacitor CS1 and the second capacitor CS2 provided by the invention can be generated by the same type capacitor device, so that the ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed, and the ratio of CS 1/(CS 1+CS 2) is fixed, therefore, the gain of the phase-locked loop provided by the invention can be a fixed value, and the phase-locked loop provided by the invention can be used for not calibrating the gain, and the gain can still keep the gain unchanged under the influence of factors such as manufacturing process variation, power supply voltage variation, temperature variation and the like, thereby improving the phase noise performance of the phase-locked loop.

In the phase-locked loop provided by the invention, each switch tube can be various electronic components capable of playing a role of switching, for example, can be a triode or a field effect tube. The buffer may be implemented by an inverter. In an embodiment of the present invention, the capacitor in the phase difference voltage converter 31 is only the first capacitor, in which case, the upper plate of the first capacitor leads out the output end of the phase difference voltage converter 31 and is electrically connected to the input end of the voltage-controlled cancellation sub-circuit 32, and the lower plate of the first capacitor is grounded. Therefore, the output voltage of the phase difference voltage converter 31, i.e. the voltage VCS1 across the first capacitor, i.e. the voltage across the upper plate of the first capacitor, can be used to control the operation of the voltage-controlled cancellation sub-circuit 32. Further preferably, the phase difference voltage converter 31 further includes a second capacitor CS2 and a switch S1, wherein two ends of the switch S1 are respectively connected to an upper plate of the first capacitor and an upper plate of the second capacitor, and a lower plate of the second capacitor is grounded. When the first capacitor CS1 is charging, the switch S1 may be turned off. After the charge sharing between the first capacitor CS1 and the second capacitor CS is completed, the switch S1 may be turned off, so that the voltage-controlled cancellation sub-circuit 32 is not affected to generate a corresponding delay signal according to the first phase difference information stored in the second capacitor CS, and the front end is not affected to continuously collect the first phase difference, so that the continuous phase noise cancellation can be implemented, and the influence of the front end circuit on the back end circuit during operation can be reduced, especially the interference to the voltage-controlled cancellation sub-circuit 32 during the sampling of the first phase difference is reduced, and the jitter of the phase-locked loop is further reduced.

In a preferred embodiment of the present invention, generating a delay signal opposite to the first phase difference based on the output voltage of the phase difference voltage converter 31 and the first intermediate output clock control, and causing the first intermediate output clock to superimpose the delay signal, includes: controlling to charge the third capacitor; comparing whether the voltage on the third capacitor is larger than the output voltage of the phase difference voltage converter 31, if so, stopping charging the third capacitor, and if not, continuing charging the third capacitor; the voltage controlled cancellation sub-circuit 32 receives the first intermediate output clock and discharges the third capacitance and taps the voltage on the third capacitance into the buffer when the first intermediate output clock is high. The voltage-controlled cancellation sub-circuit 32 outputs a high level if the voltage on the third capacitor is lower than the inverting voltage of the buffer, and the voltage-controlled cancellation sub-circuit 32 outputs a low level if the voltage on the third capacitor is higher than the inverting voltage of the buffer. In this way, the voltage controlled cancellation sub-circuit 32 is enabled to cancel the phase difference stably and thoroughly, thereby providing the second intermediate output clock with low phase noise to the second phase detector 50 as the reference clock.

One input end of the voltage-controlled cancellation sub-circuit 32 is connected with the output voltage containing the first phase difference output by the phase difference voltage converter 31, and the output voltage charges the third capacitor through the operational amplifier, so that the output voltage containing the first phase difference is copied to the third capacitor; the other input terminal of the voltage-controlled cancellation sub-circuit 32 is connected to the first intermediate output clock pll_out1, when the first intermediate output clock pll_out1 is at a high level, the switching transistor N5 is triggered to be turned on, both the switching transistor N5 and the switching transistor N4 are turned on, and the ground discharge is realized, that is, the third capacitor is discharged, and the voltage on the third capacitor is connected to the buffer, if the voltage on the third capacitor is lower than the inversion voltage of the buffer, the voltage-controlled cancellation sub-circuit 32 outputs a high level, and if the voltage on the third capacitor is higher than the inversion voltage of the buffer, the voltage-controlled cancellation sub-circuit 32 outputs a low level. In this process, a delay signal opposite to the first phase difference is formed, and the first intermediate output clock pll_out1 input to the voltage-controlled cancellation sub-circuit 32 is mixed and superimposed with the delay signal, so that the first phase difference can be cancelled, and further cancellation of phase noise can be achieved.

The phase-locked loop provided by the invention can be in the form of an IP core or a chip. The phase-locked loop provided by the embodiment of the invention can be applied to various fields, such as the AI field, for example, an analog-digital hybrid AI vision chip which is realized based on a sense-in-computation integrated technology architecture and comprises the phase-locked loop provided by the invention has better phase noise performance and lower power consumption and higher energy efficiency ratio. The corresponding AI vision chip can be applied to automatic driving, AR, VR and laser radar, and can also be widely applied to a series of application fields such as smart phones, tablet computers, wearable electronic equipment, intelligent household electronic products, industry or medical treatment or battery power supply.

In summary, the Phase-Locked Loop (PLL) provided by the embodiments of the present invention may be widely applied in many fields, including but not limited to the following application fields:

communication system: PLLs are used for clock recovery, modem, timing recovery, etc. in digital and analog communication systems.

Audio processing: PLL's may be used in digital audio processors, clock recovery in audio devices, jitter suppression, etc.

Video processing: PLL's can be used in digital video processors, clock recovery in video devices, jitter suppression, and the like.

And (3) power management: the PLL may be used in clock synchronization, frequency synthesis, etc. in a power management chip to improve the energy efficiency of the system.

Testing and measuring: PLLs can be used in testing and measuring equipment for frequency synthesis, clock recovery, etc. to improve equipment performance and accuracy.

A sensor: PLLs may be used for clock synchronization, signal conditioning, etc. in certain sensor systems.

Other applications: the PLL is also widely applied to fields and products such as radar, satellite communication, radar high-definition image processing, radar SAR imaging, optical fiber communication, airborne radar and the like.

The PLL may be applied to, but is not limited to, the following: digital televisions, digital audio processors, frequency modulated radios, GPS receivers, digitizer, mixers, radio frequency synthesizers, mobile telephones, wireless local area networks, power management chips, and the like.

The invention also provides a chip, which comprises any phase-locked loop. For example, the chip can be applied to a high-speed interface chip, a wireless communication chip, a wired communication chip, a wearable main control chip, a mobile phone main control chip, an AR/VR main control chip and the like.

The chip provided by the embodiment of the invention comprises but is not limited to the following chips:

Digital signal processing chip: including digital signal processors, digital audio processors, etc.

And a communication chip: including modems, radio frequency transceivers, baseband processors, etc.

Analog signal processing chip: including analog signal processors, analog converters, etc.

And a power management chip: including power managers, power controllers, and the like.

Test and measurement chip: including test and measurement equipment, data collectors, etc.

Other application chips: including sensors, embedded systems, etc.

The invention also provides electronic equipment comprising any one of the phase-locked loops. The corresponding electronic device is for example: smart phones, tablet computers, wearable electronic equipment, smart home electronics, AR, VR, lidar, automobiles, etc. For another example:

Digital television set top box and digital television: PLL chips are often used in digital television set-top boxes and digital televisions for clock recovery, synchronization, frequency synthesis, and the like.

Wireless local area network routers and network switches: PLL chips are commonly used in wireless lan routers and network switches for clock synchronization, frequency synthesis, and the like.

A mobile communication device: PLL chips are often used in mobile communication devices for frequency synthesis, clock synchronization, etc.

Digital audio processor and fm radio: PLL chips are often used in digital audio processors and fm radios for clock recovery, frequency synthesis, jitter suppression, and the like.

Optical fiber communication apparatus: PLL chips are often used in fiber optic communications devices for clock recovery, frequency synthesis, synchronization, and the like.

Radar and satellite communication devices: PLL chips are often used in radar and satellite communication devices for frequency synthesis, synchronization, etc.

Data collector and test equipment: PLL chips are often used in data collectors and test equipment for frequency synthesis, clock synchronization, etc.

Power manager and power controller: PLL chips are often used in power managers and power controllers for clock synchronization, frequency synthesis, and the like.

In addition to the above devices, there are many other fields of application in which PLL chips are used, such as aerospace, automotive electronics, medical devices, industrial controls, etc.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims (14)

1. A low phase noise fractional division phase locked loop comprising:

A first oscillator outputting a first intermediate output clock of the phase-locked loop according to a first control voltage;

the first frequency divider is used for carrying out integer frequency division on the first intermediate output clock to obtain a first clock, and the frequency of the first intermediate output clock is an integer multiple of the frequency of the first clock;

A first phase detector for detecting a first phase difference between the first clock and a reference clock of a phase-locked loop and converting the first phase difference into a first control voltage to control the first oscillator;

the feedforward phase noise cancellation circuit comprises a phase difference voltage converter and a voltage-controlled cancellation sub-circuit; the phase difference voltage converter is used for converting a first phase difference between the first clock and a reference clock of the phase-locked loop into a voltage; the voltage-controlled cancellation sub-circuit is configured to control and generate a delay signal opposite to the first phase difference according to the output voltage of the phase difference voltage converter and the first intermediate output clock, and enable the first intermediate output clock to superimpose the delay signal so as to cancel the first phase difference and output a second intermediate output clock, where the second intermediate output clock is a reference clock of a second phase discriminator;

A second oscillator for outputting an output clock of the phase-locked loop according to a second control voltage;

the second frequency divider is used for performing fractional frequency division on the output clock to obtain a second clock, and the frequency of the output clock is fractional times of the frequency of the second clock;

and the second phase discriminator is used for detecting a second phase difference between the second clock and the second intermediate output clock and converting the second phase difference into a second control voltage so as to control the second oscillator.

2. The phase locked loop of claim 1 wherein the voltage controlled cancellation sub-circuit comprises: the operational amplifier, the switch S2, the fourth N-type switching tube N4, the fifth N-type switching tube N5, the third capacitor CPNC and the buffer;

The positive phase input end of the operational amplifier is connected with the output end of the phase difference voltage converter, the reverse input end of the operational amplifier is connected with one end of the switch S2, and the output end of the operational amplifier is connected with the other end of the switch S2; the input end of the buffer is grounded after sequentially passing through a fifth N-type switching tube N5 and a fourth N-type switching tube N4, the input end of the buffer is connected with one end of the third capacitor and one end of the switch S2, the output end of the buffer outputs the second intermediate output clock, the grid/base electrode of the fifth N-type switching tube N5 is connected with the first intermediate output clock, and the other end of the third capacitor is grounded.

3. The phase-locked loop of claim 2, wherein the phase-difference voltage converter includes a first capacitor, the phase-difference voltage converter is configured to control a power supply voltage to charge the first capacitor until a voltage value on the first capacitor is a voltage value of the power supply voltage, and to control the first capacitor to discharge according to the first phase difference to convert the first phase difference into a voltage, and to store the converted voltage in the first capacitor.

4. The phase locked loop of claim 2, wherein the phase difference voltage converter comprises: the first P-type switching tube P1, the second N-type switching tube N2, the third N-type switching tube N3 and the first capacitor CS1;

The gate/base electrode of the first P-type switching tube P1 is connected with a reset signal RSTB, the source/emitter electrode of the first P-type switching tube P1 is connected with a power supply voltage VDD, the drain/collector electrode of the first P-type switching tube P1 is grounded through a first capacitor CS1, and the drain/collector electrode of the first P-type switching tube P1 is connected with the drain/collector electrode of a third N-type switching tube; the grid/base electrode of the third N-type switch tube N3 is connected with the first phase difference, and the source electrode/emitter electrode of the third N-type switch tube N3 is grounded through a second N-type switch tube.

5. The phase locked loop of claim 4 wherein the phase difference voltage converter further comprises: the switch S1 and the second capacitor CS2, both ends of the switch S1 are connected with the drain electrode/collector electrode of the first P-type switching tube, and the second capacitor CS2 is connected between the drain electrode/collector electrode of the first P-type switching tube and the ground, so that when the switch S1 is closed, the first voltage on the first capacitor is transmitted to the second capacitor.

6. The phase-locked loop of claim 5 wherein the reset signal controls the first P-type switching tube to be closed to charge the first capacitor, the switch S1 being opened; after the first capacitor is discharged, the switch S1 is closed, so that the first voltage on the first capacitor is transmitted to the second capacitor.

7. The phase-locked loop of claim 6, wherein the generating a delayed signal opposite the first phase difference based on the output voltage of the phase difference voltage converter and the first intermediate output clock control, and causing the first intermediate output clock to superimpose the delayed signal, comprises:

Controlling the third capacitor to be charged until the voltage on the third capacitor is equal to the voltage output by the phase difference voltage converter and the voltage on the third capacitor is enabled to follow the voltage output by the phase difference voltage converter;

The voltage-controlled cancellation sub-circuit receives the first intermediate output clock and discharges the third capacitor when the first intermediate output clock is at a high level, so that the delay time of the buffer is reversely changed, and the voltage on the third capacitor is connected to the buffer, so that the first intermediate output clock is overlapped with the delay signal.

8. The phase locked loop of claim 5 wherein a ratio of the capacitance values of the first capacitor CS1 and the second capacitor CS2 is fixed.

9. A phase locked loop as claimed in any one of claims 3 to 8, wherein the ratio of the discharge current of the first capacitor to the discharge current of the third capacitor is a fixed value.

10. A phase locked loop as claimed in any one of claims 3 to 8, further comprising: the current source and the first N-type switch tube N1, one end of the current source is connected with the power supply voltage, the other end of the current source is grounded through the first N-type switch tube, and the current on the first N-type switch tube N1, the discharging current of the first capacitor and the discharging current of the third capacitor form mirror currents.

11. A phase locked loop as claimed in any one of claims 3 to 8, further comprising: a first charge pump and a first low-pass filter connected in sequence between the first phase detector and the first oscillator; and/or

And the second charge pump and the second low-pass filter are sequentially connected between the second phase detector and the second oscillator.

12. A phase locked loop as claimed in any one of claims 3 to 8, wherein the feedforward phase noise cancellation circuit further comprises a first phase difference sampler to collect a first phase difference between the first clock and a reference clock of the phase locked loop and output the first phase difference to the phase difference voltage converter.

13. A chip comprising a phase locked loop as claimed in any one of claims 1 to 12.

14. An electronic device comprising a phase locked loop as claimed in any one of claims 1 to 12.