CN118331641A - Instruction storage system, instruction storage method, instruction reading method and electronic device - Google Patents

Abstract

The application provides an instruction storage system, an instruction storage method, an instruction reading method and electronic equipment, and belongs to the technical field of storage. The instruction storage system comprises a processor, a storage device and an instruction reading and writing device, wherein the storage device supports at least two storage modes, the at least two storage modes comprise a first storage mode and a second storage mode, the first storage mode corresponds to an instruction which is read for a plurality of times, and the second storage mode corresponds to an instruction which is read for one time; a processor for configuring a target storage mode currently supported by the storage device; the storage device comprises a memory for storing instructions corresponding to the target storage mode; and the instruction reading and writing device is used for reading and writing the instructions in the memory. The memory device of the application supports at least two memory modes, and can store different instructions in different memory modes. Because two memories do not need to be deployed, the area of a memory chip is reduced, the cost of the electronic equipment is reduced, and the performance of the electronic equipment is improved.

Description

Instruction storage system, instruction storage method, instruction reading method and electronic device

Technical Field

The present application relates to the field of storage technology, and in particular to an instruction storage system, an instruction storage method, an instruction reading method and an electronic device.

Background technique

In the field of storage technology, the instruction reading and writing device needs to read and write the MIPI (Mobile Industry Processor Interface) instructions received by the RFIC (Radio Frequency Integrated Circuit). Considering that the instruction reading and writing device has different reading requirements for MIPI instructions in different business scenarios, in some business scenarios, the instruction reading and writing device needs to read the MIPI instructions repeatedly for multiple times, and in other business scenarios, the MIPI instructions need to be read once.

To meet the reading requirements in different business scenarios, the relevant technology configures two memories, one is a FIFO (First Input First Output) memory, and the other is a RAM (Random Access Memory). The addresses of the two memories are independent of each other. For MIPI instructions that need to be read multiple times, they can be stored in RAM, and for MIPI instructions that need to be read once, they can be stored in FIFO memory, so that the required MIPI instructions can be read from different memories in different business scenarios.

However, since two memories need to be deployed, the memory chip area of the electronic device is larger, and the larger the memory chip area, the higher the cost of the electronic device and the worse the performance.

Summary of the invention

The embodiments of the present application provide an instruction storage system, an instruction storage method, an instruction reading method and an electronic device, which can reduce the area of the storage chip of the electronic device, thereby reducing the cost of the electronic device and improving the performance of the electronic device. The technical solution is as follows:

In a first aspect, an instruction storage system is provided, the system comprising a processor, a storage device and an instruction reading and writing device, the storage device supporting at least two storage modes, the at least two storage modes comprising a first storage mode and a second storage mode, the first storage mode corresponding to instructions read multiple times, the second storage mode corresponding to instructions read once, the storage device comprising a memory;

The processor is used to configure a target storage mode currently supported by the storage device;

The memory is used to store instructions corresponding to the target storage mode;

The instruction reading and writing device is used to read and write instructions in the memory.

In a first possible implementation manner of the first aspect, the storage device further includes: a multiplexer;

The multiplexer is used to obtain the state information of the memory in the target storage mode, generate a notification message based on the state information, and send the notification message to the instruction reading and writing device;

The instruction reading and writing device is also used to execute corresponding control operations after receiving the notification message.

In a second possible implementation manner of the first aspect, the multiplexer is specifically used to obtain first status information of the memory in the target storage mode, generate a first notification message based on the first status information, and send the first notification message to the instruction reading and writing device, wherein the first status information is used to indicate that the storage space of the memory in the target storage mode is full;

The instruction reading and writing device is specifically used to stop writing instructions to the memory after receiving the first notification message reported by the storage device, when there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal.

In a third possible implementation manner of the first aspect, the multiplexer is specifically used to obtain second state information of the memory in the target storage mode, generate a second notification message based on the second state information, and send the second notification message to the instruction reading and writing device, wherein the second state information is used to indicate that the storage space of the memory in the target storage mode is about to be full;

The instruction reading and writing device is specifically used to stop writing instructions to the memory after receiving the second notification message reported by the storage device when there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal.

In a fourth possible implementation manner of the first aspect, the multiplexer is specifically used to obtain third state information of the memory in the target storage mode, generate a third notification message based on the third state information, and send the third notification message to the instruction reading and writing device, wherein the third state information is used to indicate that the instructions stored in the memory in the target storage mode have been read;

The instruction reading and writing device is specifically used to stop reading instructions in the memory after receiving the third notification message reported by the storage device and when there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal.

In a fifth possible implementation manner of the first aspect, the multiplexer is specifically used to obtain fourth state information of the memory in the target storage mode, generate a fourth notification message based on the fourth state information, and send the fourth notification message to the instruction reading and writing device, wherein the fourth state information is used to indicate that the instructions stored in the memory in the target storage mode will be read completely;

The instruction reading and writing device is specifically used to stop reading instructions in the memory after receiving the fourth notification message reported by the storage device when there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal.

In a sixth possible implementation manner of the first aspect, when the target storage mode is the first storage mode, the storage device further includes: a first comparator;

The first comparator is used to generate the state information of the memory in the first storage mode, and send the state information to the multiplexer.

In a seventh possible implementation manner of the first aspect, the first comparator is specifically used to generate first status information when the N-bit latest write address corresponding to the memory is the same as the N-bit maximum write address, and send the first status information to the multiplexer, wherein the first status information is used to indicate that the storage space of the memory in the first storage mode is full, the decimal value corresponding to the N-bit maximum write address is equal to the queue depth of the memory minus 1, and N is a positive integer;

The first comparator is specifically configured to generate second status information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, and send the second status information to the multiplexer, wherein the second status information is used to indicate that the storage space of the memory in the first storage mode is about to be full;

The first comparator is specifically used to generate the third state information when the N-bit latest read address corresponding to the memory is the same as the N-bit maximum write address, and send the third state information to the multiplexer, wherein the third state information is used to indicate that the instructions stored in the memory in the first storage mode have been read;

The first comparator is specifically used to generate fourth state information and send the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest read address is less than or equal to the second value. The fourth state information is used to indicate that the instructions stored in the memory in the first storage mode will be read.

In an eighth possible implementation manner of the first aspect, the storage device further includes: a bit selector;

The bit selector is used to obtain the N+1-bit latest read address and the N+1-bit latest write address corresponding to the memory, and use the lower N bits of the N+1-bit latest read address as the N-bit latest read address, and use the lower N bits of the N+1-bit latest write address as the N-bit latest write address;

The bit selector is further configured to send the N-bit latest read address and the N-bit latest write address to the first comparator.

In a ninth possible implementation manner of the first aspect, when the target storage mode is the second storage mode, the storage device further includes: a second comparator;

The second comparator is used to generate the state information of the memory in the second storage mode when the target storage mode is the second storage mode, and send the state information to the multiplexer.

In a tenth possible implementation manner of the first aspect, the second comparator is specifically configured to generate first status information and send the first status information to the multiplexer when the values of the highest bits of the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory are different and the values of the other bits except the highest bit are the same, wherein the first status information is used to indicate that the storage space of the memory in the second storage mode is full, and N is a positive integer;

The second comparator is specifically configured to generate second status information when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is greater than or equal to a third value, and send the second status information to the multiplexer, wherein the second status information is used to indicate that the storage space of the memory in the second storage mode is about to be full;

The second comparator is specifically used to generate third state information when the N+1-bit latest read address and the N+1-bit latest write address are the same, and send the third state information to the multiplexer, wherein the third state information is used to indicate that the instructions stored in the memory in the second storage mode have been read;

The second comparator is specifically used to generate fourth state information and send the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to a fourth value. The fourth state information is used to indicate that the instructions stored in the memory in the second storage mode will be read.

In a second aspect, an instruction storage method is provided, the method being applied to the instruction storage system according to the first aspect, the method comprising:

When the storage device is in a target storage mode, in response to an instruction write request, the instruction reading and writing device writes instructions into the memory;

In the case where there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, the instruction reading and writing device stops writing instructions to the memory after receiving the first notification message, and the first notification message is used to notify the instruction reading and writing device that the storage space of the memory in the target storage mode is full;

In the case that there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, the instruction read and write device stops writing instructions to the memory after receiving the second notification message, and the second notification message is used to notify the instruction read and write device that the storage space of the memory in the target storage mode is about to be full.

In a first possible implementation manner of the second aspect, when there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, after receiving the first notification message, before the instruction reading and writing device stops writing instructions to the memory, it also includes:

The multiplexer obtains first status information, generates the first notification message based on the first status information, and sends the first notification message to the instruction reading and writing device, wherein the first status information is used to indicate that the storage space of the memory in the target storage mode is full.

In a second possible implementation manner of the second aspect, the multiplexer acquires the first state information, including:

When the target storage mode is the first storage mode, the first comparator generates the first state information when the N-bit latest write address is the same as the N-bit maximum write address, and sends the first state information to the multiplexer;

When the target storage mode is the second storage mode, the second comparator generates the first state information and sends the first state information to the multiplexer when the values of the highest bits of the N+1-bit latest write address and the N+1-bit latest read address are different, and the values of the bits other than the highest bit are the same.

In a third possible implementation manner of the second aspect, in a case where there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, after receiving the second notification message, before the instruction reading and writing device stops writing instructions to the memory, it also includes:

The multiplexer obtains second status information, generates the second notification message based on the second status information, and sends the second notification message to the instruction reading and writing device, wherein the second status information is used to indicate that the storage space of the memory in the target storage mode is about to be full.

In a fourth possible implementation manner of the second aspect, the multiplexer acquires the second state information, including:

When the target storage mode is the first storage mode, the first comparator generates the second state information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, and sends the second state information to the multiplexer;

When the target storage mode is the second storage mode, the second comparator generates the second state information when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is greater than or equal to a third value, and sends the second state information to the multiplexer.

In a third aspect, an instruction reading method is provided, the method being applied to the instruction storage system according to the first aspect, the method comprising:

When the storage device is in a target storage mode, in response to an instruction read request, the instruction read-write device reads an instruction from the memory;

In the case where there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, the instruction reading and writing device stops reading instructions in the memory after receiving the third notification message, and the third notification message is used to notify the instruction reading and writing device that the instructions stored in the memory in the target storage mode have been read;

In the case where there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, the instruction read-write device stops reading the instructions in the memory after receiving the fourth notification message, and the fourth notification message is used to notify the instruction read-write device that the instructions stored in the memory in the target storage mode will be read.

In a first possible implementation manner of the third aspect, when there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, after receiving the third notification message, before the instruction reading and writing device stops reading the instruction in the memory, it also includes:

The multiplexer obtains third status information, generates the third notification message based on the third status information, and sends the third notification message to the instruction reading and writing device, wherein the third status information is used to indicate that the instructions stored in the memory in the target storage mode have been read.

In a second possible implementation manner of the third aspect, the multiplexer acquires the third state information, including:

When the target storage mode is the first storage mode, the first comparator generates the third state information when the N-bit latest read address is the same as the N-bit maximum write address, and sends the third state information to the multiplexer;

When the target storage mode is the second storage mode, the second comparator generates the third state information when the N+1-bit latest read address and the N+1-bit latest write address are the same, and sends the third state information to the multiplexer.

In a third possible implementation manner of the third aspect, in a case where there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, after receiving the fourth notification message, the instruction reading and writing device stops reading instructions in the memory, further comprising:

The multiplexer obtains fourth status information, generates the fourth notification message based on the fourth status information, and sends the fourth notification message to the instruction reading and writing device, wherein the fourth status information is used to indicate that the instructions stored in the memory in the target storage mode will be read out.

In a fourth possible implementation manner of the third aspect, the multiplexer acquires the fourth state information, including:

When the target storage mode is the first storage mode, the first comparator generates the fourth state information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the latest read address is less than or equal to the second value, and sends the fourth state information to the multiplexer;

When the target storage mode is the second storage mode, the second comparator generates the fourth state information and sends the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to the fourth value.

According to a fourth aspect, an electronic device is provided, wherein the electronic device comprises the instruction storage system according to the first aspect.

In a fifth aspect, a computer-readable storage medium is provided, in which at least one computer program is stored. When the at least one computer program is executed by a processor, it can implement the instruction storage method described in the second aspect or the instruction reading method described in the third aspect.

In a sixth aspect, a computer program product is provided, the computer program product comprising a computer program, and when the computer program is executed by a processor, it can implement the instruction storage method described in the second aspect, or the instruction reading method described in the third aspect.

The beneficial effects of the technical solution provided by the embodiment of the present application are:

The instruction storage system provided in the embodiment of the present application includes a storage device, which supports at least two storage modes, and the at least two storage modes include a first storage mode and a second storage mode. When the storage device is in the first storage mode, the memory included in the storage device can store instructions that need to be read multiple times, and when the storage device is in the second storage mode, the memory included in the storage device can store instructions that need to be read once. Since there is no need to deploy two memories, the storage of instructions in different business scenarios can be achieved by deploying one storage device, which reduces the number of memories, and accordingly the area of the internal storage chip of the electronic device will also be reduced. As the area of the storage chip is reduced, the cost of the electronic device is reduced and the performance is improved.

In addition, the storage device provided in the embodiment of the present application is capable of monitoring the read and write status of the memory. In the instruction writing scenario, when it is monitored that the storage space of the memory is full, the storage device reports a first notification message to the instruction read and write device, and the instruction read and write device stops writing instructions to the memory when there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal; when it is monitored that the storage space of the memory is about to be full, the storage device reports a second notification message to the instruction read and write device, and the instruction read and write device stops writing instructions to the memory when there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal. In the instruction reading scenario, when it is detected that the instructions stored in the memory have been read, the storage device reports a third notification message to the instruction reading and writing device, and the instruction reading and writing device stops reading the instructions in the memory when there is no read delay between receiving the third notification message reported by the storage device and closing the write enable signal; when it is detected that the instructions stored in the memory are about to be read, the storage device reports a fourth notification message to the instruction reading and writing device, and the instruction reading and writing device stops reading the instructions in the memory when there is a read delay between receiving the fourth notification message reported by the storage device and closing the write enable signal. By monitoring the read and write status of the memory, the performance of the electronic device is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1 is a design architecture diagram of an instruction system provided by related technology;

FIG2 is a design architecture diagram of an instruction storage system provided in an embodiment of the present application;

FIG3 is a schematic diagram of the structure of an instruction storage system provided in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of another instruction storage system provided in an embodiment of the present application;

5 is a schematic diagram of a reading and writing process in a first storage mode provided in an embodiment of the present application;

6 is a schematic diagram of a reading and writing process in a second storage mode provided in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of another instruction storage system provided in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of another instruction storage system provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of another instruction storage system provided in an embodiment of the present application;

10 is a schematic diagram of a logic process for determining the empty or full state of a memory in different storage modes provided by an embodiment of the present application;

FIG11 is a flow chart of an instruction storage method provided in an embodiment of the present application;

FIG12 is a flow chart of an instruction reading method provided in an embodiment of the present application;

13 is an overall flow chart of instruction reading and writing based on an instruction storage system provided in an embodiment of the present application;

FIG. 14 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present application more clear, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

It can be understood that the terms "each", "multiple", and "any" used in the embodiments of the present application include two or more, each refers to each of the corresponding multiple, and any refers to any one of the corresponding multiple. For example, the multiple words include 10 words, and each word refers to each word of the 10 words, and any word refers to any one of the 10 words.

It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

Before executing the embodiments of the present application, the terms involved in the embodiments of the present application are first explained.

FIFO stands for First In First Out, which means the first instruction to enter is completed and retired first. Based on the FIFO mechanism, the FIFO memory can be used to store instructions that need to be read once. The instructions in the FIFO memory are read in the order of their entry time and are cleared after reading.

RAM can be used to store instructions that need to be read multiple times. Instructions in RAM can be read in the order of their entry time or randomly, and they will not be cleared after reading.

The sequencer is an important component in digital circuits and computer architecture, responsible for coordinating and controlling the operation sequence of each functional unit to ensure that data is transmitted and processed at the correct time.

CMD is the Windows command prompt, a command line operation tool of the Windows system. Users can complete various system or program operations by entering commands.

MCU (Microcontroller Unit), also known as single-chip microcomputer, appropriately reduces the main frequency and specifications of CPU (Central Process Unit), and integrates multiple functional modules and interfaces such as memory, timer, A/D conversion, clock, I/O port and serial communication on a single chip to realize the function of electronic device control. It has the advantages of high performance, low power consumption, programmability and high flexibility.

MUX (Multiplexer) is a combinational logic circuit with multiple inputs and a single output. An n-input multiplexer is an n-channel digital switch that can select one output from n inputs to a common output terminal according to different channel selection control signals.

In the field of radio frequency communication, for different business scenarios, RFIC will receive MIPI instructions with different reading requirements. In order to facilitate the management of MIPI instructions with different reading requirements, the relevant technology provides an instruction storage system, which includes two memories, one is a memory with a FIFO function (i.e., a FIFO memory), and the other is a memory with a RAM function (i.e., a RAM memory). Referring to Figure 1, for the instruction received by the RFIC, if the instruction is an instruction that needs to be read once, it can be stored in the FIFO memory; if the instruction is an instruction that needs to be read multiple times, it can be stored in the RAM memory. When the instruction needs to be read due to business needs, the instruction can be read from the corresponding memory, and then the read instruction can be loaded into the CMD process to implement the corresponding function.

The instruction storage system provided by the related art solves the problem of managing instructions with different reading requirements, but two memories need to be deployed. The more memories deployed inside the electronic device, the larger the area of the electronic device's memory chip, and the larger the area of the electronic device's memory chip, the higher the cost of the electronic device, the higher the power consumption, and the worse the performance.

The embodiment of the present application designs an instruction storage system, which includes a storage device, which includes a memory (Sequencer Memory), which has the functions of a FIFO memory and a RAM memory, and the memory has a set of read and write addresses and a storage queue. Referring to Figure 2, for the instructions received by the RFIC, whether the instructions are instructions that need to be read once or instructions that need to be read multiple times, they can be stored in the storage queue of the memory. When the instructions need to be read due to business needs, the instructions can be read from the memory, and then the read instructions can be loaded into the CMD process to implement the corresponding functions. Using the embodiment of the present application, only one memory needs to be deployed to realize the reading and writing of instructions with different reading requirements. Compared with the related art, the number of deployed memories is less, which reduces the area of the memory chip of the electronic device, reduces the cost and power consumption of the electronic device, and improves the performance of the electronic device.

In addition, the storage space of the memory is limited. In order to avoid write overflow of the memory and to avoid abnormal instruction reading in the memory, the memory needs to have an identification bit to indicate the empty and full status of the storage. Usually, the FIFO memory has an identification bit, through which the empty and full status of the FIFO memory can be known, while the RAM memory does not have an identification bit, and the empty and full status of the RAM memory cannot be known. The RAM memory included in the instruction storage system provided by the related art does not have an identification bit, so the empty and full status of the RAM memory cannot be determined, which makes it difficult for the system to perform read and write operations and flow control. The instruction storage system provided in the embodiment of the present application can determine the empty and full status of the memory regardless of the storage mode of the memory, which facilitates the system to perform read and write operations and flow control.

3 , an instruction storage system provided in an embodiment of the present application includes a processor 301 , a storage device 302 , and an instruction reading and writing device 303 .

The storage device 302 supports at least two storage modes, including a first storage mode and a second storage mode, etc. The first storage mode corresponds to instructions that need to be read multiple times, and the second storage mode corresponds to instructions that need to be read once. To realize the storage function, the storage device 302 includes a memory 3021. When the storage device 302 is in the first storage mode, the memory 3021 has the function of a RAM memory and can store instructions that need to be read multiple times. When the storage device 302 is in the second storage mode, the memory 3021 has the function of a FIFO memory and can store instructions that need to be read once. To facilitate the management of the stored instructions, the memory 3021 has a storage queue, and the queue depth of the storage queue can be 64, 128, etc. To facilitate the reading and writing of the stored instructions, the memory 3021 has a set of read and write addresses, and the set of read and write addresses can be represented by an N-bit binary number. Among them, N is a positive integer and can be determined according to the queue depth of the storage queue. For example, if the queue depth of the storage queue is 64, N can be 6; if the queue depth of the storage queue is 128, N can be 7. Each storage location of the storage queue corresponds to a write address and a read address, the write address can be expressed as seq_waddr[N-1:0], and the read address can be expressed as seq_raddr[N-1:0]. Assuming that the queue depth of the storage queue of the memory 3021 is 64, it can be determined that N is 6, the write address corresponding to each storage location can be expressed as seq_waddr[5:0], and the read address corresponding to each storage location can be expressed as seq_waddr[5:0].

Among them, the processor 301 can be an MCU, etc., and the embodiment of the present application does not make specific limitations on the processor 301. The processor 301 can configure the target storage mode currently supported by the storage device 302. When configuring the target storage mode currently supported by the storage device 302, the processor 301 can be configured according to the current business scenario. For example, in the current business scenario, it is necessary to read the instructions in the storage device 302 multiple times, and the target storage mode can be configured as the first storage mode; in the current business scenario, it is necessary to read the instructions in the storage device 302 once, and the target storage mode can be configured as the second storage mode. Based on the target storage mode configured by the processor 301, the memory 3021 can store instructions corresponding to the target storage mode.

The instruction reading and writing device 303 is used to read and write instructions in the memory 3021. Specifically, in response to an instruction writing request, the instruction reading and writing device 303 can write instructions to the memory 3021; in response to an instruction writing request, the instruction reading and writing device 303 can read instructions from the memory 3021. The instructions stored in the memory 3021 can be represented by an M-bit binary number, where M is a positive integer, and the value of M is generally greater than or equal to 2, and can be 64, 128, etc. In order to distinguish between instructions written to the memory and instructions read from the memory 3021, the instructions written to the memory 3021 can be represented as Seq_wr_cmd[M-1:0], and the instructions read from the memory 3021 can be represented as Seq_rd_cmd[M-1:0]. When the instructions stored in the memory 3021 are represented by 128-bit binary numbers, the instructions written to the memory 3021 can be represented as Seq_wr_cmd[127:0], and the instructions read from the memory 3021 can be represented as Seq_rd_cmd[127:0].

The storage device 302 of the embodiment of the present application supports at least two storage modes. By configuring the target storage mode currently supported by the storage device, instructions that need to be read once and instructions that need to be read multiple times can be stored in the same memory. Since one memory can realize the functions of multiple memories, a small amount of memory can be deployed inside the electronic device, thereby reducing the area of the memory chip of the electronic device, reducing the cost and power consumption of the electronic device, and improving the performance of the electronic device.

Referring to FIG. 4 , the storage device 302 provided in the embodiment of the present application further includes: a multiplexer 3022. The multiplexer 3022 is used to obtain the state information of the memory in the target storage mode, generate a notification message based on the state information, and send the notification message to the instruction reading and writing device 303. After receiving the notification message, the instruction reading and writing device 303 can perform corresponding control operations. The state information is used to indicate the empty and full state of the memory in the target storage mode, and may include first state information, second state information, third state information, and fourth state information. Among them, the first state information is used to indicate that the storage space of the memory is full, the second state information is used to indicate that the storage space of the memory is about to be full, the third state information is used to indicate that the instructions stored in the memory have been read, and the fourth state information is used to indicate that the instructions stored in the memory will be read. Accordingly, the notification message includes a first notification message, a second notification message, a third notification message, and a fourth notification message. Among them, the first notification message corresponds to the first status information, and is used to notify that the storage space of the instruction read and write device 303 memory is full; the second notification message corresponds to the second status information, and is used to notify that the storage space of the instruction read and write device 303 memory is about to be full; the third notification message corresponds to the third status information, and is used to notify that the instructions stored in the instruction read and write device 303 memory have been read; the fourth notification message corresponds to the fourth status information, and is used to notify that the instructions stored in the instruction read and write device 303 memory are about to be read.

Generally speaking, in the instruction writing scenario, the instruction reading and writing device will generate a write enable signal. In response to the write enable signal, instructions can be written to the memory. When the write enable signal is turned off, instructions are no longer written to the memory. In the instruction reading scenario, the instruction reading and writing device will generate a read enable signal. In response to the read enable signal, instructions can be read from the memory. When the write enable signal is turned off, instructions are no longer read from the memory. According to the different status information of the memory and whether there is a delay between the notification message reported by the instruction reading and writing device and the instruction reading and writing device turning off the enable signal, it can be divided into the following situations:

In the first case, the multiplexer 3022 obtains the first state information of the memory 3021 in the target storage mode, generates a first notification message based on the first state information, and then sends the first notification message to the instruction reading and writing device 303. When there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, the instruction control device 303 stops writing instructions to the memory after receiving the first notification message to avoid write overflow.

In the second case, the multiplexer 3022 obtains the second state information of the memory 3021 in the target storage mode, generates a second notification message based on the second state information, and then sends the second notification message to the instruction reading and writing device 303. When there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, the instruction reading and writing device 303 stops writing instructions to the memory after receiving the second notification message, thereby avoiding instruction write overflow in the memory 3021.

In the third case, the multiplexer 3022 obtains the third state information of the memory 3021 in the target storage mode, generates a third notification message based on the third state information, and then sends the third notification message to the instruction reading and writing device 303. When there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, the instruction reading and writing device 303 stops reading the instructions in the memory after receiving the third notification message, thereby avoiding abnormal instruction reading.

In the fourth case, the multiplexer 3022 obtains the fourth state information of the memory 3021 in the target storage mode, generates a fourth notification message based on the fourth state information, and then sends the fourth notification message to the instruction reading and writing device 303. When there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, the instruction reading and writing device 303 stops reading the instructions in the memory after receiving the fourth notification message, thereby not only ensuring that all instructions in the memory 3021 are read out, but also avoiding instruction reading errors.

In the embodiment of the present application, the storage device 302 supports the first storage mode and the second storage mode. When the storage device 302 is in different storage modes, the instruction reading and writing mechanism of the instruction reading and writing device 303 for the instructions in the memory 3021 included in the storage device 302 is different. When the storage device 302 is in the first storage mode, the memory 3021 stores instructions that need to be read multiple times, and the stored instructions will not be cleared after reading, that is, the number of instructions stored in the memory 3021 is fixed. For example, FIG5 shows the memory 3021 in the first storage mode. Referring to FIG5, the queue depth of the storage queue of the memory 3021 is 64, corresponding to 64 storage locations, and the 64 storage locations are numbered from 0 to 63, and each storage location corresponds to a read address and a write address. Assuming that the read address and the write address are both represented by 6-bit binary numbers, the write address of each storage location can be represented as seq_waddr[5:0], and the read address of each storage location can be represented as seq_raddr[5:0]. Assuming that the reading and writing processes are carried out simultaneously, in response to the first instruction write request, the instruction read and write device 303 starts writing instructions from the storage location numbered 2. In response to the first instruction read request, the instruction read and write device 303 starts reading instructions from the storage location numbered 0. After multiple clock cycles, the instruction read and write device 303 fills the memory 3021, while the instructions read from the memory 3021 are not cleared.

When the storage device 302 is in the second storage mode, the memory 3021 stores instructions that need to be read once. Since the stored instructions will be cleared after reading, the number of instructions stored in the memory 3021 is not fixed. Assuming that the read and write operations of the memory 3021 are performed simultaneously, and the read speed and the write speed are the same, the memory 3021 can store an unlimited number of instructions. For example, FIG6 shows the memory 3021 in the second storage mode. Referring to FIG6, the queue depth of the storage queue of the memory 3021 is 64, corresponding to 64 storage locations, and the 64 storage locations are numbered from 0 to 63. Each storage location corresponds to a read address and a write address. Assuming that the read address and the write address are both represented by 6-bit binary numbers, the write address of each storage location can be represented as seq_waddr[5:0], and the read address of each storage location can be represented as seq_raddr[5:0]. Assuming that the reading and writing processes are carried out simultaneously, in response to the first instruction write request, the instruction read and write device 303 starts writing instructions from the storage location numbered 2. In response to the first instruction read request, the instruction read and write device 303 starts reading instructions from the storage location numbered 0. After multiple clock cycles, the read instructions are cleared. After the instruction read and write device 303 writes instructions to the storage location numbered 63, it jumps to the storage location numbered 0 to continue writing. Correspondingly, after the instruction read and write device 303 reads instructions from the storage location numbered 63, it jumps to the storage location numbered 0 to continue reading.

Through the above analysis, it can be seen that when the memory 3021 is in different storage modes, the instruction reading and writing device 303 reads and writes instructions in the memory 3021 in different ways, and the judgment logic of the empty and full state of the memory 3021 is also different. Correspondingly, the multiplexer 3022 obtains the state information of the memory 3021 in a different way. For different storage modes, the embodiment of the present application deploys different comparators, and then based on different comparators, generates the state information of the empty and full state of the memory 3021 in different storage modes.

Referring to FIG. 7 , when the target storage mode is the first storage mode, the storage device further includes: a first comparator 3023. The first comparator 3023 is used to generate state information of the memory 3021 in the first storage mode, and send the state information to the multiplexer 3022. In the embodiment of the present application, the state information includes first state information, second state information, third state information and fourth state information, and the empty and full states of the memory indicated by different state information are different. For different state information, the judgment logic of the first comparator 3023 is different. Specifically, the following situations are included:

In the first case, the first comparator 3023 obtains the N-bit latest write address and the N-bit maximum write address corresponding to the memory 3021. Since the number of instructions stored in the memory 3021 in the first storage mode is fixed and will not be cleared after reading, the N-bit maximum write address can be the address corresponding to the last storage position of the storage queue when writing instructions to the memory 3021. The decimal value corresponding to the N-bit maximum write address is the queue depth of the memory 3021 minus 1. For example, if the queue depth of the memory 3021 is 64, the decimal value corresponding to the N-bit maximum write address is 63, which is converted into a binary number and represented as 111111. Based on the obtained N-bit latest write address and N-bit maximum write address, the first comparator 3023 compares the N-bit latest write address with the N-bit maximum write address. If the N-bit latest write address corresponding to the memory 3021 is the same as the N-bit maximum write address, it means that the instruction has been written to the last storage position of the storage queue of the memory 3021. At this time, the first comparator 3023 can determine that the storage space of the memory 3021 is full, and then generate the first state information indicating that the storage space of the memory 3021 is full, and then send the first state information to the multiplexer 3022. For example, if the 6-bit maximum write address corresponding to the memory 3021 is 111111, and the first comparator 3023 obtains the 6-bit latest write address as 111111, it can be determined that the storage space of the memory 3021 is full, and then generate the first state information, and then send the generated first state information to the multiplexer 3022.

In the second case, the first comparator 3023 obtains the N-bit latest write address and the N-bit maximum write address corresponding to the memory 3021, converts the binary representation of the N-bit latest write address into the corresponding decimal value, and converts the binary representation of the N-bit maximum write address into the corresponding binary value, and then compares the decimal value corresponding to the N-bit maximum write address with the decimal value corresponding to the N-bit latest write address. Since the number of instructions stored in the memory 3021 in the first storage mode is fixed and will not be cleared after reading, the binary value corresponding to each write address can indicate the number of each storage location. When the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, it means that the storage location of the latest write instruction in the memory 3021 is close to the last storage location. The first comparator 3023 can determine that the storage space of the memory 3021 is about to be full, and then generate the second state information for indicating that the storage space of the memory 3021 is about to be full, and then send the second state information to the multiplexer 3022. The first value can be 1, 2, etc. For example, the first value is 3, the decimal value corresponding to the 6-bit maximum write address is 63, the decimal value corresponding to the 6-bit latest write address is 61, and the difference between the decimal value corresponding to the 6-bit maximum write address and the decimal value corresponding to the 6-bit latest write address is 2, which is less than the first value 3. The first comparator 3023 can determine that the storage space of the memory 3021 is about to be full, and then generate second status information.

In the third case, the first comparator 3023 obtains the N-bit latest read address and the N-bit maximum write address corresponding to the memory 3021, and compares the N-bit latest read address with the N-bit maximum write address. Since the number of instructions stored in the memory 3021 is fixed in the first storage mode and will not be cleared after reading, when the N-bit latest read address is the same as the N-bit maximum write address, it means that the instruction at the last storage position in the storage queue of the memory 3021 has been read, and the first comparator 3023 can generate the third state information indicating that the instruction in the memory 3021 has been read, and then send the third state information to the multiplexer 3022. For example, the 6-bit maximum write address is 111111, the 6-bit latest read address is 111111, the 6-bit maximum write address is the same as the 6-bit latest read address, and the first comparator 3023 can determine that the instruction stored in the memory 3021 has been read, and then generate the third state information.

In the fourth case, the first comparator 3023 obtains the N-bit latest read address and the N-bit maximum write address corresponding to the memory 3021, converts the binary N-bit latest read address into the corresponding decimal value, and converts the binary N-bit maximum read address into the corresponding decimal value, and then compares the decimal value corresponding to the N-bit maximum write address with the decimal value corresponding to the latest read address. Since the number of instructions stored in the memory 3021 is fixed in the first storage mode and will not be cleared after reading, when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the latest read address is less than or equal to the second value, it means that the latest read position is close to the last storage position in the storage queue of the memory 3021. The first comparator 3023 can determine that the instructions stored in the memory will be read, and then generate the fourth state information for indicating that the instructions in the memory 3021 are about to be read, and then send the fourth state information to the multiplexer 3022. Among them, the second value can be 3, 4, etc. For example, the second value is 3, the decimal value corresponding to the 6-bit maximum write address is 63, the decimal value corresponding to the 6-bit latest read address is 61, and the difference between the decimal value corresponding to the 6-bit maximum write address and the decimal value corresponding to the 6-bit latest read address is 2, which is less than the second value 3. The first comparator 3023 can determine that the instructions stored in the memory 3021 will be read, and then generate the fourth state information.

In the embodiment of the present application, the storage address at each storage position in the storage queue of the memory 3021 is N bits, corresponding to the queue depth of the storage queue of the memory 3021. In the first storage mode, the instructions stored in the memory 3021 will not be cleared after reading, and the empty and full state of the memory 3021 can be judged by using the N-bit address, while in the second storage mode, the instructions stored in the memory 3021 will be cleared after reading, and the instructions can be written cyclically, and the use of the N-bit address is not convenient for judging the empty and full state of the memory 3021 in the second storage mode. In order to enable the empty and full state of the memory 3021 to be judged in different storage modes, after performing a read and write operation on the memory 3021, the N-bit latest read address and the N-bit latest write address can be expanded by one bit to obtain the N+1-bit latest read address and the N+1-bit latest write address, and then the N+1-bit latest read address and the N+1-bit latest write address are provided to the device for judging the empty and full state of the memory 3021. Since the first comparator 3023 performs empty or full state judgment based on the N-bit latest read address and the N-bit latest write address, in order to implement the judgment logic of the first comparator 3032, referring to FIG8 , the storage device 302 further includes: a bit selector 3024. The bit selector 3024 is used to obtain the N+1-bit latest read address and the N+1-bit latest write address corresponding to the memory 3021, use the lower N bits of the N+1-bit latest read address as the N-bit latest read address, and use the lower N bits of the N+1-bit latest write address as the N-bit latest write address, and then send the N-bit latest read address and the N-bit latest write address to the first comparator 3023. For example, the bit selector 3024 obtains the 7-bit latest read address as 0111100, the 7-bit latest write address as 0111111, obtains the lower 6 bits from the 7-bit latest read address, and obtains the 6-bit latest read address as 111100, and obtains the lower 6 bits from the 7-bit latest write address, and obtains the 6-bit latest write address as 111111.

The first and second cases mentioned above are aimed at the scenario of writing instructions into the memory 3021 in the first storage mode, and the third and fourth cases are aimed at the scenario of reading instructions from the memory 3021 in the first storage mode.

Referring to FIG9 , when the target storage mode is the second storage mode, the storage device further includes: a second comparator 3025. The second comparator 3025 can generate state information of the memory 3021 in the second storage mode, and then send the generated state information to the multiplexer 3022. In the embodiment of the present application, the state information includes first state information, second state information, third state information and fourth state information, and the empty and full states of the memory indicated by different state information are different. For different state information, the judgment logic of the second comparator 3025 is different. Specifically, the following situations are included:

In the first case, the second comparator 3025 obtains the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory 3021, and compares the N+1-bit latest write address and the N+1-bit latest read address. Since the number of instructions stored in the memory 3021 is not fixed in the second storage mode, the instruction will be cleared after reading. After the instruction is written to the last storage position in the storage queue, it can jump to the starting storage position of the storage queue to continue writing the instruction. When the instruction written to the last storage position in the storage queue jumps to the starting storage position of the storage queue, the starting storage position of the storage queue will become the highest bit value 1, and the other low N bits are 0, and the read and write operations can be performed synchronously. When the highest bits of the N+1-bit latest write address and the N+1-bit latest read address are different, and the values of the bits other than the highest bit are the same, it means that the instructions corresponding to the read and write operations differ by one storage queue. At this time, the second comparator 3025 can generate the first state information for indicating that the storage space of the memory 3021 is full, and then send the first state information to the multiplexer 3022. For example, the instruction reading and writing device 303 only performs a write operation without performing a read operation, the 7-bit latest write address is 1000000, and the 7-bit latest read address is 0000000, and the second comparator 3025 can determine that the storage space of the memory 3021 is full, and then generate the first state information. For another example, the instruction reading and writing device 303 performs a write operation and a read operation simultaneously, the 7-bit latest write address is 1000010, and the 7-bit latest read address is 0000010, and the second comparator 3025 can determine that the storage space of the memory 3021 is full, and then generate the first state information.

In the second case, the second comparator 3025 obtains the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory 3021, converts the binary representation of the N+1-bit latest write address into a decimal value, and converts the binary representation of the N+1-bit latest read address into a decimal value, and then compares the decimal value corresponding to the N+1-bit latest write address with the decimal value corresponding to the N+1-bit latest read address. If the decimal value corresponding to the N+1-bit latest write address is greater than the decimal value corresponding to the N+1-bit latest read address, then the decimal value corresponding to the N+1-bit latest write address is subtracted from the decimal value corresponding to the N+1-bit latest read address. If N+1 If the decimal value corresponding to the latest write address of the N+1 bit is less than the decimal value corresponding to the latest read address of the N+1 bit, the decimal value corresponding to the latest read address of the N+1 bit is subtracted from the decimal value corresponding to the latest write address of the N+1 bit. Since the number of instructions stored in the memory 3021 in the second storage mode is not fixed, the instructions will be cleared after reading. When the difference between the decimal value corresponding to the latest write address of the N+1 bit and the decimal value corresponding to the latest read address of the N+1 bit is greater than or equal to the third value, the second comparator 3025 can determine that the storage space of the memory 3021 is about to be full, and then generate the second state information, and then send the second state information to the multiplexer 3022. The third value can be 62, 63, etc. For example, assuming that the third value is 62, the decimal value corresponding to the 7-bit latest write address is 67, the decimal value corresponding to the 7-bit latest read address is 3, and the difference between the decimal value corresponding to the 7-bit latest write address and the decimal value corresponding to the 7-bit latest read address is 64, which is greater than the third value 62. The second comparator 3025 can determine that the storage space of the memory 3021 is about to be full, and then generate second status information.

In the third case, the second comparator 3025 obtains the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory 3021, and compares the N+1-bit latest read address with the N+1-bit latest write address. Since the number of instructions stored in the memory 3021 is not fixed in the second storage mode, the instructions will be cleared after reading. When the N+1-bit latest read address and the N+1-bit latest write address are the same, the second comparator 3025 can determine that the instructions stored in the memory 3021 have been read empty, and then generate the third state information, and then send the third state information to the multiplexer 3022. For example, the 7-bit latest write address is 0001111, the 7-bit latest read address is 0001111, the 7-bit latest write address is the same as the 7-bit latest read address, and the second comparator 3025 can determine that the instructions stored in the memory have been read, and then generate the third state information.

In the fourth case, the second comparator 3025 obtains the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory 3021, converts the binary representation of the N+1-bit latest write address into a decimal value, and converts the binary representation of the N+1-bit latest read address into a decimal value, and then compares the decimal value corresponding to the N+1-bit latest write address with the decimal value corresponding to the N+1-bit latest read address. Since the number of instructions stored in the memory 3021 is not fixed in the second storage mode, the instructions will be cleared after reading. When the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to the fourth value, the second comparator 3025 can determine that the instruction stored in the memory 3021 will be read empty, and then generate the fourth state information, and then send the fourth state information to the multiplexer 3022. The fourth value can be 3, 4, etc. For example, assuming that the fourth value is 4, the decimal value corresponding to the 7-bit latest write address is 63, the decimal value corresponding to the 7-bit latest read address is 61, and the difference between the decimal value corresponding to the 7-bit latest write address and the decimal value corresponding to the 7-bit latest read address is 2, which is less than the fourth value 3. The second comparator 3025 can determine that the instructions stored in the memory 3021 will be read, and then generate the fourth state information.

The first and second cases mentioned above are aimed at the scenario of writing instructions into the memory 3021 in the second storage mode, and the third and fourth cases are aimed at the scenario of reading instructions from the memory 3021 in the second storage mode.

In the embodiment of the present application, when the storage device 302 is in the first storage mode, the multiplexer 3022 selects to obtain the state information of the memory 3021 from the first comparator 3023; when the storage device 302 is in the second storage mode, the multiplexer 3022 selects to obtain the state information of the memory 3021 from the second comparator 3025. By obtaining the state information of the memory 3021 from different comparators, the empty and full states of the memory 3021 in different storage modes are monitored, write overflow and read abnormalities are avoided, and the performance of the system is improved.

FIG10 shows a process for judging the empty or full state of a memory included in a storage device in different storage modes. Referring to FIG10 , when the storage device is in the first storage mode, the bit selector obtains the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0] corresponding to the memory, obtains the lower 6 bits from the 7-bit latest write address Seq_waddr_ptr[6:0] to obtain the 6-bit latest write address Seq_waddr_ptr[5:0], and obtains the lower 6 bits from the 7-bit latest read address Seq_raddr _ptr[6:0] to obtain the 6-bit latest read address Seq_raddr_ptr[5:0], and then provide the 6-bit latest write address Seq_waddr_ptr[5:0] and the 6-bit latest read address Seq_raddr_ptr[5:0] to the first comparator. The first comparator generates the status information of the memory based on the latest write address Seq_waddr_ptr[5:0] and the 6-bit latest read address Seq_raddr_ptr[5:0], which are ram_almost_full (almost full in the first storage mode), ram_full (full in the first storage mode), ram_almost_empty (almost empty in the first storage mode), and ram_empty (empty in the first storage mode). Then, the status information in the first storage mode generated is sent to the multiplexer.

Referring to Figure 10, when the storage device is in the second storage mode, the second comparator obtains the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0] corresponding to the memory, and generates status information of the memory based on the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0], which are fifo_almost_full (almost full in the second storage mode), fifo_full (full in the second storage mode), fifo_almost_empty (almost empty in the second storage mode), and fifo_empty (empty in the second storage mode), and then sends the generated status information in the second storage mode to the multiplexer.

The multiplexer generates corresponding notification messages based on the empty and full status information in different storage modes, namely Seq_almost_full (the storage space is about to be full), Seq_full (the storage space is already full), Seq_almost_empty (the storage space is about to be empty), and Seq_empty (the storage space is already full), and then sends the generated notification messages to the instruction read and write device, so that the instruction read and write device can read and write instructions in the memory according to the empty and full status of the memory.

The embodiment of the present application provides an instruction storage method. Taking the instruction storage system provided in the above embodiment as an example to execute the embodiment of the present application, see FIG. 11 , the method flow provided in the embodiment of the present application is as follows:

1101. When the storage device is in a target storage mode, in response to an instruction write request, the instruction read/write device writes instructions into the memory.

The target storage mode is the first storage mode or the second storage mode. When an instruction needs to be written into the instruction storage system due to business needs, an instruction write request is sent to the instruction storage system, and in response to the instruction write request, the instruction reading and writing device of the instruction storage system writes the instruction into the memory included in the storage device.

1102. In a case where there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, after receiving the first notification message, the instruction reading and writing device stops writing instructions to the memory.

The first notification message is used to notify the instruction reading and writing device that the storage space of the memory in the target storage mode is full. The first notification message is obtained by the multiplexer from the first state information and is generated based on the first state information.

In the implementation of the present application, the target storage mode can be the first storage mode or the second storage mode. When the storage device is in different storage modes, different comparators will monitor the empty and full states of the storage. Specifically, when the target storage mode is the first storage mode, the first comparator obtains the latest N-bit write address and the maximum N-bit write address. When the latest N-bit write address is the same as the maximum N-bit write address, the first comparator generates first state information and sends the first state information to the multiplexer; when the target storage mode is the second storage mode, the second comparator obtains the latest N+1-bit write address and the latest N+1-bit read address. When the values on the highest bits of the latest N+1-bit write address and the latest N+1-bit read address are different, and the values on the bits other than the highest bit are the same, the second comparator generates first state information and sends the first state information to the multiplexer.

1103. In the case where there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, after receiving the second notification message, the instruction reading and writing device stops writing instructions to the memory.

The second notification message is used to notify the instruction reading and writing device that the storage space of the memory in the target storage mode is about to be full. The second notification message is obtained by the multiplexer from the second state information and is generated based on the second state information.

In the implementation of the present application, the target storage mode can be the first storage mode or the second storage mode. When the storage device is in different storage modes, different comparators will monitor the empty and full states of the storage. Specifically, when the target storage mode is the first storage mode, the first comparator obtains the N-bit maximum write address and the N-bit latest write address, converts the binary representation of the N-bit maximum write address into a decimal value, and converts the binary representation of the N-bit latest write address into a decimal value, and then calculates the difference between the decimal value corresponding to the N-bit maximum write address and the N-bit latest write address. When the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, the first comparator generates second state information and sends the second state information to the multiplexer; when the target storage mode is the second storage mode, the second comparator obtains the N+1-bit latest write address and the N+1-bit latest read address, converts the binary representation of the N+1-bit latest write address into a decimal value. Value, and convert the binary representation of the N+1-bit latest read address into a decimal value. If the decimal value corresponding to the N+1-bit latest write address is greater than the decimal value corresponding to the N+1-bit latest read address, the decimal value corresponding to the N+1-bit latest write address is subtracted from the decimal value corresponding to the N+1-bit latest read address. If the decimal value corresponding to the N+1-bit latest write address is less than the decimal value corresponding to the N+1-bit latest read address, the decimal value corresponding to the N+1-bit latest read address is subtracted from the decimal value corresponding to the N+1-bit latest write address. When the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is greater than or equal to the third value, the second comparator generates second state information and sends the second state information to the multiplexer.

In the instruction writing scenario, the embodiment of the present application can monitor the empty and full status of the memory. By monitoring the empty and full status of the memory, the write overflow of the memory is avoided and the system performance is improved.

The embodiment of the present application provides an instruction reading method. Taking the instruction storage system provided in the above embodiment as an example to execute the embodiment of the present application, referring to FIG. 12 , the method flow provided in the embodiment of the present application is as follows:

1201. When the storage device is in a target storage mode, in response to an instruction read request, an instruction read/write device reads instructions from a memory.

The target storage mode is the first storage mode or the second storage mode. When it is necessary to read instructions from the instruction storage system due to business needs, an instruction read request can be sent to the instruction storage system, and in response to the instruction read request, the instruction read and write device of the instruction storage system reads the instruction from the memory.

1202. In a case where there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, after receiving the third notification message, the instruction reading and writing device stops reading instructions in the memory.

The third notification message is used to notify the instruction reading and writing device that the instructions stored in the memory in the target storage mode have been read out. The third notification message is generated by the multiplexer acquiring the third state information and based on the third state information.

In the implementation of the present application, the target storage mode can be the first storage mode or the second storage mode. When the storage device is in different storage modes, different comparators will monitor the empty and full states of the storage. Specifically, when the target storage mode is the first storage mode, the first comparator obtains the latest N-bit read address and the maximum N-bit write address. When the latest N-bit read address is the same as the maximum N-bit write address, the first comparator generates third state information and sends the third state information to the multiplexer; when the target storage mode is the second storage mode, the second comparator obtains the latest N+1-bit write address and the latest N+1-bit read address. When the latest N+1-bit read address is the same as the latest N+1-bit write address, the second comparator generates third state information and sends the third state information to the multiplexer.

1203. In a case where there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, after receiving the fourth notification message, the instruction reading and writing device stops reading instructions in the memory.

The fourth notification message is used to notify the instruction reading and writing device that the instructions stored in the memory in the target storage mode will be read out. The fourth notification message is obtained by the multiplexer from the fourth state information and is generated based on the fourth state information.

In the implementation of the present application, the target storage mode can be the first storage mode or the second storage mode. When the storage device is in different storage modes, different comparators will monitor the empty and full states of the storage. Specifically, when the target storage mode is the first storage mode, the first comparator obtains the N-bit maximum write address and the N-bit latest read address, converts the binary representation of the N-bit maximum write address into a decimal value, and converts the binary representation of the N-bit latest read address into a binary value, and then calculates the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest read address. When the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest read address is less than or equal to the second value, the first comparator generates fourth state information and sends the fourth state information to the multiplexer; when the target storage mode is the first storage mode, the first comparator obtains the N-bit maximum write address and the N-bit latest read address, and the fourth state information is sent to the multiplexer. The formula is the second storage mode, the second comparator obtains the N+1-bit latest write address and the N+1-bit latest read address, converts the binary representation of the N+1-bit latest write address into a decimal value, and converts the binary representation of the N+1-bit latest read address into a decimal value, and then calculates the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address. When the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to the fourth value, the second comparator generates fourth state information and sends the fourth state information to the multiplexer.

In the instruction reading scenario, the embodiment of the present application can monitor the empty or full state of the memory. By monitoring the empty or full state of the memory, instruction reading errors of the memory are avoided and system performance is improved.

FIG13 shows the instruction reading and writing process of the instruction storage system provided in the embodiment of the present application. Referring to FIG13 , in response to an instruction write request, the instruction read and write device generates a write enable signal. In response to the write enable signal, the instruction seq_wr_cmd[127:0] can be written to the memory; in response to an instruction read request, the instruction read and write device generates a read enable signal. In response to the read enable signal, the instruction seq_rd_cmd[127:0] can be read from the memory. During the instruction writing and reading process, the storage device monitors the empty and full status of the memory, generates a corresponding notification message based on the status information of the monitored memory, and sends the notification message to the instruction read and write device, so that the instruction read and write device can read and write the instructions in the memory according to the status information of the memory. The monitoring process of the empty and full state of the memory by the storage device includes: when the storage device is in the first storage mode, the bit selector obtains the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0] corresponding to the memory, obtains the lower 6 bits from the 7-bit latest write address Seq_waddr_ptr[6:0] to obtain the 6-bit latest write address Seq_waddr_ptr[5:0], and obtains the lower 6 bits from the 7-bit latest read address Seq_raddr _ptr[6:0] to obtain the 6-bit latest read address Seq_raddr_ptr[5:0], and then provide the 6-bit latest write address Seq_waddr_ptr[5:0] and the 6-bit latest read address Seq_raddr_ptr[5:0] to the first comparator. The first comparator generates the status information of the memory based on the latest write address Seq_waddr_ptr[5:0] and the 6-bit latest read address Seq_raddr_ptr[5:0], which are ram_almost_full (almost full in the first storage mode), ram_full (full in the first storage mode), ram_almost_empty (almost empty in the first storage mode), and ram_empty (empty in the first storage mode). Then, the status information in the first storage mode generated is sent to the multiplexer. When the storage device is in the second storage mode, the second comparator obtains the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0] corresponding to the memory, and generates the empty and full status information of the memory based on the 7-bit latest write address Seq_waddr_ptr[6:0] and the 7-bit latest read address Seq_raddr_ptr[6:0], which are fifo_almost_full (almost full in the second storage mode), fifo_full (full in the second storage mode), fifo_almost_empty (almost empty in the second storage mode), and fifo_empty (empty in the second storage mode), and then sends the generated status information in the second storage mode to the multiplexer. Based on the status information under different storage modes, the multiplexer generates corresponding notification messages, namely Seq_almost_full (storage space is about to be full), Seq_full (storage space is full), Seq_almost_empty (storage space is about to be empty), and Seq_empty (storage space is full), and then sends the generated notification messages to the instruction read and write device, so that the instruction read and write device can read and write instructions in the memory.

The embodiment of the present application provides an electronic device 100, which includes the instruction storage system described in the above embodiment. FIG14 shows a schematic diagram of the structure of the electronic device 100. The electronic device 100 can be a mobile phone, a personal computer (PC), a tablet computer, an AR (Augmented Reality) device, a VR (Virtual Reality) device, a car computer, a wearable device, a smart home device, etc.

The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a Universal Serial Bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a Subscriber Identification Module (SIM) card interface 195, etc. Among them, the sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, for example, the processor 110 may include an MCU, an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and/or a neural-network processing unit (NPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interface may include an Inter-Integrated Circuit (I2C) interface, an Inter-Integrated Circuit Sound (I2S) interface, a Pulse Code Modulation (PCM) interface, a Universal Asynchronous Receiver/Transmitter (UART) interface, a MIPI interface, a General-Purpose Input/Output (GPIO) interface, a User Identity Module interface, and/or a Universal Serial Bus (USB) interface, etc.

The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple groups of I2C buses. The processor 110 can be coupled to the touch sensor 180K, the charger, the flash, the camera 193, etc. through different I2C bus interfaces. For example, the processor 110 can be coupled to the touch sensor 180K through the I2C interface, so that the processor 110 communicates with the touch sensor 180K through the I2C bus interface to realize the touch function of the electronic device 100.

The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to achieve communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 via the I2S interface to achieve the function of answering a call through a Bluetooth headset.

The PCM interface can also be used for audio communication, sampling, quantizing and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface to realize the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

The UART interface is a universal serial data bus for asynchronous communication. The bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is generally used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 through the UART interface to implement the Bluetooth function. In some embodiments, the audio module 170 can transmit an audio signal to the wireless communication module 160 through the UART interface to implement the function of playing music through a Bluetooth headset.

The MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the shooting function of the electronic device 100. The processor 110 and the display screen 194 communicate via the DSI interface to implement the display function of the electronic device 100.

The GPIO interface can be configured by software. The GPIO interface can be configured as a control signal or as a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 with the camera 193, the display screen 194, the wireless communication module 160, the audio module 170, the sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

The USB interface 130 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 130 can be used to connect a charger to charge the electronic device 100, can also be used to transfer data between the electronic device 100 and a peripheral device, and can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.

It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present application is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

The charging management module 140 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger through the USB interface 130. In some wireless charging embodiments, the charging management module 140 may receive wireless charging input through a wireless charging coil of the electronic device 100. While the charging management module 140 is charging the battery 142, it may also power the electronic device through the power management module 141.

The power management module 141 is used to connect the battery 142, the charging management module 140 and the processor 110. The power management module 141 receives input from the battery 142 and/or the charging management module 140, and supplies power to the processor 110, the internal memory 121, the display screen 194, the camera 193 and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

The wireless communication function of the electronic device 100 can be implemented through the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, the baseband processor, and the like.

Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

The mobile communication module 150 can provide solutions for wireless communications including 2G/3G/4G/5G, etc., applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, etc. the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be sent into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to a speaker 170A, a receiver 170B, etc.), or displays an image or video through a display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and may be set in the same device as the mobile communication module 150 or other functional modules.

The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc., which are applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate and amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

In some embodiments, the antenna 1 of the electronic device 100 is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include Global System For Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and/or IR technology. The GNSS may include a Global Positioning System (GPS), a Global Navigation Satellite System (GNASS), a Beidou Navigation Satellite System (BDS), a Quasi-Zenith Satellite System (QZSS) and/or a Satellite Based Augmentation System (SBAS).

The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1.

The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

The ISP is used to process the data fed back by the camera 193. For example, when taking a photo, the shutter is opened, and the light is transmitted to the camera photosensitive element through the lens. The light signal is converted into an electrical signal, and the camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin color of the image. The ISP can also optimize the exposure, color temperature and other parameters of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then transmits the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

The digital signal processor is used to process digital signals, and can process not only digital image signals but also other digital signals. For example, when the electronic device 100 is selecting a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy.

Video codecs are used to compress or decompress digital videos. The electronic device 100 may support one or more video codecs. In this way, the electronic device 100 may play or record videos in a variety of coding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

NPU is a neural network (NN) computing processor. By drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain, it can quickly process input information and can also continuously self-learn. NPU can realize applications such as intelligent cognition of electronic device 100, such as image recognition, face recognition, voice recognition, text understanding, etc.

The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function, such as storing music, video and other files in the external memory card.

The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, for example, at least one disk storage device, a flash memory device, a universal flash storage (Universal Flash Storage, UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The electronic device 100 can implement audio functions such as music playing and recording through the audio module 170 , the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be arranged in the processor 110, or some functional modules of the audio module 170 can be arranged in the processor 110.

The speaker 170A, also called a "speaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or listen to a hands-free call through the speaker 170A.

The receiver 170B, also called a "earpiece", is used to convert audio electrical signals into sound signals. When the electronic device 100 receives a call or voice message, the voice can be received by placing the receiver 170B close to the human ear.

Microphone 170C, also called "microphone" or "microphone", is used to convert sound signals into electrical signals. When making a call or sending a voice message, the user can speak by putting their mouth close to microphone 170C to input the sound signal into microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also realize noise reduction function. In other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to realize the collection of sound signals, noise reduction, identification of sound sources, realization of directional recording function, etc.

The earphone interface 170D is used to connect a wired earphone and can be the USB interface 130 or a 3.5 mm Open Mobile Terminal Platform (OMTP) standard interface or a Cellular Telecommunications Industry Association of the USA (CTIA) standard interface.

The pressure sensor 180A is used to sense the pressure signal and can convert the pressure signal into an electrical signal. In some embodiments, the pressure sensor 180A can be set on the display screen 194. There are many types of pressure sensors 180A, such as resistive pressure sensors, inductive pressure sensors, capacitive pressure sensors, etc. The capacitive pressure sensor can be a parallel plate including at least two conductive materials. When a force acts on the pressure sensor 180A, the capacitance between the electrodes changes. The electronic device 100 determines the intensity of the pressure according to the change in capacitance. When a touch operation acts on the display screen 194, the electronic device 100 detects the touch operation intensity according to the pressure sensor 180A. The electronic device 100 can also calculate the touch position according to the detection signal of the pressure sensor 180A. In some embodiments, touch operations acting on the same touch position but with different touch operation intensities can correspond to different operation instructions. For example, when a touch operation with a touch operation intensity less than the first pressure threshold acts on the short message application icon, an instruction to view the short message is executed. When a touch operation with a touch operation intensity greater than or equal to the first pressure threshold acts on the short message application icon, an instruction to create a new short message is executed.

The gyro sensor 180B can be used to determine the motion posture of the electronic device 100. In some embodiments, the angular velocity of the electronic device 100 around three axes (i.e., the x, y, and z axes) can be determined by the gyro sensor 180B. The gyro sensor 180B can be used for anti-shake shooting. For example, when the shutter is pressed, the gyro sensor 180B detects the angle of the electronic device 100 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the electronic device 100 through reverse movement to achieve anti-shake. The gyro sensor 180B can also be used for navigation and somatosensory game scenes.

The air pressure sensor 180C is used to measure air pressure. In some embodiments, the electronic device 100 calculates the altitude through the air pressure value measured by the air pressure sensor 180C to assist positioning and navigation.

The magnetic sensor 180D includes a Hall sensor. The electronic device 100 can use the magnetic sensor 180D to detect the opening and closing of the flip leather case. In some embodiments, when the electronic device 100 is a flip phone, the electronic device 100 can detect the opening and closing of the flip cover according to the magnetic sensor 180D. Then, according to the detected opening and closing state of the leather case or the opening and closing state of the flip cover, the flip cover can be automatically unlocked.

The acceleration sensor 180E can detect the magnitude of the acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device and is applied to applications such as horizontal and vertical screen switching and pedometers.

The distance sensor 180F is used to measure the distance. The electronic device 100 can measure the distance by infrared or laser. In some embodiments, when shooting a scene, the electronic device 100 can use the distance sensor 180F to measure the distance to achieve fast focusing.

The proximity light sensor 180G may include, for example, a light emitting diode (LED) and a light detector, such as a photodiode. The light emitting diode may be an infrared light emitting diode. The electronic device 100 emits infrared light outward through the light emitting diode. The electronic device 100 uses a photodiode to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it can be determined that there is an object near the electronic device 100. When insufficient reflected light is detected, the electronic device 100 can determine that there is no object near the electronic device 100. The electronic device 100 can use the proximity light sensor 180G to detect that the user holds the electronic device 100 close to the ear to talk, so as to automatically turn off the screen to save power. The proximity light sensor 180G can also be used in leather case mode and pocket mode to automatically unlock and lock the screen.

The ambient light sensor 180L is used to sense the brightness of the ambient light. The electronic device 100 can adaptively adjust the brightness of the display screen 194 according to the perceived ambient light brightness. The ambient light sensor 180L can also be used to automatically adjust the white balance when taking pictures. The ambient light sensor 180L can also cooperate with the proximity light sensor 180G to detect whether the electronic device 100 is in a pocket to prevent accidental touches.

The fingerprint sensor 180H is used to collect fingerprints. The electronic device 100 can use the collected fingerprint characteristics to implement fingerprint unlocking, access application locks, fingerprint photography, fingerprint call answering, etc.

The temperature sensor 180J is used to detect temperature. In some embodiments, the electronic device 100 uses the temperature detected by the temperature sensor 180J to execute a temperature processing strategy. For example, when the temperature reported by the temperature sensor 180J exceeds a threshold, the electronic device 100 reduces the performance of a processor located near the temperature sensor 180J to reduce power consumption and implement thermal protection. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 heats the battery 142 to avoid abnormal shutdown of the electronic device 100 due to low temperature. In other embodiments, when the temperature is lower than another threshold, the electronic device 100 boosts the output voltage of the battery 142 to avoid abnormal shutdown caused by low temperature.

The touch sensor 180K is also called a "touch control device". The touch sensor 180K can be set on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, also called a "touch control screen". The touch sensor 180K is used to detect touch operations acting on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In other embodiments, the touch sensor 180K can also be set on the surface of the electronic device 100, which is different from the position of the display screen 194.

The bone conduction sensor 180M can obtain a vibration signal. In some embodiments, the bone conduction sensor 180M can obtain a vibration signal of a vibrating bone block of the vocal part of the human body. The bone conduction sensor 180M can also contact the human pulse to receive a blood pressure beat signal. In some embodiments, the bone conduction sensor 180M can also be set in an earphone and combined into a bone conduction earphone. The audio module 170 can parse out a voice signal based on the vibration signal of the vibrating bone block of the vocal part obtained by the bone conduction sensor 180M to realize a voice function. The application processor can parse the heart rate information based on the blood pressure beat signal obtained by the bone conduction sensor 180M to realize a heart rate detection function.

The key 190 includes a power key, a volume key, etc. The key 190 may be a mechanical key or a touch key. The electronic device 100 may receive key input and generate key signal input related to user settings and function control of the electronic device 100.

Motor 191 can generate vibration prompts. Motor 191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback. For example, touch operations acting on different applications (for example, taking pictures, audio playback, etc.) can correspond to different vibration feedback effects. For touch operations acting on different areas of the display screen 194, motor 191 can also correspond to different vibration feedback effects. Different application scenarios (for example, time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also support customization.

The indicator 192 may be an indicator light, which may be used to indicate the charging status, power changes, messages, missed calls, notifications, etc.

The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and separated from the electronic device 100 by inserting it into the SIM card interface 195 or pulling it out from the SIM card interface 195. The electronic device 100 can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to implement functions such as calls and data communications. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

An embodiment of the present application provides a computer-readable storage medium, in which at least one computer program is stored. When the at least one computer program is executed by a processor, it can implement the instruction storage method described in the above embodiment, or the instruction reading method described in the above embodiment.

An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it can implement the instruction storage method described in the above embodiment, or the instruction reading method described in the above embodiment.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (24)

1. An instruction storage system, characterized in that the system comprises a processor, a storage device and an instruction reading and writing device, the storage device supports at least two storage modes, the at least two storage modes include a first storage mode and a second storage mode, the first storage mode corresponds to instructions read multiple times, the second storage mode corresponds to instructions read once, and the storage device comprises a memory; The processor is used to configure a target storage mode currently supported by the storage device; The memory is used to store instructions corresponding to the target storage mode; The instruction reading and writing device is used to read and write instructions in the memory. 2. The system according to claim 1, wherein the storage device further comprises: a multiplexer; The multiplexer is used to obtain the state information of the memory in the target storage mode, generate a notification message based on the state information, and send the notification message to the instruction reading and writing device; The instruction reading and writing device is also used to execute corresponding control operations after receiving the notification message. 3. The system according to claim 2, characterized in that the multiplexer is specifically used to obtain first status information of the memory in the target storage mode, generate a first notification message based on the first status information, and send the first notification message to the instruction reading and writing device, wherein the first status information is used to indicate that the storage space of the memory in the target storage mode is full; The instruction reading and writing device is specifically used to stop writing instructions to the memory after receiving the first notification message reported by the storage device, when there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal. 4. The system according to claim 2, characterized in that the multiplexer is specifically used to obtain second state information of the memory in the target storage mode, generate a second notification message based on the second state information, and send the second notification message to the instruction reading and writing device, wherein the second state information is used to indicate that the storage space of the memory in the target storage mode is about to be full; The instruction reading and writing device is specifically used to stop writing instructions to the memory after receiving the second notification message reported by the storage device when there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal. 5. The system according to claim 2, characterized in that the multiplexer is specifically used to obtain third state information of the memory in the target storage mode, generate a third notification message based on the third state information, and send the third notification message to the instruction reading and writing device, wherein the third state information is used to indicate that the instructions stored in the memory in the target storage mode have been read; The instruction reading and writing device is specifically used to stop reading instructions in the memory after receiving the third notification message reported by the storage device and when there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal. 6. The system according to claim 2, characterized in that the multiplexer is specifically used to obtain fourth state information of the memory in the target storage mode, generate a fourth notification message based on the fourth state information, and send the fourth notification message to the instruction reading and writing device, wherein the fourth state information is used to indicate that the instructions stored in the memory in the target storage mode will be read completely; The instruction reading and writing device is specifically used to stop reading instructions in the memory after receiving the fourth notification message reported by the storage device when there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal. 7. The system according to claim 2, characterized in that when the target storage mode is the first storage mode, the storage device further comprises: a first comparator; The first comparator is used to generate the state information of the memory in the first storage mode, and send the state information to the multiplexer. 8. The system according to claim 7, characterized in that the first comparator is specifically used to generate first status information when the N-bit latest write address corresponding to the memory is the same as the N-bit maximum write address, and send the first status information to the multiplexer, the first status information is used to indicate that the storage space of the memory in the first storage mode is full, the decimal value corresponding to the N-bit maximum write address is equal to the queue depth of the memory minus 1, and N is a positive integer; The first comparator is specifically configured to generate second status information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, and send the second status information to the multiplexer, wherein the second status information is used to indicate that the storage space of the memory in the first storage mode is about to be full; The first comparator is specifically used to generate third state information when the N-bit latest read address corresponding to the memory is the same as the N-bit maximum write address, and send the third state information to the multiplexer, wherein the third state information is used to indicate that the instructions stored in the memory in the first storage mode have been read; The first comparator is specifically used to generate fourth state information and send the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest read address is less than or equal to the second value. The fourth state information is used to indicate that the instructions stored in the memory in the first storage mode will be read. 9. The system according to claim 8, wherein the storage device further comprises: a bit selector; The bit selector is used to obtain the N+1-bit latest read address and the N+1-bit latest write address corresponding to the memory, and use the lower N bits of the N+1-bit latest read address as the N-bit latest read address, and use the lower N bits of the N+1-bit latest write address as the N-bit latest write address; The bit selector is further configured to send the N-bit latest read address and the N-bit latest write address to the first comparator. 10. The system according to claim 2, characterized in that when the target storage mode is the second storage mode, the storage device further comprises: a second comparator; The second comparator is used to generate the state information of the memory in the second storage mode when the target storage mode is the second storage mode, and send the state information to the multiplexer. 11. The system according to claim 10, characterized in that the second comparator is specifically used to generate first status information and send the first status information to the multiplexer when the values of the highest bits of the N+1-bit latest write address and the N+1-bit latest read address corresponding to the memory are different, and the values of the other bits except the highest bit are the same, and the first status information is used to indicate that the storage space of the memory in the second storage mode is full, and N is a positive integer; The second comparator is specifically configured to generate second status information when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is greater than or equal to a third value, and send the second status information to the multiplexer, wherein the second status information is used to indicate that the storage space of the memory in the second storage mode is about to be full; The second comparator is specifically used to generate third state information when the N+1-bit latest read address and the N+1-bit latest write address are the same, and send the third state information to the multiplexer, wherein the third state information is used to indicate that the instructions stored in the memory in the second storage mode have been read; The second comparator is specifically used to generate fourth state information and send the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to a fourth value. The fourth state information is used to indicate that the instructions stored in the memory in the second storage mode will be read. 12. An instruction storage method, characterized in that the method is applied to the instruction storage system according to any one of claims 1 to 11, and the method comprises: When the storage device is in a target storage mode, in response to an instruction write request, the instruction reading and writing device writes instructions into the memory; In the case where there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, the instruction reading and writing device stops writing instructions to the memory after receiving the first notification message, and the first notification message is used to notify the instruction reading and writing device that the storage space of the memory in the target storage mode is full; In the case that there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, the instruction read and write device stops writing instructions to the memory after receiving the second notification message, and the second notification message is used to notify the instruction read and write device that the storage space of the memory in the target storage mode is about to be full. 13. The method according to claim 12, characterized in that, when there is no write delay between receiving the first notification message reported by the storage device and turning off the write enable signal, after receiving the first notification message, before the instruction reading and writing device stops writing instructions to the memory, it also includes: The multiplexer obtains first status information, generates the first notification message based on the first status information, and sends the first notification message to the instruction reading and writing device, wherein the first status information is used to indicate that the storage space of the memory in the target storage mode is full. 14. The method according to claim 13, wherein the multiplexer acquires the first state information, comprising: When the target storage mode is the first storage mode, the first comparator generates the first state information when the N-bit latest write address is the same as the N-bit maximum write address, and sends the first state information to the multiplexer; When the target storage mode is the second storage mode, the second comparator generates the first state information and sends the first state information to the multiplexer when the values of the highest bits of the N+1-bit latest write address and the N+1-bit latest read address are different, and the values of the bits other than the highest bit are the same. 15. The method according to claim 12, characterized in that, in the case where there is a write delay between receiving the second notification message reported by the storage device and turning off the write enable signal, after receiving the second notification message, before the instruction reading and writing device writes the first number of instructions into the memory, it also includes: The multiplexer obtains second status information, generates the second notification message based on the second status information, and sends the second notification message to the instruction reading and writing device, wherein the second status information is used to indicate that the storage space of the memory in the target storage mode is about to be full. 16. The method according to claim 15, wherein the multiplexer acquires the second state information, comprising: When the target storage mode is the first storage mode, the first comparator generates the second state information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the N-bit latest write address is less than or equal to the first value, and sends the second state information to the multiplexer; When the target storage mode is the second storage mode, the second comparator generates the second state information when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is greater than or equal to a third value, and sends the second state information to the multiplexer. 17. An instruction reading method, characterized in that the method is applied to the instruction storage system according to any one of claims 1 to 11, and the method comprises: When the storage device is in a target storage mode, in response to an instruction read request, the instruction read/write device reads an instruction from the memory; In the case where there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, the instruction reading and writing device stops reading instructions in the memory after receiving the third notification message, and the third notification message is used to notify the instruction reading and writing device that the instructions stored in the memory in the target storage mode have been read; In the case where there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, the instruction read-write device stops reading the instructions in the memory after receiving the fourth notification message, and the fourth notification message is used to notify the instruction read-write device that the instructions stored in the memory in the target storage mode will be read. 18. The method according to claim 17, characterized in that, when there is no read delay between receiving the third notification message reported by the storage device and turning off the read enable signal, before the instruction reading and writing device stops reading the instructions in the memory after receiving the third notification message, it also includes: The multiplexer obtains third status information, generates the third notification message based on the third status information, and sends the third notification message to the instruction reading and writing device, wherein the third status information is used to indicate that the instructions stored in the memory in the target storage mode have been read. 19. The method according to claim 18, wherein the multiplexer acquires the third state information, comprising: When the target storage mode is the first storage mode, the first comparator generates the third state information when the N-bit latest read address is the same as the N-bit maximum write address, and sends the third state information to the multiplexer; When the target storage mode is the second storage mode, the second comparator generates the third state information when the N+1-bit latest read address and the N+1-bit latest write address are the same, and sends the third state information to the multiplexer. 20. The method according to claim 17, characterized in that, in the case where there is a read delay between receiving the fourth notification message reported by the storage device and turning off the read enable signal, after receiving the fourth notification message, before the instruction reading and writing device reads the second number of instructions from the memory, it further comprises: The multiplexer obtains fourth status information, generates the fourth notification message based on the fourth status information, and sends the fourth notification message to the instruction reading and writing device, wherein the fourth status information is used to indicate that the instructions stored in the memory in the target storage mode will be read out. 21. The method according to claim 20, wherein the multiplexer acquires the fourth state information, comprising: When the target storage mode is the first storage mode, the first comparator generates the fourth state information when the difference between the decimal value corresponding to the N-bit maximum write address and the decimal value corresponding to the latest read address is less than or equal to the second value, and sends the fourth state information to the multiplexer; When the target storage mode is the second storage mode, the second comparator generates the fourth state information and sends the fourth state information to the multiplexer when the difference between the decimal value corresponding to the N+1-bit latest write address and the decimal value corresponding to the N+1-bit latest read address is less than or equal to the fourth value. 22. An electronic device, characterized in that the electronic device comprises the instruction storage system according to any one of claims 1 to 11. 23. A computer-readable storage medium, characterized in that at least one computer program is stored in the computer-readable storage medium, and when the at least one computer program is executed by a processor, it can implement the instruction storage method described in any one of claims 12 to 16, or the instruction reading method described in any one of claims 17 to 21. 24. A computer program product, characterized in that the computer program product comprises a computer program, and when the computer program is executed by a processor, it can implement the instruction storage method according to any one of claims 12 to 16, or the instruction reading method according to any one of claims 17 to 21.