CN118332267A - Signal processing system, method, product, equipment and medium - Google Patents

Abstract

The invention discloses a signal processing system, a signal processing method, a signal processing product, a signal processing device and a signal processing medium, and relates to the technical field of data processing. The system comprises: the signal acquisition module is used for acquiring a sequence to be converted with the length of N, which corresponds to the input signal; the data preprocessing module is used for preprocessing the sequence to be transformed to obtain P subsequences to be transformed with the length of Q; the P fast Fourier transform modules are used for performing Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences; the data processing module is used for carrying out data processing on the sub-sequences after transformation to obtain Q new sub-sequences to be transformed with the length of P; the Q fast Fourier transform modules are used for performing Fourier transform on the new subsequences to be transformed respectively to obtain new subsequences after transformation; and the data post-processing module is used for carrying out data recombination on the Q new transformed subsequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed. The fast fourier transform capability of the field programmable gate array is improved.

Description

A signal processing system, method, product, device and medium

Technical Field

The present invention relates to the field of data processing technology, and in particular to a signal processing system, method, product, device and medium.

Background technique

Fourier Transform is a linear integral transform used to transform signals between the time domain and the frequency domain. It has many applications in physics and engineering, such as signal processing (including audio signal processing, image signal processing, etc.) using Fourier Transform. Discrete Fourier Transform is a discrete form of Fourier Transform in both the time domain and the frequency domain; Fast Fourier Transform (FFT) is an efficient algorithm for calculating discrete Fourier Transform. Field Programmable Gate Array (FPGA) is a semi-custom circuit in application-specific integrated circuits. It is a programmable logic array with rich wiring resources, reprogrammable, high integration, low power consumption, high parallelism, etc. It has been widely used in the field of digital circuit design.

In the related art, FPGA is used to implement fast Fourier transform in order to improve the signal processing speed. However, in the scheme of implementing fast Fourier transform based on FPGA, a base 2 or base 4 architecture is usually used. Such architecture can only be used for fast Fourier transform of sequences with a length of exponential power of 2, and cannot handle the case where the length is a power of exponential other than 2, which reduces the ability of fast Fourier transform based on FPGA. Therefore, how to efficiently implement signal processing is a technical problem that needs to be solved urgently.

Summary of the invention

In view of this, the purpose of the present invention is to provide a signal processing system, method, product, device and medium, which can meet the Fourier transform requirements of sequences of various lengths and improve the ability of FPGA-based fast Fourier transform. The specific scheme is as follows:

In a first aspect, the present invention discloses a signal processing system, which is applied to a field programmable gate array, and the signal processing system comprises: a signal acquisition module, a data preprocessing module, a fast Fourier transform module, a data processing module and a data post-processing module;

The signal acquisition module is used to acquire a sequence to be transformed with a length of N corresponding to the input signal;

The data preprocessing module is used to preprocess the input sequence to be transformed with a length of N to obtain P subsequences to be transformed with a length of Q; wherein N is a composite number, N=P×Q;

P fast Fourier transform modules connected to the data preprocessing module are used to perform Fourier transform on the subsequences to be transformed to obtain transformed subsequences;

The data processing module is used to perform data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P;

Q fast Fourier transform modules connected to the data processing module, used to perform Fourier transform on the new subsequences to be transformed respectively to obtain new transformed subsequences;

The data post-processing module is used to perform data reorganization on the Q new transformed sub-sequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed, so as to realize signal processing of the input signal.

Optionally, the data preprocessing module includes a data cache unit, a data grouping unit and a data encapsulation unit;

The data cache unit is used to cache the sequence to be transformed into a first register with a length of N;

The data grouping unit is used to group the sequence to be transformed in units of length Q to obtain P grouped data, and transfer the grouped data to a second register of P groups with a length of Q;

The data encapsulation unit is used to take out the grouped data from each of the second registers respectively, and encapsulate each of the grouped data into a high-level extensible interface respectively, so as to obtain P subsequences to be transformed with a length of Q.

Optionally, the data processing module includes: a complex multiplier, a data grouping unit and a data encapsulation unit;

The complex multiplier is used to obtain a product by one-to-one multiplication between the transformed subsequence and the sub-rotation factor;

The data grouping unit is used to group the product in units of length P to obtain Q grouped data;

The data encapsulation unit is used to encapsulate each grouped data to obtain Q new subsequences to be transformed with a length of P.

Optionally, the data processing module includes a rotation factor acquisition unit;

The rotation factor acquisition unit is used to determine the corresponding rotation factor according to the length of the sequence to be transformed, and group the rotation factors to obtain P sub-rotation factors.

Optionally, the data processing module includes:

A rotation factor scaling unit, configured to determine, before grouping the rotation factors, a magnification factor for the rotation factors according to a bit width representing a real part or an imaginary part of the sequence to be transformed, and amplify the rotation factors using the magnification factor;

The data truncation unit is used to reduce the product in proportion according to the magnification factor before grouping the product in units of length P to obtain Q grouped data.

Optionally, the data post-processing module includes: a data cache unit, a data reassembly unit, and a data encapsulation unit;

The data cache unit is used to cache Q new transformed subsequences respectively using Q groups of first-in first-out registers;

The data reorganization unit is used to sequentially take out the new transformed subsequences from the first-in first-out register according to the sequence sorting rule, and perform data reorganization to obtain reorganized data;

The data encapsulation unit is used to perform data encapsulation on the reorganized data to obtain the Fourier transformed sequence.

Optionally, a system interface is also included;

The system interface includes a data input interface;

The data input interface is used to output a ready signal, receive a valid signal, and receive the input of a data signal when the valid signal is at a high level to obtain a sequence to be transformed. When the last data of the sequence to be transformed is input, the end signal changes from a low level to a high level. After the input of the sequence to be transformed is completed, the valid signal and the end signal change from a high level to a low level.

Optionally, the system interface includes a clock signal interface and a reset signal interface;

The clock signal interface is used to receive a clock signal;

The reset signal interface is used to receive a reset signal.

Optionally, the system interface includes a result output interface;

The result output interface is used to receive a valid signal, output a Fourier transformed sequence when the valid signal is at a high level, and change an end signal from a low level to a high level when the last data of the Fourier transformed sequence is output. After the output of the Fourier transformed sequence is completed, the valid signal and the end signal change from a high level to a low level.

Optionally, the data preprocessing module includes:

Selecting a processing unit, for determining a calculation type according to a target parameter; the calculation type includes a fast Fourier transform and an inverse Fourier transform;

An imaginary part negation unit, used for negating the imaginary part of the sequence to be transformed;

The data post-processing module comprises:

The imaginary part negation unit is used to negate the imaginary part of the sequence to be transformed after inverse Fourier transformation, and divide both the real part and the imaginary part of the sequence by the sequence length.

In a second aspect, the present invention discloses a signal processing method, comprising:

Obtain a sequence to be transformed with a length of N corresponding to the input signal;

Preprocessing the sequence to be transformed with a length of N to obtain P subsequences to be transformed with a length of Q; wherein N is a composite number, N=P×Q;

Using P fast Fourier transform units to perform Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences;

Performing data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P;

Using Q fast Fourier transform units to perform Fourier transform on the new subsequences to be transformed respectively to obtain new transformed subsequences;

Data is reorganized on the Q new transformed subsequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed, so as to realize signal processing of the input signal.

In a third aspect, the present invention discloses a signal processing method for a sequence of arbitrary length, comprising:

The input sequence to be transformed of length M is preprocessed by using the aforementioned signal processing system to obtain S subsequences to be transformed of length D and D new subsequences to be transformed of length S; wherein M is a positive integer, M=S×D;

If S is a power exponent with base 2, a power exponential fast Fourier transform module is used to perform Fourier transform on the new subsequence to be transformed;

If D is a prime number, a prime number fast Fourier transform module is used to perform Fourier transform on the subsequence to be transformed.

In a fourth aspect, the present invention discloses a computer program product, comprising a computer program/instruction, which, when executed by a processor, implements the aforementioned signal processing method or the signal processing method for a sequence of arbitrary length.

In a fifth aspect, the present invention discloses an electronic device, comprising:

Memory, used to store computer programs;

A processor is used to execute the computer program to implement the aforementioned signal processing method or the signal processing method for a sequence of any length.

In a sixth aspect, the present invention discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned signal processing method or the signal processing method for a sequence of arbitrary length.

In the present invention, the signal processing system includes a signal acquisition module, a data preprocessing module, a fast Fourier transform module, a data processing module and a data post-processing module; wherein the signal acquisition module is used to acquire a sequence to be transformed of length N corresponding to an input signal; the data preprocessing module is used to preprocess the input sequence to be transformed of length N to obtain P subsequences to be transformed of length Q; wherein N is a composite number, N=P×Q; the P fast Fourier transform modules connected to the data preprocessing module are used to perform Fourier transform on the subsequences to obtain transformed subsequences; the data processing module is used to perform data processing on the transformed subsequences to obtain Q new subsequences to be transformed of length P; the Q fast Fourier transform modules connected to the data processing module are used to perform Fourier transform on the new subsequences to be transformed to obtain new transformed subsequences; the data post-processing module is used to perform data reorganization on the Q new transformed subsequences to obtain the Fourier transformed sequence corresponding to the sequence to be transformed.

It can be seen that for sequences with a composite length, the sequence to be transformed is divided into subsequences to be transformed through the data preprocessing module, and a Fourier transform is performed on the subsequences to be transformed. Then, the transformed subsequences are converted into new subsequences to be transformed by the data processing module, and the new subsequences to be transformed are subjected to another Fourier transform. The fast Fourier transform of the composite number is split into two Fourier transforms of short sequences, and layer-by-layer decomposition is achieved to meet the Fourier transform requirements of sequences of various lengths, improve the ability of fast Fourier transform based on FPGA, improve the efficiency of fast Fourier transform, and improve the signal processing speed.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

FIG1 is a schematic diagram of the structure of a signal processing system provided by the present invention;

FIG2 is a specific signal processing timing diagram provided by the present invention;

FIG3 is a schematic diagram of a specific signal processing system structure provided by the present invention;

FIG4 is a schematic diagram of a specific data preprocessing module structure provided by the present invention;

FIG5 is a schematic diagram of a specific data processing module structure provided by the present invention;

FIG6 is a schematic diagram of a specific data post-processing module structure provided by the present invention;

FIG7 is a flow chart of a signal processing method provided by the present invention;

FIG8 is a flow chart of a specific signal processing method for a sequence of arbitrary length provided by the present invention;

FIG9 is a schematic diagram of a specific signal processing system for sequences of arbitrary length provided by the present invention;

FIG10 is a flow chart of a specific signal processing method provided by the present invention.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

In the related art, in the scheme of implementing fast Fourier transform using field programmable gate array, a base 2 or base 4 architecture is usually adopted. Such architecture can only be used for fast Fourier transform of sequences with a length of exponential power of 2, and cannot handle the case where the length is a power of exponential other than 2, which reduces the ability of fast Fourier transform based on FPGA. In order to overcome the above technical problems, the present invention proposes a signal processing system that can meet the Fourier transform requirements of sequences of various lengths, improve the ability of fast Fourier transform based on FPGA, and improve the signal processing speed.

The embodiment of the present invention discloses a signal processing system, which is applied to a field programmable gate array. Referring to FIG1 , the system may include a signal acquisition module 11, a data preprocessing module 12, a fast Fourier transform module 13, a data processing module 14 and a data post-processing module 15;

The signal acquisition module is used to acquire a sequence to be transformed with a length of N corresponding to an input signal; the input signal may be an audio signal, a video signal, etc.

The data preprocessing module is used to preprocess the input sequence to be transformed with a length of N, and obtain P subsequences to be transformed with a length of Q; where N is a composite number, N=P×Q. A composite number refers to a natural number greater than 1 that can be divided by other numbers besides 1 and itself.

First, a brief description of the algorithm principle for splitting and calculating Fourier transform is given:

For a sequence x(n) of length N, its Fourier transform expression is:

(1);

For a sequence of composite numbers whose length N is an exponential power other than 2, its Fourier transform can be split into two Fourier transforms for calculation, namely:

(2);

(3);

Then formula (1) can be transformed into

(4);

In imperative (4)

(5);

Then formula (4) can be simplified to

(6);

In imperative (6)

(7);

Then formula (6) can be simplified to

(8);

Equations (5) and (8) are the Fourier transforms of sequences of length r1 and r2, respectively, while equation (7) is the product of the transformed sequence of equation (5) and the rotation factor. In summary, the Fourier transform of a complex number can be split into two Fourier transforms for calculation, and the product of the rotation factor is processed between the two Fourier transforms;

(9);

Finally, the transformed sequence is reordered according to formula (9). Specifically, r1 is a fixed value, a k0 value is taken, all k1 values are traversed to obtain a set of k values, and then another k0 value is taken, all K1 values are traversed to obtain another set of k values, until all k0 values are taken.

The whole calculation process is described in detail using the sequence length N=8=4×2. The process includes the following steps:

1. For an 8-point sequence x(0)~x(7), divide it into two 4-point sequences: x(0), x(2), x(4), x(6) and x(1), x(3), x(5), x(7). Perform Fourier transform on these two sequences and obtain _X1 (0), _X1 (2), _X1 (4), _X1 (6) and _X1 (1), _X1 (3), _X1 (5), _X1 (7).

2. Multiply the above two sequences by their rotation factors, the first sequence n0=0, k0=0, 1, 2, 3, and the second sequence n0=1, k0=0, 1, 2, 3, and obtain the processed sequences X ₁ '(0), X ₁ '(2), X ₁ '(4), X ₁ '(6) and X ₁ '(1), X ₁ '(3), X ₁ '(5), X ₁ '(7).

3. Recombine the above two 4-point sequences into four 2-point sequences, namely _X1 '(0), _X1 '(1), _X1 '(2), _X1 '(3), _X1 '(4), _X1 '(5), _X1 '(6), _X1 '(7), and calculate the Fourier transform of these four sequences, that is, formula (8), to obtain X2(0), X2(1), X2(2), X2(3), X2(4), X2(5), X2(6), X2(7).

4. Finally, the above four sequences are reordered according to formula (9) to obtain X2(0), X2(2), X2(4), X2(6), X2(1), X2(3), X2(5), and X2(7). It should be noted that the sequence can be divided into two subsequences of 4 points or four subsequences of 2 points, which is not limited in this embodiment.

In this embodiment, the above-mentioned signal processing system further includes a system interface; the system interface includes a data input interface; the data input interface is used to output a ready signal, receive a valid signal, and receive the input of a data signal when the valid signal is at a high level to obtain a sequence to be transformed, and when the last data of the sequence to be transformed is input, the end signal changes from a low level to a high level, and after the input of the sequence to be transformed is completed, the valid signal and the end signal change from a high level to a low level. That is, by coordinating the ready signal and the valid signal, the valid input data of the data signal is obtained to obtain the sequence to be transformed.

In this embodiment, the system interface includes a clock signal interface and a reset signal interface; the clock signal interface is used to receive a clock signal; the reset signal interface is used to receive a reset signal. The reset signal is used for system initialization.

In this embodiment, the system interface includes a result output interface; the result output interface is used to receive a valid signal, output a Fourier transformed sequence when the valid signal is at a high level, and when the last data of the Fourier transformed sequence is output, the end signal changes from a low level to a high level, and after the output of the Fourier transformed sequence is completed, the valid signal and the end signal change from a high level to a low level. That is, when the result is output, the valid output data of the data signal is obtained through the valid signal and the end signal to obtain the Fourier transformed sequence.

It is understandable that the interface of the signal processing system includes clock, reset, data input and result output. The clock and reset interface provide clock and reset signals for the signal processing unit. The data input interface is the input interface of the sequence to be transformed, and the result output interface is the output interface of the sequence after transformation. The interface form can be naked data, lightweight advanced extensible interface, or advanced extensible stream interface. In order to unify the interface, the interface complexity and flexibility are comprehensively considered. The advanced extensible stream interface is selected in this embodiment. The data input and result output interfaces are composed of ready signal, valid signal, data signal and end signal. Since each element of the sequence to be transformed is a complex number, it is composed of a real part and an imaginary part. In this embodiment, the real part and the imaginary part are represented by 32-bit data respectively, then the bit width of the data signal is 64 bits, the lower 32 bits represent the real part of the complex number, and the upper 32 bits represent the imaginary part of the complex number. Of course, the bit width of the real part and the imaginary part can be flexibly adjusted according to actual needs.

The timing diagram of the signal processing system is shown in FIG2. After the transformation system is started, it is first reset to initialize the internal register to the default value, and then the reset is canceled. Subsequently, the data input interface outputs a ready signal, indicating that the system is ready to receive the sequence to be transformed, and then the external module receives a valid signal, indicating that the input data signal is valid, and the sequence to be transformed is input in sequence. If the length of the sequence to be transformed is 8, the data input is completed after 8 clock cycles, and the end signal changes from a low level to a high level when the last data is input. After all data inputs are completed, the valid signal and the end signal change from a high level to a low level. After a period of calculation, the signal processing system completes the transformation task and starts to output the transformation results. The result output interface first receives a valid signal, and then outputs 8 transformed sequence elements in sequence, and the end signal changes from a low level to a high level when the last element is output. After all results are output, the valid signal and the end signal change from a high level to a low level, completing the entire calculation task.

Taking the signal processing system corresponding to the composite number 8 as an example, as shown in Figure 3, its interface includes clock, reset, data input and result output interfaces, and is internally composed of a data preprocessing module, a fast Fourier transform module, a data processing module and a data post-processing module. The architecture of other composite numbers is similar, except that the data grouping and the number of fast Fourier transform modules before and after are different.

In some embodiments, the data preprocessing module 12 may include a data cache unit, a data grouping unit and a data encapsulation unit; the data cache unit is used to cache the sequence to be transformed into a first register with a length of N; the data grouping unit is used to group the sequence to be transformed in units of length Q to obtain P grouped data, and transfer the grouped data to P groups of second registers with a length of Q; the data encapsulation unit is used to take out the grouped data from each of the second registers, and encapsulate each of the grouped data into a high-level extensible interface, so as to obtain P subsequences to be transformed with a length of Q. That is, the input sequence to be transformed is grouped according to the algorithm requirements using the data preprocessing module.

For example, Figure 4 shows a schematic diagram of the data preprocessing module structure, taking the sequence length of 8 and the split mode of 4×2 as an example. After receiving 8 data input from the advanced scalable stream interface, the data preprocessing module first caches the original data into a group of registers with a length of 8, and then groups the data according to the algorithm formula (3) and transfers the data to 2 groups of registers with a length of 4; finally, the data is taken out from the two groups of registers, encapsulated into the advanced scalable stream interface, and input into two fast Fourier transform modules for Fourier transform.

The P fast Fourier transform modules 13 connected to the data preprocessing module are used to perform Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences. The two groups of sequences to be transformed output by the data preprocessing module are respectively input into two fast Fourier transform modules, and the sequences after Fourier transform can be obtained after calculation. The interface output by this module is also an advanced extensible stream interface. When the subsequence to be transformed is an exponential power, the fast Fourier transform module can be a Fourier transform module for calculating an exponential power sequence with a length of 2. If the sequence to be transformed N is split into a subsequence to be transformed with a sequence length of a prime number, the Fourier transform module suitable for prime numbers is used for calculation.

The data processing module 14 is used to perform data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P.

The above-mentioned data processing module includes a rotation factor acquisition unit; the rotation factor acquisition unit is used to determine the corresponding rotation factor according to the length of the sequence to be transformed, group the rotation factor, and obtain P sub-rotation factors. It can be understood that the data processing module is used to multiply the two transformed sequences with the corresponding elements of the rotation factor respectively. The rotation factor is After the sequence length is determined, the value of the rotation factor is determined, so some rotation factors of certain lengths can be pre-defined inside the field programmable gate array device, and the rotation factor can be calculated by writing a Python or C++ program.

In some embodiments, the data processing module may include: a rotation factor scaling unit, which is used to determine the magnification factor for the rotation factor according to the bit width representing the real part or imaginary part of the sequence to be transformed before grouping the rotation factor, and use the magnification factor to amplify the rotation factor; a data truncation unit, which is used to proportionally reduce the product according to the magnification factor before grouping the product in units of length P to obtain Q grouped data. That is, in order to improve the calculation accuracy of the algorithm, in this embodiment, the rotation factor is appropriately scaled according to the data bit width. For example, if the data bit width of this embodiment is selected as 32 bits, the rotation factor can be magnified. This scaling factor can be flexibly adjusted according to actual needs. For the rotation factor, the data also needs to be grouped according to formula (3) and transferred to two groups of registers with a length of 4.

The above-mentioned data processing module may specifically include: a complex multiplier, a data grouping unit and a data encapsulation unit; wherein the complex multiplier is used to obtain a product by one-to-one multiplication between the transformed subsequence and the sub-rotation factor; the data grouping unit is used to group the product in units of length P to obtain Q grouped data; the data encapsulation unit is used to perform data encapsulation on each grouped data to obtain Q new subsequences to be transformed with a length of P.

For example, FIG5 shows a schematic diagram of the internal structure of the data processing module, where the two sets of transformed sequences are multiplied with the corresponding elements of the two sets of rotation factors. It should be noted that this is a complex number multiplication, and the real part of the product is the difference between the transformed sequence and the corresponding real part of the rotation factor and the corresponding imaginary part, and the imaginary part of the product is the sum of the cross-multiplication of the transformed sequence and the real and imaginary parts of the rotation factor. Because the rotation factor is amplified, the data is proportionally reduced by data truncation in the data processing module to ensure that the data does not overflow. Then, the data is regrouped according to the algorithm formula (3), and the two 4-point sequences are redivided into 4 2-point sequences. Finally, the grouped sequences are also encapsulated as an advanced extensible stream interface, and then input into the four fast Fourier transform modules for the next Fourier transform.

The Q fast Fourier transform modules 13 connected to the data processing module 14 are used to perform Fourier transform on the new subsequence to be transformed respectively to obtain a new transformed subsequence. That is, after obtaining the new subsequence to be transformed, the fast Fourier transform module is used again to perform calculations, and the calculation results are used as the new transformed subsequences.

The data post-processing module 15 is used to reorganize the Q new transformed subsequences to obtain the Fourier transformed sequence corresponding to the sequence to be transformed. The data post-processing module reorganizes the multiple new transformed subsequences into a sequence according to the order specified by the algorithm, and finally obtains the Fourier transformed sequence corresponding to the sequence to be transformed.

The above-mentioned data post-processing module may specifically include a data cache unit, a data reorganization unit, and a data encapsulation unit; wherein the data cache unit is used to use Q groups of first-in first-out registers to cache Q of the new transformed subsequences respectively; the data reorganization unit is used to sequentially take out the new transformed subsequences from the first-in first-out registers according to the sequence sorting rule, and perform data reorganization to obtain reorganized data; the data encapsulation unit is used to perform data encapsulation on the reorganized data to obtain the Fourier transformed sequence. For example, FIG6 shows a schematic diagram of the structure of the data post-processing module, and the data post-processing module is used for data caching and reorganization; taking the sequence to be transformed with a length of 8 as an example, 4 groups of first-in first-out registers are used to cache 4 groups of new transformed subsequences output by 4 fast Fourier transform modules. According to the algorithm formula (9), the required data is sequentially taken out from the 4 groups of first-in first-out registers, and the data is encapsulated into a high-level extensible stream interface for output, thereby completing the entire fast Fourier transform process of the composite number.

In addition to the fast Fourier transform, the above system can also implement the inverse Fourier transform. In some embodiments, the data preprocessing module includes a selection processing unit for determining the calculation type according to the target parameter; the calculation type includes fast Fourier transform and inverse Fourier transform; an imaginary part negation unit for taking a negative value for the imaginary part of the sequence to be transformed. That is, when an inverse transform is required, the imaginary part of the sequence to be transformed is taken a negative value. The above data post-processing module may include: an imaginary part negation unit for taking a negative value for the imaginary part of the sequence to be transformed after the inverse Fourier transform, and dividing both the real part and the imaginary part of the sequence by the sequence length.

That is, the input sequence to be transformed x(n) is conjugated, and then the subsequent operations are performed. The new transformed subsequence X2(n) is conjugated and divided by the sequence length. After adding these two processings, the inverse fast Fourier transform of the complex number can be completed. In the system architecture, a parameter definition (IFFT) is added. If IFFT is defined as 0, a fast Fourier transform is performed. If it is defined as 1, it means that an inverse fast Fourier transform is performed. A step of selection processing is added to the data preprocessing module. When performing an inverse fast Fourier transform, the imaginary part of the input sequence element to be transformed is negative, and the input sequence element to be transformed is not processed when performing a fast Fourier transform. At the same time, a step of selection processing is also added to the data post-processing module. When performing an inverse fast Fourier transform, the imaginary part of the transformed sequence element is negative, and the real and imaginary parts of the element are divided by the sequence length. When performing a fast Fourier transform, the transformed sequence element is not processed.

As can be seen from the above, the signal processing system in this embodiment includes a data preprocessing module, a fast Fourier transform module, a data processing module and a data post-processing module; wherein the data preprocessing module is used to preprocess the input sequence to be transformed with a length of N to obtain P subsequences to be transformed with a length of Q; wherein N is a composite number, N=P×Q; the P fast Fourier transform modules connected to the data preprocessing module are used to perform Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences; the data processing module is used to perform data processing on the transformed subsequences to obtain Q new subsequences to be transformed with a length of P; the Q fast Fourier transform modules connected to the data processing module are used to perform Fourier transform on the new subsequences to be transformed respectively to obtain new transformed subsequences; the data post-processing module is used to perform data reorganization on the Q new transformed subsequences to obtain the Fourier transformed sequence corresponding to the sequence to be transformed. Therefore, for a sequence whose length is a composite number, the sequence to be transformed is divided into subsequences to be transformed through a data preprocessing module, a Fourier transform is performed on the subsequences to be transformed, and then the transformed subsequences are converted into new subsequences to be transformed by the data processing module, and the new subsequences to be transformed are subjected to another Fourier transform, the fast Fourier transform of the composite number is split into two Fourier transforms of short sequences, and layer-by-layer decomposition is achieved to meet the Fourier transform requirements of sequences of various lengths, improve the capability of fast Fourier transform based on FPGA, and improve the signal processing speed.

Correspondingly, an embodiment of the present invention further discloses a signal processing method, which is applied to FPGA and is applicable to any positive integer. For example, as shown in FIG7 , the method includes the following steps:

Step S11: obtaining a sequence to be transformed with a length of N corresponding to the input signal;

Step S12: using a signal processing system to preprocess the input sequence to be transformed of length M, to obtain S subsequences to be transformed of length D, and D new subsequences to be transformed of length S; wherein M is a positive integer, M=S×D;

Step S13: if S is a power exponent with base 2, using a power exponential fast Fourier transform module to perform Fourier transform on the new subsequence to be transformed;

Step S14: If D is a prime number, a prime number fast Fourier transform module is used to perform Fourier transform on the subsequence to be transformed.

Based on the above signal processing system and the exponential fast Fourier transform module and the prime fast Fourier transform module, the fast Fourier transform of a sequence of any length can be realized. Take a sequence of length 56 as an example, and the calculation principle of sequences of other lengths is similar. For example, FIG8 shows a fast Fourier transform flow chart corresponding to a sequence of length 56, and FIG9 shows a schematic diagram of the fast Fourier transform system architecture corresponding to a sequence of length 56. For a sequence of length 56, a composite number signal processing system is first used for transformation, and it is split into two 7×8 Fourier transforms. For a subsequence of length 7, a prime number Fourier transform module is used for transformation; and for a subsequence of length 8 (exponential power of 2), an exponential power of 2 Fourier transform module is used for transformation. For the prime number 7, after using the prime number Fourier transform module, the subsequence is converted into a Fourier transform of length 6, and combined with the inverse Fourier transform; the Fourier transform of the sequence of length 6 can be further split into two 2×3 Fourier transforms, and the prime number 3 can be converted into a Fourier transform of length 2 using the prime number Fourier transform unit. Finally, the underlying Fourier transforms are all transformed using the Fourier transform unit of the exponential power of 2.

Before the above-mentioned use of the signal processing system to preprocess the input sequence to be transformed with a length of M, it also includes: judging whether the M is a power exponent with a base of 2, and if so, using the power exponential fast Fourier transform module to perform Fourier transform on the sequence to be transformed, and if not, executing the operation of using the signal processing system to preprocess the input sequence to be transformed with a length of M. After the above-mentioned use of the prime number fast Fourier transform module to perform Fourier transform on the subsequence to be transformed, it also includes: judging whether the subsequence with a length of H after the subsequence to be transformed is a power exponent with a base of 2, and if so, using the power exponential fast Fourier transform module to perform Fourier transform on the subsequence with a length of H, and if not, using the signal processing system to preprocess the subsequence with a length of H. For field programmable gate arrays, the most basic Fourier transform is completed using an ordinary radix 2 architecture, combined with a composite number signal processing system and a prime number Fourier transform system, which can meet the Fourier transform requirements of sequences of any length in various application scenarios.

Correspondingly, an embodiment of the present invention further discloses a signal processing method for a sequence of arbitrary length, as shown in FIG10 , the method comprises the following steps:

Step S21: preprocessing the input sequence to be transformed of length N to obtain P subsequences to be transformed of length Q; wherein N is a composite number, N=P×Q;

Step S22: using P fast Fourier transform units to perform Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences;

Step S23: performing data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P;

Step S24: using Q fast Fourier transform units to perform Fourier transform on the new subsequence to be transformed respectively to obtain a new transformed subsequence;

Step S25: reorganize the Q new transformed subsequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed.

As can be seen from the above, in this embodiment, for a sequence whose length is a composite number, the sequence to be transformed is divided into subsequences to be transformed, a Fourier transform is performed on the subsequences to be transformed, and then the transformed subsequences are converted into new subsequences to be transformed, and the new subsequences to be transformed are subjected to another Fourier transform, the fast Fourier transform of the composite number is split into two Fourier transforms of short sequences, and layer-by-layer decomposition is implemented to meet the Fourier transform requirements of sequences of various lengths, thereby improving the capability of fast Fourier transform based on FPGA.

In some specific embodiments, preprocessing the input sequence to be transformed with a length of N to obtain P subsequences to be transformed with a length of Q may specifically include:

Cache the sequence to be transformed into a first register of length N;

The sequence to be transformed is grouped in units of length Q to obtain P grouped data, and the grouped data is transferred to a second register of P groups with a length of Q;

The grouped data are taken out from each of the second registers respectively, and each of the grouped data is encapsulated into a high-level extensible interface respectively, so as to obtain P subsequences to be transformed with a length of Q.

In some specific embodiments, the performing data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P may specifically include:

Obtaining a product by performing one-to-one multiplication between the transformed subsequence and the sub-rotation factor;

Grouping the product in units of length P to obtain Q grouped data;

Data encapsulation is performed on each grouped data to obtain Q new subsequences to be transformed with a length of P.

In some specific embodiments, the signal processing method may specifically include:

A corresponding rotation factor is determined according to the length of the sequence to be transformed, and the rotation factor is grouped to obtain P sub-rotation factors.

In some specific embodiments, the signal processing method may specifically include:

Before grouping the rotation factors, determine a magnification factor for the rotation factors according to a bit width representing a real part or an imaginary part of the sequence to be transformed, and perform a magnification process on the rotation factors using the magnification factor;

Before grouping the product in units of length P to obtain Q grouped data, the product is proportionally reduced according to the magnification factor.

In some specific embodiments, the performing data reorganization on the Q new transformed subsequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed may specifically include:

Using Q groups of first-in first-out registers to cache the Q new transformed subsequences respectively;

Taking out the new transformed subsequences from the first-in first-out register in sequence according to the sequence sorting rule, and performing data reorganization to obtain reorganized data;

The reorganized data is encapsulated to obtain the Fourier transformed sequence.

In some specific embodiments, the signal processing method may specifically include:

A ready signal is output through a data input interface, a valid signal is received, and a data signal is input while the valid signal is at a high level to obtain a sequence to be transformed. When the last data of the sequence to be transformed is input, an end signal changes from a low level to a high level. After the input of the sequence to be transformed is completed, the valid signal and the end signal change from a high level to a low level.

In some specific embodiments, the signal processing method may specifically include:

receiving a clock signal through a clock signal interface;

Receive the reset signal through the reset signal interface.

In some specific embodiments, the signal processing method may specifically include:

A valid signal is received through a result output interface, and a Fourier transformed sequence is output while the valid signal is at a high level. When the last data of the Fourier transformed sequence is output, an end signal changes from a low level to a high level. After the output of the Fourier transformed sequence is completed, the valid signal and the end signal change from a high level to a low level.

In some specific embodiments, the signal processing method may specifically include:

Determine the calculation type according to the target parameter; the calculation type includes fast Fourier transform and inverse Fourier transform;

Taking the imaginary part of the sequence to be transformed as a negative value;

The imaginary part of the sequence to be transformed after inverse Fourier transformation is negative, and both the real part and the imaginary part of the sequence are divided by the sequence length.

Furthermore, an embodiment of the present invention also discloses an electronic device, which may specifically include: at least one processor and at least one memory, wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the signal processing disclosed in any of the above embodiments.

Furthermore, an embodiment of the present invention also discloses a computer storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the signal processing steps disclosed in any of the aforementioned embodiments are implemented.

Furthermore, an embodiment of the present invention also discloses a computer program product, including a computer program/instruction, which implements the aforementioned signal processing method or a signal processing method for a sequence of any length when executed by a processor.

In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the system part description.

The steps of the system or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, system, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, system, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the existence of other identical elements in the process, system, article or device including the elements.

The signal processing system, method, product, device and medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the system of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims (15)

1. A signal processing system, characterized in that it is applied to a field programmable gate array, and the signal processing system comprises: a signal acquisition module, a data preprocessing module, a fast Fourier transform module, a data processing module and a data post-processing module; The signal acquisition module is used to acquire a sequence to be transformed with a length of N corresponding to the input signal; The data preprocessing module is used to preprocess the sequence to be transformed with a length of N to obtain P subsequences to be transformed with a length of Q; wherein N is a composite number, N=P×Q; P fast Fourier transform modules connected to the data preprocessing module are used to perform Fourier transform on the subsequences to be transformed to obtain transformed subsequences; The data processing module is used to perform data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P; Q fast Fourier transform modules connected to the data processing module, used to perform Fourier transform on the new subsequences to be transformed respectively to obtain new transformed subsequences; The data post-processing module is used to perform data reorganization on the Q new transformed sub-sequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed, so as to realize signal processing of the input signal. 2. The signal processing system according to claim 1, characterized in that the data preprocessing module comprises a data cache unit, a data grouping unit and a data encapsulation unit; The data cache unit is used to cache the sequence to be transformed into a first register with a length of N; The data grouping unit is used to group the sequence to be transformed in units of length Q to obtain P grouped data, and transfer the grouped data to a second register of P groups with a length of Q; The data encapsulation unit is used to take out the grouped data from each of the second registers respectively, and encapsulate each of the grouped data into a high-level extensible interface respectively, so as to obtain P subsequences to be transformed with a length of Q. 3. The signal processing system according to claim 1, characterized in that the data processing module comprises: a complex multiplier, a data grouping unit and a data encapsulation unit; The complex multiplier is used to obtain a product by one-to-one multiplication between the transformed subsequence and the sub-rotation factor; The data grouping unit is used to group the product in units of length P to obtain Q grouped data; The data encapsulation unit is used to encapsulate each grouped data to obtain Q new subsequences to be transformed with a length of P. 4. The signal processing system according to claim 3, characterized in that the data processing module comprises a rotation factor acquisition unit; The rotation factor acquisition unit is used to determine the corresponding rotation factor according to the length of the sequence to be transformed, and group the rotation factors to obtain P sub-rotation factors. 5. The signal processing system according to claim 4, characterized in that the data processing module comprises: A rotation factor scaling unit, configured to determine, before grouping the rotation factors, a magnification factor for the rotation factors according to a bit width representing a real part or an imaginary part of the sequence to be transformed, and amplify the rotation factors using the magnification factor; The data truncation unit is used to reduce the product in proportion according to the magnification factor before grouping the product in units of length P to obtain Q grouped data. 6. The signal processing system according to claim 1, characterized in that the data post-processing module comprises: a data cache unit, a data reassembly unit, and a data encapsulation unit; The data cache unit is used to cache Q new transformed subsequences respectively using Q groups of first-in first-out registers; The data reorganization unit is used to sequentially take out the new transformed subsequences from the first-in first-out register according to the sequence sorting rule, and perform data reorganization to obtain reorganized data; The data encapsulation unit is used to perform data encapsulation on the reorganized data to obtain the Fourier transformed sequence. 7. The signal processing system according to claim 1, further comprising a system interface; The system interface includes a data input interface; The data input interface is used to output a ready signal, receive a valid signal, and receive the input of a data signal when the valid signal is at a high level to obtain a sequence to be transformed. When the last data of the sequence to be transformed is input, the end signal changes from a low level to a high level. After the input of the sequence to be transformed is completed, the valid signal and the end signal change from a high level to a low level. 8. The signal processing system according to claim 7, characterized in that the system interface includes a clock signal interface and a reset signal interface; The clock signal interface is used to receive a clock signal; The reset signal interface is used to receive a reset signal. 9. The signal processing system according to claim 7, characterized in that the system interface comprises a result output interface; The result output interface is used to receive a valid signal, output a Fourier transformed sequence when the valid signal is at a high level, and change an end signal from a low level to a high level when the last data of the Fourier transformed sequence is output. After the output of the Fourier transformed sequence is completed, the valid signal and the end signal change from a high level to a low level. 10. The signal processing system according to any one of claims 1 to 9, wherein the data preprocessing module comprises: Selecting a processing unit, for determining a calculation type according to a target parameter; the calculation type includes a fast Fourier transform and an inverse Fourier transform; An imaginary part negation unit, used for negating the imaginary part of the sequence to be transformed; The data post-processing module comprises: The imaginary part negation unit is used to negate the imaginary part of the sequence to be transformed after inverse Fourier transformation, and divide both the real part and the imaginary part of the sequence by the sequence length. 11. A signal processing method, comprising: Obtain a sequence to be transformed with a length of N corresponding to the input signal; Preprocessing the sequence to be transformed of length N to obtain P subsequences to be transformed of length Q; wherein N is a composite number, N=P×Q; Using P fast Fourier transform units to perform Fourier transform on the subsequences to be transformed respectively to obtain transformed subsequences; Performing data processing on the transformed subsequence to obtain Q new subsequences to be transformed with a length of P; Using Q fast Fourier transform units to perform Fourier transform on the new subsequences to be transformed respectively to obtain new transformed subsequences; Data is reorganized on the Q new transformed subsequences to obtain a Fourier transformed sequence corresponding to the sequence to be transformed, so as to realize signal processing of the input signal. 12. A signal processing method for a sequence of arbitrary length, comprising: Using the signal processing system according to any one of claims 1 to 10, a sequence to be transformed having an input length of M is preprocessed to obtain S subsequences to be transformed having a length of D, and D new subsequences to be transformed having a length of S; wherein M is a positive integer, M=S×D; If S is a power exponent with base 2, a power exponential fast Fourier transform module is used to perform Fourier transform on the new subsequence to be transformed; If D is a prime number, a prime number fast Fourier transform module is used to perform Fourier transform on the subsequence to be transformed. 13. A computer program product, comprising a computer program/instruction, characterized in that when the computer program/instruction is executed by a processor, it implements the signal processing method according to claim 11 or the signal processing method for a sequence of arbitrary length according to claim 12. 14. An electronic device, comprising: Memory, used to store computer programs; A processor is used to execute the computer program to implement the signal processing method according to claim 11 or the signal processing method for a sequence of arbitrary length according to claim 12. 15. A computer-readable storage medium, characterized in that it is used to store a computer program; wherein when the computer program is executed by a processor, it implements the signal processing method according to claim 11 or the signal processing method for a sequence of arbitrary length according to claim 12.