CN118354594A

CN118354594A - Semiconductor structure and preparation method thereof

Info

Publication number: CN118354594A
Application number: CN202310027453.2A
Authority: CN
Inventors: 曹新满
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2024-07-16

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method comprises providing a substrate with multiple bit line structures arranged at intervals along a first direction; forming first contact holes arranged at intervals along a second direction and isolation structures for separating the first contact holes between every two adjacent bit line structures; forming a first contact pad lower than the bit line structure in the first contact hole; a second contact pad is formed on the top surface of the first contact pad and the second contact pad exposed at the side and top surface of one of the bit line structures within the first contact hole. The present disclosure is for improving yield of a second contact pad.

Description

Semiconductor structure and preparation method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

A dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory that randomly writes and reads data at high speed, and is widely used in data storage devices or apparatuses.

Dynamic random access memory is formed from a plurality of memory cells, each memory cell typically including a capacitive structure and a transistor; the gate of the transistor is connected to a word line and the capacitive structure is typically connected to one of the source and drain through a storage contact structure ((Stock NodeContact, SNC for short).

However, the storage contact structure in the related art is easy to break, so that the yield of the storage contact structure is reduced, and the yield of the semiconductor structure is further reduced.

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are used for improving the yield of a memory contact structure, thereby improving the yield of the semiconductor structure.

A first aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the steps of:

Providing a substrate, and forming a plurality of bit line structures which are arranged at intervals along a first direction on the substrate;

forming a plurality of first contact holes arranged at intervals along a second direction between each adjacent bit line structure and an isolation structure for separating the first contact holes, wherein the second direction intersects with the first direction;

forming a first contact pad lower than the bit line structure in the first contact hole;

A second contact pad is formed on the top surface of the first contact pad and on the side and top surfaces of one of the bit line structures exposed in the first contact hole.

In some embodiments, after the step of forming the first contact pad, before the step of forming the second contact pad, the method of preparing further comprises:

And removing part of the bit line structure exposed in the first contact hole, and reaming the first contact hole to form a second contact hole.

In some embodiments, the bit line structure includes a bit line and an isolation sidewall covering the bit line sidewall; the isolation side wall comprises a first isolation layer, a second isolation layer and a third isolation layer which are arranged in a stacked mode, and the first isolation layer is connected with the side wall of the bit line;

The step of removing the portion of the bit line structure exposed in the first contact hole includes: and removing the second isolation layer and the third isolation layer exposed in the first contact hole to form a second contact hole.

In some embodiments, the step of forming the second contact pad on the first contact pad extending to the top and side surfaces of the bit line structure comprises:

Forming a first conductive layer, wherein the first conductive layer is filled with the first contact hole above the first contact pad and covers the top surface of the bit line structure;

And removing part of the first conductive layer to form a second contact pad, wherein the second contact pad is positioned on the top surface of the first contact pad and the side surface and the top surface of one of the bit line structures exposed in the first contact hole, and the second contact pad and the first contact pad form a contact pad.

In some embodiments, the step of forming the first contact pad includes:

forming a barrier layer, wherein the barrier layer covers the bottom wall and part of the side wall of the first contact hole;

and forming a second conductive layer, wherein the second conductive layer fills the area surrounded by the barrier layer.

In some embodiments, the step of forming the first contact pad includes:

forming a blocking material layer on the inner wall of the first contact hole, wherein the blocking material layer extends out of the first contact hole and covers the top surface of the bit line structure;

Forming a second conductive material layer on the barrier material layer;

removing the second conductive material layer and the barrier material layer on the bit line structure by adopting a chemical mechanical polishing process;

and removing part of the second conductive material layer and part of the blocking material layer which are positioned in the first contact hole by adopting an etching process so as to form a first contact pad.

In some embodiments, the barrier material layer comprises a first barrier material layer and a second barrier material layer; the first blocking material layer is arranged on the inner wall of the first contact hole, and the second blocking material layer is arranged on the first blocking material layer.

In some embodiments, the etching process comprises a wet etching process.

In some embodiments, the step of removing a portion of the first conductive layer comprises:

and removing the part of the other bit line structure exposed in the same first contact hole.

A second aspect of the disclosed embodiments provides a semiconductor structure comprising:

A substrate; the substrate is provided with a plurality of bit line structures, and the bit line structures are arranged at intervals along a first direction;

The isolation structures are arranged between any adjacent bit line structures at intervals along the second direction, and the adjacent isolation structures and the bit line structures form a first contact hole;

A first contact pad, wherein the first contact pad is arranged in the first contact hole, and the top surface of the first contact hole is lower than the bit line structure;

and the second contact pad is positioned on the top surface of the first contact pad and the side surface and the top surface of one bit line structure exposed in the first contact hole.

In some embodiments, the second contact pad includes a first segment, a second segment, and a third segment connected in sequence, the first segment being disposed at a bottom of the first contact hole, the second segment being disposed on a side of the bit line structure, the third segment being connected to the second segment and being located on a top surface of the bit line structure;

The dimension of the relative position of the bit line structure and the second section is smaller than the dimension of the relative position of the bit line structure and the first section.

In some embodiments, the first contact pad includes a barrier layer and a second conductive layer;

The barrier layer is disposed on the storage contact plug, and the second conductive layer is disposed in an area surrounded by the barrier layer.

In some embodiments, the barrier layer comprises a first barrier layer and a second barrier layer disposed in a stack, the first barrier layer disposed on the storage contact plug;

the first barrier layer and the second barrier layer are different in material.

In some embodiments, the first section has a cross-sectional area perpendicular to the substrate that is greater than a cross-sectional area of the first contact pad.

In some embodiments, the bit line structure includes a bit line and an isolation sidewall covering the bit line sidewall; the isolation side wall comprises a first isolation layer, a second isolation layer and a third isolation layer which are arranged in a laminated mode, and the first isolation layer is connected with the side wall of the bit line.

In the semiconductor structure and the preparation method thereof provided by the embodiment of the disclosure, the first contact pad is formed in the first contact hole, the top surface of the first contact pad is lower than the top surface of the bit line structure, and the first contact pad only covers the bottom wall and part of the side wall of the first contact hole. Compared with the prior art, the first contact pad covers all the side walls of the first contact hole, the space for forming the second contact pad subsequently can be increased, the second contact pad is prevented from being disconnected, the yield of the second contact pad is improved, and the yield of the semiconductor structure is further improved.

In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the semiconductor structure and the method for manufacturing the semiconductor structure provided in the embodiments of the present disclosure solve other technical problems, other technical features included in the technical solutions, and beneficial effects caused by the technical features, which are described in detail above, will be described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 to 3 are schematic structural views of a related art method for manufacturing a semiconductor structure;

Fig. 4 is a process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

Fig. 5 is a schematic diagram of forming a storage contact plug in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 6 is a schematic diagram of forming a barrier material layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 7 is a schematic view of forming a second conductive material layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a semiconductor structure according to an embodiment of the disclosure after removing a portion of a barrier material layer and a second conductive material layer;

Fig. 9 is a schematic diagram of forming a first contact pad in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 10 is a schematic diagram illustrating formation of a second contact hole in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 11 is a schematic view illustrating formation of a first conductive material layer in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 12 is a schematic diagram illustrating formation of a second contact pad in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.

Reference numerals:

10: a barrier layer; 20: a conductive layer; 30: a contact pad;

100: a substrate; 110: shallow trench isolation structures;

200: a bit line structure; 210: a bit line; 211: a bit line contact layer; 212: a bit line conductive layer; 213: bit line isolation layers; 220: isolating the side wall; 221: a first isolation layer; 222: a second isolation layer; 223: a third isolation layer;

300: storing the contact plug;

400: a first contact hole;

500: a first contact pad; 510: a barrier layer; 511: a first barrier layer; 512: a second barrier layer; 513: a barrier material layer; 5131: a first barrier material layer; 5132: a second barrier material layer; 520: a second conductive layer; 521: a second conductive material layer;

600: a second contact hole;

700: a second contact pad; 710: a first section; 720: a second section; 730: a third section; 740: a first conductive layer;

800: and a buffer layer.

Detailed Description

As described in the background art, the storage contact structure in the related art has a problem of low yield. The inventor has found that the problem is caused by the fact that referring to fig. 1 to 3, in the related art, a storage contact plug 300 is generally formed between adjacent bit line structures 200, and the storage contact plug 300 is used for connecting with a source or drain of a substrate 100; thereafter, a barrier layer 10 and a conductive layer 20 are formed in a stacked arrangement between the memory contact plug and the bit line structure to enclose a fill region, and then a portion of the conductive layer 20 is removed to form a contact pad 30. The storage contact plug and the contact pad constitute a storage contact structure. However, in view of the smaller size between adjacent bit line structures 200 during the removal process, on the one hand, the conductive layer 20 and the barrier layer 10 on the sidewalls of the bit line structures 200 are over-etched, so that the contact pads on the top surface of the bit line structures 200 are disconnected from the contact pads on the storage contact plugs (see fig. 2), and the yield of the contact pads is reduced. On the other hand, short circuits are likely to occur in the case where adjacent contact pads 30 are connected together due to insufficient etching (refer to fig. 3), which reduces the yield of the contact pads.

In view of the above technical problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, in which a first contact pad is formed in a first contact hole, a top surface of the first contact pad is lower than a top surface of a bit line structure, and the first contact pad only covers a bottom wall and a portion of a sidewall of the first contact hole. Compared with the prior art, the first contact pad covers all the side walls of the first contact hole, the space for forming the second contact pad later can be increased, and further, the second contact pad is prevented from being partially disconnected from the side surface of the bit line structure, the yield of the second contact pad is improved, and the yield of the semiconductor structure is improved.

In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of the present disclosure.

The semiconductor structure is not limited in this embodiment, and a Dynamic Random Access Memory (DRAM) will be described as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.

As shown in fig. 4, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes the following steps:

step S100: a substrate is provided, the substrate is provided with a plurality of bit line structures, and the plurality of bit line structures are arranged at intervals along a first direction.

Referring to fig. 5, a substrate 100 is used to support a semiconductor device disposed thereon. The substrate 100 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (Silicon on Insulator, abbreviated as SOI) substrate, or a germanium-on-insulator (Germanium on Insulator, abbreviated as GOI) substrate, etc.

It should be noted that, the substrate 100 has a plurality of active regions, and a shallow trench isolation (Shallow Trench Isolation, abbreviated as STI) structure 110 may be disposed between the plurality of active regions, and the plurality of active regions are separated by the shallow trench isolation structure 110 to ensure that the active regions are independent of each other. Illustratively, a shallow trench is formed in a substrate by a patterning process and filled with an insulating material, thereby defining a plurality of active regions on the substrate separated by shallow trench isolation structures. The patterning process may be a Self-aligned double pattern (Self-Aligned Double Patterning, referred to as SADP) process or a Self-aligned quadruple pattern (Self-Aligned Quadruple Patterning, referred to as SAQP) process. Wherein the insulating material may include silicon oxide, but is not limited thereto.

A plurality of bit line structures 200 are disposed on the substrate 100, and the bit line structures 200 are used to connect with source or drain regions of an active region. The plurality of bit line structures 200 are spaced apart along the first direction, and each bit line structure 200 extends along the second direction for connecting the plurality of active regions extending along the second direction. The first direction and the second direction intersect. For example, the first direction X and the second direction Y are perpendicular to each other.

The bit line structure 200 includes a bit line 210 and isolation sidewalls 220 covering sidewalls of the bit line 210. The isolation sidewall 220 is used to provide insulation between adjacent bit lines 210.

The bit line 210 includes a bit line contact layer 211, a bit line conductive layer 212, and a bit line isolation layer 213, which are stacked. The portion of the bit line contact layer 211 extends into the substrate 100, so as to increase the contact area between the bit line contact layer 211 and the active region, thereby reducing the contact resistance between the bit line contact layer 211 and the active region, and improving the stability and timeliness of the signal transmission process between the bit line 210 and the active region.

The material of the bit line contact layer 211 typically comprises polysilicon. The material of the bit line conductive layer 212 typically comprises tungsten. The material of the bit line isolation layer 213 is typically comprised of silicon nitride.

The isolation sidewall 220 may be a single film or a composite film. Illustratively, the isolation sidewall 220 includes a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223, which are sequentially stacked. The first isolation layer 221 contacts the bit line 210, and the first isolation layer 221 and the third isolation layer 223 are made of the same material, for example, the first isolation layer 221 and the third isolation layer 223 are made of silicon nitride, but not limited thereto. The second isolation layer 222 is made of a material different from that of the first isolation layer 221, for example, the material of the second isolation layer 222 includes silicon oxide, but is not limited thereto.

It should be noted that the material of the bit line isolation layer 213 is generally the same as that of the first isolation layer 221, so that the bit line isolation layer 213 and the first isolation layer 221 shown in fig. 5 to 10 are connected together. In order to clearly show the position of the bit line isolation layer 213, the region between the two dotted lines in fig. 5 may be referred to as the bit line isolation layer 213.

Step S200: a plurality of first contact holes and isolation structures for separating the first contacts are formed between each adjacent bit line structure at intervals along a second direction, and the second direction intersects with the first direction.

Illustratively, an insulating layer (not shown) is formed covering the bit line structures 200 and the substrate 100 between adjacent bit line structures 200. The insulating layer is patterned to form a plurality of first contact holes 400 spaced apart in the second direction between adjacent bit line structures 200. Wherein the remaining insulating layer forms an isolation structure. The isolation structure serves to separate the respective first contact holes 400 such that the respective first contact holes 400 exist independently.

The first direction may be the X direction in fig. 5, and the second direction may be the Y direction in fig. 5.

After the step of forming the first contact hole, the storage contact plug 300 may be formed before the step of forming the first contact pad lower than the bit line structure in the first contact hole. Illustratively, a conductive material layer is deposited within the fill holes using a deposition process and etched back to form storage contact plugs 300, the top surfaces of the storage contact plugs 300 being lower than the top surfaces of the bit line structures 200. The storage contact plug 300 is used to electrically connect with the source region or the drain region of the substrate 100. In this embodiment, the material of the conductive material layer includes polysilicon.

After forming the storage contact plug 300, a buffer layer 800 may be formed on a top surface of the storage contact plug 300 facing away from the substrate 100. Illustratively, a buffer material layer is formed on the inner wall of the first contact hole 400 using an atomic layer deposition process, and then the buffer material layer is etched back to leave the buffer material layer on the storage contact plug 300 to form the buffer layer 800.

The material of the buffer layer 800 includes cobalt silicide, but is not limited thereto. The buffer layer 800 can be used to reduce contact resistance between the storage contact plug 300 and the first contact pad 500, and also can reduce stress between the storage contact plug 300 and the first contact pad 500, prevent the storage contact plug 300 and the first contact pad 500 from being separated, and improve yield of the semiconductor structure.

Step S300: a first contact pad is formed in the first contact hole below the bit line structure.

Step S310: a barrier layer 510 is formed, the barrier layer 510 covering the bottom wall and a portion of the side wall of the first contact hole 400. The structure of which can be seen in fig. 9.

For example, referring to fig. 6, a barrier material layer 513 is formed on the inner wall of the first contact hole 400 by a deposition process, wherein the barrier material layer 513 extends out of the first contact hole 400 and covers the top surface of the bit line structure 200.

It should be noted that the barrier material layer 513 may be a single film layer or may be formed by stacking a plurality of film layers. For example, the barrier material layer 513 includes a first barrier material layer 5131 and a second barrier material layer 5132. The first blocking material layer 5131 is in direct contact with the inner wall of the first contact hole 400. A second barrier material layer 5132 is disposed on the first barrier material layer 5131. The material of the first barrier material layer 5131 is different from the material of the second barrier material layer 5132. For example, the material of the first barrier material layer 5131 includes titanium, and the material of the second barrier material layer 5132 includes titanium nitride.

Wherein, titanium or titanium nitride prevents the penetration between the conductive material and the bit line structure 200 in the second conductive layer formed later, and has conductivity at the same time, thus ensuring the performance of the semiconductor device.

In this embodiment, the blocking material layer 513 is in a double-layer structure, so that the blocking capability of the blocking material layer 513 can be improved, the interconnection between the first contact pad and the bit line structure 200 is reduced or even avoided, and the yield of the semiconductor structure is improved.

Note that, in this embodiment, the deposition process may include a process such as chemical vapor deposition (Chemical Vapor Deposition, CVD for short), physical vapor deposition (Physical Vapor Deposition, PVD for short), or atomic layer deposition (Atomic Layer Deposition, ALD for short).

Step S320: and forming a second conductive layer, wherein the second conductive layer fills the area surrounded by the barrier layer. The structure of which is shown in fig. 9.

For example, referring to fig. 7, a second conductive material layer 521 is formed on the barrier material layer 513 by using a deposition process, and the second conductive material layer 521 fills the area surrounded by the barrier material layer 513. The material of the second conductive material layer 521 includes tungsten, but is not limited thereto.

Referring to fig. 8, a Chemical Mechanical Polishing (CMP) process is used to remove the second conductive material layer 521 and the barrier material layer 513 on the bit line structure 200 to expose the top surface of the bit line structure 200. The present embodiment provides a guarantee for the accuracy of removing the remaining second conductive material layer 521 and the barrier material layer 513 by using the etching process in the following step for flattening the semiconductor structure through the chemical mechanical polishing process.

Thereafter, referring to fig. 9, an etching process is used to remove a portion of the second conductive material layer 521 and a portion of the barrier material layer 513 located in the first contact hole 400, where the remaining second conductive material layer 521 forms the second conductive layer 520, and the remaining barrier material layer 513 forms the barrier layer 510. The barrier layer 510 and the second conductive layer 520 constitute the first contact pad 500.

In this embodiment, a wet etching process is used to remove portions of the second conductive material layer 521 and the barrier material layer 513. The wet etching process has a better selectivity, and when the second conductive material layer 521 and the blocking material layer 513 are etched by the wet etching process, the isolation side wall 220 of the exposed bit line structure 200 can be prevented from being damaged, and the insulating property of the isolation side wall 220 is ensured.

In the embodiment of the disclosure, the second conductive material layer 521 and the barrier material layer 513 on the bit line structure 200 are removed through a chemical mechanical polishing process, and then portions of the second conductive material layer 521 and the barrier material layer 513 in the first contact hole 400 are removed through an etching process. By the arrangement, the etching precision can be ensured, the damage to the bit line structure 200 can be reduced, and the yield of the semiconductor structure is improved.

Step S400: a second contact pad is formed on the top surface of the first contact pad and on the side and top surfaces of one of the bit line structures exposed in the first contact hole. The structure is shown in fig. 12.

For example, please refer to fig. 11, step S410: a first conductive layer is formed, fills the first contact hole over the first contact pad, and covers the top surface of the bit line structure.

In this embodiment, the first conductive layer for forming the second contact pad may be deposited directly in the first contact hole 400 located above the first contact pad 500. The first conductive layer for forming the second contact pad may be deposited after the reaming process of the first contact hole 400 located above the first contact pad 500 to increase the size of the region.

It should be noted that, in order to facilitate the subsequent processing, for example, etching, the top surface of the first conductive layer 740 may be planarized by using a chemical mechanical polishing process, so that the top surface of the first conductive layer 740 is parallel to the substrate 100.

Referring to fig. 12, step S420: and removing part of the first conductive layer to form a second contact pad, wherein the second contact pad is positioned on the top surface of the first contact pad and the side surface and the top surface of one bit line structure exposed in the first contact hole, and the second contact pad and the first contact pad form a contact pad.

Illustratively, a mask layer (not shown) having mask openings may be formed over the first conductive layer 740, the mask openings exposing at least portions of the first conductive layer 740 between adjacent bit line structures 200.

Thereafter, referring to fig. 12, the first conductive layer 740 exposed in the mask opening is removed by using an etching solution or an etching gas, and the remaining first conductive layer 740 forms the second contact pad 700.

The second contact pad 700 includes a first section 710, a second section 720, and a third section 730 connected in sequence. The first section 710 is disposed over the first contact pad 500, and the second section 720 is connected to an end of the first section 710 facing away from the first contact pad 500, the second section 720 being located on a side of one of the bit line structures 200 exposed in the first contact hole or the second contact hole. Taking the orientation shown in fig. 12 as an example, the second section 720 overlies the left side of the bit line structure 200. The third section 730 is connected to an end of the second section 720 facing away from the first section 710, and the third section 730 is located on the top surface of the bit line structure 200 such that the second contact pad 700 has a zigzag shape.

In comparison with the related art, the barrier layer 510 of the first contact pad 500 is located only on a portion of the sidewall of the first contact hole, and it can be avoided that the barrier layer 510 of the first contact pad 500 occupies the entire sidewall of the second contact hole. So set up, can increase the size of first conducting layer along the first direction, follow-up removal part first conducting layer can slow down the overetching to the first conducting layer that is located on the lateral wall of second contact hole, can remain the second section 720 that is located on the side of bit line structure 200, and then prevent that second contact pad's first section 710 and third section 730 disconnection, improved second contact pad 700's yield, and then improved semiconductor structure's yield.

In one possible embodiment, after the step of forming the first contact pad and before the step of forming the second contact pad, the method of fabricating a semiconductor structure further includes:

Referring to fig. 10, a portion of the bit line structure 200 exposed in the first contact hole is removed, and the first contact hole is subjected to a reaming process to form a second contact hole 600. For example, in the first direction, the bit line structure 200 of a partial width exposed in the first contact hole by the etching process increases the size of the first contact hole located above the first contact pad 500 in the first direction to form the second contact hole 600.

That is, in the first direction, the size of the second contact hole 600 is larger than that of the first contact hole. The area of the second contact hole 600 is increased, and thus the size of the first conductive layer 740 (see fig. 11) formed later in the first direction is increased, and the yield of the second contact pad 700 (see fig. 12) is improved.

Illustratively, the second and third isolation layers 222 and 223 exposed within the first contact hole are removed to form the second contact hole 600. By the arrangement, the size of the second contact hole 600 in the first direction can be increased, the isolation side wall 220 can be prevented from being damaged excessively, and the insulating capability of the isolation side wall 220 is ensured.

In one possible embodiment, the step of removing a portion of the first conductive layer further comprises: portions of the other bit line structure exposed in the same first contact hole are removed.

With continued reference to fig. 12, when the first conductive layer is removed, portions of another bit line structure 200 located in the same first contact hole are also removed simultaneously. Taking the orientation of fig. 12 as an example, the mask opening also exposes a portion of the bit line structure 200 located on the right side in the same first contact hole, so that the connection of the two second contact pads 700 can be prevented, and the yield of the semiconductor structure is improved.

The embodiment of the disclosure also provides a semiconductor structure, which is prepared by the preparation method in the embodiment.

Referring to fig. 12, the semiconductor structure includes: a substrate 100, a plurality of isolation structures, a first contact pad 500, and a second contact pad 700.

The substrate 100 has a plurality of bit line structures 200 spaced apart along a first direction, each bit line structure 200 extending along a second direction for connecting a plurality of active regions spaced apart along the second direction. To facilitate writing of stored data to the capacitive structure or reading of stored data in the capacitive structure by the bit line structure 200. The bit line structure 200 includes a bit line 210 and an isolation sidewall 220 covering a sidewall of the bit line 210. The isolation sidewall 220 is used to provide insulation between adjacent bit lines 210.

A plurality of isolation structures (not shown) are disposed between any adjacent bit line structures 200 at intervals along the second direction, and the adjacent isolation structures and bit line structures 200 enclose the first contact hole 400. The two ends of the isolation structure are connected to the bit line structure 200. The isolation structure is made of silicon nitride, and is arranged in an insulating manner between adjacent contact pads formed later, so that errors of stored data in the capacitor structure read later are prevented, and the yield of the semiconductor structure is improved.

The first contact pad 500 is disposed within the first contact hole 400, and a top surface of the first contact pad 500 is lower than the bit line structure 200.

In any adjacent two bit line structures 200, a second contact pad 700 is disposed on the first contact pad 500 and is located on the side and top of one of the bit line structures 200. That is, the second contact pad 700 has a predetermined interval from the side of the other bit line structure 200.

The second contact pad 700 and the first contact pad 500 constitute a contact pad, one end of which is electrically connected to the active region of the substrate 100, and the other end of which is used to be connected to the capacitive structure, so as to realize the electrical connection of the capacitive structure to the active region located in the substrate 100.

In the semiconductor structure provided in the embodiment of the disclosure, the first contact pad 500 is only connected with a part of the side surface of the bit line structure 200, and compared with the case that the first contact pad 500 covers the whole side surface of the bit line structure 200 in the related art, the thickness of the second contact pad 700 in the area opposite to the side surface of the bit line structure 200 can be increased, so that the disconnection between the second contact pad 700 located on the top surface of the bit line structure 200 and the second contact pad 700 located on the first contact pad 500 is avoided, the yield of the second contact pad 700 is improved, and the yield of the semiconductor structure is further improved.

It should be noted that, the first contact pad 500 may be directly connected to the active region of the substrate 100 or may be indirectly connected to the active region. Illustratively, the semiconductor structure further includes a plurality of storage contact plugs 300, the plurality of storage contact plugs 300 being disposed in one-to-one correspondence with the plurality of first contact pads 500, i.e., one storage contact plug 300 is disposed at a bottom surface of each first contact pad 500. Each storage contact plug 300 is used to realize connection between the capacitor structure and the active region to write storage data into the capacitor structure.

The bottom of each storage contact plug 300 extends to the substrate 100, so that the contact area between the storage contact plug 300 and the substrate 100 can be increased, the contact resistance between the storage contact plug 300 and the active region can be reduced, and the performance of the semiconductor structure can be improved.

In one possible implementation, second contact pad 700 includes a first segment 710, a second segment 720, and a third segment 730. In two adjacent bit line structures 200, a first segment 710 is disposed over the first contact pad 500, a second segment 720 is connected to an end of the first segment 710 facing away from the first contact pad 500, and the second segment 720 is located on a side of one of the bit line structures 200. The third section 730 is connected to an end of the second section 720 facing away from the first section 710, and the third section 730 is located on the top surface of the bit line structure 200 such that the second contact pad 700 has a zigzag shape.

In the same bit line structure 200, the dimension of the bit line structure 200 at the position opposite to the second section 720 is smaller than the dimension of the bit line structure 200 at the position opposite to the first section 710, that is, D1 is smaller than D2. By the arrangement, the adjacent second contact pads 700 can be prevented from being electrically connected, and the yield of the semiconductor structure is improved. Accordingly, the distance between two second segments 720 in adjacent second contact pads 700 can also be reduced to reduce parasitic capacitance between adjacent second contact pads 700, thereby improving performance of the semiconductor structure.

In one possible embodiment, the cross-sectional area of the first section 710 is greater than the contact area of the first contact pad 500 in a cross-section perpendicular to the substrate 100.

That is, in the first direction, the size of the first section 710 is greater than the size of the first contact pad 500 such that the cross-sectional area of the first section 710 is greater than the contact area of the first contact pad 500. The contact area between the first segment 710 and the first contact pad 500 may be increased, the contact resistance between the first segment 710 and the first contact pad 500 may be reduced, and thus the signal delay between the first segment 710 and the first contact pad 500 may be reduced, improving the performance of the semiconductor structure.

In one possible implementation, the first contact pad 500 includes a barrier layer 510 and a second conductive layer 520, the second conductive layer 520 being disposed within an area surrounded by the barrier layer 510. The barrier layer 510 serves to prevent the conductive material in the second conductive layer 520 from penetrating into the bit line structure 200, improving the conductive performance of the first contact pad 500.

Wherein the barrier layer 510 includes a first barrier layer 511 and a second barrier layer 512 which are stacked, the first barrier layer 511 being disposed on the storage contact plug 300; the first barrier layer 511 and the second barrier layer 512 are different in material. For example, the material of the first barrier layer 511 includes titanium; the material of the second barrier layer 512 includes titanium nitride. By the arrangement, the blocking effect of the blocking layer 510 can be improved, and meanwhile, the blocking layer 510 can be guaranteed to have certain conductive performance, so that timeliness of signal transmission between the active area and the capacitor structure is guaranteed.

In one possible embodiment, the semiconductor structure includes a buffer layer 800, the buffer layer 800 being disposed between the storage contact plug 300 and the first contact pad 500.

The material of the storage contact plug 300 typically includes polysilicon, and the material of the barrier layer 510 in the first contact pad 500 typically includes titanium or titanium nitride. If the storage contact plug 300 is in direct contact with the first contact pad 500, a certain stress is generated therebetween, which may cause separation between the storage contact plug 300 and the first contact pad 500. Further, the contact resistance between the storage contact plug 300 and the first contact pad 500 is large.

The buffer layer 800 is disposed between the storage contact plug 300 and the first contact pad 500, and the buffer layer 800 is used for reducing the contact resistance between the storage contact plug 300 and the first contact pad 500, and also reducing the stress between the storage contact plug 300 and the first contact pad 500, preventing the separation of the storage contact plug 300 and the first contact pad 500, and improving the yield of the semiconductor structure.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method of fabricating a semiconductor structure, comprising the steps of:

2. The method of manufacturing a semiconductor structure of claim 1, wherein after the step of forming the first contact pad, before the step of forming the second contact pad, the method further comprises:

3. The method of claim 2, wherein the bit line structure comprises a bit line and an isolation sidewall covering a sidewall of the bit line; the isolation side wall comprises a first isolation layer, a second isolation layer and a third isolation layer which are arranged in a stacked mode, and the first isolation layer is connected with the side wall of the bit line;

4. A method of fabricating a semiconductor structure according to any one of claims 1-3, wherein forming the second contact pad on the first contact pad extending to the top and side surfaces of the bit line structure comprises:

5. A method of fabricating a semiconductor structure according to any one of claims 1-3, wherein the step of forming the first contact pad comprises:

6. The method of fabricating a semiconductor structure of claim 5, wherein the step of forming the first contact pad comprises:

Forming a second conductive material layer on the barrier material layer;

7. The method of manufacturing a semiconductor structure of claim 5, wherein the barrier material layer comprises a first barrier material layer and a second barrier material layer; the first blocking material layer is arranged on the inner wall of the first contact hole, and the second blocking material layer is arranged on the first blocking material layer.

8. The method of claim 6, wherein the etching process comprises a wet etching process.

9. The method of fabricating a semiconductor structure of claim 4, wherein removing a portion of the first conductive layer comprises:

10. A semiconductor structure, the semiconductor structure comprising:

11. The semiconductor structure of claim 10, wherein the second contact pad comprises a first segment, a second segment, and a third segment connected in sequence, the first segment being disposed at a bottom of the first contact hole, the second segment being disposed on a side of the bit line structure, the third segment being connected to the second segment and being located on a top surface of the bit line structure;

12. The semiconductor structure of claim 11, wherein the first contact pad comprises a barrier layer and a second conductive layer;

13. The semiconductor structure of claim 12, wherein the barrier layer comprises a first barrier layer and a second barrier layer disposed in a stack, the first barrier layer disposed on the storage contact plug;

the first barrier layer and the second barrier layer are different in material.

14. The semiconductor structure of any of claims 11-13, wherein a cross-sectional area of the first segment is greater than a cross-sectional area of the first contact pad in a cross-section perpendicular to the substrate.

15. The semiconductor structure of any of claims 10-13, wherein the bit line structure comprises a bit line and an isolation sidewall covering the bit line sidewall; the isolation side wall comprises a first isolation layer, a second isolation layer and a third isolation layer which are arranged in a laminated mode, and the first isolation layer is connected with the side wall of the bit line.