CN118351906A

CN118351906A - Refreshing circuit, method and memory

Info

Publication number: CN118351906A
Application number: CN202310025866.7A
Authority: CN
Inventors: 谷银川
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-01-09
Filing date: 2023-01-09
Publication date: 2024-07-16
Also published as: WO2024148706A1

Abstract

The embodiment of the disclosure provides a refresh circuit, a refresh method and a memory, wherein the refresh circuit comprises: a refresh address generator configured to count a refresh operation to generate a first count value, generate and output a row address signal based on the first count value, and output a switching flag signal based on a comparison result of the first count value and a first threshold value; a weak address storage module configured to store and output a weak address signal; a selection module configured to receive the switching flag signal, the row address signal, and the weak address signal, select one of the row address signal and the weak address signal as an address signal to be refreshed based on the switching flag signal, and output; and the refreshing module is configured to receive the refreshing command signal and the address signal to be refreshed, and execute one-time refreshing operation on the memory row indicated by the address signal to be refreshed based on the refreshing command signal. Thus, the refresh circuit can improve the storage stability and improve the data failure phenomenon.

Description

Refreshing circuit, method and memory

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a refresh circuit, a refresh method, and a memory.

Background

The dynamic random access memory (Dynamic Random Access Memory, DRAM) has an error checking and correction (Error Check and Correct, ECC) mode and an error checking and clearing ECS (Error Check and Scrub, ECS) mode. The ECC mode can automatically correct errors of single-bit failed in the DRAM, and the ECS mode can periodically check and correct data. Currently, due to the gradual reduction of the volume of the DRAM, a Single-Bit Fail (Single-Bit Fail) phenomenon of a memory cell in the DRAM is rapidly increased, resulting in a decrease in yield of the DRAM, which affects the performance of the memory.

Disclosure of Invention

The present disclosure provides a refresh circuit, method and memory capable of improving storage stability and improving a data failure phenomenon.

The technical scheme of the present disclosure is realized as follows:

in a first aspect, embodiments of the present disclosure provide a refresh circuit, comprising:

a refresh address generator configured to count a refresh operation to generate a first count value, generate and output a row address signal based on the first count value, and output a switching flag signal based on a comparison result of the first count value and a first threshold value;

a weak address storage module configured to store and output a weak address signal; wherein the weak address signal indicates a memory row in which an error bit is greater than a second threshold in an error checking and clearing (ECS) operation;

A selection module configured to receive the switching flag signal, the row address signal, and the weak address signal, select one of the row address signal and the weak address signal as an address signal to be refreshed based on the switching flag signal, and output;

And the refreshing module is configured to receive the refreshing command signal and the address signal to be refreshed, and execute a refreshing operation on the memory row with knowledge of the address signal to be refreshed based on the refreshing command signal.

In some embodiments of the present invention, in some embodiments,

The refresh address generator is specifically configured to output the switching flag signal at a first level when the first count value is smaller than the first threshold value; outputting the switching flag signal at a second level when the first count value is equal to or greater than the first threshold value;

The selection module is specifically configured to output the row address signal as the address signal to be refreshed when the switching flag signal is at a first level; and outputting the weak address signal as the address signal to be refreshed when the switching flag signal is at a second level.

In some embodiments, the refresh module is further configured to generate and output a count clock signal; wherein a count pulse is generated on the count clock signal before each refresh operation is performed;

The refresh address generator is further configured to receive the count clock signal; and adding one to the first count value according to each count pulse on the count clock signal.

In some embodiments, the weak address storage module stores a plurality of the weak address signals;

the refresh address generator is further configured to output the count clock signal as a weak address clock signal when the switching flag signal is at a second level; when the switching mark signal is in a first level state, the level state of the weak address clock signal is kept unchanged;

The weak address storage module is specifically configured to receive the weak address clock signal and sequentially output the weak address signal according to each counting pulse on the weak address clock signal.

In some embodiments, the refresh address generator is further configured to reset the first count value when the first count value reaches a third threshold; wherein the third threshold is greater than the first threshold.

In some embodiments, the first count value includes an M-bit sub-signal, and an mth-bit sub-signal is a highest-bit sub-signal; the row address signal includes an N-bit sub-signal;

The refresh address generator outputs 1 st to N th bit sub-signals of the first count value as the row address signals; and outputting an Mth bit sub-signal of the first count value as the switching flag signal; the row address signal indicates a next memory row in an auto-refresh mode;

wherein M is an integer greater than 1, N is an integer greater than or equal to 1 and less than M, and the first threshold is a power of 2 to (M-1).

In some embodiments, the refresh address generator comprises an asynchronous binary counter, a first and gate, and a second and gate, wherein:

The asynchronous binary counter comprises M sequentially cascaded triggers, wherein the input end of each stage of trigger is connected with the inverting output end of the trigger, the non-inverting end output end of the ith stage of trigger is used for outputting the ith sub-signal of the first count value, the clock end of the 1 st stage of trigger is used for receiving the count clock signal, and the clock end of the (i+1) th stage of trigger is connected with the inverting output end of the ith stage of trigger; wherein i is an integer of 1 or more and less than M;

The first input end of the first AND gate is connected with the normal phase output end of the trigger of the M-th stage, the second input end of the first AND gate is connected with the normal phase output end of the L-th trigger, and the output ends of the first AND gate are connected with the reset ends of all the triggers;

The first input end of the second AND gate is connected with the normal phase output end of the trigger of the M-th stage, the second input end of the second AND gate receives the counting clock signal, and the output end of the second AND gate is used for outputting the weak address clock signal;

When the non-inverting output end of the Mth trigger is at a high level, the first count value is larger than or equal to the first threshold value; when the positive phase output end of the Mth trigger and the positive phase output end of the L th trigger are at a high level, the first count value reaches the third threshold value; wherein L is a positive integer less than or equal to N.

In some embodiments, the weak address storage module is further configured to receive a current ECS operation row address signal and a corresponding storage flag signal, store the current ECS operation row address signal as the weak address signal when the storage flag signal is valid;

Wherein the storage flag signal indicates whether an error bit of a storage row corresponding to the current ECS operation row address signal is greater than a second threshold.

In some embodiments, the weak address storage module comprises a first-in first-out register, a latch, an address comparator, and a logic unit, wherein:

The first-in first-out register is configured to store a plurality of weak address signals and output the weak address signals according to a first-in first-out sequence;

the latch is configured to latch the weak address signal stored last time;

The address comparator is configured to receive the current ECS operation row address signal and the weak address signal stored last time; outputting a valid update flag signal when the current ECS operation row address signal and the last stored weak address signal are different;

the logic unit is configured to receive the storage flag signal and the update flag signal; outputting a valid load clock signal when both the store flag signal and the update flag signal are valid;

The latch is further configured to receive the load clock signal and the current ECS operation row address signal; when the loading clock signal is valid, latching the current ECS operation row address signal as the weak address signal to be stored;

the first-in first-out register is further configured to receive the load clock signal delayed by a first preset time and the weak address signal to be stored, and store the weak address signal to be stored based on the load clock signal.

In some embodiments, the first-in first-out register is further configured to receive the weak address clock signal, and sequentially output the weak address signal based on the weak address clock signal.

In some embodiments, the logic unit comprises a third and gate and a pulse generator, wherein:

The first input end of the third AND gate receives the storage mark signal, the second input end of the third AND gate receives the update mark signal, the output end of the third AND gate is connected with the input end of the pulse generator, and the output end of the pulse generator is used for outputting a loading clock signal.

In some embodiments, the pulse generator comprises a first not gate, a delay unit, and a fourth and gate, wherein:

The input end of the first NOT gate is connected with the output end of the third AND gate, the output end of the first NOT gate is connected with the input end of the delay unit, the output end of the delay unit is connected with the second input end of the fourth AND gate, the first input end of the fourth AND gate is connected with the output end of the third AND gate, and the output end of the fourth AND gate is used for outputting the loading clock signal.

In some embodiments, the refresh circuit further comprises an ECS module and a threshold module, wherein:

The ECS module is configured to output the current ECS operation row address signal and a second count value; wherein the second count value refers to the number of error bits of the memory row corresponding to the current ECS operation row address signal;

The threshold module is configured to receive the second count value and output the storage mark signal based on a comparison result of the second count value and the second threshold value; if the second count value is greater than or equal to the second threshold value, outputting the effective storage mark signal; and outputting the invalid storage mark signal if the second count value is smaller than the second threshold value.

In some embodiments, the threshold module is further configured to receive a threshold setting signal, the threshold module setting the second threshold according to the threshold setting signal.

In a second aspect, an embodiment of the present disclosure provides a refresh method applied to the refresh circuit according to the first aspect, the method including:

adding a first count value before the memory performs refresh operation each time;

When the first count value is smaller than a first threshold value, refreshing the next memory row according to refreshing in an automatic refresh mode;

Performing refresh operation on the weak memory line under the condition that the first count value is greater than or equal to a first threshold value; wherein, the weak memory line refers to a memory line with an error bit greater than a second threshold in the ECS mode.

In some embodiments, when the first count value reaches a third threshold value, resetting the first count value;

wherein the third threshold is greater than the first threshold.

In some embodiments, during the period that the first count value is at the first threshold value and the third threshold value, the memory sequentially refreshes memory rows corresponding to a plurality of weak address signals.

In a third aspect, embodiments of the present disclosure provide a memory comprising a refresh circuit as described in the first aspect.

The embodiment of the disclosure provides a refresh circuit, a refresh method and a memory, wherein the refresh circuit comprises: a refresh address generator configured to count a refresh operation to generate a first count value, generate and output a row address signal based on the first count value, and output a switching flag signal based on a comparison result of the first count value and a first threshold value; a weak address storage module configured to store and output a weak address signal; wherein the weak address signal indicates a memory row having an error bit greater than a second threshold in an error checking and clearing (ECS) operation; a selection module configured to receive the switching flag signal, the row address signal, and the weak address signal, select one of the row address signal and the weak address signal as an address signal to be refreshed based on the switching flag signal, and output; and the refreshing module is configured to receive the refreshing command signal and the address signal to be refreshed, and execute one-time refreshing operation on the memory row indicated by the address signal to be refreshed based on the refreshing command signal. In this way, according to the switching flag signal, the refresh circuit selects to execute the refresh operation on the normal row address signal or the weak address signal detected by the ECS operation, and can additionally insert the refresh operation on the memory row corresponding to the weak address signal in the normal refresh operation, thereby improving the storage stability and improving the data failure phenomenon.

Drawings

Fig. 1 is a schematic diagram of an ECC mode according to an embodiment of the present disclosure;

Fig. 2 is a schematic diagram of a refresh circuit according to an embodiment of the present disclosure;

Fig. 3 is a schematic diagram of a refresh circuit according to a second embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a refresh address generator according to an embodiment of the present disclosure;

Fig. 5 is a schematic diagram of a refresh address generator according to a second embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a weak address memory module according to an embodiment of the disclosure;

fig. 7 is a schematic diagram ii of a weak address memory module according to an embodiment of the disclosure;

Fig. 8 is a schematic diagram III of a refresh circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic flow chart of a refreshing method according to an embodiment of the disclosure;

Fig. 10 is a schematic diagram of a composition structure of a memory according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first/second/third" in relation to embodiments of the present disclosure is used merely to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if permitted, to enable embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described herein.

Before proceeding to further detailed description of the embodiments of the present disclosure, the terms and terms involved in the embodiments of the present disclosure will be described, which are suitable for the following explanation:

A dynamic random access memory (Dynamic Random Access Memory, DRAM);

-a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM);

double Data Rate (DDR);

generation 5 DDR (5 th DDR, DDR 5);

Low power DDR (Low Power Double Data Rate, LPDDR);

Error checking and correction (Error Check and Correct, ECC);

Error checking and clearing (Error Check and Scrub, ECS);

Each row of error counters (Error per Row Counter, epRC).

With the scaling of the process, the Single-Bit Fail (Single-Bit Fail) challenge becomes more and more severe. Taking DDR5 DRAM as an example, to cope with single bit failures, an On-Die ECC (On-Die ECC) structure is introduced so that the DRAM can automatically correct the failed single bit. Based On-Die ECC, DDR5 has also introduced ECS operations that perform at least one complete error check and clear of DRAM within 24 hours, including error checking of all Banks (BG), blocks (Bank, BA), rows (Row), and columns (Col) of DRAM. The ECS operation may record the row address with the highest number of data failures in a complete ECS cycle and send it to a Mode Register (MR) for readout by the Controller (Controller) of the memory.

As shown in fig. 1, the ECS Address generator (ECS ADDRESS Counters) gives the storage line Address of the detection object, after the ECC Error correction logic module (ECC Correction Logic) detects that the data in the storage line fails, the count value of the Error Counter (EC) and each line Error Counter (EpRC) are increased by one, after reading all Code words (Code Word) in the storage line, the comparison module (computer) compares the current line Error count with the maximum line Error count (Previous High Error Count), and if the current line Error count is greater than the maximum line Error count, the current line Error count and the storage line Address of the detection object replace the maximum line Error count and the maximum line Error Address (Previous High Error Count Row/Bank Address) to be saved in the MR; if the current row error count is not greater than the maximum row error count, the maximum row error count and the maximum row error address will always be saved in the MR. In particular, the (Reset) error counter is Reset every time a row address is toggled.

After the DRAM completes a complete ECS operation, the maximum row error address is saved in the mode register MR <16:18>, and the maximum row error count is saved in MR 19. While the MR recorded Row/codeword error count REC [5:0] (Row/Word Code Error Count, REC) is shown as being within range, the Row error count threshold (Row Error Threshold Count, RETC) may mask codeword error counts less than the set threshold, with RETC default value of 4 in DDR 5. It should be appreciated that FIG. 1 is from a solid State technology Association industry Standard document, and that those skilled in the art will be able to see SPEC for meanings related to various nouns and abbreviations, and that this section does not influence an understanding of the disclosed embodiments, and so will not be described in detail herein.

However, the conventional ECC check method (hamming code) in DRAM has a limitation that only a failed single Bit can be corrected, and if a Double-Bit Fail (Double-Bit Fail) or a multiple-Bit Fail (Multi-Bit Fail) occurs in the memory, a memory read data error will be caused. The checking period of the ECS mode is 24 hours, and only the row address with the most failed bits is recorded, and other memory rows with a plurality of errors checked in the ECS mode are not recorded, so that the phenomenon of single-bit failure cannot be fundamentally and greatly improved.

Based on this, in order to improve occurrence of the data failure phenomenon, the embodiment of the disclosure provides a refresh circuit, which performs a refresh operation based on a normal row address signal or an ECS operation to detect that there are a plurality of erroneous memory rows, and can additionally insert a refresh operation for a memory row corresponding to a weak address signal in the normal refresh operation, thereby improving storage stability and improving the data failure phenomenon.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to fig. 2, a schematic diagram of the composition of a refresh circuit 10 provided in an embodiment of the present disclosure is shown. As shown in fig. 2, the refresh circuit 10 includes:

a refresh address generator 101 configured to count a refresh operation to generate a first count value, generate and output a row address signal based on the first count value, and output a switching flag signal based on a comparison result of the first count value and a first threshold value;

A weak address storage module 102 configured to store and output a weak address signal; wherein the weak address signal indicates a memory row having an error bit greater than a second threshold in an error checking and clearing (ECS) operation;

A selection module 103 configured to receive the switching flag signal, the row address signal, and the weak address signal, select one of the row address signal and the weak address signal as an address signal to be refreshed based on the switching flag signal, and output;

The refresh module 104 is configured to receive the refresh command signal and the address signal to be refreshed, and perform a refresh operation on the memory row indicated by the address signal to be refreshed based on the refresh command signal.

It should be noted that the refresh circuit 10 of the embodiment of the present disclosure may be applied to, but not limited to, a memory, such as DRAM, SDRAM, DDR. In addition, in other analog/digital circuits, the memory stability can be improved by the refresh circuit 10 provided by the embodiments of the present disclosure.

Note that the row Address signal, the switching flag signal, the weak Address signal, the refresh command signal, and the Address signal to be refreshed in fig. 2 are denoted by Normal REF Addr, addr Exchange Flag, out Address, REF AB CMD, and REFRESH ADDRESS, respectively, in the following explanation.

It should be noted that the memory controller typically periodically inputs a refresh command signal (REF AB CMD) to the memory at predetermined time intervals calculated based on the data retention time of the memory. Some memory cells in the memory are called Weak cells (Weak cells) and the corresponding addresses are called Weak addresses if the data retention time of the memory cells does not satisfy the prescribed reference time.

In addition, since ultra-high integration requires integration of at least several tens of millions of memory cells into one chip, the probability of weak cells being present increases even though the manufacturing process has been greatly improved. Therefore, it is necessary to increase the refresh frequency of weak cells to ensure the integrity of the memory data.

Note that the refresh operation of the memory is divided into two types: auto Refresh (AR) and self Refresh (SELF REFRESH, SR). No external supply of row address information is required, whatever the refresh mode, since this is an internal automatic operation. For AR, a row address generator (or refresh address generator 101) is provided inside the SDRAM to automatically generate row addresses in sequence. Since the refresh is performed for all banks in a Row, no Column addressing is required, or Column address selection (Column ADDRESS SELECT, CAS) is active before Row address selection (Row ADDRESS SELECT, RAS). Therefore, the AR is also called CBR (CAS Before RAS, column ahead of row location) refresh. The refresh sequence of the refresh address generator 101 is to sequentially refresh the internally generated row addresses.

It will be appreciated that each refresh command signal (REF AB CMD) may allow the memory to perform multiple refresh operations, as determined by the refresh circuitry of each DRAM product design. In addition, each refresh operation should have an internal refresh command, and the refresh address generator 101 is used to count the number of refresh operations in this embodiment of the disclosure, and each refresh operation not only refreshes one row, but also refreshes multiple rows (which may be consecutive multiple rows or multiple rows in a certain logic order) of Bank at the same time. For example, if 6 refresh operations (where 4 normal row addresses are refreshed and 2 weak addresses are refreshed) can be performed per refresh command, each refresh operation simultaneously refreshes 4 rows, which is equivalent to 4×4=16 rows per refresh command, and if there are 1024 rows in 1 Bank, 64 refresh commands are needed to complete 1 refresh of all addresses; if 3 refresh operations (2 times of refreshing normal row addresses and 1 time of refreshing weak addresses) can be performed per refresh command, each refresh operation simultaneously refreshes 4 rows, which is equivalent to 2×4=8 rows per refresh command, if there are 1024 rows in 1 Bank, 128 refresh commands are needed to complete 1 refresh of all addresses. In both cases, the time intervals of the refresh commands are different.

It should be further noted that, the main function of the refresh address generator 101 is to count the number of refresh operations in the memory and generate a row address signal (Normal REF Addr) indicating the next address to be refreshed in the auto-refresh mechanism; the weak Address memory module 102 outputs a weak Address signal (Out Address) indicating an Address of a memory row to which the weak cell belongs. Meanwhile, the refresh Address generator 101 outputs a switching flag signal (Addr Exchange Flag) based on the relationship between the first count value and the first threshold value, where the switching flag signal (Addr Exchange Flag) is used to select a row Address signal (Normal REF Addr) or a weak Address signal (Out Address) as a next refresh object, so that a refresh operation for weak cells/weak addresses is inserted in the Normal refresh mechanism, thereby avoiding a memory row failure corresponding to the weak Address signal (Out Address) and improving data stability.

In some embodiments, the refresh address generator 101 is specifically configured to output a switching flag signal (Addr Exchange Flag) at a first level when the first count value is less than a first threshold; outputting a switching flag signal (Addr Exchange Flag) at a second level when the first count value is equal to or greater than the first threshold value;

A selection module 103 specifically configured to output a row address signal (Normal REF Addr) as an address signal to be refreshed (REFRESH ADDRESS) when the switching flag signal (Addr Exchange Flag) is at a first level; when the switching flag signal (Addr Exchange Flag) is at the second level, a weak Address signal (Out Address) is output as an Address signal (REFRESH ADDRESS) to be refreshed.

Thus, when the first count value is less than the first threshold, the selection module 103 outputs a row address signal (Normal REF Addr) as the address signal to be refreshed (REFRESH ADDRESS) and performs a subsequent refresh operation; when the first count value is greater than or equal to the first threshold value, the refresh Address generator 101 outputs a switching flag signal (Addr Exchange Flag), thereby changing the selection module 103 to output a weak Address signal (Out Address) and performing a subsequent refresh operation.

That is, in the refresh process, after performing the traversal refresh on the memory rows corresponding to all Normal row Address signals (Normal REF Addr) in each pair of memories, the refresh on the weak Address signal (Out Address) is inserted; in addition, after performing the traversal refresh on the memory row corresponding to the partial Normal row Address signal (Normal REF Addr), the refresh on the weak Address signal (Out Address) may be inserted, where the first thresholds set in the above two cases are different.

Specifically, the first threshold may be selected according to an actual application scenario. The memory array in the memory includes a plurality of memory groups, each memory group includes a plurality of banks, each Bank includes 4096 memory rows, and in the refreshing process, after the memory rows corresponding to all word lines in each Bank are traversed and refreshed, refreshing of the weak Address signal (Out Address) is inserted. In the refresh process, the row address signal (Normal REF Addr) output by the selection module 103 is a row address signal of Bank, and the first threshold is set to be a maximum 4096 of the number of Bank row addresses correspondingly; in other embodiments, 1 Bank may be divided into 16 segments (sections), each Section may include 256 word lines, and during the refresh process, after the memory rows (part of the Normal row Address signals of the Bank) corresponding to all the word lines in each Section are traversed and refreshed, that is, the weak Address signals (Out Address) are inserted, during the refresh process, the row Address signal (Normal REF Addr) output by the selection module 103 is the row Address signal (part of the fields of the Bank row Address signals) of the Section, and the first threshold is set to be 256 corresponding to the maximum value of the number of row addresses of the Section.

It should be further noted that the selecting module 103 may adopt a two-Out selector, and includes a first input terminal, a second input terminal, a control terminal and an output terminal, where the first input terminal is a row Address signal (Normal REF Address), the second input terminal is a weak Address signal (Out Address), and the output terminal selects and outputs one of the row Address signal (Normal REF Address) and the weak Address signal (Out Address) based on the switching flag signal (Addr Exchange Flag) of the control terminal.

Illustratively, for the switch flag signal (Addr Exchange Flag), the first level refers to a level state of low (0) and the second level refers to a level state of high (1). Specifically, when the switch flag signal (Addr Exchange Flag) is 0, the selection module 103 outputs a row address signal (Normal REF Addr); when the switching flag signal (Addr Exchange Flag) is 1, the selection module 103 outputs a weak Address signal (Out Address). That is, it is determined whether the row Address signal (Normal REF Addr) or the weak Address signal (Out Address) is refreshed by setting the control switch flag signal (Addr Exchange Flag) to 0 or 1. Similarly, the switch flag signal (Addr Exchange Flag) may be set to be active when set to 0 and inactive when set to 1, specifically determined according to the internal circuit structure of the selection module 103 and the function of the switch flag signal (Addr Exchange Flag) in the circuit.

In this way, the refresh circuit 10 can control the selection module 103 to output a row Address signal (Normal REF Addr) or a weak Address signal (Out Address) through the switching flag signal (Addr Exchange Flag) and perform subsequent refresh, so that the refresh frequency of the weak cells in the memory is improved, the possibility of failure of the stored data is reduced, and the integrity of the data is ensured.

In some embodiments, referring to fig. 4, the first count value includes an M-bit sub-signal, and the M-th sub-signal is the highest sub-signal; the row address signal (Normal REF Addr) includes an N-bit sub-signal;

The refresh address generator 101 outputs 1 st to N th bit sub-signals of the first count value as a row address signal (Normal REF Addr); and outputting an Mth bit sub-signal of the first count value as a switching flag signal (Addr Exchange Flag); a row address signal (Normal REF Addr) indicates a next memory row in the auto-refresh mode;

Here, the number of row address signals (Normal REF Addr) is 2 ^N. When the first count value of the refresh Address generator 101 reaches the first threshold 2 ^(M-1), the refresh Address generator 101 outputs the mth bit sub-signal of the first count value as a switching flag signal (Addr Exchange Flag) at the second level, so as to control the selection module 103 to output the weak Address signal (Out Address) as the Address signal to be refreshed (REFRESH ADDRESS).

It should be further noted that, in the embodiment of the present disclosure, the refresh Address generator 101 generates the switch flag signal (Addr Exchange Flag) at the second level for refreshing the weak Address signal (Out Address) after 2 ^(M-1-N) times of refreshing of all the row Address signals (Normal REF Addr) by the refresh module 104; after generating the switching flag signal (Addr Exchange Flag) at the second level, the refresh Address generator 101 generates a reset signal after a refresh operation for isolating a plurality of weak Address signals (Out addresses), so that the switching flag signal (Addr Exchange Flag) is restored to the first level, and the refresh Address generator 101 restarts counting for performing a normal refresh operation.

In some embodiments, as shown in FIG. 3, refresh module 104 is further configured to generate and output a count clock signal (CBR_CLK); wherein a count pulse is generated on the count clock signal (cbr_clk) before each refresh operation is performed;

The refresh address generator 101 is further configured to receive a count clock signal (cbr_clk); and increments the first count value according to each count pulse on the count clock signal (cbr_clk).

It should be noted that, the refresh module 104 performs refresh according to the refresh command signal (REF AB CMD) and the address signal to be refreshed (REFRESH ADDRESS). Specifically, after the refresh module 104 completes the refresh operation for a specific number of row addresses, the generated plurality of count clock signals (cbr_clk) are sent to the refresh address generator 101, and the first count value of the refresh address generator 101 is incremented by 1. In addition, in one example, each memory includes 2048 refresh rows, and row addresses (REF ab_cnt <10:0 >) are 00000000000, 00000000001, 00000000010 … … in order, so the first count value REF ab_cnt <10:0> is the row address signal (Normal REF Addr); when REF ab_cnt <11> =1 in the first count value (i.e., when REF ab_cnt <11:0> is changed from 01111111111111 to 100000000000), it indicates that the refresh of the memory row Address signal (Normal REF Addr) is completed, and the refresh of the weak Address signal (Out Address) may be inserted.

In some embodiments, as shown in fig. 3, the weak Address storage module 102 stores a plurality of weak Address signals (Out addresses);

the refresh address generator 101 is further configured to output the count clock signal (cbr_clk) as a weak address clock signal (out_clk) when the switching flag signal (Addr Exchange Flag) is at the second level; when the switching flag signal (Addr Exchange Flag) is at the first level, the level state of the weak address clock signal (out_clk) is kept unchanged;

The weak Address storage module 102 is specifically configured to receive the weak Address clock signal (out_clk) and sequentially output the weak Address signal (Out Address) according to each count pulse on the weak Address clock signal (out_clk).

It should be noted that, there may be a plurality of weak memory cells in the memory, and thus the number of weak Address signals (Out addresses) may be a plurality.

It should be further noted that, in the embodiment of the present disclosure, during the period when the switch flag signal (Addr Exchange Flag) is at the second level, all weak Address signals (Out Address) need to be traversed for refreshing, so that the stability of all weak memory cells is better improved. That is, if the switching flag signal (Addr Exchange Flag) is at the second level, the refresh Address generator 101 outputs the weak Address clock signal (out_clk) to the weak Address storage block 102 according to the count clock signal (cbr_clk), so that the weak Address storage block 102 sequentially outputs the weak Address signal (Out Address) according to each count pulse on the weak Address clock signal (out_clk) to perform a refresh operation on the weak Address signal (Out Address).

Specifically, when the switch flag signal (Addr Exchange Flag) is at the first level, the weak Address clock signal (out_clk) does not have a count pulse, and a plurality of weak Address signals (Out Address) are stored in the weak Address storage module 102; when the switch flag signal (Addr Exchange Flag) is at the second level, the weak Address clock signal (out_clk) has a count pulse, and when the weak Address clock signal (out_clk) arrives, the weak Address storage module 102 sequentially outputs the stored plurality of weak Address signals (Out Address) in response to the count pulse on the weak Address clock signal (out_clk) to sequentially perform a refresh operation on the memory row corresponding to the weak Address signal (Out Address).

In this way, since the refresh Address generator 101 stops refreshing the row Address signal (Normal REF Addr) when the switching flag signal (Addr Exchange Flag) is generated, it is possible to avoid a memory failure caused by simultaneously performing the refresh operation of the row Address signal (Normal REF Addr) during the refresh operation of the weak Address signal (Out Address).

In some embodiments, as shown in fig. 4, the refresh address generator 101 is further configured to perform a reset process on the first count value when the first count value reaches a third threshold; wherein the third threshold is greater than the first threshold.

Thus, the switching flag signal (Addr Exchange Flag) and the weak address clock signal (out_clk) at the second level are generated every time the refresh is completed for all the row address signals (Normal REF Addr). The weak Address clock signal (out_clk) is outputted to the weak Address storage module 102, and then the command selection module 103 outputs the weak Address signal (Out Address), after the first count value reaches the third threshold, and after the refresh of part or all of the weak Address signal (Out Address) in the memory is completed, the refresh Address generator 101 is reset, and at this time, the switching flag signal (Addr Exchange Flag) becomes the first level, and the refresh Address generator 101 performs the next cycle.

It should be noted that the third threshold value and the first threshold value are fixed values set in advance, and the number of times of the auto-refresh operation and the number of times of the weak address refresh operation are related to the first threshold value and the third threshold value, respectively; the number of weak Address signals (Out addresses) is not determined and is independent of the first and third thresholds, and is related to the performance of the memory and the environmental parameters in which the current ECS test is performed. Specifically, the difference between the third threshold and the first threshold is the number of weak Address signals (Out addresses) that the weak Address storage module 102 sequentially outputs to the refresh module 104 to perform the refresh operation, and the number may be far greater than or less than the number of weak Address signals (Out addresses) stored in the weak Address storage module 102. Therefore, it is necessary to modify the first threshold value and the third threshold value according to the actual situation to improve the above-described mismatch situation.

As shown in fig. 4, the third threshold value and the first threshold value may be modified by parameters in the mode register in the test mode. Specifically, in response to control of the control signal (Choose Control), the selector (MUX) 23 may select the data bit of the first count value that is output as the switching flag signal (Addr Exchange Flag), that is, the first count value (first threshold value) that needs to be satisfied when the switching flag signal (Addr Exchange Flag) is output. Similarly, the selector 23 may select the data bit of the first count value output as the reset flag signal in response to the control of the control signal (Choose Control), and select the first count value (third threshold value) to be satisfied when the reset flag signal is output.

In some embodiments, as shown in fig. 4 and 5, the refresh address generator 101 includes an asynchronous binary counter 20, a first and gate 21, and a second and gate 22, wherein:

The asynchronous binary counter 20 comprises M sequentially cascaded flip-flops, wherein the input end of each stage of flip-flop is connected with the inverting output end of each stage of flip-flop, the output end of the non-inverting end of the i-th stage of flip-flop is used for outputting an i-th bit sub-signal of a first count value, the clock end of the 1-th stage of flip-flop is used for receiving a count clock signal (CBR_CLK), and the clock end of the i+1-th stage of flip-flop is connected with the inverting output end of the i-th stage of flip-flop; wherein i is an integer of 1 or more and less than M;

The first input end of the first AND gate 21 is connected with the normal phase output end of the Mth stage trigger, the second input end of the first AND gate 21 is connected with the normal phase output end of the L-th stage trigger, and the output end of the first AND gate 21 is connected with the reset ends of all the triggers;

The first input end of the second and gate 22 is connected with the non-inverting output end of the mth stage flip-flop, the second input end of the second and gate 22 receives the count clock signal (cbr_clk), and the output end of the second and gate 22 is used for outputting the weak address clock signal (out_clk);

When the positive phase output end of the Mth trigger is at a high level, the first count value is larger than or equal to a first threshold value; when the positive phase output end of the Mth trigger and the positive phase output end of the L-th trigger are at a high level, the first count value reaches a third threshold value; wherein L is a positive integer less than or equal to N.

As shown in fig. 4, the refresh address generator 101 further includes a selector 23 and a first buffer 24, an input terminal of the selector 23 is connected to non-inverting output terminals of the n+1th to mth flip-flops, and an output terminal of the selector 23 outputs a switching flag signal (Addr Exchange Flag) based on the control signal (Choose Control); the input of the first buffer 24 is connected to the non-inverting outputs of the M-N flip-flops, and the output of the first buffer 24 outputs a row address signal (Normal REF Addr).

It should be understood that, as shown in fig. 4, the bit number N of the row address signal (Normal REF Addr) is a fixed value, and the data bit of the first count value outputted as the switching flag signal (Addr Exchange Flag) can be selected by the control signal (Choose Control). Illustratively, the selector 23 may output the n+1th bit of the first count value as the switching flag signal (Addr Exchange Flag), or the n+2th bit of the first count value as the switching flag signal (Addr Exchange Flag) output … …, i.e., the first threshold may be 2 ^N/2^(N+1)/2^(N+2)…/2^(M-1), such that the n+1n+ …/M bit of the first count value may be selected by the selector 23 via the control signal (Choose Control) which bit sub-signal is output as the switching flag signal (Addr Exchange Flag) to control the first threshold. Therefore, by controlling the time interval in which the switching flag signal (Addr Exchange Flag) switches from the first level to the second level, the refresh frequency of the weak Address signal (Out Address) can be controlled.

One input data bit due to the reset flag signal may select the output switching flag signal (Addr Exchange Flag) to control the first threshold value by the control signal of the selector 23; accordingly, another input data bit (REFAB CNT < L-1 >) of the reset flag signal may also be selectively output by the control signal of the selector to control the third threshold. Illustratively, the selector may take the l+1 th bit of the first count value as one input of the reset flag signal, or take the l+2 th bit of the first count value as one input … … of the reset flag signal, i.e., the third threshold may be (2 ^(M-1)+2^L)/(2^(M-1)+2^(L+1))/(2^(M-1)+2^(L+2)) … such that the l+1/l+2 … th bit of the first count value may select which sub-signal is output as the data bit of the other input of the reset flag signal through the control signal of the selector to control the third threshold.

As shown in fig. 5, the embodiment of the present disclosure specifically illustrates an asynchronous binary counter 20 composed of 12D flip-flops (i.e., m=12, n=11). The input terminal of the first buffer 24 of the refresh address generator 101 is connected to the non-inverting output terminals of the 11 flip-flops, and the output terminal of the first buffer 24 outputs a row address signal (Normal REF Addr). In addition, the refresh address generator 101 further includes a second buffer 25, an input terminal of the second buffer 25 is connected to a non-inverting output terminal of the 12 th flip-flop, and an output terminal of the second buffer 25 outputs a switching flag signal (Addr Exchange Flag).

Specifically, the inverting output terminal (QB) of each D flip-flop is connected to the input terminal (D) and to the clock terminal (CLK) of the next stage D flip-flop, the non-inverting output terminal (Q) of each D flip-flop serves as a count terminal, and the reset terminal (RST) resets the level of the non-inverting output terminal (Q) to 0 after receiving the reset signal.

Wherein the clock terminal (CLK) of the first stage D flip-flop 201 is configured to receive the row count clock signal (cbr_clk), the first stage D flip-flop 201 has a first count terminal configured to output REF ab_cnt <0>; the second stage D flip-flop 202 has a second count terminal for outputting REF AB_CNT <1>; third stage D flip-flop 203 has a third count for outputting REF AB_CNT <2> … … and tenth stage D flip-flop 211 has an eleventh count for outputting REF AB_CNT <10>; twelfth stage D flip-flop 212 has a twelfth count for outputting REF ab_cnt <11>.

Thus, when the asynchronous binary counter 20 is reset, the first count value REF ab_cnt <11:0> =000000000000, and once a count clock signal (cbr_clk) is received, the count value is incremented once, that is, the count value REF ab_cnt is incremented in the order of 000000000000, 000000000001, 000000000010, 000000000011 … … 111111111111; when the asynchronous binary counter 20 is reset, the count value returns to the initial state of 000000000000.

Further, the output terminal of the first and gate 21 is connected to the reset terminals of the 12 flip-flops, and when the first input terminal of the first and gate 21 is the count terminal of the twelfth stage D flip-flop 212 and the second input terminal of the first and gate 21 is the count terminal of the seventh stage D flip-flop 207 (i.e., the output of the asynchronous binary counter 20 is 100001000000), the asynchronous binary counter 20 performs a reset operation, which is determined by the counting rule of the counter and the internal structure of the DRAM.

In some embodiments, as shown in fig. 6, the weak address storage module 102 includes a first-in first-out register 30, a latch 31, an address comparator 32, and a logic unit 33, wherein:

A first-in first-Out register 30 configured to store a plurality of weak Address signals (Out Address) and output the weak Address signals (Out Address) in a first-in first-Out order;

A latch 31 configured to store a last stored Weak address signal (weak_addr_ecs_);

An Address comparator 32 configured to receive a current ECS operation Row Address signal (Row Address) and a last stored Weak Address signal (weak_addr_ecs_); outputting a valid update Flag signal (diff_flag) when the current ECS operation Row Address signal (Row Address) and the last stored Weak Address signal (weak_addr_ecs_) are different;

A logic unit 33 configured to receive the storage Flag signal (Bigger _flag) and the update Flag signal (diff_flag), and output a valid load clock signal (in_clk) when both the storage Flag signal (Bigger _flag) and the update Flag signal (diff_flag) are valid;

A latch 31 further configured to receive a load clock signal (in_clk) and a current ECS operation Row Address signal (Row Address), latch the current ECS operation Row Address signal (Row Address) as a weak Address signal (Out Address) to be stored when the load clock signal (in_clk) is valid;

The first-IN first-Out register 30 is further configured to receive a load clock signal (in_clk) delayed by a first preset time and a weak Address signal (Out Address) to be stored, and store the weak Address signal (Out Address) to be stored based on the load clock signal (in_clk).

The clock delay unit 3313 is configured to delay the load clock signal (in_clk) to ensure that the weak Address signal (Out Address) is first entered into the first-IN first-Out register 30, so that the weak Address signal (Out Address) can be stored when the rising edge of the load clock signal (in_clk) arrives.

It should be noted that, after the Weak Address storage module 102 receives the current ECS operation Row Address signal (Row Address), the current ECS operation Row Address signal (Row Address) is compared with the Weak Address signal (weak_addr_ecs_) stored last time; if the two are the same, the current ECS operation Row Address signal (Row Address) is not required to be latched and stored; if the two are different, the Latch (Latch) will Latch the current ECS operation Row Address signal (Row Address) again, and send the current ECS operation Row Address signal (Row Address) as the weak Address signal (Out Address) to be stored into the first in first Out Register (FIRST IN FIRST Out Register) 30.

It should be further noted that, the current ECS operation Row Address signal (Row Address) is latched as the weak Address signal (Out Address) to be stored, so that not only the weak Address signal (Out Address) can be better latched, but also the weak Address signal (Out Address) to be stored is provided for the latch 31.

In some embodiments, as shown in fig. 6, the first-in first-Out register 30 is further configured to receive a weak Address clock signal (out_clk), and sequentially output a weak Address signal (Out Address) based on the weak Address clock signal (out_clk).

It should be noted that the primary function of the first-IN first-Out register 30 is to access an Address, store a weak Address signal (Out Address) to be stored when the load clock signal (IN CLK) has a pulse, and output the weak Address signal (Out Address) to be stored when the weak Address clock signal (out_clk) has a pulse.

In some embodiments, as shown in fig. 7, the logic unit 33 includes a third and gate 330 and a pulse generator 331, wherein:

A first input terminal of the third and gate 330 receives the storage Flag signal (Bigger _flag), a second input terminal of the third and gate 330 receives the update Flag signal (diff_flag), an output terminal of the third and gate 330 is connected to an input terminal of the pulse generator 331, and an output terminal of the pulse generator 331 is configured to output the load clock signal (IN CLK).

The validity of the storage Flag signal (Bigger _flag) and the update Flag signal (diff_flag) may be valid or valid at high level, and the embodiments of the present disclosure will be described by taking valid at high level as an example. As shown in fig. 6, when the storage Flag signal (Bigger _flag) and the update Flag signal (diff_flag) are active high, a corresponding circuit function can be implemented using the third and gate 330; when the store Flag signal (Bigger _flag) and the update Flag signal (diff_flag) are active low, the nor gate may be used to perform the relevant function of the circuit. Therefore, to complete a certain logic function of the circuit, the selection of the gate circuit is not unique, and the selection is performed according to actual needs and the functional structure of the circuit.

When the storage Flag signal (Bigger _flag) and the update Flag signal (diff_flag) are both active, the load clock signal (IN CLK) is active, and the weak Address signal (Out Address) to be stored may be stored IN the fifo 30.

In some embodiments, as shown in fig. 7, the pulse generator 331 includes a first not gate 3310, a delay unit 3311, and a fourth and gate 3312, wherein:

The input end of the first not gate 3310 is connected to the output end of the third and gate 330, the output end of the first not gate 3310 is connected to the input end of the delay unit 3311, the output end of the delay unit 3311 is connected to the second input end of the fourth and gate 3312, the first input end of the fourth and gate 3312 is connected to the output end of the third and gate 330, and the output end of the fourth and gate 3312 is used for outputting a load clock signal (IN CLK).

It should be noted that, the pulse generator 331 is for generating an automatic pulse of 2ns (nanosecond ns), the load clock signal (IN CLK) is valid, the latch 31 latches the weak Address signal (Out Address), and the delay unit 3311 IN the pulse generator 331 causes the load clock signal (IN CLK) to be low after 2ns, so that the output of the latch 31 remains unchanged, and the data can be latched well.

It should be noted that when both input terminals of the fourth and gate 3312 are at high level, a valid load clock signal (IN CLK) is outputted; otherwise, an invalid load clock signal is output. Thus, the nor gate may also be used to implement the relevant functions of the circuit in place of the fourth and gate 3312. That is, when the signals at both inputs of the nor gate are active low, the nor gate outputs an active load clock signal (IN CLK); otherwise, an inactive load clock signal (IN CLK) is output.

In some embodiments, as shown in fig. 8, the refresh circuit further includes an ECS module 105 and a threshold module 106, wherein:

an ECS module 105 configured to output a current ECS operation Row Address signal (Row Address) and a second count value (EpRC); wherein the second count value (EpRC) refers to the number of error bits of the memory Row corresponding to the current ECS operation Row Address signal (Row Address);

A threshold module 106 configured to receive the second count value (EpRC), and output a storage Flag signal (Bigger _flag) based on a comparison result of the second count value (EpRC) and the second threshold; wherein, if the second count value (EpRC) is greater than or equal to the second threshold value, outputting a valid storage Flag signal (Bigger _flag); if the second count value (EpRC) is smaller than the second threshold value, an invalid storage Flag signal (Bigger _flag) is output.

It should be noted that the ECS module 105 may be applied to a related circuit for performing an ECS function in a DRAM DDR5 chip, and the function is to detect a weak memory line in a DRAM and store an Address signal of the detected weak memory line to obtain a weak Address signal (Out Address).

It should be appreciated that the ECS operation is to check all memory cells of each row in turn. Taking the second threshold value of 5 as an example, if the error bit of the current ECS operation row address is less than 5, which indicates that the current ECS operation row address is not a weak address, the threshold module 106 outputs an invalid storage Flag signal (Bigger _flag), and the weak address stored last time is still stored in the weak address storage module 102; if the error bit of the current ECS operation row address is equal to 5, the ECS module 105 and the threshold module 106 output a valid storage Flag signal (Bigger _flag) and the current ECS operation row address; if the current ECS operation Row Address signal (Row Address) is changed from 5 to 6, the ECS module 105 and the threshold module 106 output the same ECS operation Row Address and valid storage Flag signal (Bigger _Flag) as when the second threshold is 5. By analogy, as long as the current ECS operation Row Address signal (Row Address) error bit is greater than or equal to 5, the ECS module 105 and the threshold module 106 will output the same Row Address and valid storage Flag signal (Bigger _flag) until a line is swapped. Thus, the weak address storage module 102 only needs to hold once for the same row address.

In some embodiments, as shown in fig. 8, the weak Address storage module 102 is further configured to receive a current ECS operation Row Address signal (Row Address) and a corresponding storage Flag signal (Bigger _flag), and when the storage Flag signal (Bigger _flag) is valid, store the current ECS operation Row Address signal (Row Address) as a weak Address signal (Out Address);

Wherein the storage Flag signal (Bigger _flag) indicates whether an error bit of a storage Row corresponding to the current ECS operation Row Address signal (Row Address) is greater than a second threshold.

Specifically, if the error bit of the memory Row corresponding to the current ECS operation Row Address signal (Row Address) is smaller than the second threshold, the second count value (EpRC) is filtered out by the memory, and the storage Flag signal (Bigger _flag) is invalid; if the error bit of the memory line corresponding to the current ECS operation Row Address signal (Row Address) is greater than or equal to the second threshold, the storage Flag signal (Bigger _flag) is valid, which indicates that the current ECS operation Row Address signal (Row Address) is a weak Address signal (Out Address), and the current ECS operation Row Address signal (Row Address) needs to be stored in the weak Address storage module 102.

Illustratively, for the storage Flag signal (Bigger _flag), inactive means that the level state is low (0), and active means that the level state is high (1).

In some embodiments, as shown in FIG. 8, the threshold module 106 is further configured to receive a threshold setting signal (TM/Fuse Thresholding Setting), and the threshold module 106 sets a second threshold according to the threshold setting signal (TM/Fuse Thresholding Setting).

Taking the second threshold value of 5 as an example, if the error bit of the current ECS operation Row Address signal (Row Address) is less than 5, it is indicated that the current ECS operation Row Address signal (Row Address) is not a weak Address signal (Out Address), the memory automatically masks the current ECS operation Row Address signal (Row Address) by using the threshold module 106, and the storage Flag signal (Bigger _flag) is invalid and the current ECS operation Row Address signal (Row Address) is not stored; if the error bit of the current ECS operation Row Address signal (Row Address) is greater than or equal to 5, it is indicated that the current ECS operation Row Address signal (Row Address) is a weak Address signal (Out Address), and the memory stores the current ECS operation Row Address signal (Row Address) as the weak Address signal (Out Address).

It should be further noted that the second threshold may be a determined value or a range of values, depending on the actual application scenario.

The embodiment of the disclosure provides a refreshing circuit, a refreshing method and a memory, which detect weak memory rows in a DRAM through ECS operation, store the detected weak memory row address signals by using a weak address memory module, and then improve the refreshing frequency of the weak memory row address signals based on a switching mark signal, so that the occurrence of single bit failure phenomenon can be greatly reduced, and the data integrity of the DRAM is further improved.

In another embodiment of the present disclosure, referring to fig. 9, a schematic flow chart of a refresh method provided by an embodiment of the present disclosure is shown. As shown in fig. 9, the method includes:

S401: the first count value is incremented before each refresh operation is performed on the memory.

S402: and when the first count value is smaller than the first threshold value, carrying out refreshing operation on the next memory row according to the refreshing sequence in the automatic refreshing mode.

S403: performing refresh operation on the weak memory line when the first count value is greater than or equal to a first threshold value; wherein, the weak memory row refers to a memory row in which the error bit is greater than the second threshold in the ECS mode.

It should be noted that, the refresh method provided by the embodiments of the present disclosure is applied to the refresh circuit provided by the foregoing embodiments, and for details not disclosed in the embodiments of the present disclosure, please refer to the description of the foregoing embodiments for understanding.

In some embodiments, when the first count value reaches a third threshold value, the first count value is reset; wherein the third threshold is greater than the first threshold.

When the first count value reaches the third threshold value, it indicates that the refresh address generator has performed a round of refresh operation on all the memory rows corresponding to the normal row address and the weak addresses, and at this time, the counter in the refresh address generator generates a reset signal to instruct the refresh address generator to start the next round of operation.

In some embodiments, the memory sequentially refreshes the memory rows corresponding to the plurality of weak address signals during the period when the first count value is at the first threshold and the third threshold.

When the first count value is smaller than the first threshold value, the switching flag signal generated by the refresh address generator is at the first level, and the memory performs refresh operation on all the row address signals; when the first count value is equal to the first threshold value, the refresh address generator generates a switching flag signal at a second level, which indicates that the memory is to start refresh operation on the plurality of weak address signals; when the first count value reaches a third threshold value from the first threshold value, the memory is completely refreshed by the weak address signals. In this way, the refresh frequency for the weak address signals is increased in a normal refresh operation.

According to the refreshing method provided by the embodiment of the disclosure, the weak memory rows in the DRAM are detected through ECS operation, the detected weak memory row addresses are stored by the weak address storage module, and then the refreshing frequency of the weak memory row address signals is improved based on the switching mark signals, so that the occurrence of single-bit failure phenomenon can be greatly reduced, and the data integrity of the DRAM is further improved.

In another embodiment of the present disclosure, reference is made to fig. 10, which shows a schematic diagram of the composition of a memory 50 provided by an embodiment of the present disclosure. As shown in fig. 10, the memory 50 may include the refresh circuit 10 of any of the previous embodiments.

In some embodiments, the memory 50 may comprise DRAM.

It should be noted that, the embodiment of the disclosure improves the refresh frequency of the weak memory cell in the DDR5, and outputs the row address signal and the switching flag signal through the refresh address generator, and the refresh address generator outputs the highest one-bit address as the switching flag signal of the address; meanwhile, outputting a weak address signal through a weak address storage module; when all the row address signals generated by the refresh address generator are output by the selection module and sent to the refresh module for refreshing, the whole refresh of the weak address signals is carried out, so that the refresh frequency of the weak memory cells can be improved by switching the level state of the mark signals, and the data integrity of the memory is ensured.

In the embodiment of the present disclosure, the DRAM may not only conform to the memory specifications of DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also conform to the memory specifications of LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., and is not limited herein.

In the embodiment of the disclosure, since the memory 50 includes the refresh circuit 10 described in the foregoing embodiment, the refresh frequency of the weak storage row address signal in the memory can be increased, so as to improve the performance of the memory.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A refresh circuit for use with a memory, the refresh circuit comprising:

A weak address storage module configured to store and output a weak address signal; wherein the weak address signal indicates a memory row having an error bit greater than a second threshold in an error checking and clearing (ECS) mode;

And the refreshing module is configured to receive a refreshing command signal and the address signal to be refreshed, and execute a refreshing operation on the memory row indicated by the address signal to be refreshed based on the refreshing command signal.

2. The refresh circuit of claim 1, wherein the refresh circuit comprises a refresh circuit,

3. The refresh circuit of claim 2, wherein the refresh circuit comprises a refresh circuit,

The refreshing module is further configured to generate and output a counting clock signal; wherein a count pulse is generated on the count clock signal before each refresh operation is performed;

4. The refresh circuit of claim 3, wherein the weak address memory module stores a plurality of the weak address signals;

The refresh address generator is further configured to output the count clock signal as a weak address clock signal when the switching flag signal is at a second level; when the switching flag signal is at a first level, keeping the level state of the weak address clock signal unchanged;

5. The refresh circuit of claim 4, wherein the refresh address generator is further configured to reset the first count value when the first count value reaches a third threshold;

wherein the third threshold is greater than the first threshold.

6. The refresh circuit of claim 5, wherein the first count value comprises an M-bit sub-signal and an mth-bit sub-signal is a highest-bit sub-signal; the row address signal includes an N-bit sub-signal;

7. The refresh circuit of claim 6, wherein the refresh address generator comprises an asynchronous binary counter, a first and gate, and a second and gate, wherein:

8. The refresh circuit of claim 4, wherein the refresh circuit comprises a refresh circuit,

The weak address storage module is further configured to receive a current ECS operation row address signal and a corresponding storage flag signal, and store the current ECS operation row address signal as the weak address signal when the storage flag signal is valid;

9. The refresh circuit of claim 8, wherein the weak address storage module comprises a first-in-first-out register, a latch, an address comparator, and a logic unit, wherein:

the latch is configured to latch the weak address signal stored last time;

10. The refresh circuit of claim 9, wherein the first-in-first-out register is further configured to receive the weak address clock signal, the weak address signal being sequentially output based on the weak address clock signal.

11. The refresh circuit of claim 9, wherein the logic unit comprises a third and gate and a pulse generator, wherein:

12. The refresh circuit of claim 11, wherein the pulse generator comprises a first not gate, a delay unit, and a fourth and gate, wherein:

13. The refresh circuit of claim 8, further comprising an ECS module and a threshold module, wherein:

14. The refresh circuit of claim 13, wherein the threshold module is further configured to receive a threshold setting signal, the threshold module setting the second threshold in accordance with the threshold setting signal.

15. A refresh method for a memory, the method comprising:

When the first count value is smaller than a first threshold value, refreshing the next memory row according to a refreshing sequence in an automatic refreshing mode;

16. The method of claim 15, wherein the method further comprises:

When the first count value reaches a third threshold value, resetting the first count value;

wherein the third threshold is greater than the first threshold.

17. The method of claim 16, wherein the memory sequentially refreshes memory rows corresponding to a plurality of weak address signals during the period when the first count value is at the first threshold and the third threshold.

18. A memory comprising a refresh circuit as claimed in any one of claims 1 to 14.