CN118353393A - An operational amplifier circuit with common-mode feedback - Google Patents

Abstract

The invention discloses an operational amplifier circuit with common mode feedback, and the fields of microelectronics and solid state electronics. The operational amplifier circuit is a two-stage operational amplifier and mainly comprises a biasing circuit, a first-stage operational amplifier, a second-stage operational amplifier, a switched capacitor common-mode feedback, a feedback secondary circuit, a proper common-mode feedback node and the like. By combining the switch capacitor common mode feedback and the source follower structure, the loop gain is 94.45dB, the operational amplifier gain is 86.84dB, the unit gain bandwidth is 70.5MHz, the common mode gain 148.41dB, the phase margin of the loop and the operational amplifier is larger than 60 degrees, and the stability requirement is met. Compared with the traditional structure, the invention realizes high loop gain, gao Yun amplification gain, larger operational amplifier bandwidth and higher common mode rejection ratio. Compared with the structure in recent years, the invention has obvious bandwidth advantage and can be applied in a wider range.

Description

An operational amplifier circuit with common-mode feedback

Technical Field

The invention relates to the fields of microelectronics and solid-state electronics, and is applied to a Sigma-delta analog-to-digital converter to design an operational amplifier circuit with novel common-mode feedback for a switched capacitor integrator.

Background technique

An analog-to-digital converter is a circuit system that converts analog signals into digital signals. According to the sampling frequency, analog-to-digital converters can be divided into Nyquist analog-to-digital converters and oversampling analog-to-digital converters. A Nyquist analog-to-digital converter is an analog-to-digital converter whose sampling frequency is exactly the Nyquist frequency. However, the accuracy that a Nyquist analog-to-digital converter can achieve under the same process is limited. In order to achieve higher-precision analog-to-digital conversion, oversampling analog-to-digital converters have emerged. Sigma Delta ADC is the most widely used oversampling ADC. Sigma Delta ADC first uses oversampling technology to sample the analog input signal at a very high sampling frequency, reducing the quantization noise energy within the signal bandwidth, and then modulates the quantization noise energy within the signal bandwidth to a high-frequency range outside the signal bandwidth through noise shaping technology, further reducing the quantization noise within the signal bandwidth, which can be filtered out by a post-stage digital filter.

The key unit integrator of discrete Sigma Delta ADC is susceptible to non-ideal factors such as nonlinearity of switches and limited performance of op amps, making it difficult to achieve a truly ideal design, thus affecting the dynamic performance of the overall circuit. The fully differential operational amplifier is one of the most critical modules in the discrete time Sigma-delta modulator and is the core module of each level of integrator. The non-ideal characteristics of the op amp in the integrator, such as limited gain, limited gain-bandwidth product, and slew rate, will limit the performance of the integrator and then affect the realization of the noise transfer function. Therefore, the design of the operational amplifier is more important. The two-stage differential operational amplifier is a typical structure of an operational amplifier due to its high gain, but because it consists of two stages, it is a challenging difficulty to perform effective common-mode feedback stabilization.

In the prior art, a single switched capacitor common-mode feedback is usually used in discrete integrator operational amplifiers. Although this structure does not limit the output swing of the operational amplifier, it also has certain defects, such as slow common-mode voltage settling time, large common-mode stable voltage fluctuation, low loop gain, and the use of more MOS switches introduces noise through clock feedthrough and charge, limiting the speed and accuracy of the fully differential operational amplifier, common-mode rejection ratio, etc.

Therefore, there is an urgent need for a high-performance fully differential operational amplifier with high loop gain, a fast and stable common-mode feedback circuit, and a high common-mode rejection ratio.

Summary of the invention

The purpose of the present invention is to provide a common-mode feedback circuit, a common-mode feedback method and a high-performance fully differential operational amplifier, which are applied in a high-performance Sigma-Delta discrete integrator. The present invention improves the shortcomings of the operational amplifier in the prior art, such as poor speed and accuracy, large common-mode interference, slow common-mode voltage establishment and low loop gain in the common-mode feedback structure of the switched capacitor.

In one aspect, the present invention provides a common-mode feedback circuit, comprising a switched capacitor common-mode feedback circuit and a feedback secondary circuit, wherein:

The switched capacitor common-mode feedback circuit is composed of three switches S11, S12, and S13 controlled by two non-overlapping clocks CLK1, and three switches S21, S22, and S23 controlled by CLK2, as well as capacitors C11, C12, C21, and C22; the capacitances of C11 and C12 are the same, the capacitances of C21 and C22 are the same, and the capacitance of capacitor C21 is five times that of C11; the common-mode voltage V _cm is connected to one end of S21, S22, and S23 respectively, the other end of S21 is connected to one end of S11 and one end of C21, the other end of S11 is connected to the differential output V _op and one end of C11, the other end of S22 is connected to one end of S12, the other end of C21, and one end of C22, the other end of S12 is connected to the other end of C11, the feedback signal V _cmfb , and one end of C12; the other end of S23 is connected to the other end of C22 and one end of S13, and the other end of S13 is connected to the other end of C12 and the differential output V _on ;

The feedback secondary circuit consists of a source follower M8 and two common sources M9 and M10; the gate of the source follower M8 is connected to the V _cmfb feedback signal, the source is the output stage, and is connected to the source ends of the two common sources M9 and M10; the gates of the common sources M9 and M10 are V _cm signals, and the drains are connected to the appropriate nodes of the main op amp as outputs; after comparing the V _cm signal with the output of the source follower M8, if the voltage difference between the two fluctuates, the magnitude of the extracted current also fluctuates, and under the negative feedback mechanism, the common-mode output level is stabilized.

On the other hand, the common-mode feedback method refers to different ways of connecting the common-mode feedback circuit to the high-gain operational amplifier; the error signal generated by the comparison of the feedback secondary circuit can be fed back to different nodes of the main operational amplifier. The connected nodes are different, and the gain from the feedback node of the common-mode feedback to the final output is also different, that is, the loop gain of the common-mode feedback is also different. The feedback node of the error signal of the present invention is between the first-stage common-source MOS tubes M13 and M14 and the common-gate MOS tubes M15 and M16 of the operational amplifier. In addition, the load MOS tube M11 of the source follower is a current mirror, and its gate is connected to the gates of the first-stage load tubes M17 and M18 of the differential operational amplifier. The fluctuation of the common-mode signal can also be well regulated through this current replication path.

Finally, the present invention proposes an operational amplifier circuit with common-mode feedback, including a bias current mirror, a first-stage operational amplifier and a second-stage operational amplifier; the bias current mirror part includes MOS tubes M0, M1 and M2, the PMOS tube M0 is diode-connected, that is, the gate and drain are short-circuited, the source of M0 is connected to VDD, the drain is connected to the current source PIB, the gate is connected to the gate of the PMOS tube M1, the source of M1 is connected to VDD, and at the same time, M1 and the NMOS tube M2 are in the same branch, and the currents flowing through the two are equal; the drain of M1 is connected to the drain of M2, the source of M2 is connected to the GND signal, M2 is also diode-connected, and its gate and drain are connected to the gates of NMOS tubes M3, M4, M5, M6 and M7, and the current of the current source PIB is proportionally copied to the M1 branch, M3 branch, M4 branch, M5 branch, M6 branch and M7 branch through the current mirror; the source of M3 is connected to the GND signal;

The tail current source of the first-stage operational amplifier is MOS tube M6, the source is connected to the GND signal, and the drain is connected to the source of differential input tubes M13 and M14; the gates of differential input tubes M13 and M14 are connected to inputs INp and INn respectively, and M15, M16 and differential input tubes M13 and M14 form a common source and common gate structure, the source of M15 is connected to the drain of M13, the source of M16 is connected to the drain of M14, and the gate of M15 is connected to the drain of M5 as a bias, and the bias branch has a resistor R0, and the two ends of R0 are connected to VDD and the gates of the common gate tubes M15 and M16 respectively; the common gate The drain of tube M15 is connected to the drain of load PMOS tube M17, the drain of M16 is connected to the drain of load PMOS tube M18, the sources of M17 and M18 are connected to VDD signal, the gate of M17, the gate of M18, the gate of load MOS tube M11, the drain of load MOS tube M11, the gate of load MOS tube M12, the drain of load MOS tube M12, and the drain of M8 are connected in common; M11 and M12 are connected in parallel and are both diode-connected, M12 and M11 form a current mirror with M17 and M18; the sources of M11 and M12 are connected to VDD;

The output stage of the second stage op amp is a common source. The sources of the common source PMOS tubes M19 and M20 are connected to the VDD signal. The gate of M19 is connected to the drain of M15. The gate of M20 is connected to the drain of M16. The drain of M19 is connected to the drain of the load tube M4. The drain of M20 is connected to the drain of the load tube M7. The sources of M4 and M7 are grounded. The drain of M19 is connected to the gate of M19 through the capacitor C3 and the resistor R1 in sequence; the drain of M20 is connected to the gate of M20 in sequence after being connected to the capacitor C4 and the resistor R2; the output signal nodes V _op and V _on correspond to the drains of M19 and M20 respectively;

The source of M8 is connected to the drain of M3, the drain of M9 is connected to the source of M15, and the drain of M10 is connected to the source of M16.

The present invention introduces Miller compensation, connects the drains of M19 and M20 with the drains of M15 and M16, bridges compensation capacitors C3 and C4, and adjusts resistors R1 and R2 at the zero point position, so that the frequency response of the second-stage operational amplifier is more stable; it has obvious advantages over the prior art in terms of loop gain, common-mode voltage establishment time, and common-mode rejection ratio, and achieves a good balance between the bandwidth and gain of the operational amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a circuit diagram of a typical folded cascode.

Figure 2 shows a typical switched capacitor common-mode feedback circuit.

FIG3 shows an operational amplifier circuit and a common-mode feedback circuit, a feedback secondary circuit, and feedback nodes X1 , X2 , Y1 , Y2 , Z1 , and Z2 of the present invention.

FIG4 is a simulation diagram of the feedback loop performance of the present invention, wherein the solid line is a gain curve and the dotted line is a phase curve.

FIG5 is a performance simulation diagram of the operational amplifier of the present invention, wherein the solid line is a gain curve and the dotted line is a phase curve.

Detailed ways

The invention is characterized in that the loop gain of the common mode feedback circuit is high, the stabilization time is fast, and the fully differential operational amplifier has high gain, high common mode rejection ratio (CMRR), and high bandwidth. The specific working principle of the circuit is as follows:

The fully differential operational amplifier of the present invention is shown in FIG1 . The leftmost M0 and M1 form a basic current mirror structure. The reference current flowing through the branch where M0 is located will be copied to the branch where M1 is located according to the aspect ratio. M1 and M2 are in the same branch, and the currents of the two are the same. M2 and MOS tubes such as M3-M7 are in a current mirror structure, and the current of this branch will be copied to each branch of M3-M7 in proportion.

The fully differential operational amplifier applied to the integrator in the Sigma-Delta modulator requires high gain and high bandwidth. In order to achieve high gain, the present invention selects a differential two-stage structure. In the first stage, M6 is a tail current source MOS tube, and a structure similar to a sleeve-type common source and common gate is adopted. Unlike the traditional sleeve-type common source and common gate structure, the load MOS tube of the first stage of the operational amplifier is only a single common source M17, M18. Although this reduces the load resistance of the first stage of the operational amplifier, it increases the common mode input range. Since the integrator of the Sigma-Delta modulator may have to process feedback signals containing many high-frequency components, the output swing of the integrator is generally large, and the swing requirements of the operational amplifier are also very large. At the same time, in the multi-stage modulator, the output of the front-stage integrator will be connected to the input of the rear-stage integrator, so the common mode input range is also required to be large.

M13 and M15, M14 and M16 form a differential common source and common gate structure. M13 and M14 are differential input pairs, and M15 and M16 are common gate tubes. The first-stage gain of the op amp is:

A _v1 = g _m13 ·( r _o17 // g _m15 r _o15 r _o13 )

Here, g _m13 and g _m15 are the transconductances of M13 and M15, and r _o17 , r _o15 and r _o13 are the output impedances of M17, M15 and M13 respectively.

The second stage of the op amp is a common source M19 (M20), and the load is only a single NMOS tube M4 (M7), which increases the output swing of the integrator. The gain of the second stage of the op amp is:

A _v2 = g _m19 ·(r _o19 //r _o4 )

The total gain is therefore:

A _v =A _v1 ·A _v2 =g _m19 ·g _m13 ·(r _o17 //g _m15 r _o15 r _o13 )·(r _o19 //r _o4 )

The two-stage operational amplifier of the present invention adopts Miller compensation, separates the primary and secondary poles, introduces Miller capacitor C3 (C4) and zero adjustment resistor R1 (R2), and improves the phase margin. The main pole position after compensation is:

Secondary pole position:

After adding the zero adjustment resistor, the zero point position is:

The value of _R1 is greater than The zero point is located in the left half plane, which can improve the phase margin and enhance stability.

As shown on the right side of FIG. 1 below, it is a schematic diagram of the switch capacitor common-mode feedback structure used in the fully differential operational amplifier of the present invention, V _op and V _on are the differential output voltages of the fully differential operational amplifier, V _cmfb is the feedback bias voltage of the common-mode feedback, and V _cm is the ideal common-mode voltage. The switches S1 and S2 are controlled by clocks CLK1 and CLK2, respectively. CLK1 and CLK2 are a set of two-phase non-overlapping clocks. The capacitance of the capacitor C1 is one-fifth of the capacitance of C2.

When in the CLK2 clock phase, switch S2 is closed and switch S1 is open. According to the charge distribution principle, the total charge stored on all capacitors is:

_Q1 [n-1]= _2C2 ·( _VcmVcm )+( _Vop [n-1 _{] Vcmfb} [n-1])· _C1 +( _Von [n-1] _Vcmfb [n-1])· _C1

=(V _op [n-1]+V _on [n-1]2V _cmfb [n-1])·C ₁

In the CLK1 clock phase, switch S1 is closed, switch S2 is open, capacitors C1 and C2 are connected in parallel, and the total charge stored on all capacitors is:

_Q2 [n]＝( _Vop [n]+ _Von [n] _2Vcmfb [n])·( _C1 + _C2 )

According to the charge conservation principle,

Q ₁ = (V _op [n-1] + V _on [n-1] 2 V _cmfb [n-1]) · C ₁

=Q ₂ =(V _op [n]+V _on [n]2V _cmfb [n])·(C ₁ +C ₂ )

After sorting, we can get:

Where, V _o,com [n] is the common-mode voltage of the op amp output, From the first cycle to the nth cycle, we can get:

From the above formula, we know that when n approaches infinity,

V _cmfb [∞]＝V _o,com [∞]

The settling speed of V _cmfb is About, when The smaller it is, the faster the common-mode feedback output voltage V _cmfb stabilizes. The speed at which V _cmfb settles is also related to the GBW of the common-mode loop.

The feedback secondary circuit is the branch where M3 is located. V _cmfb is the feedback signal, which is connected to the gate of the M8 source follower. When the output common mode V _o,com increases, V _cmfb will increase, and the source output of M8 will also increase. The source output is connected to the source of M9 and M10, and the difference with V _cm decreases, and the current flowing through M9 and M10 will decrease. Since the current flowing into M6 of the first-stage op amp is fixed, the current flowing through M13 and M14 remains unchanged, and the current flowing out of the X1 and X2 nodes decreases, then the sum of the current flowing from the Y1 and Y2 nodes to the X1 and X2 nodes will decrease. On the other hand, the current flowing through M3 comes from the current mirror copy and remains unchanged in this fluctuation. The reduction of the current flowing into M9 and M10 will cause the current flowing through M8 and M11 to increase. After being proportionally copied by the load current mirror of the parallel MOS tubes M11 and M12, the branch current flowing through M17 and M18 increases.

At this time, the current flowing into the Y1 and Y2 nodes increases, and the current flowing out of the Y1 and Y2 nodes decreases, so the voltage of the Y1 and Y2 nodes will increase, and the second-stage op amp is a common source, the voltage will be reversely amplified, the V _op and V _on voltages will decrease, and the output common mode V _o,com will decrease. Such negative feedback regulation makes the common mode well stabilized.

The drains of M9 and M10 are connected to the feedback nodes X1 and X2, which are selected between the drain sources of M13 and M15, and M14 and M16. Different feedback nodes will lead to different loop gains of the common-mode feedback circuit. The loop gain is:

A _{v, loop} = A _{v, cmfb} · A _{v, X-out}

Here A _v,X-out is the gain from the X node to the output V _op :

A _v,X-out = g _m15 ·( r _o15 // r _o17 ) · g _m19 ·( r _o19 // r _o4 )

For feedback nodes Y1 and Y2, A _v,Y-out is:

A _{v, Y-out} = g _m19 · ( r _o19 // r _o4 )

For feedback nodes Z1 and Z2, A _{v, Z-out} is:

The A _{v, cmfb} of the three common-mode feedback methods are the same, while A _{v, Y-out} is the smallest, A _{v, X-out} is close to A _{v, Z-out} , and the loop gain of the latter two is larger. However, when the feedback nodes connected to the main op amp are Z1 and Z2, the common-mode gain of the op amp will be affected at the expense of the phase margin. Therefore, it is more reasonable to select the feedback nodes X1 and X2 connected to the main op amp.

Different feedback methods will bring different loop gains and phase margins. Table 1 compares the performance of common-mode feedback loops and fully differential operational amplifiers based on different feedback nodes Y1 and Y2, Z1 and Z2. Among them, M9 and M10 are connected to the feedback nodes X1 and X2 of the main operational amplifier for the present invention, connected to the first-stage feedback nodes Y1 and Y2 for scheme 2, and connected to the first-stage feedback nodes Z1 and Z2 for scheme 3. In addition, Table 1 also lists the performance comparison of the traditional folded common source and common gate, the second-stage operational amplifier and their respective common-mode loops in the literature [R. Sahu, S. Kundu and A. Kumar, "A Novel Technique of Enhancing CMRR of Fully-Differential Instrumentation Amplifier Using High Gain CMFB Loop," 2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON), Kolkata, India, 2022, pp. 409-414].

It can be seen that the present invention has advantages in loop gain, common-mode voltage establishment time, and common-mode rejection ratio under the condition that the operational amplifier phase margin is greater than 60°, and achieves a good balance between the bandwidth and gain of the operational amplifier.

Table 1 is a performance comparison of the operational amplifiers of the present invention and other conventional solutions and similar designs in the literature.

this invention Folded Cascode Option II third solution literature Common mode voltage settling time (μs) 2.45 3.5 2.48 2.45 / Loop gain (dB) 94.45 73.24 85.96 94.89 94.02 Loop phase margin (deg) 66.27 83.93 65.31 66.6 62.69 Op amp gain (dB) 86.84 56.69 82.19 90.75 119.5 Unity gain bandwidth(MHz) 70.50 44.37 65.64 96.71 0.71 Op amp phase margin (deg) 62.27 85.73 58.88 46.27 70.11 Common mode rejection ratio (dB) 148.41 78.28 143.74 92.12 148.08

Claims (2)

1. A common-mode feedback circuit, comprising a switched capacitor common-mode feedback circuit and a feedback secondary circuit, wherein: The switched capacitor common-mode feedback circuit is composed of three switches S11, S12, and S13 controlled by two non-overlapping clocks CLK1, and three switches S21, S22, and S23 controlled by CLK2, as well as capacitors C11, C12, C21, and C22; the capacitances of C11 and C12 are the same, the capacitances of C21 and C22 are the same, and the capacitance of capacitor C21 is five times that of C11; the common-mode voltage V _cm is connected to one end of S21, S22, and S23 respectively, the other end of S21 is connected to one end of S11 and one end of C21, the other end of S11 is connected to the differential output V _op and one end of C11, the other end of S22 is connected to one end of S12, the other end of C21, and one end of C22, the other end of S12 is connected to the other end of C11, the feedback signal V _cmfb , and one end of C12; the other end of S23 is connected to the other end of C22 and one end of S13, and the other end of S13 is connected to the other end of C12 and the differential output V _on ; The feedback secondary circuit consists of a source follower M8 and two common sources M9 and M10; the gate of the source follower M8 is connected to the V _cmfb feedback signal, the source is the output stage, and is connected to the source ends of the two common sources M9 and M10; the gates of the common sources M9 and M10 are V _cm signals, and the drains are connected to the appropriate nodes of the main op amp as outputs; after comparing the V _cm signal with the output of the source follower M8, if the voltage difference between the two fluctuates, the magnitude of the extracted current also fluctuates, and under the negative feedback mechanism, the common-mode output level is stabilized. 2. An operational amplifier circuit with the common-mode feedback circuit of claim 1, comprising a bias current mirror, a first-stage operational amplifier and a second-stage operational amplifier; the bias current mirror part comprises MOS tubes M0, M1 and M2, the PMOS tube M0 is diode-connected, that is, the gate and drain are short-circuited, the source of M0 is connected to VDD, the drain is connected to the current source PIB, the gate is connected to the gate of the PMOS tube M1, the source of M1 is connected to VDD, and at the same time, M1 and the NMOS tube M2 are in the same branch, and the currents flowing through the two are equal; the drain of M1 is connected to the drain of M2, the source of M2 is connected to the GND signal, and M2 is also diode-connected, and its gate and drain are connected to the gates of NMOS tubes M3, M4, M5, M6 and M7, and the current of the current source PIB is proportionally copied to the M1 branch, M3 branch, M4 branch, M5 branch, M6 branch and M7 branch through the current mirror; the source of M3 is connected to the GND signal; The tail current source of the first-stage operational amplifier is MOS tube M6, the source is connected to the GND signal, and the drain is connected to the source of differential input tubes M13 and M14; the gates of differential input tubes M13 and M14 are connected to inputs INp and INn respectively, and M15, M16 and differential input tubes M13 and M14 form a common source and common gate structure, the source of M15 is connected to the drain of M13, the source of M16 is connected to the drain of M14, and the gate of M15 is connected to the drain of M5 as a bias, and the bias branch has a resistor R0, and the two ends of R0 are connected to VDD and the gates of the common gate tubes M15 and M16 respectively; the common gate The drain of tube M15 is connected to the drain of load PMOS tube M17, the drain of M16 is connected to the drain of load PMOS tube M18, the sources of M17 and M18 are connected to VDD signal, the gate of M17, the gate of M18, the gate of load MOS tube M11, the drain of load MOS tube M11, the gate of load MOS tube M12, the drain of load MOS tube M12, and the drain of M8 are connected in common; M11 and M12 are connected in parallel and are both diode-connected, M12 and M11 form a current mirror with M17 and M18; the sources of M11 and M12 are connected to VDD; The output stage of the second stage op amp is a common source. The sources of the common source PMOS tubes M19 and M20 are connected to the VDD signal, the gate of M19 is connected to the drain of M15, the gate of M20 is connected to the drain of M16, the drain of M19 is connected to the drain of the load tube M4, the drain of M20 is connected to the drain of the load tube M7, the sources of M4 and M7 are grounded, the drain of M19 is connected to the gate of M19 through the capacitor C3 and the resistor R1 in turn; the drain of M20 is connected to the gate of M20 in turn after being connected to the capacitor C4 and the resistor R2; The output signal nodes V _op and V _on correspond to the drains of M19 and M20 respectively; The source of M8 is connected to the drain of M3, the drain of M9 is connected to the source of M15, and the drain of M10 is connected to the source of M16.