CN118367926A

CN118367926A - Charge pump circuit for phase-locked loop, control method thereof and phase-locked loop circuit

Info

Publication number: CN118367926A
Application number: CN202310075042.0A
Authority: CN
Inventors: 乔劲轩; 翟羽健
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2023-01-18
Filing date: 2023-01-18
Publication date: 2024-07-19

Abstract

The invention discloses a charge pump circuit for a phase-locked loop, a control method and a phase-locked loop circuit, wherein the charge pump circuit comprises the following components: a charge pump and a control unit; the charge pump is a current steering charge pump and has a switchable topological structure; the charge pump comprises a charging current source, a discharging current source, an upper switch group, a lower switch group and a feedback unit; the control unit outputs a control signal, when the phase-locked loop is unlocked, the charge pump is controlled to work by adopting a first topological structure, and the feedback unit is used for feeding back the voltage of the second connection node to the first connection node so as to lock the voltage of the second connection node to a target voltage; after the phase-locked loop is locked, the charge pump is controlled to work by adopting a second topological structure, and the feedback unit is used for collecting the voltages of the first connecting node and the second connecting node and controlling the value of the discharging current source or the charging current source according to the collected voltages so as to correct the voltage difference between the first connecting node and the second connecting node. The scheme of the invention can avoid the jitter generated in the output of the phase-locked loop.

Description

Charge pump circuit for phase-locked loop, control method thereof and phase-locked loop circuit

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to a charge pump circuit for a phase-locked loop, a control method thereof, and a phase-locked loop circuit.

Background

As pll circuits are increasingly used in chips, how to design pll circuits with low jitter characteristics is also becoming an important issue for intense research.

The charge pump is used as an important module in the phase-locked loop circuit, receives the output signal of the phase frequency detector, generates corresponding current, and outputs the corresponding current to the loop filter so as to generate control voltage for controlling the voltage-controlled oscillator, so that the desired output frequency of the phase-locked loop is obtained. However, in order to avoid the phase detection dead zone, the phase frequency detector usually adds a delay circuit artificially, so that there is a time for the charge current and the discharge current output by the charge pump to be conducted simultaneously, during which any mismatch of the charge current and the discharge current causes a ripple on the control voltage of the vco, thereby causing jitter on the output of the pll. In addition, in a fractional-n pll, nonlinearity caused by mismatch between charge pump charging current and discharge current may cause quantization noise of high frequency to be folded to low frequency, thereby deteriorating phase noise of the pll circuit. It is therefore desirable to improve the matching of the output currents of the charge pumps.

Disclosure of Invention

The embodiment of the invention provides a charge pump circuit, a control method and a phase-locked loop circuit for a phase-locked loop, which are used for improving the matching degree of output current of the charge pump and further avoiding jitter of output of the phase-locked loop.

In one aspect, an embodiment of the present invention provides a charge pump circuit for a phase locked loop, the charge pump circuit comprising: a charge pump and a control unit; the charge pump is a current steering charge pump and has a switchable topology;

The charge pump comprises a charging current source, a discharging current source, an upper switch group, a lower switch group and a feedback unit; the upper switch group is connected with the charging current source, the lower switch group is connected with the discharging current source, and the upper switch group is connected with the lower switch group and is provided with a first connecting node and a second connecting node;

The control unit is used for outputting a control signal, and the control signal is used for controlling the charge pump to work by adopting a first topological structure when the phase-locked loop is unlocked; after the phase-locked loop is locked, controlling the charge pump to work by adopting a second topological structure;

In the first topology structure, the feedback unit is configured to feed back the voltage of the second connection node to the first connection node, so that the voltage of the second connection node is locked to a target voltage; in the second topology structure, the feedback unit is configured to collect voltages of the first connection node and the second connection node, and control a value of the discharging current source or the charging current source according to the collected voltages, so as to correct a voltage difference between the first connection node and the second connection node.

Optionally, the discharge current source includes a first current source and a second current source connected in parallel, and the second current source is an adjustable current source.

Optionally, the charging current source includes a third current source and a fourth current source connected in parallel, and the fourth current source is an adjustable current source.

Optionally, in the second topology, the feedback unit is configured to control the value of the adjustable current source according to the voltages of the first connection node and the second connection node.

Optionally, the feedback unit is an error amplifier.

Optionally, in the first topology, a positive input end of the error amplifier is connected to the second connection node, and a negative input end and an output end of the error amplifier are connected to the first connection node.

Optionally, in the second topology structure, a positive input end of the error amplifier is connected with the second connection node, an output end of the error amplifier is connected with the adjustable current source, and a negative input end of the error amplifier is connected with the first connection node.

Optionally, the second connection node is connected with a loop filter; the loop filter comprises at least a resistor and a capacitor connected in series between the second connection node and ground;

In the second topological structure, the positive input end of the error amplifier is connected with the second connecting node, the output end of the error amplifier is connected with the adjustable current source, and the negative input end of the error amplifier is connected with the connecting point of the resistor and the capacitor in the loop filter.

Optionally, the phase-locked loop includes a phase frequency detector connected to the charge pump;

And the control unit is used for outputting the control signal according to the input signal of the phase frequency detector.

Optionally, the control unit includes:

a first switch disposed between the first current source and the second current source;

A second switch arranged between the second current source and the output end of the error amplifier;

The third switch is arranged between the negative input end and the output end of the error amplifier;

a fourth switch arranged between the output end of the error amplifier and the first connection node;

a fifth switch disposed between the output terminal and the positive input terminal of the error amplifier;

A sixth switch arranged between a negative input end of the error amplifier and a connection point of the resistor and the capacitor in the loop filter;

and a seventh switch arranged between the positive input end of the error amplifier and the second connection node or between the positive input end of the error amplifier and the connection point of the resistor and the capacitor in the loop filter.

On the other hand, the embodiment of the invention also provides a control method for a charge pump of a phase-locked loop, wherein the charge pump comprises a charging current source, a discharging current source, an upper switch group, a lower switch group and a feedback unit; the upper switch group is connected with the charging current source, the lower switch group is connected with the discharging current, and the upper switch group is connected with the lower switch group and is provided with a first connecting node and a second connecting node; the method comprises the following steps:

When the phase-locked loop is unlocked, the charge pump is controlled to work in a first topological structure, and the voltage of the second connection node is fed back to the first connection node through the feedback unit so as to lock the voltage of the second connection node to a target voltage;

after the phase-locked loop is locked, the charge pump is controlled to work by adopting a second topological structure, the voltage of the first connecting node and the voltage of the second connecting node are collected through the feedback unit, and the value of the discharging current source is controlled according to the collected voltage so as to correct the voltage difference between the first connecting node and the second connecting node.

Optionally, the phase-locked loop includes a phase frequency detector connected to the charge pump; the method further comprises the steps of: and determining whether the phase-locked loop is locked or not according to the input signal of the phase frequency detector.

In another aspect, an embodiment of the present invention further provides a phase-locked loop circuit, where the phase-locked loop circuit includes the aforementioned charge pump circuit for a phase-locked loop.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

the charge pump circuit for the phase-locked loop, the control method and the phase-locked loop circuit provided by the embodiment of the invention control the charge pump to work by adopting different topologies respectively before and after the phase-locked loop is locked by designing the circuit of the current steering charge pump into a variable topology, particularly, when the phase-locked loop is unlocked, the charge pump is controlled to work by adopting a first topology, and the voltage of the second connection node is fed back to the first connection node through the feedback unit so as to lock the voltage of the second connection node to a target voltage; after the phase-locked loop is locked, the charge pump is controlled to work by adopting a second topological structure, the voltage of the first connecting node and the voltage of the second connecting node are collected through the feedback unit, and the value of the discharging current source is controlled according to the collected voltage so as to correct the voltage difference between the first connecting node and the second connecting node. Therefore, the matching degree of the output current of the charge pump can be improved, and the phase-locked loop output is prevented from shaking. Moreover, through the transformation of the topological structure, the risk of unstable phase-locked loop caused by misjudgment of a feedback unit before the phase-locked loop is locked in a single topological structure is avoided, and meanwhile, the effect of inhibiting the mismatch of charge and discharge currents after the phase-locked loop is locked is realized.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional charge pump phase-locked loop;

Fig. 2 is a schematic circuit diagram of a conventional current steering charge pump;

fig. 3 is a schematic block diagram of a charge pump circuit for a phase locked loop provided by an embodiment of the present invention;

FIG. 4a is a schematic diagram of a first topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention;

FIG. 4b is a simplified schematic diagram of FIG. 4 a;

Fig. 5a is a schematic diagram of a second topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention;

FIG. 5b is a simplified schematic diagram of FIG. 5 a;

Fig. 6a is another schematic diagram of a first topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention;

FIG. 6b is a simplified schematic diagram of FIG. 6 a;

Fig. 7a is another schematic diagram of a second topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention;

FIG. 7b is a simplified schematic diagram of FIG. 7 a;

fig. 8 is a schematic diagram of a phase-locked loop circuit according to an embodiment of the present invention;

Fig. 9 is a flowchart of a control method of a charge pump for a phase locked loop according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The phase-locked loop (phase locked loop) is a negative feedback control system which uses the voltage generated by phase synchronization to tune the voltage-controlled oscillator to generate the target frequency, is a typical feedback control circuit, and uses the externally input reference signal to control the frequency and phase of the oscillation signal in the loop, so as to realize the automatic tracking of the output signal frequency to the input signal frequency.

The charge pump phase locked loop adds a charge pump structure between the phase detector and the loop filter, and an integrator is formed by driving a capacitor in the loop filter to improve the loop gain.

A conventional charge pump phase locked loop circuit is shown in fig. 1, and includes: a prescaler (/ M) 11, a Phase Frequency Detector (PFD) 12, a charge pump Circuit (CP) 13, a loop filter 14, a Voltage Controlled Oscillator (VCO) 15, a loop divider (/ N) 16, output dividers (/ K) 17 and (/ L) 18.

The functions of the modules are as follows:

Prescaler 11: a clock signal with fref from the outside of the phase-locked loop is received, and a reference clock signal with fref/M after frequency reduction suitable for the phase-locked loop application is output. Typically implemented as a digital counter, and the size of M is variable depending on the application requirements.

Phase frequency detector 12: receives the reference clock signal from the prescaler 11 and the feedback clock signal from the loop divider 16, compares the phase differences between the two signals, and outputs corresponding up and down signals. If the phase difference of the reference clock compared with the feedback clock is negative, namely the reference clock signal is behind the feedback clock signal, the down signal is high, and the up signal is low; if the phase difference of the reference clock compared with the feedback clock is positive, i.e. the reference clock signal leads the feedback clock signal, the up signal is high and the down signal is low; if the reference clock arrives at the same time as the feedback clock, the output up and down signals are both high and low for a period of time, which is typically determined by a delay circuit in the phase frequency detector circuit.

Charge pump circuit 13: receiving the up signal and the down signal from the phase frequency detector 12, if the up signal is high, the down signal is low, the charge pump circuit 13 outputs a charging current to the loop filter 14, so that the output voltage Vc of the loop filter 14 is increased, and the frequency of the voltage-controlled oscillator 15 is increased; if the up signal is low and the down signal is high, the charge pump circuit 13 draws a discharge current from the loop filter 14, and reduces the output voltage Vc of the loop filter 14, thereby reducing the frequency of the voltage-controlled oscillator 25; if the up signal and the down signal are at high level at the same time, the charge and discharge currents are simultaneously turned on, and if no mismatch exists between the charge and discharge currents, the output voltage Vc of the loop filter 14 is kept unchanged, and the output frequency of the voltage-controlled oscillator 15 is unchanged; if the up signal and the down signal are both low, and the charge and discharge currents are simultaneously turned off, the output voltage Vc of the loop filter 14 remains unchanged, and the output frequency of the voltage-controlled oscillator 15 remains unchanged.

Loop filter 14: the loop filter 14 shown in fig. 1 is composed of two capacitors C1, C2 and a resistor R, receives a current signal output from the charge pump circuit 15, and converts the current signal into a voltage signal Vc to output to the voltage-controlled oscillator 15, and the voltage-controlled oscillator 15 changes its output frequency according to the magnitude of Vc.

Voltage controlled oscillator 15: the output voltage Vc from the loop filter 14 is received, and a clock signal of a corresponding frequency fout is output according to the magnitude of Vc.

Loop divider 16: the clock signal from the output of the voltage controlled oscillator 15 is received and the down-converted feedback clock signal having a frequency fout/N is output. Typically implemented as a digital counter, and the size of N is variable depending on the application requirements.

Output dividers 17 and 18: the clock signal from the output of the voltage controlled oscillator 25 is received, the down-converted clock signals having frequencies fclk1=fout/K and fclk2=fout/L are output, and the clock signals are provided to a module other than the phase locked loop. Typically implemented as digital counters, and the size of K and L is variable depending on the application requirements.

Since the pll is a negative feedback system, after the pll is locked, fout/n=fref/M is found, fclk1=n×fref/(k×m), and fclk1=n×fref/(l×m). By selecting appropriate values of M, N, K, L, the desired output frequency clock signal can be obtained.

A charge pump (charge pump) receives the signal containing the phase information from the phase frequency detector output and generates a corresponding current signal. A current steering charge pump 20 as shown in fig. 2 is used in a charge pump circuit that is currently widely used in phase locked loops, and for ease of understanding, the phase frequency detector 12 and loop filter 14 are shown in fig. 2 in conjunction with the current steering charge pump 20. The current steering charge pump 20 receives the up and down signals from the phase frequency detector 12 and provides a charge and discharge current to the loop filter 14.

The working principle of the current steering charge pump is briefly described below in connection with fig. 2.

As shown in fig. 2, the current steering charge pump 20 includes a charge current source I _p and a discharge current source I _n, an upper switch group and a lower switch group, a unity gain follower U, a first inverter D1 providing an inverted input signal for the upper switch group, and a second inverter D2 providing an inverted input signal for the lower switch group. The upper switch group consists of a pair of PMOS tubes PM1 and PM2, and the lower switch group consists of a pair of NMOS tubes NM1 and NM 2.

In general, the charge current source I _p and the discharge current source I _n in the current steering charge pump 20 are copied from the same reference current source through a current mirror.

The current steering charge pump 20 receives the UP signal UP and the DOWN signal DOWN from the output of the phase frequency detector 12 and operates in three states, specifically as follows:

If the UP signal UP is high, the DOWN signal DOWN is low, PM2 and NM1 are on, PM1 and NM2 are off; correspondingly, the charging current source I _p - > P2- > forms a charging branch, and the current steering charge pump 20 outputs charging current to the loop filter 14, so that the output voltage Vc of the loop filter 14 is increased; due to the conduction of NM1, the voltage Vc is raised to the target voltage and locked by the action of the unit gain follower U;

If the UP signal UP is low, the DOWN signal DOWN is high, PM1 and NM2 are on, PM2 and NM1 are off; correspondingly, the loop filter- > N2- > discharge current source I _n forms a discharge branch, and the current steering charge pump 20 extracts discharge current from the loop filter 14, so that the output voltage Vc of the loop filter 14 is reduced; due to the conduction of P1, the voltage Vc is lowered to the target voltage and locked by the action of the unity gain follower U.

If the UP signal UP and the DOWN signal DOWN are at high level at the same time, PM2 and NM2 are on, PM1 and NM1 are off, and the charge-discharge current is on at the same time, at this time, if there is no mismatch between the charge-discharge currents, the output voltage Vc of the loop filter 14 remains unchanged and is locked at a target voltage, which is typically the voltage of the best matching point of the current mirror (typically VDD/2, VDD is the operating voltage of the current mirror and the charge pump).

If UP signal UP and DOWN signal DOWN are at low level at the same time, PM1 and NM1 are on, PM2 and NM2 are off, charge-discharge current goes through paths of PM1 and NM1 at the same time, no effect is exerted on the loop filter, and the loop filter voltage remains unchanged.

However, since the pll circuit may operate at different frequencies according to different requirements, the output voltage Vc of the loop filter 14 may be locked at a voltage deviating from the optimum matching point of the current mirror, and due to the delay circuit in the phase frequency detector 12, there is a time for the charge current and the discharge current output by the charge pump to be conducted simultaneously, which causes mismatch of the charge current and the discharge current output by the charge pump, thereby causing deterioration of the output characteristics of the pll.

Therefore, the embodiment of the invention provides a charge pump circuit, which adopts a current steering charge pump, designs the circuit into a variable topology structure, and sets a control unit to control which topology structure the charge pump adopts to work. Specifically, when the phase-locked loop is unlocked, the charge pump is controlled to work by adopting a first topological structure, and the voltage of the second connection node is fed back to the first connection node through the feedback unit so as to lock the voltage of the second connection node to a target voltage; after the phase-locked loop is locked, the charge pump is controlled to work by adopting a second topological structure, the voltage of the first connecting node and the voltage of the second connecting node are collected through the feedback unit, and the value of the discharging current source is controlled according to the collected voltage so as to correct the voltage difference between the first connecting node and the second connecting node.

Fig. 3 is a schematic block diagram of a charge pump circuit for a phase locked loop according to an embodiment of the present invention.

The charge pump circuit includes: a charge pump 301, and a control unit 302; the charge pump is a current steering charge pump and has a switchable topology;

The charge pump 301 includes a charge current source 31, a discharge current source 32, an upper switch group 311, a lower switch group 312, and a feedback unit 313; the upper switch group 311 is connected to the charging current source 31, the lower switch group 312 is connected to the discharging current source 32, and the upper switch group 311 is connected to the lower switch group 312 and has a first connection node P1 and a second connection node P2;

the control unit 302 is configured to output a control signal, where the control signal is configured to control the charge pump to operate in a first topology when the phase-locked loop is unlocked; after the phase-locked loop is locked, controlling the charge pump to work by adopting a second topological structure;

In the first topology, the feedback unit 313 is configured to feed back the voltage of the second connection node P2 to the first connection node P1, so that the voltage of the second connection node P2 is locked to a target voltage; in the second topology, the feedback unit 313 is configured to collect voltages of the first connection node and the second connection node P2, and control a value of the discharging current source or the charging current source according to the collected voltages, so as to correct a voltage difference between the first connection node and the second connection node.

In this embodiment, the charge pump 301 is connected to a phase frequency detector and a loop filter in a phase locked loop, respectively, and receives an UP signal UP and a DOWN signal DOWN from the phase frequency detector, and specifically, the UP signal UP controls the UP switch group 311, and the DOWN signal DOWN controls the DOWN switch group 312. The second connection node P2 of the charge pump 301 is connected to a loop filter to which the charge pump 301 outputs a charge current or from which a discharge current is drawn, in accordance with control of the UP signal UP and the DOWN signal DOWN. The method comprises the following steps:

If the UP signal UP is high and the DOWN signal DOWN is low, the charge pump 301 outputs a charging current to the loop filter, so that the output voltage Vc of the loop filter is raised;

if the UP signal UP is low and the DOWN signal DOWN is high, the charge pump 301 draws a discharge current from the loop filter, so that the output voltage Vc of the loop filter is reduced;

if the UP signal UP and the DOWN signal DOWN are at high level at the same time, the charge and discharge currents are simultaneously turned on, and the output voltage Vc of the loop filter is kept unchanged;

If UP signal UP and DOWN signal DOWN are simultaneously low, charge and discharge currents are simultaneously turned off, and output voltage Vc of the loop filter remains unchanged.

In a specific application, the feedback unit 313 may be implemented using an error amplifier.

The control unit 302 may be implemented by a set of switches to switch the topology of the charge pump 301. For example, in one non-limiting embodiment, the control unit 302 may include the following switches: the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the seventh switch S7.

In one non-limiting embodiment, the feedback unit 313 may control the discharge current source 32 in the second topology. Accordingly, the discharge current source 32 may include a first current source and a second current source connected in parallel, the second current source being an adjustable current source; the feedback unit 313 controls the value of the adjustable current source (i.e., the second current source) according to the voltages of the first and second connection nodes P1 and P2.

In another non-limiting embodiment, the feedback unit 313 may control the charging current source 31 in the second topology. Accordingly, the charging current source 31 may include a third current source and a fourth current source connected in parallel, and the fourth current source is an adjustable current source. The feedback unit 313 is configured to control a value of the adjustable current source (i.e., the fourth current source) according to voltages of the first connection node P1 and the second connection node P2.

The circuit configuration of the two control modes is similar, and the discharge current source 32 is controlled as an example.

Referring simultaneously to fig. 4a, 4b, 5a, 5b, wherein:

Fig. 4a is a schematic diagram of a first topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention, and fig. 4b is a simplified schematic diagram of fig. 4 a.

Fig. 5a is a schematic diagram of a second topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention, and fig. 5b is a simplified schematic diagram of fig. 5 a.

In this embodiment, the switches in the control unit 302 are set as follows:

The first switch S1 is disposed between the first current source I _n and the second current source I _n,t;

The second switch S2 is arranged between the second current source I _n,t and the output of the error amplifier EA;

The third switch S3 is arranged between the negative input and the output of the error amplifier EA;

the fourth switch S4 is arranged between the output of the error amplifier EA and said first connection node P1;

the fifth switch S5 is arranged between the output and the positive input of the error amplifier EA;

A sixth switch S6 is arranged between the negative input of the error amplifier EA and the junction P of the resistor R and the capacitor C1 in the loop filter 14;

A seventh switch S7 is arranged between the positive input of the error amplifier EA and said second connection node P2.

When the phase locked loop is unlocked, as shown in fig. 4a, S1, S3, S4 and S7 are closed, S2, S5 and S6 are open, and the circuit configuration can be simplified as shown in fig. 4 b.

As can be seen from fig. 4b, at this time, the charging current I _p and the discharging current are both from the duplication of the current mirror, the charging current I _p and the discharging current I _n+I_n,t, the circuit structure is identical to the conventional current steering charge pump structure in fig. 2, the working principle is the same, and the description of the working mode of the current steering charge pump in fig. 2 can be seen, which is not repeated here.

It should be noted that, the discharge current is not particularly required to be I _n and I _n,t, and only the sum of the two is required to be mirrored with the current mirror.

As shown in fig. 5a, after the phase-locked loop is locked, S1, S3, S4 and S7 are opened, S2, S5 and S6 are closed, and the circuit structure can be simplified as shown in fig. 5 b.

Referring to fig. 5b, after the pll locks, in most of the reference clock period, the charging current and the discharging current are applied to the first connection node P1 at the same time, at this time, any current mismatch between the charging current and the discharging current causes the voltage Vcc of the first connection node P1 to change, the error amplifier EA detects the voltage change and compares the voltage Vc1 of the node P, and generates a corresponding output voltage to adjust the current of the second current source I _n,t, so as to match the current charged by the charging current source I _p to the first connection node P1 and the current drawn by the second discharging current source I _n from the first connection node P1.

The charging current I _p comes from the copy of the current mirror, the discharging current is divided into two parts, one part comes from the copy I _n of the current mirror, and the other part is generated based on the detection result of the error discharger EA, namely I _n,t, so that the matching of the charging current and the discharging current is realized.

Referring also to fig. 6a, 6b, 7a, 7b, wherein:

Fig. 6a is another schematic diagram of a first topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention, and fig. 6b is a simplified schematic diagram of fig. 6 a.

Fig. 7a is another schematic diagram of a second topology of a charge pump circuit for a phase locked loop according to an embodiment of the present invention, and fig. 7b is a simplified schematic diagram of fig. 7 a.

In this embodiment, the switches in the control unit 302 are set as follows:

The first switch S1 is disposed between the first current source I _n and the second current source I _nt;

a seventh switch S7 is arranged between the positive input of the error amplifier EA and the junction P of the resistor R and the capacitor C1 in the loop filter 14.

When the phase locked loop is unlocked, as shown in fig. 6a, S1, S3, S4 and S7 are closed, S2, S5 and S6 are open, and the circuit configuration can be simplified as shown in fig. 6 b.

Referring to fig. 6b and 4b together, it can be seen that the circuit configuration shown in fig. 6b differs from that shown in fig. 4b in that in fig. 6b the positive input of the error amplifier EA is connected to node P. The charge pump circuit for the phase locked loop shown in fig. 6b is similar to the charge pump circuit shown in fig. 4b in operation, and will not be described again here.

As shown in fig. 7a, after the phase locked loop is locked, S1, S3, S4 and S7 are opened, S2, S5 and S6 are closed, and the circuit structure can be simplified as shown in fig. 7 b. The charge pump circuit for the phase locked loop shown in fig. 7b has the same structure as the charge pump circuit shown in fig. 5b, and the working principle thereof can be referred to the previous description of the working principle of the charge pump circuit shown in fig. 5b, and will not be repeated here.

Referring to fig. 7b, after the phase-locked loop is locked, the charging current and the discharging current are simultaneously applied to the first connection node P1 in most of the reference clock period, at this time, any current mismatch between the charging current and the discharging current causes the voltage Vcc of the first connection node P1 to change, the error amplifier EA detects the voltage change and compares the voltage Vc1 of the node P, and a corresponding output voltage is generated to adjust the current of the second current source I _n,t to match the current charged by the charging current source I _p to the first connection node P1 and the current drawn by the second discharging current source I _n from the first connection node P1.

Correspondingly, the embodiment of the invention also provides a phase-locked loop circuit, as shown in fig. 8, which is a schematic structural diagram of the phase-locked loop circuit.

The phase-locked loop circuit includes: the prescaler 11, the phase frequency detector 12, the loop filter 14, the voltage controlled oscillator 15, the loop divider 16, the output dividers 17 and 18, and the charge pump circuit provided by the embodiment of the invention described above. These functional units are the same as in the prior art and see in particular the description of fig. 1 above.

Referring to fig. 8, the charge pump circuit includes a charge pump 301 and a control unit 302.

The control unit 302 is configured to output a control signal according to an input signal of the phase frequency detector 12, where the control signal is configured to control the charge pump 301 to operate in a first topology when the phase locked loop is unlocked; after the phase locked loop is locked, the charge pump 301 is controlled to operate in a second topology.

The specific functions and working manners of the above units can be referred to the previous description, and are not repeated here.

Correspondingly, the embodiment of the invention also provides a control method for the charge pump of the phase-locked loop, wherein the charge pump comprises a charging current source, a discharging current source, an upper switch group, a lower switch group and a feedback unit; the upper switch group is connected with the charging current source, the lower switch group is connected with the discharging current, and the upper switch group is connected with the lower switch group and is provided with a first connecting node and a second connecting node.

Referring to fig. 9, the method includes the steps of:

Step 901: when the phase-locked loop is unlocked, the charge pump is controlled to work in a first topological structure, and the voltage of the second connection node is fed back to the first connection node through the feedback unit so as to lock the voltage of the second connection node to a target voltage;

Step 902: after the phase-locked loop is locked, the charge pump is controlled to work by adopting a second topological structure, the voltage of the first connecting node and the voltage of the second connecting node are collected through the feedback unit, and the value of the discharging current source is controlled according to the collected voltage so as to correct the voltage difference between the first connecting node and the second connecting node.

Wherein it is possible to determine whether the phase locked loop is locked or not based on the input signal of the phase frequency detector.

In a specific implementation, regarding each apparatus and each module/unit included in each product described in the above embodiments, it may be a software module/unit, or a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially.

For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least some modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the remaining (if any) part of modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented in hardware such as a circuit, where different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least some modules/units may be implemented in a software program, where the software program runs on a processor integrated within the terminal, and the remaining (if any) some modules/units may be implemented in hardware such as a circuit.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present application limited, and no limitation on the embodiments of the present application should be construed.

The "connection" in the embodiment of the present application refers to various connection manners such as direct connection or indirect connection, so as to implement communication between devices, which is not limited in the embodiment of the present application.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A charge pump circuit for a phase locked loop, the charge pump circuit comprising: a charge pump and a control unit; the charge pump is a current steering charge pump and has a switchable topology;

2. The charge pump circuit for a phase locked loop of claim 1, wherein the discharge current source comprises a first current source and a second current source connected in parallel, the second current source being an adjustable current source.

3. The charge pump circuit for a phase locked loop of claim 1, wherein the charging current source comprises a third current source and a fourth current source connected in parallel, the fourth current source being an adjustable current source.

4. The charge pump circuit for a phase locked loop of claim 2, wherein in the second topology, the feedback unit is configured to control the value of the adjustable current source in accordance with the voltages of the first and second connection nodes.

5. The charge pump circuit for a phase locked loop of claim 2, wherein the feedback unit is an error amplifier.

6. The charge pump circuit for a phase locked loop of claim 5, wherein in the first topology, a positive input of the error amplifier is connected to the second connection node, and a negative input and an output of the error amplifier are connected to the first connection node.

7. The charge pump circuit for a phase locked loop of claim 5, wherein in the second topology, a positive input of the error amplifier is connected to the second connection node, an output of the error amplifier is connected to the adjustable current source, and a negative input of the error amplifier is connected to the first connection node.

8. The charge pump circuit for a phase locked loop of claim 5, wherein the second connection node is connected to a loop filter; the loop filter comprises at least a resistor and a capacitor connected in series between the second connection node and ground;

9. The charge pump circuit for a phase locked loop of claim 8, wherein the phase locked loop comprises a phase frequency detector coupled to the charge pump;

10. The charge pump circuit for a phase locked loop of claim 9, wherein the control unit comprises:

11. A control method of a charge pump for a phase locked loop, wherein the charge pump comprises a charging current source, a discharging current source, an upper switch group, a lower switch group and a feedback unit; the upper switch group is connected with the charging current source, the lower switch group is connected with the discharging current, and the upper switch group is connected with the lower switch group and is provided with a first connecting node and a second connecting node; the method comprises the following steps:

12. The method of claim 11, wherein the phase locked loop includes a phase frequency detector coupled to the charge pump; the method further comprises the steps of:

And determining whether the phase-locked loop is locked or not according to the input signal of the phase frequency detector.

13. A phase locked loop circuit comprising a charge pump circuit for a phase locked loop as claimed in any one of claims 1 to 10.