CN118367958A - Processing method, processing device and related equipment - Google Patents

Abstract

The present disclosure provides a processing method, apparatus, and related devices, where the method includes: configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components; configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, wherein the adjustment circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal; communicating with the plurality of radio frequency front end components based on the second timing signal; the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

Description

Processing method, processing device and related equipment

Technical Field

The disclosure relates to the field of radio frequency technology, and in particular, to a processing method, a processing device and related equipment.

Background

The driving versions of mobile industry processor interfaces (MIPI, mobile Industry Processor Interface) used by devices in the same radio frequency Front End (RFFE, RF Front-End) group may be different, and one-to-one configuration is required for different driving versions to realize normal communication, so that the operation is complex, errors are easy to occur, and the devices are easy to be unidentified.

Disclosure of Invention

The present disclosure provides a processing method, apparatus, and related devices, so as to at least solve the above technical problems in the prior art.

In a first aspect, embodiments of the present disclosure provide a processing method, the method including:

configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components;

configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, wherein the adjustment circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal;

communicating with the plurality of radio frequency front end components based on the second timing signal;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

In a second aspect, embodiments of the present disclosure provide a processing apparatus, the processing apparatus comprising:

the controller is used for configuring the serial interface bus to work on a first timing signal, and the first timing signal is matched with a first driving version of a first radio frequency device in the plurality of radio frequency front-end components;

An adjustment circuit coupled to the serial interface bus, capable of adjusting an impedance of the serial interface bus;

The processor is used for configuring a first working parameter of the adjusting circuit so that the first time sequence signal is adjusted to a second time sequence signal;

The controller is used for communicating with a plurality of radio frequency front-end components based on the second time sequence signals;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

In a third aspect, an embodiment of the present disclosure provides an electronic device, including:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the present disclosure.

In a fourth aspect, the disclosed embodiments provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the methods described in the disclosure.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:

In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

Fig. 1 is a schematic flow chart of a processing method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a first timing signal according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a second timing signal according to an embodiment of the disclosure;

fig. 4 is a schematic structural diagram of a capacitor bank according to an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a processing device according to an embodiment of the disclosure;

Fig. 6 is a schematic structural diagram of a processing apparatus according to an embodiment of the disclosure;

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, the terms "first", "second", and the like are merely used to distinguish between similar objects and do not represent a particular ordering of the objects, it being understood that the "first", "second", or the like may be interchanged with one another, if permitted, to enable embodiments of the disclosure described herein to be implemented in an order other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the present disclosure is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

It should be understood that, in various embodiments of the present disclosure, the size of the sequence number of each implementation process does not mean that the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

Fig. 1 is a schematic flow chart of a processing method according to an embodiment of the disclosure; as shown in fig. 1, the processing method includes:

Step 101, configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components;

step 102, configuring a first operating parameter of an adjusting circuit coupled to the serial interface bus, wherein the adjusting circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal;

Step 103, communicating with the plurality of radio frequency front end components based on the second timing signal;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

In some embodiments, the method may be applied to an electronic device having a radio frequency chip and a plurality of radio frequency front end components. The radio frequency chip communicates with the plurality of radio frequency front end components using a serial interface bus.

The plurality of radio frequency front end components may include: a Power Amplifier (PA), a Switch (Switch), and the like. In a radio frequency front end, a power amplifier may be used to amplify the power of the radio frequency signal to an appropriate level in order to drive the antenna and transmit the signal. The switch can be used to select different antennas, frequency bands or signal sources, adjust the system configuration to meet different requirements, and optimize the signal transmission quality.

In some embodiments, the configuring the serial interface bus to operate on a first timing signal includes:

the radio frequency chip configures the serial interface bus to operate on the first timing signal based on the signal requirements of the first drive version.

Specifically, each rf front-end component in the same rf front-end group uses the same or different MIPI driven versions.

A first RF device in the plurality of RF front-end components uses a first drive version; a second RF device in the plurality of RF front-end components uses a second drive version; the number of first radio frequency devices may be one or more; the number of second rf devices may be one or more, and the second drive versions of any two second rf devices may be the same or different.

The radio frequency chip configures the serial interface bus to operate on the first timing signal based on the first driving version, which may cause that the second radio frequency device adopting the second driving version cannot normally receive the information transmitted based on the first timing signal. Based on this, the disclosed embodiments provide a method of adjusting a first timing signal to a second timing signal to communicate by matching a second timing signal of a first driven version of a first radio frequency device in the plurality of radio frequency front end components and a second driven version of a second radio frequency device in the plurality of radio frequency front end components.

In some embodiments, the serial interface bus may include a clock signal line and a data signal line;

Accordingly, the first timing signal may include: a clock signal and a data signal.

The adjusting circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal, comprising:

The adjustment circuit can apply a first adjustment signal to the clock signal line and/or the adjustment circuit can apply a second adjustment signal to the data signal line;

the clock signal and the data signal corresponding to the first timing signal have a first timing relationship;

the clock signal and the data signal corresponding to the second time sequence signal have a second time sequence relation, and the first time sequence relation is different from the second time sequence relation.

Specifically, the serial interface bus includes a clock signal line and a data signal line, and a signal on any one of the clock signal line and the data signal line can be adjusted to obtain the second timing signal.

In an example, the signal on the clock signal line is kept unchanged, and a second adjustment signal is applied to the data signal line by using an adjustment circuit to obtain an adjusted first timing signal;

in another example, a first adjustment signal is applied to the clock signal line by the adjustment circuit, and a second adjustment signal is applied to the data signal line, resulting in an adjusted first timing signal;

In yet another example, the signal on the data signal line is kept unchanged, and a first adjustment signal is applied to the clock signal line by using an adjustment circuit to obtain an adjusted first timing signal;

The timing relationship between the clock signal and the data signal can be changed in any of the above ways, i.e. the first timing signal can be adjusted to obtain the second timing signal.

In some embodiments, the adjustment circuit comprises an array of capacitors;

Configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, comprising:

The capacitor array is configured to generate a first target capacitance value that is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal.

Specifically, one end of the capacitor array is grounded, the other end of the capacitor array is connected with the serial interface bus, and the impedance of the serial interface bus can be adjusted by changing the capacitance value of the capacitor array, so that the time sequence signal transmitted by the serial interface bus is changed.

Specifically, by varying the capacitance value of the capacitor array, the ability of the capacitor array to store charge can be adjusted, thereby affecting the transmission speed and phase delay of the signal. The principle is that increasing the capacitance increases the capacity of the capacitor array to store charge, since a larger capacitor array can store more charge, while decreasing the capacitance decreases the capacity to store charge. Meanwhile, the larger capacitance value can lead to the impedance reduction of the capacitor array, so that the transmission speed of the capacitor array to low-frequency signals is slower, and the phase delay is caused; for high frequency signals, a larger capacitance value also results in a larger phase delay, because the capacitor array requires a certain time to store and release charge, thereby delaying the phase of the high frequency signal. In summary, the larger capacitance value can slow down the signal transmission speed and increase the phase delay; the smaller capacitance value can make the signal transmission speed faster, and the phase delay is reduced.

Thus, the signal transmission speed and the phase delay on the serial interface bus are adjusted, and the adjustment and the control of the time sequence signals are realized.

In some embodiments, the adjustment circuit comprises an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank;

Configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, comprising:

Configuring the first capacitor group to generate a second target capacitance value and/or configuring the second capacitor group to generate a third target capacitance value;

The second target capacitance value is capable of adjusting an impedance of the clock signal line, and the third target capacitance value is capable of adjusting an impedance of the data signal line such that the first timing signal is adjusted to the second timing signal.

Specifically, the serial interface bus includes a clock signal line and a data signal line; the first timing signal includes: a clock signal and a data signal. The capacitor array may include: a first capacitor bank and a second capacitor bank. In practical application, the clock signal line can be adjusted by using the first capacitor bank; or adjusting the data signal line by using the second capacitor group; or simultaneously adjusting the clock signal line and the data signal line by using the first capacitor group and the second capacitor group, respectively. In any of the above ways, the clock signal and the data signal may be changed to have a timing relationship, i.e., the first timing signal may be adjusted to the second timing signal.

In some embodiments, the configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus comprises:

Transmitting first instruction information to the plurality of radio frequency front end components based on the first timing signal;

acquiring a plurality of feedback information corresponding to the plurality of radio frequency front-end components;

If the feedback information meets the target condition, recording the working parameters of the adjusting circuit as the first working parameters when the target condition is met; or alternatively

And if the feedback information does not meet the target condition, adjusting the working parameters of the adjusting circuit until the feedback information meets the target condition, and recording the working parameters meeting the target condition as the first working parameters.

Wherein the plurality of feedback information satisfies a target condition, comprising:

The plurality of feedback information comprises feedback information corresponding to each of the plurality of radio frequency front end components.

Specifically, the checking whether the timing signal can match the driving versions of the plurality of radio frequency front end components can be actually realized by checking whether the radio frequency chip can normally communicate with the plurality of radio frequency front end components at the same time based on the timing signal. Therefore, the first instruction information is sent to the plurality of radio frequency front end components through the time sequence signal, and feedback information of the plurality of radio frequency front end components is detected to check whether the time sequence signal can match with driving versions of the plurality of radio frequency front end components.

Here, the first instruction information may be used to request reading of an address of the radio frequency front end component; the corresponding feedback information may be address information of the radio frequency front end component.

If the plurality of feedback information includes feedback information corresponding to each of the plurality of radio frequency front-end components, the feedback information indicates that each radio frequency front-end component successfully receives the first instruction signal; that is, the first timing signal may be adjusted to a second timing signal, where the second timing signal may match a first driving version of a first rf device in the plurality of rf front-end components and a second driving version of a second rf device in the plurality of rf front-end components.

As shown in fig. 2 and 3, schematic diagrams of a first timing signal and a second timing signal are provided; in the figure, the broken line represents the clock signal, and the solid line is the data signal. The abscissa represents time in ns (nanoseconds); the ordinate is the voltage amplitude in V.

It is assumed that the first timing signal matches the first driving version, and the three rf front-end components match the first driving version, the second driving version, and the third driving version, respectively.

Each drive version specifies the timing relationship of the data signal and the clock signal, i.e. the range of relative time differences between the data signal and the clock signal.

Examples of timing relationships, relative time difference ranges, of the first drive version, the second drive version, and the third drive version are provided herein, as shown in table 1 below.

TABLE 1

Table 1 shows that the first drive version requires a relative time difference between the data signal and the clock signal of between-1 ns and 3ns, where 3ns indicates that the clock signal leads the data signal by 3ns and-1 ns indicates that the data signal leads the clock signal by 1ns.

The second drive version requires the timing relationship of the data signal and the clock signal to be: the clock signal leads the data signal, and the relative time difference between the clock signal and the data signal is between 2ns and 6 ns;

the third drive version requires the timing relationship of the data signal and the clock signal to be: the clock signal leads the data signal by a relative time difference between 0 and 4 ns.

As can be seen from fig. 2, which shows a first timing signal, in combination with the marked interval, the slope of the rising edge of the clock signal is close to the slope of the rising edge of the data signal, i.e. the relative time difference between the clock signal and the data signal is small, i.e. the relative time difference between the two is about 0, belonging to the relative time difference range of the first driving version.

The first timing signal is adjusted by the method disclosed by the invention, wherein only the data signal can be adjusted, only the clock signal can be adjusted, and the data signal and the clock signal can be adjusted at the same time; after the adjustment, a second timing signal is obtained, as shown in fig. 3, and it can be seen that the rising edge of the clock signal has a steeper gradient than the rising edge of the data signal, that is, the clock signal leads the data signal, and the relative time difference between the two signals is about 2ns, and belongs to the relative time difference ranges of the first driving version, the second driving version and the third driving version.

It should be noted that the ranges of the relative time differences required by the multiple driving versions may not be consistent, but there must be an overlap between each other, so the timing relationship between the clock signal and the data signal that match the multiple driving versions simultaneously must be adjusted by the method of the present disclosure. In addition, it will be appreciated that by varying the rising edge herein, there may be a corresponding change in the waveform of the subsequent signal, for example, if the rising edge of the data signal becomes steeper, the time of the next cycle may be advanced.

In an example, the rf chip starts to send the instruction (i.e. the first instruction information) for reading the address with the first timing signal as shown in fig. 2, but since the corresponding multiple rf front-end components (assuming three rf front-end components, respectively FEM1, FEM2, FEM 3) respectively adopt the first driving version, the second driving version, and the third driving version, the FEM1, FEM2, and FEM3 have the problem that the instruction for reading the address cannot be received correctly because the driving versions are not compatible, and the address cannot be sent correctly. By using the method disclosed by the invention, the second time sequence signal shown in fig. 3 is obtained after the first time sequence signal is regulated by the regulating circuit, and the restarting mechanism of the FEM1, the FEM2 and the FEM3 is triggered due to the change of the time sequence relation, and the FEM1, the FEM2 and the FEM3 after restarting directly send the default address to the radio frequency chip according to the received second time sequence signal (the second time sequence signal is matched with a plurality of driving versions), so that the radio frequency chip successfully obtains the address, and then the radio frequency chip and a plurality of radio frequency front-end devices can also continue to normally communicate based on the second time sequence signal. Meanwhile, the phenomenon that the address of the device at the front end of the scanning radio frequency is wrong due to different driving versions in the earlier stage is avoided, and the normal implementation of communication is ensured.

In actual application, in the initial stage of starting, a driving version and the size of a capacitance to ground which are uniformly and downwards compatible are selected according to the actual condition of each radio frequency front-end device, when a time sequence signal needs to be adjusted, the first working parameter is obtained by adjusting the working parameters of the adjusting circuit and detecting whether the time sequence relationship between a clock signal and a digital signal is proper (namely whether the plurality of feedback information meets the target condition) after each adjustment, if so, the working parameters when the target condition is met are directly determined, and if not, the working parameters of the adjusting circuit are continuously adjusted until the working parameters when the target condition is determined to be met. When the radio frequency chip is applied, the obtained first working parameter setting adjusting circuit can be used for coupling the adjusting circuit to the serial interface bus, so that the first time sequence signal is adjusted to be a second time sequence signal, and the radio frequency chip can communicate with a plurality of radio frequency front-end components based on the second time sequence signal.

Therefore, complex driving configuration is not needed in the early stage, the problem related to time sequence can be solved through the adjusting circuit, and complex operations such as later software change and the like are avoided. And the adjusting circuit is realized by adopting a capacitor, so that the cost is lower, and the adjusting mode is simple.

In some embodiments, the adjustment circuit comprises an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank; the first capacitor group and the second capacitor group respectively comprise at least two capacitor units connected in parallel; each of the capacitor units includes: a capacitor and a switch connected in series; adjusting the operating parameters of the adjusting circuit, comprising:

Adjusting the on-off state of the switch of one or more capacitor units in the first capacitor group to increase or decrease the capacitance value of the first capacitor group; and/or the number of the groups of groups,

And adjusting the on-off state of the switch of one or more capacitor units in the second capacitor group so as to increase or decrease the capacitance value of the second capacitor group.

Specifically, the capacitance value of the capacitor group is adjusted by adjusting the number of capacitors connected in parallel.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a capacitor bank according to an embodiment of the disclosure; where Vref denotes ground, reset denotes Reset, vout is connected to a serial interface bus (clock signal line or data signal line) for applying an adjustment signal to the clock signal line (SCLK) and/or the data signal line (SDATA).

As can be seen, the capacitor bank includes: a plurality of capacitor units connected in parallel, such as:

A first capacitance unit 401 composed of a capacitance C _L1 and a switch S _L1;

a second capacitance unit 402 composed of a capacitance C _L3 and a switch S _L3;

a third capacitance unit 403 composed of a capacitance C _H1 and a switch S _H1;

A fourth capacitance unit 404 composed of a capacitance C _H4 and a switch S _H4;

Of course, other capacitor units are also included, each of which is not labeled one by one in fig. 4, and each of which includes a capacitor (e.g., any of C _L1、C_L2……C_L6,C_H1、C_H2……C_H6) and a switch (e.g., the next switch to which the capacitor is connected: S _L1、S_L2……S_L6,S_H1、S_H2……S_H6).

When one switch is closed, one capacitor is connected in parallel, and the rising edge and the falling edge are controlled by changing the capacitance value, namely changing the peak value of the waveform of the time sequence signal by utilizing the characteristics of the capacitor. Therefore, the capacitance value of the capacitor group can be increased or reduced by adjusting the on-off state of the switch.

In the drawing, the capacitance values of the respective capacitances (C _L1、C_L2……C_L6,C_H1、C_H2……C_H6, C1, C2) may be the same or different. The radio frequency front-end components adopting the MIPI drive version necessarily correspond to time sequence signals which simultaneously meet the communication requirements of the MIPI drive version, so that if the working parameters of the adjusting circuit can not be obtained when the target conditions are met through various capacitance values of a certain capacitance group, a capacitance unit can be added or the currently adopted capacitance can be replaced. The number of the capacitor units and the capacitance values of the capacitors used in the present disclosure are not limited.

Fig. 5 is a schematic structural diagram of a processing apparatus according to an embodiment of the disclosure; as shown in fig. 5, the processing device includes: a radio frequency chip (RFIC) 501, a timing adjustment integrated circuit 502.

The rf chip 501 is connected to a plurality of rf front-end components 503, respectively denoted as FEM1, FEM2, … … FEMn, via a clock signal line (SCLK) and a data signal line (SDATA).

The rf chip 501 may configure the clock signal line and the data signal line to operate on a first timing signal that matches a first driven version of a first rf device in the plurality of rf front-end components 503. The plurality of radio frequency front end components 503 include: FEM1, FEM2, FEM3 … … FEMn. N is 1 or more.

The timing adjustment integrated circuit 502 includes: two capacitor groups (e.g., a first capacitor group, a second capacitor group) respectively connected to the clock signal line (SCLK) and the data signal line (SDATA); each capacitor group comprises at least two capacitor units connected in parallel; each of the capacitor units includes: a capacitor and a switch in series. The capacitor bank may be the capacitor bank shown in fig. 2.

The timing adjustment integrated circuit 502 may further be provided with a processor, configured to adjust on/off states of switches of one or more capacitor units in the first capacitor bank, so as to increase or decrease a capacitance value of the first capacitor bank; and/or the number of the groups of groups,

And adjusting the on-off state of the switch of one or more capacitor units in the second capacitor group to increase or decrease the capacitance value of the second capacitor group.

The processor may configure a first operating parameter of two capacitance sets coupled to the clock signal line and the data signal line; the two capacitor groups can adjust the impedance of the clock signal line and the data signal line so that the first time sequence signal is adjusted to be a second time sequence signal; here, the second timing signal can match a first driving version of a first rf device in the plurality of rf front-end components 503 and a second driving version of a second rf device in the plurality of rf front-end components 503, the first driving version being different from the second driving version;

As such, the rf chip 501 may communicate with the plurality of rf front-end components 503 based on the second timing signal.

Fig. 6 is a schematic structural diagram of a processing apparatus according to an embodiment of the disclosure; as shown in fig. 6, the processing apparatus includes:

A controller 601, configured to configure the serial interface bus to operate on a first timing signal, where the first timing signal matches a first driving version of a first rf device in the plurality of rf front-end components;

an adjustment circuit 603 coupled to the serial interface bus, capable of adjusting the impedance of the serial interface bus;

A processor 602, configured to configure a first operation parameter of the adjusting circuit 603 so that the first timing signal is adjusted to a second timing signal;

The controller 601 is configured to communicate with a plurality of radio frequency front end components 604 based on the second timing signal;

wherein the second timing signal is capable of matching a first driven version of a first rf device in the plurality of rf front-end components 604 and a second driven version of a second rf device in the plurality of rf front-end components 604, the first driven version being different from the second driven version.

In some embodiments, the plurality of rf front-end components 604 comprise: rf front-end module 1, rf front-end module 2 … … rf front-end module n. n is 1 or more.

In some embodiments, the processing means is applied to an electronic device; the controller is a radio frequency chip (RFIC) in an electronic device; the processor may be a central processor, an application processor, etc. in the electronic device.

In some embodiments, the conditioning circuit 603 includes an array of capacitors; the processor is configured to configure a capacitance combination of the capacitor array to generate a first target capacitance value, the first target capacitance value being capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal.

In some embodiments, the conditioning circuit 603 includes an array of capacitors;

the processor is configured to configure a capacitance combination of the capacitor array to generate a first target capacitance value, the first target capacitance value being capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal.

In some embodiments, the conditioning circuit 603 includes an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank;

The processor is configured to configure the first capacitor bank to generate a second target capacitance value, and/or configure the second capacitor bank to generate a third target capacitance value;

The second target capacitance value is capable of adjusting an impedance of the clock signal line, and the third target capacitance value is capable of adjusting an impedance of the data signal line such that the first timing signal is adjusted to the second timing signal.

In some embodiments, the processor is configured to send first instruction information to the plurality of radio frequency front end components 604 based on the first timing signal;

Obtaining a plurality of feedback information corresponding to the plurality of rf front-end components 604;

If the feedback information satisfies a target condition, recording the working parameter of the adjusting circuit 603 as the first working parameter when the target condition is satisfied; or alternatively

And if the feedback information does not meet the target condition, adjusting the working parameters of the adjusting circuit 603 until the feedback information meets the target condition, and recording the working parameters meeting the target condition as the first working parameters.

In some embodiments, the conditioning circuit 603 includes an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank; the first capacitor group and the second capacitor group respectively comprise at least two capacitor units connected in parallel; each of the capacitor units includes: a capacitor and a switch connected in series;

The processor is used for adjusting the on-off state of the switch of one or more capacitor units in the first capacitor group so as to increase or decrease the capacitance value of the first capacitor group; and/or the number of the groups of groups,

And adjusting the on-off state of the switch of one or more capacitor units in the second capacitor group so as to increase or decrease the capacitance value of the second capacitor group.

In some embodiments, the plurality of feedback information satisfies a target condition, including:

the plurality of feedback information includes feedback information corresponding to each of the plurality of rf front-end components 604.

It will be appreciated that, when implementing the corresponding processing method, the processing apparatus provided in the foregoing embodiment may allocate the processing to be performed by different program modules according to need, so as to complete all or part of the processing described above. In addition, the apparatus provided in the foregoing embodiments and the embodiments of the corresponding methods belong to the same concept, and specific implementation processes of the apparatus and the embodiments of the methods are detailed in the method embodiments, which are not described herein again.

The disclosed embodiments provide a computer readable storage medium having stored therein executable instructions that, when executed by a processor, will trigger the processor to perform the processing methods provided by the disclosed embodiments.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure; as shown in fig. 7, the electronic device 70 includes: a processor 701, and a memory 702 communicatively coupled to the processor 701; the memory 702 stores instructions executable by the processor 701 to enable the processor 701 to perform:

configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components;

configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, wherein the adjustment circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal;

communicating with a plurality of radio frequency front end components based on the second timing signal;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

The electronic device 70 further includes: an adjustment circuit is coupled to the serial interface bus, capable of adjusting an impedance of the serial interface bus.

In practical applications, the electronic device 70 may further include: at least one network interface 703. The various components in the electronic device 70 are coupled together by a bus system 704. It is appreciated that bus system 704 is used to enable connected communications between these components. The bus system 704 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 704 in fig. 7. The number of the processors 701 may be at least one, and the number of the memories 702 may be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

The memory 702 in the disclosed embodiments is used to store various types of data to support the operation of the electronic device 70.

The methods disclosed in the embodiments of the present disclosure may be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 701 or by instructions in the form of software. The Processor 701 may be a general purpose Processor, a digital signal Processor (DSP, diGital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 701 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present disclosure. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in the decoded processor. The software modules may be located in a storage medium in a memory 702. The processor 701 reads information in the memory 702 and, in combination with its hardware, performs the steps of the method as described above.

In some embodiments, the electronic device 70 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex Programmable logic devices (CPLDs, complex Programmable Logic Device), field-Programmable gate arrays (FPGAs), general purpose processors, controllers, microcontrollers (MCUs, micro Controller Unit), microprocessors (microprocessors), or other electronic elements for performing the foregoing methods.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel or sequentially or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A method of processing, the method comprising:

configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components;

configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, wherein the adjustment circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal;

communicating with the plurality of radio frequency front end components based on the second timing signal;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

2. The method of claim 1, wherein the serial interface bus comprises a clock signal line and a data signal line; the adjusting circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal, comprising:

The adjustment circuit can apply a first adjustment signal to the clock signal line and/or the adjustment circuit can apply a second adjustment signal to the data signal line;

the clock signal and the data signal corresponding to the first timing signal have a first timing relationship;

the clock signal and the data signal corresponding to the second time sequence signal have a second time sequence relation, and the first time sequence relation is different from the second time sequence relation.

3. The method of claim 1, wherein the conditioning circuit comprises an array of capacitors; configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, comprising:

The capacitor array is configured to generate a first target capacitance value that is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal.

4. The method of claim 2, wherein the conditioning circuit comprises an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank; configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, comprising:

Configuring the first capacitor group to generate a second target capacitance value and/or configuring the second capacitor group to generate a third target capacitance value;

The second target capacitance value is capable of adjusting an impedance of the clock signal line, and the third target capacitance value is capable of adjusting an impedance of the data signal line such that the first timing signal is adjusted to the second timing signal.

5. The method of claim 1, wherein configuring the first operating parameter of the adjustment circuit coupled to the serial interface bus comprises:

Transmitting first instruction information to the plurality of radio frequency front end components based on the first timing signal;

acquiring a plurality of feedback information corresponding to the plurality of radio frequency front-end components;

If the feedback information meets the target condition, recording the working parameters of the adjusting circuit as the first working parameters when the target condition is met; or alternatively

And if the feedback information does not meet the target condition, adjusting the working parameters of the adjusting circuit until the feedback information meets the target condition, and recording the working parameters meeting the target condition as the first working parameters.

6. The method of claim 5, wherein the conditioning circuit comprises an array of capacitors; the capacitor array includes: a first capacitor bank and a second capacitor bank; the first capacitor group and the second capacitor group respectively comprise at least two capacitor units connected in parallel; each of the capacitor units includes: a capacitor and a switch connected in series; adjusting the operating parameters of the adjusting circuit, comprising:

Adjusting the on-off state of the switch of one or more capacitor units in the first capacitor group to increase or decrease the capacitance value of the first capacitor group; and/or the number of the groups of groups,

And adjusting the on-off state of the switch of one or more capacitor units in the second capacitor group so as to increase or decrease the capacitance value of the second capacitor group.

7. The method of claim 5, wherein the plurality of feedback information satisfies a target condition, comprising:

The plurality of feedback information comprises feedback information corresponding to each of the plurality of radio frequency front end components.

8. A processing apparatus, the processing apparatus comprising:

the controller is used for configuring the serial interface bus to work on a first timing signal, and the first timing signal is matched with a first driving version of a first radio frequency device in the plurality of radio frequency front-end components;

An adjustment circuit coupled to the serial interface bus, capable of adjusting an impedance of the serial interface bus;

The processor is used for configuring a first working parameter of the adjusting circuit so that the first time sequence signal is adjusted to a second time sequence signal;

The controller is used for communicating with a plurality of radio frequency front-end components based on the second time sequence signals;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.

9. The apparatus of claim 8, wherein the adjustment circuit comprises an array of capacitors; the processor is configured to configure a capacitance combination of the capacitor array to generate a first target capacitance value, the first target capacitance value being capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal.

10. An electronic device, comprising:

A plurality of radio frequency front end components,

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform:

configuring a serial interface bus to work on a first timing signal, wherein the first timing signal is matched with a first driving version of a first radio frequency device in a plurality of radio frequency front-end components;

configuring a first operating parameter of an adjustment circuit coupled to the serial interface bus, wherein the adjustment circuit is capable of adjusting an impedance of the serial interface bus such that the first timing signal is adjusted to a second timing signal;

communicating with a plurality of radio frequency front end components based on the second timing signal;

the second timing signal can match a first driving version of a first radio frequency device in the plurality of radio frequency front end components and a second driving version of a second radio frequency device in the plurality of radio frequency front end components, wherein the first driving version is different from the second driving version.