CN118368163A

CN118368163A - LIN bus system and slave addressing method based on LIN bus system

Info

Publication number: CN118368163A
Application number: CN202410758456.8A
Authority: CN
Inventors: 浦亚军; 林凯; 黄昊丹
Original assignee: WUXI SI-POWER MICRO-ELECTRONICS CO LTD
Current assignee: WUXI SI-POWER MICRO-ELECTRONICS CO LTD
Priority date: 2024-06-13
Filing date: 2024-06-13
Publication date: 2024-07-19
Anticipated expiration: 2044-06-13
Also published as: CN118368163B

Abstract

The application relates to a LIN bus system and a slave addressing method based on the LIN bus system, which relates to the technical field of LIN buses. The system comprises a host, a bus and at least two slaves; the host computer is connected with the slave computer through a bus, and the host computer and the slave computer are connected into a power supply; the slave is used for realizing single-round addressing in the addressing process based on the LIN bus; the slave comprises a slave power supply end, a first switch, a second switch, a first resistor, a mirror current source, a second resistor, an amplifier, an analog-to-digital converter ADC, a divider and an arithmetic logic unit ALU. The voltage signal is converted into a target address indication signal indicating an address allocated in the communication process based on the reading of the second resistance drop in the different state. In the case of an accurate measurement, the addressing of the LIN bus slave addresses can be done in the course of one LIN poll.

Description

LIN bus system and slave addressing method based on LIN bus system

Technical Field

The application relates to the technical field of local interconnection network (Local Interconnect Network, LIN) buses, in particular to a LIN bus system and a slave addressing method based on the LIN bus system.

Background

The development of automotive electronics systems has become an important trend in the automotive industry. The advent of distributed electronic systems has allowed a substantial increase in the number of electronic control units for automobiles, thereby improving the level of functionality and intelligence of the vehicle. The LIN bus, however, has emerged in this context as one of the key components of distributed electronic systems. The LIN bus is mainly applied to a structure that a LIN bus of an electric door and window control system, a seat adjusting system, a car lamp lighting system, a windshield wiper system, an air conditioning system, a sound box system and the like is a single master and multiple slaves, and two modes exist, namely a serial mode and a parallel mode, wherein the serial mode adopts a daisy chain mode, in one example, as shown in fig. 1, in the case of having a single host 110, one bus 120 can be connected with 16 nodes at most, and each node corresponds to one slave 130. Therefore, in the actual use process, the addresses of all slave nodes need to be allocated in part of occasions, the addresses are allocated in two ways, one way is a preset way, the addresses are pre-solidified in the equipment in the production and manufacturing process of the equipment, the corresponding modules in the way need to be clearly distinguished, the fault tolerance rate in the assembly process is relatively high, but if the modules in all the positions cannot be distinguished, errors can easily occur in the assembly and subsequent maintenance, and the requirement of automatic addressing is put forward for the LIN slave modules. The prior art has different automatic addressing schemes.

Patent US7091876B2 describes a method for implementing automatic addressing by detecting the current above the internal sense resistor, comparing with an internally set threshold, which implementation is relatively long, requires a maximum 16 rounds of polling for addressing, and takes a relatively long time; patent EP2717547B1 also describes a method for implementing automatic addressing of a LIN bus system, which is implemented in a similar manner to patent US7091876B2, but by setting upper and lower thresholds, a round of address allocation of up to 5 nodes is implemented, and multiple polls are required to meet the requirements; patent CN115086278a also describes a way of implementing automatic addressing of the system of the LIN bus, which is similar to US7091876B2, except that the current source is changed to a step-wise way, and the polling 16 is also needed at maximum.

The above-mentioned mode can realize the function of LIN slave node automatic addressing, but there is certain problem at the same time, the main problem is concentrated in the related art, the polling frequency of automatic addressing is too high, it is easy to cause the waste of the resource.

Disclosure of Invention

The application relates to a LIN bus system and a slave addressing method based on the LIN bus system, which can complete the addressing of the slave address in the process of word LIN polling, and the technical proposal is as follows:

In one aspect, a LIN bus system is provided that includes a master, a bus, and at least two slaves;

The host computer is connected with the slave computer through a bus, and the host computer and the slave computer are connected into a power supply;

the slave is used for realizing single-round addressing in the addressing process based on the LIN bus;

The slave comprises a slave power supply end, a first switch, a second switch, a first resistor, a mirror current source, a second resistor, an amplifier, an Analog-to-digital converter (ADC), a divider and an arithmetic logic unit (ARITHMETIC LOGIC UNIT, ALU);

The first switch is connected with the first resistor and then connected to the slave power supply end, and the second switch is connected with the mirror current source and then connected to the slave power supply end; the first resistor and the second resistor are connected to the bus;

the second resistor is connected in series on the bus;

The amplifier is connected to two ends of the second resistor and used for amplifying voltage drop data of the second resistor;

The ADC is connected with the amplifier and used for reading the amplified voltage drop data;

The divider is connected with the ADC and is used for determining an initial address indication signal based on the amplified voltage drop data;

The ALU is connected with the divider, and is used for determining a target address indication signal corresponding to the slave machine based on the address indication signal, wherein the target address indication signal is used for indicating an addressing result of the slave machine.

In an alternative embodiment, the slave further comprises a first diode and a second diode;

the first resistor is connected to the bus through a first diode;

the second resistor is connected to the bus through a second diode;

the first diode and the second diode are used for limiting the current flow direction.

In an alternative embodiment, the slave further comprises a third diode and a third switch;

the third diode is connected to the third switch, and the third switch is grounded;

in an alternative embodiment, the divider has a second input;

a second input of the divider is connected to a reference voltage source.

In an alternative embodiment, the slave further comprises an address memory;

the address memory is connected with the ALU;

The address memory is used for storing a target address indication signal.

In an alternative embodiment, the mirrored current source is implemented as a transformer.

In another aspect, there is provided a method of slave addressing of a LIN bus system, the method being applied to a slave within a LIN bus system as any one of the above, the method comprising:

controlling the first switch and the second switch to be turned off;

in response to the LIN communication entering a Break frame, first voltage drop data acquired by an ADC sense amplifier;

Controlling the second switch to be closed, and reading second voltage drop data acquired by the amplifier through the ADC;

inputting the difference value of the first voltage drop data and the second voltage drop data into a divider, and outputting to obtain an initial address indication signal corresponding to the slave;

The destination address indication signal is determined by the ALU based on the initial address indication signal, the destination address indication signal being used to indicate the addressing result of the slave.

In an alternative embodiment, the slave further comprises an address memory;

the address memory is connected with the ALU;

After determining the target address indication signal based on the initial address indication signal by the ALU, comprising:

The target address indication signal is acquired and stored by the address memory.

In an alternative embodiment, controlling the first switch and the second switch to open includes:

And controlling the first switch to be disconnected from the second switch in response to the absence of the target address indication signal in the address memory.

In an alternative embodiment, determining, by the ALU, the target address indication signal based on the initial address indication signal includes:

pre-storing a conversion relation table in the ALU, wherein the conversion relation table is used for indicating the corresponding relation between the initial address indication signal and the target address indication signal;

The target address indication signal is determined based on the initial address indication signal through the conversion relation table.

The technical effects included in each embodiment of the application at least include:

In a master-slave architecture based on the LIN bus, the voltage signal is converted into a target address indication signal indicating the address allocated during communication based on the reading of the second resistance drop in the different states by means of an amplifier, an analog-to-digital converter, a divider and an ALU within the slave. In the case of an accurate measurement, the addressing of the LIN bus slave addresses can be done in the course of one LIN poll.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic diagram of an architecture of a LIN bus system in the related art.

Fig. 2 shows a schematic logic structure of a LIN bus system according to an exemplary embodiment of the present application.

Fig. 3 shows a schematic flow chart of a slave addressing method based on a LIN bus system according to an exemplary embodiment of the present application.

Fig. 4 illustrates a logical block diagram of a slave provided by an exemplary embodiment of the present application.

Fig. 5 shows a flow chart of another slave addressing method based on the LIN bus system according to an exemplary embodiment of the present application.

Fig. 6 is a schematic diagram of a relationship conversion table according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

Fig. 2 shows a schematic structural diagram of a LIN bus system according to an exemplary embodiment of the present application. Referring to fig. 1, the system includes a master 210, a bus 220, and at least two slaves 230. The master 210 and the slave 230 are connected through the bus 220, and the master 210 and the slave 220 are connected to the power BAT.

In an embodiment of the application, the host is implemented as a master control unit of the LIN bus system. In the example shown in fig. 2, the host 210 is equivalently represented by a host first diode 211, a host second diode 212, a host function switch SM, and a host equivalent resistor R _MAST, which include the current flow direction. The application is not limited to the specific structure and function of the host in the LIN bus system. The number of hosts is one.

At least two slaves belong to the same set of slaves corresponding to the master, and the slaves are used for realizing single-round addressing in the addressing process based on the LIN bus. The number of slaves is not limited in the embodiment of the present application, and in one example, the maximum number of slaves is 16.

IN the embodiment of the present application, between the slave signal input terminal lin_in and the slave signal output terminal lin_out, the slave 230 includes a slave power source terminal VS, a first switch S1, a second switch S2, a first resistor R _SLAVE, a mirror current source I _SHUNT, a second resistor R _SHUNT, an amplifier 231, an ADC232, a divider 233, and an ALU234. The first switch is connected with the first resistor and then connected to the slave power supply end, and the second switch is connected with the mirror current source and then connected to the slave power supply end; the first resistor and the second resistor are connected to the bus; the second resistor is connected in series on the bus; the amplifier is connected to two ends of the second resistor, and the voltage drop data ADC for amplifying the second resistor is connected with the amplifier and used for reading the amplified voltage drop data; the divider is connected with the ADC and is used for determining an initial address indication signal based on the amplified voltage drop data; the ALU is connected with the divider, and is used for determining a target address indication signal corresponding to the slave machine based on the address indication signal, wherein the target address indication signal is used for indicating an addressing result of the slave machine.

In the embodiment of the application, the first resistor is a pull-up resistor of the slave, the second resistor is a small resistor connected in parallel with the first resistor, after the LIN bus system is communicated with the Break frame, the current passes through the first resistor and the second resistor to generate voltage drop, and the voltage drop signal of the second resistor is acquired by the amplifier for subsequent processing.

In the embodiment of the application, since the second resistor is a small resistor, in order to ensure that individual differences of the resistors in the slaves do not cause errors in subsequent use, a round of correction is required in the chip production test. In one example, the correction is by sinking a standard operating current across the second resistor. The working current is 2mA, corresponding voltage is acquired through an internal ADC after the working current is amplified by 80 times through an amplifier, and the voltage is stored in an internal base number register and can be used as a reference voltage in a divider.

Alternatively, in some embodiments of the application, the amplifier can be implemented as a Programmable gain amplifier (Programmable GAIN AMPLIFIER, PGA).

In the embodiment of the application, a plurality of slaves in the slave set are connected through a bus.

It should be noted that, in the embodiment of the present application, the power supply terminal of the slave and the power supply terminal of the host access the same power line.

Fig. 3 is a schematic flow chart of a slave addressing method based on a LIN bus system according to an exemplary embodiment of the present application, where the method is applied to the LIN bus system shown in fig. 2, and the method includes:

in step 301, the first switch and the second switch are controlled to be turned off.

In this process, both the first resistor and the mirror current source, which are corresponding pull-up resistors, are not powered up.

Step 302, in response to the LIN communication entering a Break frame, reads the first voltage drop data acquired by the amplifier through the ADC.

Optionally, break is used to perform a communication synchronization procedure. In an embodiment of the present application, when LIN communication enters a Break frame, an amplifier implemented as PGA will read the voltage drop data in this state and read by an ADC after amplification. Optionally, the PGA has a magnification of 80 times.

Step 303, controlling the second switch to close and reading the second voltage drop data obtained by the amplifier through the ADC.

When the mirror current source is turned on, the second voltage drop data is correspondingly read through the ADC.

And 304, inputting the difference value between the first voltage drop data and the second voltage drop data into a divider, and outputting an initial address indication signal corresponding to the slave.

In the embodiment of the application, the divider calculates the difference between the first voltage drop data and the second voltage drop data, and obtains the reference voltage, so as to obtain an initial address indication signal, that is, the initial address indication signal is realized in a numerical form. In this case, the first pressure drop is V1, the second pressure drop is V2, and the difference between the first pressure drop and the second pressure drop is V _DIFF =v2-V1. The reference voltage is V _{SHUNT_REF}, and the value of the initial address indication signal is add_data=v _DIFF/V_{SHUNT_REF}.

In step 305, a target address indication signal is determined by the ALU based on the initial address indication signal.

As can be seen from the above description, the target address indication signal is used to indicate the address result of the slave. In the embodiment of the application, the target address indication signal, that is, the correspondence between the target address indication signal and the base address indication signal, can be determined based on the initial address indication signal realized as a numerical value by the logic operation function of the ALU.

Fig. 4 is a schematic structural diagram of a slave according to an exemplary embodiment of the present application, and referring to fig. 4, the slave may be implemented in place of the slave 230 in the LIN bus system shown in fig. 2. The slave includes a slave power source VS, a first switch S1, a second switch S2, a first resistor R _SLAVE, a mirror current source I _SHUNT, a second resistor R _SHUNT, an amplifier 231, an ADC232, a divider 233, and an arithmetic logic unit ALU234. In the case that the operation principle and connection relation of the above components are the same as those of the components in the slave unit shown in fig. 2, in the embodiment of the present application, the slave unit further includes a first diode 235 and a second diode 236; the first resistor is connected to the bus through a first diode; the second resistor is connected to the bus through a second diode; the first diode and the second diode are used for limiting the current flow direction.

In the embodiment of the present application, the slave further includes a third diode 237 and a third switch S3; the third diode is connected to the third switch, and the third switch is grounded; the third diode is used for preventing reverse connection, and the third switch is used for realizing the communication function of the slave machine.

In the embodiment of the application, the divider is provided with a second input end; a second input of the divider is connected to a reference voltage source V _{SHUNT_REF}. Alternatively, as previously indicated, the input of the divider may be directly connected to a register to obtain the reference voltage value.

In an embodiment of the present application, the slave further includes an address memory 238, which is connected to the ALU, and is configured to store the target address indication signal.

Optionally, referring to fig. 2 and 4, in the embodiment of the present application, the mirror current source is implemented as a transformer.

Fig. 5 shows a schematic flow chart of another slave addressing method based on the LIN bus system according to an exemplary embodiment of the present application, where the method is applied to the slave as shown in fig. 4, and the method includes:

Step 501, a conversion relation table is pre-stored in the ALU.

In the embodiment of the application, the conversion relation table is used for indicating the corresponding relation between the initial address indication signal and the target address indication signal. In one example, the conversion relation table is shown in fig. 6, where TYP corresponds to the target address indication signal, and there is a correspondence between TYP and the slave address, add_data is the initial address indication signal.

Step 502, in response to the absence of the target address indication signal in the address memory, controlling the first switch to be disconnected from the second switch.

In the embodiment of the application, the condition that the address memory exists in the slave machine is corresponding to the condition that whether the target address indicating signal exists in the slave machine needs to be determined, and if the target address indicating signal exists in the slave machine, the flow is jumped out.

In response to the LIN communication entering a Break frame, the first voltage drop data acquired by the ADC sense amplifier is read 503.

This process corresponds to the process shown in step 302 and will not be described in detail herein.

Step 504 controls the second switch to close and reads the second voltage drop data obtained by the amplifier through the ADC.

This process corresponds to the process shown in step 303 and will not be described in detail here.

Step 505, the difference value between the first voltage drop data and the second voltage drop data is input into a divider, and an initial address indication signal corresponding to the slave is output.

This process corresponds to the process shown in step 304 and will not be described in detail here.

In step 506, a target address indication signal is determined by the ALU based on the initial address indication signal.

In the embodiment of the application, namely through the conversion relation table, the target address indication signal is determined based on the initial address indication signal.

In step 507, the target address indication signal is acquired and stored by the address memory.

In summary, in the system and method provided in the embodiments of the present application, in a master-slave architecture based on the LIN bus, by performing an amplifier, an analog-to-digital converter, a divider, and an ALU in a slave, based on the reading of the second resistance voltage drop in different states, the voltage signal is converted into a target address indication signal indicating the address allocated in the communication process. In the case of an accurate measurement, the addressing of the LIN bus slave addresses can be done in the course of one LIN poll.

The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the present application.

Claims

1. A LIN bus system, wherein the local interconnect network LIN bus system comprises a master, a bus, and at least two slaves;

The host computer is connected with the slave computer through the bus, and the host computer is connected with the slave computer into a power supply;

the slave comprises a slave power supply end, a first switch, a second switch, a first resistor, a mirror current source, a second resistor, an amplifier, an analog-to-digital converter ADC, a divider and an arithmetic logic unit ALU;

The second resistor is connected in series with the bus;

The ADC is connected with the amplifier and is used for reading amplified voltage drop data;

the ALU is connected with the divider and used for determining a target address indication signal corresponding to the slave machine based on the address indication signal, and the target address indication signal is used for indicating an addressing result of the slave machine.

2. The LIN bus system of claim 1, wherein the slave further comprises a first diode and a second diode;

The first resistor is connected to the bus through the first diode;

the second resistor is connected to the bus through the second diode;

The first diode and the second diode are used for limiting current flow.

3. The LIN bus system of claim 1, wherein the slave further comprises a third diode and a third switch;

The third diode is used for preventing reverse connection, and the third switch is used for realizing the communication function of the slave machine.

4. The LIN bus system of claim 1, wherein the divider has a second input;

the second input of the divider is connected to a reference voltage source.

5. The LIN bus system of claim 1, wherein the slave further comprises an address memory;

The address memory is connected with the ALU;

the address memory is used for storing the slave address signals.

6. The LIN bus system of claim 1, wherein the mirrored current source is implemented as a transformer.

7. A method of slave addressing based on a LIN bus system, characterized in that the method is applied to a slave within a LIN bus system as claimed in any one of claims 1 to 6, the method comprising:

controlling the first switch and the second switch to be turned off;

and determining a target address indication signal by the ALU based on the initial address indication signal, wherein the target address indication signal is used for indicating the addressing result of the slave.

8. The LIN bus system-based slave addressing method of claim 7, wherein the slave further comprises an address memory;

The address memory is connected with the ALU;

after the determination of the target address indication signal by the ALU based on the initial address indication signal, the method comprises:

and acquiring and storing the target address indication signal through the address memory.

9. The LIN bus system-based slave addressing method of claim 8, wherein controlling the first switch and the second switch to open comprises:

And controlling the first switch to be disconnected from the second switch in response to the absence of a target address indication signal in the address memory.

10. The LIN bus system-based slave addressing method of claim 7, wherein the determining, by the ALU, a target address indication signal based on the initial address indication signal, comprises:

and determining the target address indication signal based on the initial address indication signal through the conversion relation table.