CN118363257B - Mask plate and correction method thereof - Google Patents
Mask plate and correction method thereof Download PDFInfo
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- CN118363257B CN118363257B CN202410797839.6A CN202410797839A CN118363257B CN 118363257 B CN118363257 B CN 118363257B CN 202410797839 A CN202410797839 A CN 202410797839A CN 118363257 B CN118363257 B CN 118363257B
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
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Abstract
The application discloses a mask plate and a correction method thereof. The mask is formed with a plurality of wiring patterns and a plurality of connection hole patterns therein. The correction method comprises the following steps: obtaining an original pattern of the mask; modifying the position and/or shape of a first connection hole pattern of the plurality of connection hole patterns in the original pattern of the mask, thereby generating a modified pattern of the mask, wherein the distance between the first connection hole pattern and an adjacent wiring pattern of the plurality of wiring patterns in the original pattern of the mask is smaller than a threshold value, and the modification is used for increasing the distance between the first connection hole pattern and the adjacent wiring pattern of the plurality of wiring patterns. According to the correction method of the mask, the distance between the first connecting hole pattern and the adjacent wiring pattern is increased on the basis of the original pattern, so that a process window is enlarged, and the yield and the electrical performance of the semiconductor device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a mask plate and a correction method thereof.
Background
In semiconductor manufacturing processes, both photolithography and etching are critical steps for patterning. The mask pattern is transferred into the resist layer by photolithography to form a mask pattern, which is then transferred into a silicon wafer by ion implantation or etching to form the structure of the semiconductor device.
The semiconductor device is, for example, a CMOS (Complementary Metal Oxide Semiconductor ) device. In a process for fabricating a CMOS device, a "damascene process" (DAMASCENE PROCESS) is used to form a connection via (via) to an active region, including forming a connection hole in an interlayer dielectric layer of a semiconductor device, and filling the connection hole with a conductive material to form a connection via for connecting a wiring layer and the active region.
However, due to the process deviation in the above-described patterning step, there may be an alignment deviation or overetching of the connection hole formed in the semiconductor device to deviate from a predetermined position, the connection hole not only contacting the desired wiring but also bridging with the adjacent wiring, eventually leading to failure of the semiconductor device. As the size of semiconductor devices has been reduced, bridging of connection holes with adjacent wirings has become an important cause of reduction in yield of semiconductor devices.
Disclosure of Invention
In view of the above, it is an object of the present application to provide a reticle and a correction method thereof, which modify an original pattern of the reticle to expand a process window, thereby improving yield and electrical performance of a semiconductor device.
According to an aspect of the present invention, there is provided a correction method of a mask having a plurality of wiring patterns and a plurality of connection hole patterns formed therein, the correction method comprising: obtaining an original pattern of the mask; modifying the position and/or shape of a first connection hole pattern of the plurality of connection hole patterns in the original pattern of the mask, thereby generating a modified pattern of the mask, wherein the distance between the first connection hole pattern and an adjacent wiring pattern of the plurality of wiring patterns in the original pattern of the mask is smaller than a threshold value, and the modification is used for increasing the distance between the first connection hole pattern and the adjacent wiring pattern of the plurality of wiring patterns.
Optionally, the modified distance is greater than an overetch process error of the plurality of connection holes.
Optionally, the modifying includes: identifying, in the original pattern, a first wiring pattern to which the plurality of connection hole patterns are desirably connected and a second wiring pattern adjacent to the plurality of connection hole patterns, the plurality of connection hole patterns being arranged between a first side of the first wiring pattern away from the second wiring pattern and a second side of the second wiring pattern close to the first wiring pattern; obtaining a first distance between the first connection hole pattern and a first side of the first wiring pattern and a second distance between the first connection hole pattern and a second side of the second wiring pattern; the second distance is increased if the first distance and the second distance meet design rules.
Optionally, the plurality of connection hole patterns are arranged laterally between a first side of the first wiring pattern and a second side of the second wiring pattern, the first connection hole pattern being nearest to the second wiring pattern, and the first connection hole pattern being moved toward the first side to increase the second distance.
Optionally, the plurality of connection hole patterns are longitudinally arranged between a first side of the first wiring pattern and a second side of the second wiring pattern, the first connection hole pattern being nearest to the second wiring pattern, and a lateral dimension of the first connection hole pattern is reduced to increase the second distance.
Optionally, the longitudinal dimension of the first connection hole pattern is increased while the lateral dimension of the first connection hole pattern is reduced to maintain the contact area of the first connection hole pattern with the first wiring pattern.
Optionally, the mask is used for forming a wiring layer of the semiconductor device and a plurality of connection holes, and the connection holes penetrate through an interlayer dielectric layer of the semiconductor device to connect the wiring layer to an active region of the semiconductor device.
Optionally, the lateral dimensions of the plurality of connection holes along the thickness direction of the interlayer dielectric layer are gradually reduced, a second contact area between the plurality of connection holes and the active region is smaller than a first contact area between the plurality of connection holes and the wiring layer, and the modification is at least used for ensuring that the second contact area is larger than a predetermined area.
According to another aspect of the present invention, there is provided a reticle in which a plurality of wiring patterns and a plurality of connection hole patterns, which are corrected by the above-described reticle correction method, are formed.
Optionally, the plurality of wiring patterns and the plurality of connection hole patterns are a light shielding region and a light transmitting region of the reticle, respectively, or the plurality of wiring patterns and the plurality of connection hole patterns are a light transmitting region and a light shielding region of the reticle, respectively.
The unexpected technical effects of the application are:
According to the correction method of the mask plate, the positions and/or shapes of the plurality of connecting hole patterns are corrected in the original pattern of the mask plate to generate the corrected pattern of the mask plate, and the position and/or shape change of the first connecting hole pattern in the plurality of connecting hole patterns can increase the distance between the first connecting hole pattern and the adjacent wiring pattern, so that a process window can be enlarged. Even if there is a process deviation in the patterning step, for example, there is an alignment deviation or overetching of the connection hole formed in the semiconductor device to deviate from a predetermined position, the connection hole of the semiconductor device does not bridge with the adjacent wiring due to the enlargement of the process window, and thus the yield of the semiconductor device can be improved.
Further, the correction method of the mask plate selects different correction strategies according to the arrangement direction of the plurality of connecting hole patterns.
In a case where the plurality of connection hole patterns are arranged laterally with respect to the side edges of the adjacent wiring patterns, the nearest neighboring first connection hole pattern is moved in a direction away from the adjacent wiring patterns, thereby changing the position of the first connection hole pattern. The correction strategy may increase the distance between the first connection hole pattern and the adjacent wiring pattern using an uneven distribution of the plurality of connection hole patterns. On the one hand, the distance between the first connection hole pattern and the adjacent wiring pattern may be greater than the overetching process error, and on the other hand, the alignment between the first connection hole pattern and the wiring pattern desired to be connected is advantageous to maintain the contact area, so that the process window may be enlarged, and thus the yield of the semiconductor device may be improved and the contact resistance may be maintained stable.
In the case where the plurality of connection hole patterns are longitudinally arranged with respect to the side edges of the adjacent wiring patterns, the lateral dimension of the first connection hole pattern is reduced, thereby changing the shape of the first connection hole pattern. The correction strategy uses a shape change of the first connection hole pattern in the reticle to increase a distance between the first connection hole pattern and an adjacent wiring pattern in the semiconductor device. On the one hand, the distance between the first connecting hole pattern and the adjacent wiring pattern can be larger than the overetching process error, on the other hand, the distance between the first connecting hole pattern and one side of the wiring pattern expected to be connected is still kept unchanged, so that the contact area is maintained, the process window can be enlarged, and the yield of the semiconductor device can be improved.
Further, in the correction method of the mask, not only is the lateral dimension of the first connection hole pattern reduced, but also the longitudinal dimension of the first connection hole pattern is increased under the condition that the shape of the first connection hole is corrected, so that the contact area between the first connection hole pattern and the wiring pattern which is expected to be connected is maintained, and the contact resistance is kept stable.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1 shows a schematic cross-sectional view of a semiconductor device;
Fig. 2 is a schematic cross-sectional view showing a patterning step of forming a connection hole in a manufacturing process of a semiconductor device;
fig. 3 is a schematic cross-sectional view showing a patterning step of forming a wiring layer in a manufacturing process of a semiconductor device;
Fig. 4a, 4b and 4c are schematic cross-sectional views showing different cases of connection of a connection via and a wiring in a semiconductor device, respectively;
FIG. 5 illustrates a flow chart of a reticle correction method according to an embodiment of the invention;
FIGS. 6a and 6b are schematic plan views showing an original pattern and a corrected pattern, respectively, in a reticle correction method according to a first embodiment of the present invention;
fig. 7a and 7b are schematic plan views showing an original pattern and a corrected pattern, respectively, in a reticle correction method according to a second embodiment of the present invention.
Reference numerals illustrate: a 100-semiconductor device; a 101-semiconductor layer; 102-shallow trench structure; 103-source region; 104-a drain region; 105-gate dielectric layer; 106-a gate conductor; 108-an interlayer dielectric layer; 111-connection channels; 112-connecting channels; 121-wiring; 122-wiring; 131-connecting holes; 132-connecting holes; 10-mask plate; 11-a light-shielding region; 12-a light-transmitting region; 13-a light-transmitting region; 20-mask plate; 21-a light-transmitting region; 22-shading areas; 23-shading areas; 201-original pattern; 211-wiring patterns; 212-wiring patterns; 21 a-a pattern of connecting holes; 21 b-a pattern of connecting holes; 202-correcting the pattern; 22 a-a pattern of connecting holes; 22 b-a pattern of connecting holes; 301-original pattern; 311-wiring patterns; 312-wiring patterns; 31 a-a pattern of connecting holes; 31 b-a pattern of connecting holes; 302-correcting the pattern; 32 a-a pattern of connecting holes; 32 b-a pattern of connecting holes.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
The application may be embodied in various forms, some examples of which are described below.
Fig. 1 shows a schematic cross-sectional view of a semiconductor device. The semiconductor device 100 is, for example, a MOSFET (i.e., a metal oxide semiconductor field effect transistor), but is not limited thereto. In a preferred embodiment, the semiconductor device 100 is an N-type MOSFET, for example. For clarity, the interconnect structure of the semiconductor device 100 is shown separated from the body structure along the vertical direction in the figures.
As shown in fig. 1, a semiconductor device 100 includes a semiconductor layer 101, and a shallow trench structure 102 in the semiconductor layer 101. The semiconductor layer 101 may be composed of any one selected from a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor layer 101 is P-type doped; for a P-type MOSFET, the semiconductor layer 101 is N-doped. The shallow trench structure 102 extends downward from the surface of the semiconductor layer 101, forming an isolation structure surrounding the active region of the semiconductor device 100 for separating the semiconductor device 100 from adjacent semiconductor devices. The shallow trench structure 102 may be composed of any one selected from silicon oxide, silicon nitride, and silicon oxynitride.
Further, the semiconductor device 100 includes a source region 103 and a drain region 104 in the semiconductor layer 101, a gate stack over the semiconductor layer 101. The source region 103 and the drain region 104 are doped regions in the semiconductor layer 101. For example, for an N-type MOSFET, source region 103 and drain region 104 are N-type doped; for a P-type MOSFET, the source 103 and drain 104 regions are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 105 and a gate conductor 106, wherein the gate dielectric layer 105 is sandwiched between the semiconductor layer 101 and the gate conductor 106. The gate dielectric layer 105 is composed of, for example, silicon oxide, and the gate conductor 106 is composed of, for example, doped polysilicon.
Further, the semiconductor device 100 includes an interlayer dielectric layer 108 over the gate stack and the source and drain regions 103 and 104, and an interconnect structure connected to the gate stack and the source and drain regions 103 and 104. The interlayer dielectric layer 108 is composed of, for example, silicon oxide for isolation between the active region and the wiring layer of the semiconductor device 100. The interconnect structure of semiconductor device 100 includes connection vias 111 and 112 that extend through interlayer dielectric layer 108 and a wiring layer that is located over interlayer dielectric layer 108. For example, the wiring layer includes a wiring 121 connected to the connection via 111, and a wiring 122 connected to the connection via 112. The connection channels 111 and 112, the wirings 121 and 122 may be composed of metal, for example: copper, aluminum, etc.
The manufacturing process of the semiconductor device 100 includes a front-end process and a back-end process, wherein the front-end process includes thin film deposition, ion implantation, and patterning, and is mainly used to form the source region 103, the drain region 104, and the gate stack of the semiconductor device 100; the back-end process includes thin film deposition and patterning, which are mainly used to form the interconnect structure of the semiconductor device 100, including the connection channels 111 and 112, and the wirings 121 and 122 of the semiconductor device 100.
The correction method of the mask plate is applied to the back-end process. In the back-end process, the connection channels 111 and 112 are formed using a "damascene process" (DAMASCENE PROCESS), including forming connection holes 131 and 132 penetrating the interlayer dielectric layer 108 in the interlayer dielectric layer 108 of the semiconductor device, and filling metal materials in the connection holes 131 and 132 to form the connection channels 111 and 112. In forming the wirings 121 and 122, a metal layer is formed over the interlayer dielectric layer 108 of the semiconductor device, and the metal layer is etched into a plurality of wirings. The relevant steps of the back-end process of the semiconductor device 100 will be described in detail below.
Fig. 2 shows a schematic cross-sectional view of a patterning step for forming a connection hole in a manufacturing process of a semiconductor device. In the semiconductor process, the photolithography step and the etching step for patterning are independent of each other, however, successive steps of photolithography and etching are combined together in fig. 2 to clearly illustrate the principle of the connection hole patterning.
An interlayer dielectric layer 108 of the semiconductor device 100 covers the source region 103, the drain region 104, and the gate stack. A resist layer PR1 is formed on the interlayer dielectric layer 108, and a reticle 10 is disposed above the resist layer PR 1.
The positive resist and the negative resist can be classified according to the reaction manner of the resist layer PR 1. The exposed portions of the positive resist are removed upon development to form open areas, and the exposed portions of the negative resist remain upon development to form blocked areas. It will be appreciated that in the case of using a negative resist, the pattern of the connection holes of the reticle is a complementary pattern using a positive resist.
In this embodiment, a positive resist is described as an example. The reticle 10 includes a light shielding region 11 and light transmitting regions 12 and 13. In the photolithography step, the resist layer PR1 is exposed via the mask 10, and the exposed portion of the resist layer PR1 is removed at the time of development, thereby forming an opening region in the resist layer PR1 corresponding to the light transmitting regions 12 and 13 of the mask 10. In the etching step, the resist layer PR1 is used as a mask, and exposed portions of the interlayer dielectric layer 108 are removed through the opening regions of the resist layer PR1 to form connection holes 131 and 132. Due to the selectivity of the etchant, etching stops at the surfaces of the source region 103, the drain region 104, and the gate conductor 106 of the semiconductor device 100, thereby forming a connection hole pattern corresponding to the light-transmitting regions 12 and 13 of the reticle 10.
Fig. 3 shows a schematic cross-sectional view of a patterning step for forming a wiring layer in a manufacturing process of a semiconductor device. Similar to fig. 2, successive steps of photolithography and etching are combined together in fig. 3 to clearly illustrate the principle of wiring patterning.
The wiring layer of semiconductor device 100 overlies inter-level dielectric layer 108. A resist layer PR2 is formed on the wiring layer, and a reticle 20 is disposed above the resist layer PR 2.
In this embodiment, a positive resist is described as an example. Reticle 20 includes a light-transmitting region 21 and light-shielding regions 22 and 23. In the photolithography step, the resist layer PR2 is exposed via the reticle 20, and the exposed portion of the resist layer PR2 is removed at the time of development, thereby forming an opening region corresponding to the light transmitting region 21 of the reticle 20 in the resist layer PR 2. In the etching step, the resist layer PR2 is used as a mask, and exposed portions of the wiring layer are removed via the opening regions of the resist layer PR2 to form the wirings 121 and 122. Due to the selectivity of the etchant, etching is stopped at the surface of the interlayer dielectric layer 108, thereby forming a wiring pattern corresponding to the light shielding regions 22 and 23 of the reticle 20.
Fig. 4a, 4b and 4c show schematic cross-sectional views of different cases of connection of a connection via and a wiring in a semiconductor device, respectively.
Referring to fig. 4a, the connection channels 111 and 112 of the semiconductor device 100 are connected to the wirings 121 and 122, respectively, and the contact area is equal to the top surface area of the connection channels 111 and 112, the connection channels 111 are spaced apart from the adjacent wirings 122, and the semiconductor device 100 can operate normally.
Referring to fig. 4b, the connection channels 111 and 112 of the semiconductor device 100 are connected to the wirings 121 and 122, respectively, and the connection channel 111 and the adjacent wiring 122 are spaced apart from each other. However, there is a misalignment of the connection channel 111 of the semiconductor device 100 with respect to the wiring 121 desired to be connected, and thus, the contact area of the connection channel 111 with the wiring 121 is smaller than the top surface area of the connection channel 111, the source contact resistance of the semiconductor device 100 will increase, resulting in deterioration of the electrical performance of the semiconductor device 100.
Referring to fig. 4c, the connection channel 111 of the semiconductor device 100 is connected not only to the wiring 121 desired to be connected but also to bridge the adjacent wiring 122; the connection channel 112 is connected not only to the wiring 122 to be connected but also bridges with the adjacent wiring 121. Thus, the gate conductor 106 of the semiconductor device 100 is shorted to the source region 103, which results in failure of the semiconductor device 100.
The inventors have noted the original pattern created using existing reticle design tools, where no correction was made to the overetch of the connection holes. Overetching that occurs in the connection hole patterning step is a major cause of failure of the semiconductor device 100.
In the connection hole patterning step described above in connection with fig. 2, since the reaction of the etchant with the interlayer dielectric layer 108 starts from the surface, the etching time passed at the surface of the interlayer dielectric layer 108 is longer than the etching time passed at the bottom surface of the interlayer dielectric layer 108 during etching, and thus the cross-sectional shapes of the connection holes 131 and 132 formed by etching are wider at the bottom. With continued reference to fig. 4c, the cross-sectional shapes of the connection channels 111 and 112 along the thickness direction of the interlayer dielectric layer 108 are in a shape of being wide at the top and narrow at the bottom, and the cross-sectional shapes of the connection channels 111 and 112 are identical to the cross-sectional shapes of the connection holes 131 and 132 shown in fig. 2. Therefore, if overetching is performed in the patterning step of the connection holes, the top surfaces of the connection holes 131 and 132 are too wide to overlap with the adjacent wirings. The connection holes 131 and 132 are filled with a metal material, and then chemical mechanical polishing is performed to remove portions of the metal material located outside the connection holes 131 and 132, forming the connection channels 111 and 112. At this time, the connection channels 111 and 112 bridge with the adjacent wirings to cause device failure.
Accordingly, the present inventors have proposed a correction method of a reticle in which a plurality of wiring patterns and a plurality of connection hole patterns are formed, and a flowchart of the correction method is shown in fig. 5. Referring to fig. 5, the correction method includes:
Step S110, obtaining an original pattern of the mask plate;
And step S120, modifying the position and/or shape of a first connecting hole pattern in the plurality of connecting hole patterns in the original pattern of the mask so as to generate a modified pattern of the mask, wherein the distance between the first connecting hole pattern in the original pattern of the mask and an adjacent wiring pattern in the plurality of wiring patterns is smaller than a threshold value, and the modification is used for increasing the distance between the first connecting hole pattern and the adjacent wiring pattern in the plurality of wiring patterns.
The threshold value is determined based on practical process errors (such as alignment deviation and overetching process errors), and if the distance between a connection hole pattern in the original pattern of the reticle and an adjacent wiring pattern in the plurality of wiring patterns is not smaller than the threshold value, even if a practical process error exists, the connection via formed based on the connection hole pattern will not bridge a wiring formed based on the adjacent wiring pattern.
In particular, the modification of the position and/or shape of the first pattern of connection holes may be implemented by means of a brin operation.
Optionally, the distance after modification is greater than an overetching process error of the plurality of connection holes, so that the modification can avoid bridging of the connection channels and the adjacent wirings caused by overetching. In some examples, if there is a misalignment of the connection channel relative to the desired connection wire in the opposite direction to fig. 4b, the increased distance may be further increased after alignment is achieved until the connection channel is formed to align with the desired connection wire and not bridge with adjacent wires in consideration of overetching process errors.
The above-described reticle may be used to form a wiring layer and a plurality of connection holes of a semiconductor device, and in particular, the connection hole pattern in the reticle forms a connection hole of the semiconductor device, and the wiring pattern in the reticle forms a wiring in the wiring layer of the semiconductor device. The plurality of connection holes penetrate through the interlayer dielectric layer of the semiconductor device to connect the wiring layer to the active region of the semiconductor device, specifically, the connection holes and the wirings in the wiring layer have a corresponding relationship based on the connection function herein, and accordingly the connection hole pattern and the wiring pattern also have a corresponding relationship based on the connection function herein, and the connection hole pattern having a corresponding relationship with the wiring pattern is referred to as a desired connection to the wiring pattern in the present application.
In view of the over etching, the lateral dimensions of the plurality of connection holes along the thickness direction of the interlayer dielectric layer are gradually reduced, the second contact area between the plurality of connection holes and the active region is smaller than the first contact area between the plurality of connection holes and the wiring layer, and the modification may be used at least to ensure that the second contact area is larger than a predetermined area, so that the contact resistance between the first connection hole and the active region is not too large to cause the semiconductor device to be operated.
Further, the modifying includes: identifying, in the original pattern, a first wiring pattern to which the plurality of connection hole patterns are desirably connected and a second wiring pattern adjacent to the plurality of connection hole patterns, wherein the plurality of connection hole patterns are arranged between a first side of the first wiring pattern away from the second wiring pattern and a second side of the second wiring pattern close to the first wiring pattern; obtaining a first distance between the first connection hole pattern and a first side of the first wiring pattern and a second distance between the first connection hole pattern and a second side of the second wiring pattern; the second distance is increased in the event that the first distance and the second distance meet the design rules.
The connection hole patterns and the wiring patterns on the mask are arranged in different areas, the plurality of connection hole patterns are expected to be connected with the first wiring pattern, and the second wiring pattern adjacent to the plurality of connection hole patterns refers to the wiring pattern adjacent to the first wiring pattern in the area where the wiring patterns on the mask are located, so that the first wiring pattern has the first side far away from the second wiring pattern, and the second wiring pattern also has the second side close to the first wiring pattern.
Specifically, the connection hole patterns and the wiring patterns have a correspondence relationship based on the connection function as described above, and thus a first wiring pattern to which each of the plurality of connection hole patterns is desired to be connected is identified based on the connection function, and a second wiring pattern adjacent to each of the plurality of connection hole patterns is identified based on a positional relationship between the plurality of wiring patterns in the original pattern of the reticle and the positional relationship of the plurality of connection hole patterns.
The design rule is that a first distance is set to be not less than 0 in view of the expected connection between the first connection hole pattern and the first wiring pattern, and the first distance accords with the design rule to ensure the correctness of the original pattern in design; in addition, the design rule sets a second distance smaller than the corresponding threshold value, wherein the second distance accords with the design rule to indicate that the distance between the first connecting hole pattern and the second wiring pattern is too close, and the connecting channel formed based on the first connecting hole pattern can bridge the wiring formed based on the second wiring pattern.
The correction method of the mask plate selects different correction strategies according to the arrangement direction of the plurality of connecting hole patterns. In practice, the arrangement direction of the plurality of connection hole patterns may be determined according to the first distance, where if the first distance is greater than the preset value, the first distance indicates that other connection hole patterns in the plurality of connection hole patterns exist between the first connection hole pattern and the first wiring pattern, so that the plurality of connection hole patterns are determined to be transversely arranged; if the first distance is not greater than the preset value, the first distance indicates that no other connecting hole patterns exist between the first connecting hole pattern and the first wiring pattern, and therefore the plurality of connecting hole patterns are determined to be longitudinally arranged.
Fig. 6a and 6b are schematic plan views showing an original pattern and a corrected pattern, respectively, in a reticle correction method according to a first embodiment of the present invention.
The original pattern 201 of the reticle is generated using existing reticle design tools. The original pattern 201 of the reticle includes wiring patterns 211 and 212 and connection hole patterns 21a and 21b. The connection hole patterns 21a and 21b are connected to the wiring pattern 211 and are adjacent to the wiring pattern 212. The connection hole patterns 21a and 21B are arranged between the first side a 1A2 of the wiring pattern 211 and the second side B 1B2 of the wiring pattern 212. In the present embodiment, the connection hole patterns 21a and 21B are longitudinally aligned with respect to the second side B 1B2 of the wiring pattern 212 at a distance X1 from the first side a 1A2 of the wiring pattern 211 and at a distance X2 from the second side B 1B2 of the wiring pattern 212.
The reticle correction method according to the first embodiment of the invention obtains a corrected pattern 202 of the reticle. The corrected pattern 202 of the reticle includes wiring patterns 211 and 212 and connection hole patterns 22a and 22b. The connection hole patterns 22a and 22b are connected to the wiring pattern 211 and are adjacent to the wiring pattern 212. The connection hole patterns 22a and 22B are arranged between the first side a 1A2 of the wiring pattern 211 and the second side B 1B2 of the wiring pattern 212. In the present embodiment, the connection hole patterns 22a and 22B are longitudinally aligned with respect to the second side B 1B2 of the wiring pattern 212 at a distance X1 from the first side a 1A2 of the wiring pattern 211 and at a distance X3 from the second side B 1B2 of the wiring pattern 212.
The corrected pattern 202 of the reticle modifies the shape of the connection hole patterns 22a and 22B as compared to the original pattern 201 of the reticle, and thus, the lateral dimensions of the connection hole patterns 22a and 22B are reduced such that the distance of the connection hole patterns 22a and 22B from the second side B 1B2 of the wiring pattern 212 increases from X2 to X3 in the original pattern 201; also, the longitudinal dimensions of the connection hole patterns 22a and 22b are increased to maintain the contact areas of the connection hole patterns 22a and 22b and the wiring patterns 211.
In the example shown in fig. 6a and 6b, the wiring pattern 212 is on the left side of the wiring pattern 211, and thus the lateral size reduction of the connection hole patterns 22a and 22b is achieved by cutting down the left side portion. In other examples, if the wiring pattern 212 is on the right side of the wiring pattern 211, the lateral size reduction of the connection hole patterns 22a and 22b is achieved by cutting down the right side portion. It should be understood that if there is one adjacent wiring pattern on both left and right sides of the wiring pattern 211 in some examples, in the case where the second distance between each of the connection hole patterns 22a and 22b and the adjacent wiring patterns on both sides is increased, the lateral dimension of the connection hole patterns 22a and 22b is reduced by simultaneously cutting down the left and right side portions, in which case the longitudinal dimension of the connection hole patterns 22a and 22b is increased more greatly to maintain the contact area of the connection hole patterns 22a and 22b with the wiring pattern 211.
The correction strategy uses the shape change of the connection hole patterns 22a and 22b in the reticle to increase the distance between the connection hole patterns 22a and 22b and the adjacent wiring pattern 212 in the semiconductor device. In one aspect, the distance between the connection hole patterns 22a and 22b and the adjacent wiring pattern 212 may be greater than the overetch process error; on the other hand, the distance between the connection hole patterns 22a and 22b and one side of the wiring pattern 211 to be connected is maintained, which is advantageous in maintaining the contact area, so that the process window can be enlarged, and thus the yield of the semiconductor device can be improved.
Fig. 7a and 7b are schematic plan views showing an original pattern and a corrected pattern, respectively, in a reticle correction method according to a second embodiment of the present invention.
The original pattern 301 of the reticle is generated using existing reticle design tools. The original pattern 301 of the reticle includes wiring patterns 311 and 312 and connection hole patterns 31a and 31b. The connection hole patterns 31a and 31b are connected to the wiring pattern 311 and are adjacent to the wiring pattern 312. The connection hole patterns 31a and 31b are arranged between the first side C 1C2 of the wiring pattern 311 and the second side D 1D2 of the wiring pattern 312. In the present embodiment, the connection hole patterns 31a and 31b are arranged laterally with respect to the second side D 1D2 of the wiring pattern 312, the connection hole pattern 31a of the connection hole patterns 31a and 31b is nearest to the wiring pattern 312, the connection hole pattern 31a is spaced apart from the first side C 1C2 of the wiring pattern 311 by Y1, and the second side D 1D2 of the wiring pattern 312 by Y2.
The reticle correction method according to the second embodiment of the invention obtains a corrected pattern 302 of the reticle. The corrected pattern 302 of the reticle includes wiring patterns 311 and 312 and connection hole patterns 32a and 32b. The connection hole patterns 32a and 32b are connected to the wiring pattern 311 and are adjacent to the wiring pattern 312. The connection hole patterns 32a and 32b are arranged between the first side C 1C2 of the wiring pattern 311 and the second side D 1D2 of the wiring pattern 312. In the present embodiment, the connection hole patterns 32a and 32b are arranged laterally with respect to the second side D 1D2 of the wiring pattern 312, the connection hole pattern 32a of the connection hole patterns 32a and 32b is nearest to the wiring pattern 312, the connection hole pattern 32a is spaced apart from the first side C 1C2 of the wiring pattern 311 by Y3, and is spaced apart from the second side D 1D2 of the wiring pattern 312 by Y4.
The corrected pattern 302 of the reticle maintains the shapes of the connection hole patterns 32a and 32b unchanged compared to the original pattern 301 of the reticle, and only the position of the connection hole pattern 32a is moved, i.e., the connection hole pattern 32a is moved in a direction away from the wiring pattern 312, so that the distance of the connection hole pattern 32a from the first side C 1C2 of the wiring pattern 311 decreases from Y1 to Y3 in the original pattern 301 and the distance from the second side D 1D2 of the wiring pattern 312 increases from Y2 to Y4 in the original pattern 301. The shapes of the connection hole patterns 32a and 32b in this embodiment are unchanged to maintain the contact areas of the connection hole patterns 32a and 32b with the wiring patterns 311.
In the example shown in fig. 7a and 7b, the position of the connection hole pattern 32a is shifted to ensure no misalignment with the wiring pattern 311. The wiring pattern 312 is on the left side of the wiring pattern 311 in this example, and thus only the position of the connection hole pattern 32a is shifted. In other examples, if the wiring pattern 312 is on the right side of the wiring pattern 311, only the position of the connection hole pattern 32b is shifted. It should be understood that if one adjacent wiring pattern exists on both the left and right sides of the wiring pattern 311 in some examples, the positions of the connection hole patterns 32a and the positions of the connection hole patterns 32b are moved in the case where the second distance between the connection hole patterns 32a and the left adjacent wiring pattern increases and the second distance between the connection hole patterns 32b and the right adjacent wiring pattern increases.
The correction strategy may utilize the uneven distribution of the connection hole patterns 32a and 32b to increase the distance between the connection hole pattern 32a and the adjacent wiring pattern 312. On the one hand, the distance between the connection hole pattern 32a and the adjacent wiring pattern 312 may be greater than the overetching process error, and on the other hand, the alignment between the connection hole pattern 32a and the wiring pattern 311 desired to be connected is advantageous to maintain the contact area, so that the process window may be enlarged, and thus the yield of the semiconductor device may be improved and the contact resistance may be maintained stable.
Corresponding to the method for correcting the mask provided by the embodiment, the embodiment of the application also provides a mask, wherein a plurality of wiring patterns and a plurality of connecting hole patterns are formed in the mask, and the plurality of connecting hole patterns are corrected by the method for correcting the mask. The connection channel formed based on the corrected pattern can effectively avoid bridging between the connection channel and the adjacent wiring, and the yield and the electrical performance of the semiconductor device are improved. The corrected patterns shown in fig. 6b and fig. 7b are exemplary patterns of the mask plate in the embodiment of the present application. It should be appreciated that the patterns shown in fig. 6b and 7b are not intended to limit the reticle pattern in embodiments of the application.
Further, in view of the fact that the resist used in the etching process may be a positive resist or a negative resist, the plurality of wiring patterns and the plurality of connection hole patterns are a light-shielding region and a light-transmitting region of the reticle, respectively, or the plurality of wiring patterns and the plurality of connection hole patterns are a light-transmitting region and a light-shielding region of the reticle, respectively. In connection with fig. 2 and 3, in the case where the resist is a positive resist, the plurality of wiring patterns are light shielding regions of the reticle, and the connection hole pattern is a light transmitting region of the reticle. In contrast, in the case where the resist is a negative resist, the plurality of wiring patterns are light-transmitting regions of the reticle, and the connection hole pattern is a light-shielding region of the reticle. Therefore, the mask provided by the embodiment can be suitable for the etching process using the positive resist and the etching process using the negative resist by reasonably arranging the shading area and the backlight area.
It should be noted that, the exemplary patterns of the mask of the embodiment of the present application shown in fig. 6b and fig. 7b are for convenience of understanding that the connecting hole patterns and the wiring patterns are displayed in an overlapping manner, in the mask formed in the embodiment of the present application, the connecting hole patterns are distributed in a first area, the wiring patterns are distributed in a second area, and the first area and the second area are two different areas of the mask, and the relative positions between the connecting hole patterns in the first area and the relative positions between the wiring patterns in the second area are fixed. It should be understood that the connection hole patterns are aligned with predetermined areas of the wiring patterns to which they are desired to be connected in the rules of use of the reticle configuration, and that the overlapping areas of the connection hole patterns and the wiring patterns shown in fig. 6b and 7b, i.e., the predetermined areas corresponding to the wiring patterns described herein.
In addition, the descriptions of the relative positions of the connection hole pattern and the wiring pattern in the embodiments of the present application refer to the relative horizontal positions between the connection hole pattern and the wiring pattern in the case that the connection hole pattern is aligned to a predetermined area of the wiring pattern to which it is desired to connect according to the usage rule of the reticle. For example, the distance between the first connection hole pattern and the adjacent wiring pattern of the plurality of wiring patterns in the original pattern of the reticle mentioned in step S120 refers to a horizontal distance between the first connection hole pattern and the adjacent wiring pattern of the plurality of wiring patterns in the case where the first connection hole pattern is aligned to a predetermined area of the wiring pattern to which it is desired to connect according to the rule of use of the reticle, and here the adjacent wiring pattern of the plurality of wiring patterns may be understood as an adjacent wiring pattern of the wiring pattern to which the first connection hole pattern is desired to connect.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (7)
1. A correction method of a mask in which a plurality of wiring patterns and a plurality of connection hole patterns are formed, the correction method comprising:
obtaining an original pattern of the mask;
Modifying the position and/or shape of a first connecting hole pattern of the plurality of connecting hole patterns in the original pattern of the mask plate, thereby generating a modified pattern of the mask plate;
Wherein a distance between the first connection hole pattern and an adjacent wiring pattern of the plurality of wiring patterns in an original pattern of the reticle is less than a threshold, the modification being for increasing a distance between the first connection hole pattern and an adjacent wiring pattern of the plurality of wiring patterns;
The modification includes: identifying, in the original pattern, a first wiring pattern to which the plurality of connection hole patterns are desirably connected and a second wiring pattern adjacent to the plurality of connection hole patterns, the plurality of connection hole patterns being arranged between a first side of the first wiring pattern away from the second wiring pattern and a second side of the second wiring pattern close to the first wiring pattern; obtaining a first distance between the first connection hole pattern and a first side of the first wiring pattern and a second distance between the first connection hole pattern and a second side of the second wiring pattern; the second distance is increased if the first distance and the second distance meet design rules.
2. The correction method of claim 1, wherein the modified distance is greater than an overetch process error of the plurality of connection holes.
3. The correction method according to claim 1, wherein the plurality of connection hole patterns are arranged laterally between a first side of the first wiring pattern and a second side of the second wiring pattern with a second side of the second wiring pattern being in a longitudinal direction, the first connection hole pattern being nearest to the second wiring pattern, the first connection hole pattern being moved toward the first side to increase the second distance.
4. The correction method according to claim 1, wherein the plurality of connection hole patterns are arranged longitudinally between the first side of the first wiring pattern and the second side of the second wiring pattern with the second side of the second wiring pattern being in a longitudinal direction, the first connection hole pattern being nearest neighbor to the second wiring pattern, and a lateral dimension of the first connection hole pattern is reduced to increase the second distance.
5. The correction method according to claim 4, wherein a longitudinal dimension of the first connection hole pattern is increased while a lateral dimension of the first connection hole pattern is reduced to maintain a contact area of the first connection hole pattern with the first wiring pattern.
6. The correction method of claim 1, wherein the reticle is used to form a wiring layer of a semiconductor device and a plurality of connection holes that extend through an interlayer dielectric layer of the semiconductor device to connect the wiring layer to an active region of the semiconductor device.
7. The correction method according to claim 6, wherein the plurality of connection holes gradually decrease in size in a direction perpendicular to a thickness direction of the interlayer dielectric layer, a second contact area between the plurality of connection holes and the active region is smaller than a first contact area between the plurality of connection holes and the wiring layer, and the modification is at least for ensuring that the second contact area is larger than a predetermined area so that a contact resistance between the first connection hole and the active region is smaller than a contact resistance when the contact area is the predetermined area.
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| CN202410797839.6A CN118363257B (en) | 2024-06-20 | 2024-06-20 | Mask plate and correction method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005062601A (en) * | 2003-08-18 | 2005-03-10 | Matsushita Electric Ind Co Ltd | Photomask pattern verification and correction method |
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| KR102787841B1 (en) * | 2019-10-21 | 2025-03-31 | 삼성전자주식회사 | Semiconductor memory devices |
| US11716838B2 (en) * | 2021-08-11 | 2023-08-01 | Micron Technology, Inc. | Semiconductor device and method for forming the wiring structures avoiding short circuit thereof |
| CN115293097B (en) * | 2022-08-05 | 2024-07-02 | 北京华大九天科技股份有限公司 | Wiring method meeting minimum through hole spacing constraint in integrated circuit layout wiring |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2005062601A (en) * | 2003-08-18 | 2005-03-10 | Matsushita Electric Ind Co Ltd | Photomask pattern verification and correction method |
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