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CN118398618B - Shielded gate power device with low leakage and fast recovery capability - Google Patents

Shielded gate power device with low leakage and fast recovery capability Download PDF

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CN118398618B
CN118398618B CN202410814070.4A CN202410814070A CN118398618B CN 118398618 B CN118398618 B CN 118398618B CN 202410814070 A CN202410814070 A CN 202410814070A CN 118398618 B CN118398618 B CN 118398618B
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electrode body
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CN118398618A (en
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安俊杰
金波
朱琦
陈宗琪
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Wuxi Xichang Microchip Semiconductor Co ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers

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Abstract

本发明涉及一种屏蔽栅功率器件,尤其是一种具有低漏电及快恢复能力的屏蔽栅功率器件。按照本发明提供的技术方案,一种具有低漏电及快恢复能力的屏蔽栅功率器件,所述屏蔽栅功率器件包括:半导体基板,呈第一导电类型;有源区,分布于半导体基板的中心区域,包括若干SGT元胞以及至少一个类肖特基二极管,其中,所述类肖特基二极管为沟槽型类肖特基二极管,所述类肖特基二极管包括位于有源区内的类二极管沟槽;在有源区内,类二极管沟槽的槽深大于任一SGT元胞的元胞沟槽槽深。本发明能有效降低屏蔽栅功率器件的漏电流,增强雪崩能力,提高SGT功率器件工作时的稳定性及可靠性。

The present invention relates to a shielded gate power device, in particular to a shielded gate power device with low leakage and fast recovery capability. According to the technical solution provided by the present invention, a shielded gate power device with low leakage and fast recovery capability, the shielded gate power device comprises: a semiconductor substrate, which is of a first conductive type; an active region, distributed in the central area of the semiconductor substrate, including a number of SGT cells and at least one Schottky-like diode, wherein the Schottky-like diode is a trench-type Schottky-like diode, and the Schottky-like diode includes a diode-like trench located in the active region; in the active region, the trench depth of the diode-like trench is greater than the trench depth of the cell trench of any SGT cell. The present invention can effectively reduce the leakage current of the shielded gate power device, enhance the avalanche capability, and improve the stability and reliability of the SGT power device during operation.

Description

具有低漏电及快恢复能力的屏蔽栅功率器件Shielded gate power device with low leakage and fast recovery capability

技术领域Technical Field

本发明涉及一种屏蔽栅功率器件,尤其是一种具有低漏电及快恢复能力的屏蔽栅功率器件。The invention relates to a shielded gate power device, in particular to a shielded gate power device with low leakage and fast recovery capability.

背景技术Background Art

SGT(Shield Gate Trench,屏蔽栅极沟槽)功率器件是一种新型的功率半导体器件,与传统功率半导体器件相比,具有低导通损耗及低开关损耗的优点。SGT功率器件可包括SGT MOSFET器件以及SGT IGBT(Insulated Gate Bipolar Transistor)器件,其中,SGTMOSFET(Metal-Oxide- Semiconductor Field-Effect Transistor)器件作为开关器件应用广泛,能够起到优秀的功率控制效果。SGT (Shield Gate Trench) power devices are a new type of power semiconductor devices, which have the advantages of low conduction loss and low switching loss compared with traditional power semiconductor devices. SGT power devices can include SGT MOSFET devices and SGT IGBT (Insulated Gate Bipolar Transistor) devices. Among them, SGTMOSFET (Metal-Oxide- Semiconductor Field-Effect Transistor) devices are widely used as switching devices and can achieve excellent power control effects.

现有的SGT功率器件的元胞,一般由屏蔽栅和控制栅两部分组成,SGT功率器件导通时,漏极电流顺着SGT沟槽的纵向侧壁,在体区表面形成反型层沟道。当源极加正偏压时,电子沿反型层沟道,从源区传输到漏区。电子从源区通过沟道后,进入槽栅底部的外延区,然后在整个有源区的宽度内展开。The cell of the existing SGT power device is generally composed of two parts: a shield gate and a control gate. When the SGT power device is turned on, the drain current follows the longitudinal sidewall of the SGT trench to form an inversion layer channel on the surface of the body region. When the source is positively biased, electrons are transmitted from the source region to the drain region along the inversion layer channel. After passing through the channel from the source region, the electrons enter the epitaxial region at the bottom of the trench gate and then expand across the width of the entire active region.

为了提高SGT功率器件的反向恢复效率以及反向恢复能力,目前多在有源区内集成类肖特基二极管(Schottky like diode),但在有源区内集成类肖特基二极管后,会容易引起电场集中,进一步导致漏电大,雪崩能力低,会降低SGT功率器件的可靠性。In order to improve the reverse recovery efficiency and reverse recovery capability of SGT power devices, Schottky-like diodes are currently integrated in the active region. However, after the Schottky-like diodes are integrated in the active region, it is easy to cause electric field concentration, which further leads to large leakage and low avalanche capability, which will reduce the reliability of SGT power devices.

发明内容Summary of the invention

本发明的目的是克服现有技术中存在的不足,提供一种具有低漏电及快恢复能力的屏蔽栅功率器件,其能有效降低屏蔽栅功率器件的漏电流,增强雪崩能力,提高SGT功率器件工作时的稳定性及可靠性。The purpose of the present invention is to overcome the deficiencies in the prior art and provide a shielded gate power device with low leakage and fast recovery capability, which can effectively reduce the leakage current of the shielded gate power device, enhance the avalanche capability, and improve the stability and reliability of the SGT power device during operation.

按照本发明提供的技术方案,一种具有低漏电及快恢复能力的屏蔽栅功率器件,所述屏蔽栅功率器件包括:According to the technical solution provided by the present invention, a shielded gate power device with low leakage and fast recovery capability comprises:

半导体基板,呈第一导电类型;A semiconductor substrate having a first conductivity type;

有源区,分布于半导体基板的中心区域,包括若干SGT元胞以及至少一个类肖特基二极管,其中,The active region is distributed in the central area of the semiconductor substrate and includes a plurality of SGT cells and at least one Schottky-like diode, wherein:

所述类肖特基二极管为沟槽型类肖特基二极管,所述类肖特基二极管包括位于有源区内的类二极管沟槽;The Schottky-like diode is a trench-type Schottky-like diode, and the Schottky-like diode includes a diode-like trench located in an active region;

在有源区内,类二极管沟槽的槽深大于任一SGT元胞的元胞沟槽槽深。In the active region, the trench depth of the diode-like trench is greater than the trench depth of the cell trench of any SGT cell.

对所述类肖特基二极管,包括填充于所述类二极管沟槽内的二极管电极体,其中,The Schottky-like diode comprises a diode electrode body filled in the diode-like trench, wherein:

所述二极管电极体包括槽内第一电极体以及与所述槽内第一电极体对应的槽内第二电极体,且槽内第二电极体邻近所在类二极管沟槽的槽口;The diode electrode body comprises a first electrode body in the groove and a second electrode body in the groove corresponding to the first electrode body in the groove, and the second electrode body in the groove is adjacent to the groove opening of the diode groove;

槽内第一电极体包括进入槽内第二电极体内的槽内第一电极体第一区域以及位于槽内第二电极体下方的槽内第一电极体第二区域,其中,The first electrode body in the groove includes a first region of the first electrode body in the groove that enters into the second electrode body in the groove and a second region of the first electrode body in the groove that is located below the second electrode body in the groove, wherein:

槽内第一电极体第一区域通过电极体隔离介质层与槽内第二电极体间隔,槽内第一电极体第二区域利用槽内场氧化层与所在类二极管沟槽的底壁以及对应的侧壁绝缘隔离;The first region of the first electrode body in the groove is separated from the second electrode body in the groove by the electrode body isolation dielectric layer, and the second region of the first electrode body in the groove is insulated and isolated from the bottom wall and the corresponding side wall of the diode trench by the field oxide layer in the groove;

槽内第二电极体利用槽内栅氧化层与所在类二极管沟槽的侧壁绝缘隔离,槽内栅氧化层的厚度小于槽内场氧化层的厚度,且槽内栅氧化层与槽内场氧化层接触;The second electrode body in the groove is insulated and isolated from the sidewall of the diode groove by the gate oxide layer in the groove, the thickness of the gate oxide layer in the groove is less than the thickness of the field oxide layer in the groove, and the gate oxide layer in the groove contacts the field oxide layer in the groove;

槽内第一电极体、槽内第二电极体均与半导体基板上方的器件第一电极金属电连接,其中,The first electrode body in the groove and the second electrode body in the groove are both electrically connected to the first electrode metal of the device above the semiconductor substrate, wherein:

所述器件第一电极金属还与类二极管沟槽外侧相应的二极管第一导电类型源区以及横贯有源区的第二导电类型基区欧姆接触,The first electrode metal of the device also makes ohmic contact with the first conductive type source region of the diode corresponding to the outer side of the diode-like trench and the second conductive type base region that traverses the active region.

二极管第一导电类型源区以及第二导电类型基区均与所述类二极管沟槽的外侧壁接触。The first conductive type source region and the second conductive type base region of the diode are both in contact with the outer sidewall of the diode-like trench.

在类二极管沟槽内,槽内第二电极体的宽度大于槽内第一电极体的宽度;In the diode-like trench, the width of the second electrode body in the trench is greater than the width of the first electrode body in the trench;

槽内第一电极体第一区域的宽度小于槽内第一电极体第二区域的宽度;The width of the first region of the first electrode body in the groove is smaller than the width of the second region of the first electrode body in the groove;

槽内第一电极体第一区域的端面位于第二导电类型基区的底面的上方;The end surface of the first region of the first electrode body in the groove is located above the bottom surface of the second conductive type base region;

槽内第二电极体邻近类二极管沟槽槽底的端面不高于第二导电类型基区的底面。The end surface of the second electrode body in the groove adjacent to the bottom of the diode-like groove is not higher than the bottom surface of the second conductive type base region.

在有源区内,至少在所述类肖特基二极管的一侧设置自隔离单元,其中,In the active area, a self-isolation unit is provided at least on one side of the Schottky-like diode, wherein:

所述自隔离单元包括自隔离沟槽以及填充于所述自隔离沟槽内的隔离单元电极体;The self-isolation unit comprises a self-isolation trench and an isolation unit electrode body filled in the self-isolation trench;

所述隔离单元电极体通过隔离沟槽内氧化层与所在自隔离沟槽的侧壁以及底壁绝缘隔离;The isolation unit electrode body is insulated and isolated from the sidewalls and bottom wall of the self-isolation trench where it is located by an oxide layer in the isolation trench;

所述隔离单元电极体与器件第一电极金属电连接。The isolation unit electrode body is electrically connected to the first electrode metal of the device.

在有源区内,自隔离沟槽的槽深与类二极管沟槽的槽深相一致;In the active area, the trench depth of the self-isolation trench is consistent with the trench depth of the diode-like trench;

隔离单元电极体的高度与槽内第一电极体的高度相一致,且隔离单元电极体的第二端端部与槽内第一电极体第一区域的端部平齐;The height of the isolation unit electrode body is consistent with the height of the first electrode body in the groove, and the second end of the isolation unit electrode body is flush with the end of the first region of the first electrode body in the groove;

隔离单元电极体的第一端邻近所在自隔离沟槽的槽底。The first end of the isolation unit electrode body is adjacent to the bottom of the self-isolation trench.

对自隔离单元,还包括位于自隔离沟槽外侧的隔离单元第一导电类型源区,其中,The self-isolation unit further includes an isolation unit first conductivity type source region located outside the self-isolation trench, wherein:

隔离单元第一导电类型源区位于自隔离沟槽外侧的第二导电类型基区内,且隔离单元第一导电类型源区、第二导电类型基区均与自隔离沟槽的外侧壁接触;The first conductive type source region of the isolation unit is located in the second conductive type base region outside the self-isolation trench, and both the first conductive type source region and the second conductive type base region of the isolation unit are in contact with the outer side wall of the self-isolation trench;

器件第一电极金属还与隔离单元第一导电类型源区以及第二导电类型基区电连接。The first electrode metal of the device is also electrically connected to the first conductivity type source region and the second conductivity type base region of the isolation unit.

对自隔离单元,还包括设置于自隔离沟槽外侧的隔离单元第二导电类型注入区以及与所述隔离单元第二导电类型注入区对应的隔离单元外接触孔,其中,The self-isolation unit further includes an isolation unit second conductivity type injection region disposed outside the self-isolation trench and an isolation unit external contact hole corresponding to the isolation unit second conductivity type injection region, wherein:

所述隔离单元第二导电类型注入区贯穿自隔离沟槽外侧的第二导电类型基区,隔离单元第二导电类型注入区的掺杂浓度大于第二导电类型基区的掺杂浓度,且隔离单元第二导电类型注入区的底部位于第二导电类型基区底面的下方;The second conductive type injection region of the isolation unit penetrates the second conductive type base region outside the isolation trench, the doping concentration of the second conductive type injection region of the isolation unit is greater than the doping concentration of the second conductive type base region, and the bottom of the second conductive type injection region of the isolation unit is located below the bottom surface of the second conductive type base region;

隔离单元第二导电类型注入区与自隔离沟槽相应的外侧壁接触,且隔离单元第二导电类型注入区与填充在隔离单元外接触孔内的器件第一电极金属欧姆接触。The second conductive type implantation region of the isolation unit contacts the corresponding outer sidewall of the self-isolation trench, and the second conductive type implantation region of the isolation unit is in ohmic contact with the first electrode metal of the device filled in the external contact hole of the isolation unit.

在所述屏蔽栅功率器件的截面上,隔离单元外接触孔呈梯形状,其中,On the cross section of the shielded gate power device, the isolation unit external contact hole is in a trapezoidal shape, wherein:

隔离单元外接触孔第一端的宽度小于所述隔离单元外接触孔第二端的宽度,其中,隔离单元外接触孔第一端位于自隔离沟槽槽口的下方;The width of the first end of the isolation unit external contact hole is smaller than the width of the second end of the isolation unit external contact hole, wherein the first end of the isolation unit external contact hole is located below the notch of the self-isolation trench;

隔离单元外接触孔第二端的宽度大于隔离单元第二导电类型注入区的宽度,以使得隔离单元外接触孔的第二端进入自隔离沟槽的槽口区域。The width of the second end of the isolation unit external contact hole is greater than the width of the second conductivity type implantation region of the isolation unit, so that the second end of the isolation unit external contact hole enters the notch region of the self-isolation trench.

对任一SGT元胞,在所述SGT元胞的元胞沟槽内设置SGT结构,其中,For any SGT cell, an SGT structure is provided in the cell groove of the SGT cell, wherein:

所述SGT结构采用上下结构时,所述SGT结构包括元胞下电极体以及元胞上电极体,元胞上电极体位于元胞下电极体的上方,且元胞上电极体与元胞下电极体间绝缘隔离;When the SGT structure adopts a top-bottom structure, the SGT structure includes a cell bottom electrode body and a cell top electrode body, the cell top electrode body is located above the cell bottom electrode body, and the cell top electrode body is insulated and isolated from the cell bottom electrode body;

所述元胞上电极体通过元胞栅氧化层与所在元胞沟槽的侧壁绝缘隔离;The cell upper electrode body is insulated and isolated from the sidewall of the cell trench through the cell gate oxide layer;

元胞栅氧化层的厚度大于槽内栅氧化层的厚度;The thickness of the cell gate oxide layer is greater than the thickness of the gate oxide layer in the trench;

所述元胞上电极体与半导体基板上方的器件第二电极金属电连接,元胞下电极体与器件第一电极金属电连接。The upper electrode body of the cell is electrically connected to the second electrode metal of the device above the semiconductor substrate, and the lower electrode body of the cell is electrically connected to the first electrode metal of the device.

在有源区内,设置若干源区接触孔单元,其中,In the active area, a number of source area contact hole units are arranged, wherein:

所述源区接触孔单元至少分布于相邻的两个SGT元胞之间;The source region contact hole unit is distributed at least between two adjacent SGT cells;

所述源区接触孔单元包括源区接触孔以及位于所述源区接触孔正下方的接触孔下第二导电类型注入区,其中,The source contact hole unit includes a source contact hole and a second conductive type implantation region under the contact hole located directly below the source contact hole, wherein:

接触孔下第二导电类型注入区的掺杂浓度大于第二导电类型基区的掺杂浓度,接触孔下第二导电类型注入区位于第二导电类型基区的下方,且与对应的第二导电类型基区接触;The doping concentration of the second conductive type injection region under the contact hole is greater than the doping concentration of the second conductive type base region, and the second conductive type injection region under the contact hole is located below the second conductive type base region and contacts the corresponding second conductive type base region;

器件第一电极金属填充在源区接触孔内,且器件第一电极金属与接触孔下第二导电类型注入区、第二导电类型基区以及所填充源区接触孔两侧的元胞第一导电类型源区欧姆接触;The first electrode metal of the device is filled in the source contact hole, and the first electrode metal of the device is in ohmic contact with the second conductivity type injection region under the contact hole, the second conductivity type base region, and the first conductivity type source region of the cell on both sides of the filled source contact hole;

元胞第一导电类型源区与对应元胞沟槽的外侧壁接触。The first conductive type source region of the cell contacts the outer sidewall of the corresponding cell trench.

本发明的优点:在有源区内通过设置类肖特基二极管提升屏蔽栅功率器件的快恢复能力时,可通过配置类肖特基二极管的类二极管沟槽的深度、增加自隔离单元和/或源区接触孔单元,避免漏电击穿发生在类肖特基二极管的槽内栅氧化层处,可降低屏蔽栅功率器件的漏电,提升屏蔽栅功率器件的耐压,增强屏蔽栅功率器件的雪崩能力。The advantages of the present invention are as follows: when the fast recovery capability of the shielded gate power device is improved by arranging a Schottky-like diode in the active region, the depth of the diode-like groove of the Schottky-like diode can be configured, and the self-isolation unit and/or the source region contact hole unit can be increased to avoid leakage breakdown from occurring at the gate oxide layer in the groove of the Schottky-like diode, thereby reducing the leakage of the shielded gate power device, improving the withstand voltage of the shielded gate power device, and enhancing the avalanche capability of the shielded gate power device.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1为本发明第一种实施例的结构剖视图。FIG1 is a structural cross-sectional view of a first embodiment of the present invention.

图2为本发明第二种实施例的结构剖视图。FIG. 2 is a structural cross-sectional view of a second embodiment of the present invention.

图3为本发明第三种实施例的结构剖视图。FIG3 is a structural cross-sectional view of a third embodiment of the present invention.

图4为本发明第四种实施例的结构剖视图。FIG. 4 is a structural cross-sectional view of a fourth embodiment of the present invention.

图5为本发明第五种实施例的结构剖视图。FIG5 is a structural cross-sectional view of a fifth embodiment of the present invention.

附图标记说明:1-衬底、2-外延层、3-元胞沟槽、4-类二极管沟槽、5-元胞场氧化层、6-元胞下电极体、7-P型基区、8-元胞上电极体、9-层间氧化层、10-元胞栅氧化层、11-槽口氧化层、12-元胞N+源区、13-接触P+注入区、14-槽内场氧化层、15-槽内第一电极体、16-槽内栅氧化层、17-槽内第二电极体、18-电极体隔离介质层、19-自隔离沟槽、20-隔离沟槽内氧化层、21-隔离单元电极体、22-二极管电极体接触孔、23-接触孔下P+注入区、24-隔离单元P+注入区、25-隔离单元外接触孔、26-隔离单元内接触孔、27-源区接触孔、28-二极管N+源区、29-隔离单元N+源区。Description of the accompanying drawings: 1-substrate, 2-epitaxial layer, 3-cell trench, 4-diode-type trench, 5-cell field oxide layer, 6-cell lower electrode body, 7-P-type base region, 8-cell upper electrode body, 9-interlayer oxide layer, 10-cell gate oxide layer, 11-notch oxide layer, 12-cell N+ source region, 13-contact P+ injection region, 14-field oxide layer in the groove, 15-first electrode body in the groove, 16-gate oxide layer in the groove, 17- 7-the second electrode body in the groove, 18-the electrode body isolation dielectric layer, 19-the self-isolation groove, 20-the oxide layer in the isolation groove, 21-the isolation unit electrode body, 22-the diode electrode body contact hole, 23-the P+ injection region under the contact hole, 24-the isolation unit P+ injection region, 25-the isolation unit external contact hole, 26-the isolation unit internal contact hole, 27-the source region contact hole, 28-the diode N+ source region, 29-the isolation unit N+ source region.

具体实施方式DETAILED DESCRIPTION

下面结合具体附图和实施例对本发明作进一步说明。The present invention will be further described below in conjunction with specific drawings and embodiments.

为了能有效降低屏蔽栅功率器件的漏电流,增强雪崩能力,提高SGT功率器件工作时的稳定性及可靠性,本发明提供一种具有低漏电及快恢复能力的屏蔽栅功率器件,以第一导电类型为N型为例,具体地,所述屏蔽栅功率器件包括:In order to effectively reduce the leakage current of the shielded gate power device, enhance the avalanche capability, and improve the stability and reliability of the SGT power device during operation, the present invention provides a shielded gate power device with low leakage and fast recovery capability. Taking the first conductive type as N type as an example, specifically, the shielded gate power device includes:

半导体基板,呈N导电类型;A semiconductor substrate having an N conductivity type;

有源区,分布于半导体基板的中心区域,包括若干SGT元胞以及至少一个类肖特基二极管,其中,The active region is distributed in the central area of the semiconductor substrate and includes a plurality of SGT cells and at least one Schottky-like diode, wherein:

所述类肖特基二极管为沟槽型类肖特基二极管,所述类肖特基二极管包括位于有源区内的类二极管沟槽4;The Schottky-like diode is a trench-type Schottky-like diode, and the Schottky-like diode includes a diode-like trench 4 located in the active area;

在有源区内,类二极管沟槽4的槽深大于任一SGT元胞的元胞沟槽3槽深。In the active region, the depth of the diode-like trench 4 is greater than the depth of the cell trench 3 of any SGT cell.

可以理解的是,屏蔽栅功率器件可为上述提到的SGT MOSFET器件、SGT IGBT器件或其他类型的功率器件,屏蔽栅功率器件的类型可根据需要选择,以能满足实际的应用需求为准。对于屏蔽栅功率器件,一般均包括半导体基板,也即功率器件一般制备在半导体基板上,半导体基板的导电类型呈N型,图1~图5中示出了半导体基板的一种实施例,图中,半导体基板包括衬底1以及位于衬底1上的外延层2,此时,衬底1以及外延层2的导电类型均为N型。一般地,外延层2的掺杂浓度小于衬底1的掺杂浓度,外延层2的厚度大于衬底1的厚度,衬底1、外延层2的情况均与现有半导体基板相一致,此处不再赘述。It can be understood that the shielded gate power device can be the SGT MOSFET device, SGT IGBT device or other types of power devices mentioned above, and the type of the shielded gate power device can be selected as needed to meet the actual application requirements. For shielded gate power devices, they generally include a semiconductor substrate, that is, the power device is generally prepared on a semiconductor substrate, and the conductivity type of the semiconductor substrate is N-type. Figures 1 to 5 show an embodiment of a semiconductor substrate. In the figure, the semiconductor substrate includes a substrate 1 and an epitaxial layer 2 located on the substrate 1. At this time, the conductivity types of the substrate 1 and the epitaxial layer 2 are both N-type. Generally, the doping concentration of the epitaxial layer 2 is less than the doping concentration of the substrate 1, and the thickness of the epitaxial layer 2 is greater than the thickness of the substrate 1. The conditions of the substrate 1 and the epitaxial layer 2 are consistent with the existing semiconductor substrates and will not be repeated here.

对于屏蔽栅功率器件,一般包括有源区以及位于所述有源区外圈的终端区域,终端区域一般环绕包围有源区,利用终端区域可提升有源区的耐压,有源区、终端区域在半导体基板上的分布,以及具体配合工作方式均与现有相一致,此处不再赘述。For shielded gate power devices, they generally include an active area and a terminal area located on the outer circle of the active area. The terminal area generally surrounds the active area. The terminal area can be used to improve the voltage resistance of the active area. The distribution of the active area and the terminal area on the semiconductor substrate, as well as the specific coordinated working methods are consistent with the existing ones and will not be repeated here.

对本发明的屏蔽栅功率器件,在有源区内包括若干SGT元胞,有源区内的SGT元胞并联成一体,有源区内SGT元胞的数量可根据实际场景选择,以能满足实际的需求为准。The shielded gate power device of the present invention includes a plurality of SGT cells in the active region, and the SGT cells in the active region are connected in parallel as a whole. The number of SGT cells in the active region can be selected according to actual scenarios to meet actual needs.

为了提高屏蔽栅功率器件的反向恢复效率以及反向恢复能力,由上述说明可知,可在有源区内至少设置一个类肖特基二极管,也即利用设置的类肖特基二极管,可提高屏蔽栅功率器件的反向恢复效率以及反向恢复能力。与此同时,在有源区内设置类肖特基二极管后,会导致屏蔽栅功率器件的漏电流增加,降低雪崩能力,可以理解的是,设置类肖特基二极管后,发生漏电的区域即类肖特基二极管所在的区域。In order to improve the reverse recovery efficiency and reverse recovery capability of the shielded gate power device, it can be seen from the above description that at least one Schottky-like diode can be set in the active area, that is, the reverse recovery efficiency and reverse recovery capability of the shielded gate power device can be improved by using the Schottky-like diode set. At the same time, after setting the Schottky-like diode in the active area, the leakage current of the shielded gate power device will increase and the avalanche capability will be reduced. It can be understood that after the Schottky-like diode is set, the area where leakage occurs is the area where the Schottky-like diode is located.

为了能降低屏蔽栅功率器件的漏电流,并增强雪崩能力,本发明的一种实施例中,将类肖特基二极管选择为沟槽型类肖特基二极管,因此,类肖特基二极管至少包括位于有源区内的类二极管沟槽4,当然,在类二极管沟槽4内还需制备对应的类肖特基二极管结构,类肖特基二极管结构会在下面进行详细说明。In order to reduce the leakage current of the shielded gate power device and enhance the avalanche capability, in one embodiment of the present invention, the Schottky-like diode is selected as a trench-type Schottky-like diode. Therefore, the Schottky-like diode at least includes a diode-like groove 4 located in the active area. Of course, a corresponding Schottky-like diode structure needs to be prepared in the diode-like groove 4. The Schottky-like diode structure will be described in detail below.

本发明的一种实施例中,类二极管沟槽4的槽深大于任一SGT元胞的元胞沟槽3的槽深,图1~图5中示出了类二极管沟槽4、元胞沟槽3的一种分布实施例,图中,类二极管沟槽4的槽口以及元胞沟槽3的槽口均位于外延层2的表面,类二极管沟槽4的槽底以及元胞沟槽3的槽底均位于外延层2内。一般地,有源区内所有的元胞沟槽3可具有相同的槽深,当然,有源区内的元胞沟槽3也可以选择不同的槽深,具体可根据需要选择,以能满足实际的需求为准。图1~图5中示出了有源区内所有的元胞沟槽3具有相同槽深的一种实施例。In one embodiment of the present invention, the groove depth of the diode-like groove 4 is greater than the groove depth of the cell groove 3 of any SGT cell. FIG. 1 to FIG. 5 show a distribution embodiment of the diode-like groove 4 and the cell groove 3. In the figure, the notch of the diode-like groove 4 and the notch of the cell groove 3 are both located on the surface of the epitaxial layer 2, and the groove bottom of the diode-like groove 4 and the groove bottom of the cell groove 3 are both located in the epitaxial layer 2. Generally, all the cell grooves 3 in the active area can have the same groove depth. Of course, the cell grooves 3 in the active area can also have different groove depths, which can be selected according to needs to meet actual needs. FIG. 1 to FIG. 5 show an embodiment in which all the cell grooves 3 in the active area have the same groove depth.

具体实施时,有源区内所有元胞沟槽3的槽深均小于类二极管沟槽4的槽深,其中,类二极管沟槽4的槽深大于元胞沟槽3的槽深时,类二极管沟槽4的槽底位于元胞沟槽3槽底的下方。由上述说明可知,当在有源区内设置类肖特基二极管时,漏电流增加的区域会发生在类肖特基二极管所在的区域。当类二极管沟槽4的槽深大于元胞沟槽3的槽深时,则能增加类肖特基二极管所在区域的耐压,使得屏蔽栅功率器件在反向关断时,击穿的区域尽可能发生在SGT元胞所在的区域,从而可以降低屏蔽栅功率器件在反向关断时的漏电流,增强雪崩能力。In a specific implementation, the groove depth of all the cell grooves 3 in the active area is less than the groove depth of the diode-like groove 4, wherein when the groove depth of the diode-like groove 4 is greater than the groove depth of the cell groove 3, the groove bottom of the diode-like groove 4 is located below the groove bottom of the cell groove 3. It can be seen from the above description that when a Schottky-like diode is set in the active area, the area where the leakage current increases will occur in the area where the Schottky-like diode is located. When the groove depth of the diode-like groove 4 is greater than the groove depth of the cell groove 3, the withstand voltage of the area where the Schottky-like diode is located can be increased, so that when the shielded gate power device is reversely turned off, the breakdown area occurs as much as possible in the area where the SGT cell is located, thereby reducing the leakage current of the shielded gate power device when it is reversely turned off and enhancing the avalanche capability.

本发明的一种实施例中,对所述类肖特基二极管,包括填充于所述类二极管沟槽4内的二极管电极体,其中,In one embodiment of the present invention, the Schottky-like diode comprises a diode electrode body filled in the diode-like trench 4, wherein:

所述二极管电极体包括槽内第一电极体15以及与所述槽内第一电极体15对应的槽内第二电极体17,且槽内第二电极体17邻近所在类二极管沟槽4的槽口;The diode electrode body includes a first in-groove electrode body 15 and a second in-groove electrode body 17 corresponding to the first in-groove electrode body 15, and the second in-groove electrode body 17 is adjacent to the notch of the diode trench 4;

槽内第一电极体15包括进入槽内第二电极体17内的槽内第一电极体第一区域以及位于槽内第二电极体17下方的槽内第一电极体第二区域,其中,The first in-slot electrode body 15 includes a first in-slot electrode body first region entering into the second in-slot electrode body 17 and a second in-slot electrode body second region located below the second in-slot electrode body 17, wherein:

槽内第一电极体第一区域通过电极体隔离介质层18与槽内第二电极体17间隔,槽内第一电极体第二区域利用槽内场氧化层14与所在类二极管沟槽4的底壁以及对应的侧壁绝缘隔离;The first region of the first electrode body in the groove is separated from the second electrode body 17 in the groove by the electrode body isolation dielectric layer 18, and the second region of the first electrode body in the groove is insulated and isolated from the bottom wall and the corresponding side wall of the diode trench 4 by the field oxide layer 14 in the groove;

槽内第二电极体17利用槽内栅氧化层16与所在类二极管沟槽4的侧壁绝缘隔离,槽内栅氧化层16的厚度小于槽内场氧化层14的厚度,且槽内栅氧化层16与槽内场氧化层14接触;The second electrode body 17 in the trench is insulated and isolated from the sidewall of the diode trench 4 in which it is located by the gate oxide layer 16 in the trench, the thickness of the gate oxide layer 16 in the trench is less than the thickness of the field oxide layer 14 in the trench, and the gate oxide layer 16 in the trench is in contact with the field oxide layer 14 in the trench;

槽内第一电极体15、槽内第二电极体17均与半导体基板上方的器件第一电极金属电连接,其中,The first electrode body 15 in the groove and the second electrode body 17 in the groove are both electrically connected to the first electrode metal of the device above the semiconductor substrate, wherein:

所述器件第一电极金属还与类二极管沟槽4外侧相应的二极管N+源区28以及横贯有源区的P型基区7欧姆接触,The first electrode metal of the device also makes ohmic contact with the corresponding diode N+ source region 28 outside the diode-like trench 4 and the P-type base region 7 that traverses the active region.

二极管N+源区28以及P型基区7均与所述类二极管沟槽4的外侧壁接触。The diode N+ source region 28 and the P-type base region 7 are both in contact with the outer sidewall of the diode-like trench 4 .

图1~图5均示出了设置类肖特基二极管的实施例,也即示出了类二极管沟槽4内类肖特基二极管结构的实施例,图中,类肖特基二极管还包括填充在类二极管沟槽4内的二极管电极体,也即二极管电极体位于类二极管沟槽4内;此外,图中示出了二极管电极体包括槽内第一电极体15以及槽内第二电极体17的一种实施例,槽内第一电极体15、槽内第二电极体17一般可选为现有常用的导电多晶硅,当然,还可以采用其他常用的电极体材料,槽内第一电极体15、槽内第二电极体17相应的材料可根据实际需要选择,以能满足实际的应用需求为准。Figures 1 to 5 all show an embodiment of setting up a Schottky-like diode, that is, an embodiment of a Schottky-like diode structure in a diode-like groove 4. In the figure, the Schottky-like diode also includes a diode electrode body filled in the diode-like groove 4, that is, the diode electrode body is located in the diode-like groove 4; in addition, the figure shows an embodiment in which the diode electrode body includes a first electrode body 15 in the groove and a second electrode body 17 in the groove. The first electrode body 15 in the groove and the second electrode body 17 in the groove can generally be selected as existing commonly used conductive polysilicon. Of course, other commonly used electrode body materials can also be used. The corresponding materials of the first electrode body 15 in the groove and the second electrode body 17 in the groove can be selected according to actual needs, so as to meet the actual application requirements.

图1~图5中,在类二极管沟槽4内,槽内第二电极体17邻近所在类二极管沟槽4的槽口,槽内第一电极体15的长度方向与类二极管沟槽4的长度方向相一致,槽内第一电极体15的下端邻近类二极管沟槽4的槽底,槽内第一电极体15上端与槽内第二电极体17对应配合。具体地,槽内第一电极体15包括进入槽内第二电极体17内的槽内第一电极体第一区域以及位于槽内第二电极体17下方的槽内第一电极体第二区域,图1、图2、图4和图5中示出了槽内第一电极体第一区域小于槽内第二电极体17高度/厚度的一种实施例,图3中示出了槽内第一电极体第一区域与槽内第二电极体17的高度/厚度相同的一种实施例。In Fig. 1 to Fig. 5, in the diode-like groove 4, the second electrode body 17 in the groove is adjacent to the groove opening of the diode-like groove 4, the length direction of the first electrode body 15 in the groove is consistent with the length direction of the diode-like groove 4, the lower end of the first electrode body 15 in the groove is adjacent to the groove bottom of the diode-like groove 4, and the upper end of the first electrode body 15 in the groove corresponds to the second electrode body 17 in the groove. Specifically, the first electrode body 15 in the groove includes a first region of the first electrode body in the groove that enters the second electrode body 17 in the groove and a second region of the first electrode body in the groove that is located below the second electrode body 17 in the groove. Fig. 1, Fig. 2, Fig. 4 and Fig. 5 show an embodiment in which the first region of the first electrode body in the groove is smaller than the height/thickness of the second electrode body 17 in the groove, and Fig. 3 shows an embodiment in which the first region of the first electrode body in the groove is the same as the height/thickness of the second electrode body 17 in the groove.

图1~图5中,槽内第一电极体第一区域通过电极体隔离介质层18与槽内第二电极体17间隔,电极体隔离介质层18可为二氧化硅层,电极体隔离介质层18包覆在槽内第一电极体第一区域上;其中,图3中,槽内第一电极体第一区域的端面可由类二极管沟槽4内其他隔离介质层覆盖。图1、图2、图4和图5中,电极体隔离介质层18可对槽内第一电极体第一区域全覆盖。In Figures 1 to 5, the first region of the first electrode body in the groove is separated from the second electrode body 17 in the groove by an electrode body isolation dielectric layer 18, and the electrode body isolation dielectric layer 18 can be a silicon dioxide layer, and the electrode body isolation dielectric layer 18 is coated on the first region of the first electrode body in the groove; wherein, in Figure 3, the end surface of the first region of the first electrode body in the groove can be covered by other isolation dielectric layers in the diode-like groove 4. In Figures 1, 2, 4 and 5, the electrode body isolation dielectric layer 18 can fully cover the first region of the first electrode body in the groove.

槽内第一电极体第二区域也即为槽内第一电极体15的下部区域,槽内第一电极体第二区域利用槽内场氧化层14与所在类二极管沟槽4的底壁以及对应的侧壁绝缘隔离。槽内第二电极体17利用槽内栅氧化层16与所在类二极管沟槽4的侧壁绝缘隔离,因此,槽内栅氧化层16也邻近所在类二极管沟槽4的槽口,槽内栅氧化层16的高度一般要小于槽内第二电极体17的高度,其中,所述的高度即为沿类二极管沟槽4长度方向的尺寸。The second region of the first electrode body in the groove is also the lower region of the first electrode body 15 in the groove. The second region of the first electrode body in the groove is insulated and isolated from the bottom wall and the corresponding side wall of the diode trench 4 in which it is located by the field oxide layer 14 in the groove. The second electrode body 17 in the groove is insulated and isolated from the side wall of the diode trench 4 in which it is located by the gate oxide layer 16 in the groove. Therefore, the gate oxide layer 16 in the groove is also adjacent to the groove opening of the diode trench 4 in which it is located. The height of the gate oxide layer 16 in the groove is generally smaller than the height of the second electrode body 17 in the groove, wherein the height is the dimension along the length direction of the diode trench 4 in which it is located.

槽内栅氧化层16与槽内场氧化层14接触,从而类二极管沟槽4的内壁以及底壁均覆盖有氧化层。可选地,电极体隔离介质层18的厚度与槽内栅氧化层16的厚度相一致;当然,电极体隔离介质层18的厚度也可与槽内栅氧化层16的厚度不同,具体可根据需要选择。当电极体隔离介质层18与槽内栅氧化层16的厚度相同,且均为二氧化硅层时,电极体隔离介质层18与槽内栅氧化层16可通过同一热氧化工艺制备形成。The gate oxide layer 16 in the groove contacts the field oxide layer 14 in the groove, so that the inner wall and the bottom wall of the diode-like groove 4 are covered with an oxide layer. Optionally, the thickness of the electrode body isolation dielectric layer 18 is consistent with the thickness of the gate oxide layer 16 in the groove; of course, the thickness of the electrode body isolation dielectric layer 18 can also be different from the thickness of the gate oxide layer 16 in the groove, which can be selected according to needs. When the electrode body isolation dielectric layer 18 and the gate oxide layer 16 in the groove have the same thickness and are both silicon dioxide layers, the electrode body isolation dielectric layer 18 and the gate oxide layer 16 in the groove can be prepared and formed by the same thermal oxidation process.

具体实施时,槽内第一电极体15、槽内第二电极体17均与半导体基板上方的器件第一电极金属电连接,其中,器件第一电极金属未在图1~图5中示出,可以理解的时,器件第一电极金属可形成屏蔽栅功率器件的第一电极,当屏蔽栅功率器件为SGT MOSFET器件时,则第一电极即为源电极;当屏蔽栅功率器件为SGT IGBT器件时,则第一电极即为发射极,当屏蔽栅功率器件为其他类型时,则可确定基于器件第一电极金属所形成第一电极的类型,此处不再一一举例说明。In specific implementation, the first electrode body 15 in the groove and the second electrode body 17 in the groove are electrically connected to the first electrode metal of the device above the semiconductor substrate, wherein the first electrode metal of the device is not shown in Figures 1 to 5. It can be understood that the first electrode metal of the device can form the first electrode of the shielded gate power device. When the shielded gate power device is an SGT MOSFET device, the first electrode is the source electrode; when the shielded gate power device is an SGT IGBT device, the first electrode is the emitter. When the shielded gate power device is of other types, the type of the first electrode formed based on the first electrode metal of the device can be determined, and examples will not be given one by one here.

可以理解的是,槽内第一电极体15、槽内第二电极体17可采用现有常用的方式引出,以在引出后实现与器件第一电极金属间的电连接。当槽内第一电极体15、槽内第二电极体17采用导电多晶硅时,槽内第一电极体15、槽内第二电极体17与器件第一电极金属间的电连接,具体是指与器件第一电极金属形成欧姆接触;当槽内第一电极体15、槽内第二电极体17采用其他材料时,可得到与器件第一电极金属间电连接的具体状态,此处不再一一举例说明。It is understandable that the first electrode body 15 in the groove and the second electrode body 17 in the groove can be led out in an existing commonly used manner to achieve electrical connection with the first electrode metal of the device after being led out. When the first electrode body 15 in the groove and the second electrode body 17 in the groove are made of conductive polysilicon, the electrical connection between the first electrode body 15 in the groove and the second electrode body 17 in the groove and the first electrode metal of the device specifically refers to forming an ohmic contact with the first electrode metal of the device; when the first electrode body 15 in the groove and the second electrode body 17 in the groove are made of other materials, a specific state of electrical connection with the first electrode metal of the device can be obtained, which will not be explained one by one here.

需要说明的是,在有源区内还设置有P型基区7,其中,P型基区7一般横贯有源区,也即P型基区7分布整个有源区,元胞沟槽3的槽底以及类二极管沟槽4相应的槽底均位于P型基区7的下方。为了能在类二极管沟槽4的侧壁形成导电沟道,在类二极管沟槽4的外侧需设置二极管N+源区28,二极管N+源区28一般位于与类二极管沟槽4接触P型基区7的区域内,图1~图5所示,二极管N+源区28与类二极管沟槽4相应的侧壁接触,二极管N+源区28的结深小于P型基区7的结深。It should be noted that a P-type base region 7 is also provided in the active region, wherein the P-type base region 7 generally traverses the active region, that is, the P-type base region 7 is distributed throughout the active region, and the bottom of the cell trench 3 and the corresponding bottom of the diode-like trench 4 are both located below the P-type base region 7. In order to form a conductive channel on the sidewall of the diode-like trench 4, a diode N+ source region 28 needs to be provided on the outside of the diode-like trench 4. The diode N+ source region 28 is generally located in the region of the P-type base region 7 that contacts the diode-like trench 4. As shown in FIGS. 1 to 5 , the diode N+ source region 28 contacts the corresponding sidewall of the diode-like trench 4, and the junction depth of the diode N+ source region 28 is less than the junction depth of the P-type base region 7.

具体实施时,器件第一电极金属同时还要与二极管N+源区28以及类二极管沟槽4外侧的P型基区7电连接,其中,器件第一电极金属一般与二极管N+源区28间欧姆接触,器件第一电极金属可与二极管N+源区28所在P型基区7欧姆接触或其他方式电连接,也即器件第一电极金属与二极管N+源区28所在的P型基区7间的电连接方式可选择。当在类二极管沟槽4内设置槽内第一电极体15以及槽内第二电极体17,同时,槽内第一电极体15、槽内第二电极体17间通过电极体隔离介质层18间隔,且槽内第一电极体15以及槽内第二电极体17均与器件第一电极金属电连接后,可减少屏蔽栅功率器件的栅漏电容Cgd,进而可降低屏蔽栅功率器件的开关损耗。In specific implementation, the first electrode metal of the device is also electrically connected to the diode N+ source region 28 and the P-type base region 7 outside the diode-like groove 4, wherein the first electrode metal of the device is generally in ohmic contact with the diode N+ source region 28, and the first electrode metal of the device can be in ohmic contact with the P-type base region 7 where the diode N+ source region 28 is located or electrically connected in other ways, that is, the electrical connection method between the first electrode metal of the device and the P-type base region 7 where the diode N+ source region 28 is located can be selected. When the first electrode body 15 in the groove and the second electrode body 17 in the groove are set in the diode-like groove 4, at the same time, the first electrode body 15 in the groove and the second electrode body 17 in the groove are separated by the electrode body isolation dielectric layer 18, and the first electrode body 15 in the groove and the second electrode body 17 in the groove are both electrically connected to the first electrode metal of the device, the gate-drain capacitance Cgd of the shielded gate power device can be reduced, thereby reducing the switching loss of the shielded gate power device.

本发明的一种实施例中,在类二极管沟槽4内,槽内第二电极体17的宽度大于槽内第一电极体15的宽度;In one embodiment of the present invention, in the diode-like trench 4, the width of the second electrode body 17 in the trench is greater than the width of the first electrode body 15 in the trench;

槽内第一电极体第一区域的宽度小于槽内第一电极体第二区域的宽度;The width of the first region of the first electrode body in the groove is smaller than the width of the second region of the first electrode body in the groove;

槽内第一电极体第一区域的端面位于P型基区7的底面的上方;The end surface of the first region of the first electrode body in the groove is located above the bottom surface of the P-type base region 7;

槽内第二电极体17邻近类二极管沟槽4槽底的端面不高于P型基区7的底面。The end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is not higher than the bottom surface of the P-type base region 7 .

图1~图5中,示出了槽内第二电极体17的宽度大于槽内第一电极体15宽度的实施例,图中,槽内第二电极体17直接与槽内栅氧化层16接触,槽内第一电极体15的槽内第一电极体第二区域与槽内场氧化层14接触;槽内第一电极体第一区域的宽度小于槽内第一电极体第二区域的宽度。Figures 1 to 5 show an embodiment in which the width of the second electrode body 17 in the groove is greater than the width of the first electrode body 15 in the groove. In the figures, the second electrode body 17 in the groove is directly in contact with the gate oxide layer 16 in the groove, and the second region of the first electrode body 15 in the groove is in contact with the field oxide layer 14 in the groove; the width of the first region of the first electrode body in the groove is smaller than the width of the second region of the first electrode body in the groove.

为了能进一步分散电场,降低经由槽内栅氧化层16发生的漏电,槽内第一电极体第一区域的端面位于P型基区7的底面的上方,其中,P型基区7的底面,具体是指P型基区7邻近类二极管沟槽4槽底的表面。此外,槽内第二电极体17邻近类二极管沟槽4槽底的端面不高于P型基区7的底面。图1~图5中,槽内第二电极体17邻近类二极管沟槽4槽底的端面位于P型基区7底面的下方,也即所述端面位于P型基区7与类二极管沟槽4的槽底之间。此外,图1~图5中,还示出了槽内第二电极体17邻近类二极管沟槽4槽底的端面呈倾斜状的一种实施例,可以理解的是,槽内第二电极体17邻近类二极管沟槽4槽底的端面位于P型基区7底面的下方,且槽内第二电极体17邻近类二极管沟槽4槽底的端面呈倾斜状时,可进一步减少屏蔽栅功率器件的栅漏电容Cgd。In order to further disperse the electric field and reduce leakage through the gate oxide layer 16 in the groove, the end surface of the first region of the first electrode body in the groove is located above the bottom surface of the P-type base region 7, wherein the bottom surface of the P-type base region 7 specifically refers to the surface of the P-type base region 7 adjacent to the bottom of the diode-like groove 4. In addition, the end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is not higher than the bottom surface of the P-type base region 7. In Figures 1 to 5, the end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is located below the bottom surface of the P-type base region 7, that is, the end surface is located between the P-type base region 7 and the bottom of the diode-like groove 4. In addition, Figures 1 to 5 also show an embodiment in which the end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is inclined. It can be understood that when the end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is located below the bottom surface of the P-type base region 7 and the end surface of the second electrode body 17 in the groove adjacent to the bottom of the diode-like groove 4 is inclined, the gate-drain capacitance Cgd of the shielded gate power device can be further reduced.

由上述说明可知,器件第一电极金属与二极管N+源区28以及对应的P型基区7电连接,图1~图3中示出了一种欧姆接触的实施例,其中,图1~图3中,在P型基区7内还设置接触P+注入区13,接触P+注入区13的掺杂浓度大于P型基区7的掺杂浓度,接触P+注入区13与二极管N+源区28接触,此时,器件第一电极金属可直接与二极管N+源区28欧姆接触,同时,器件第一电极金属通过接触P+注入区13与对应的P型基区7电连接。此外,槽内第一电极体15以及槽内第二电极体17可通过本技术领域常用的引出方式实现与器件第一电极金属电连接,具体引出的方式图中未示出。As can be seen from the above description, the first electrode metal of the device is electrically connected to the diode N+ source region 28 and the corresponding P-type base region 7. Figures 1 to 3 show an embodiment of ohmic contact, wherein, in Figures 1 to 3, a contact P+ injection region 13 is also provided in the P-type base region 7, the doping concentration of the contact P+ injection region 13 is greater than the doping concentration of the P-type base region 7, and the contact P+ injection region 13 is in contact with the diode N+ source region 28. At this time, the first electrode metal of the device can directly make ohmic contact with the diode N+ source region 28, and at the same time, the first electrode metal of the device is electrically connected to the corresponding P-type base region 7 through the contact P+ injection region 13. In addition, the first electrode body 15 in the groove and the second electrode body 17 in the groove can be electrically connected to the first electrode metal of the device by a lead-out method commonly used in the technical field, and the specific lead-out method is not shown in the figure.

图4~图5中的实施例中,器件第一电极金属可与二极管N+源区28直接欧姆接触,此外,通过在类二极管沟槽4的槽口区域设置二极管电极体接触孔22,二极管电极体接触孔22贯穿槽内第二电极体17,并与槽内第一电极体第一区域对应,从而器件第一电极金属填充在二极管电极体接触孔22后,可使得器件第一电极金属与槽内第一电极体15以及槽内第二电极体17电连接。图4~图5中,填充在隔离单元外接触孔25内的器件第一电极金属与隔离单元P+注入区24接触,隔离单元P+注入区24与对应的P型基区7接触,从而依然可在类二极管沟槽4邻近隔离单元外接触孔25的侧壁形成导电沟道,也即不会影响类肖特基二极管的正常工作。In the embodiments in FIG. 4 and FIG. 5 , the first electrode metal of the device can be in direct ohmic contact with the diode N+ source region 28. In addition, by setting a diode electrode body contact hole 22 in the notch region of the diode-like groove 4, the diode electrode body contact hole 22 penetrates the second electrode body 17 in the groove and corresponds to the first region of the first electrode body in the groove, so that after the first electrode metal of the device is filled in the diode electrode body contact hole 22, the first electrode metal of the device can be electrically connected to the first electrode body 15 in the groove and the second electrode body 17 in the groove. In FIG. 4 and FIG. 5 , the first electrode metal of the device filled in the isolation unit outer contact hole 25 contacts the isolation unit P+ injection region 24, and the isolation unit P+ injection region 24 contacts the corresponding P-type base region 7, so that a conductive channel can still be formed on the side wall of the diode-like groove 4 adjacent to the isolation unit outer contact hole 25, that is, it will not affect the normal operation of the Schottky-like diode.

本发明的一种实施例中,在有源区内,至少在所述类肖特基二极管的一侧设置自隔离单元,其中,In one embodiment of the present invention, a self-isolation unit is provided in the active region at least on one side of the Schottky-like diode, wherein:

所述自隔离单元包括自隔离沟槽19以及填充于所述自隔离沟槽19内的隔离单元电极体21;The self-isolation unit includes a self-isolation trench 19 and an isolation unit electrode body 21 filled in the self-isolation trench 19;

所述隔离单元电极体21通过隔离沟槽内氧化层20与所在自隔离沟槽19的侧壁以及底壁绝缘隔离;The isolation unit electrode body 21 is insulated and isolated from the sidewalls and bottom wall of the self-isolation trench 19 through the oxide layer 20 in the isolation trench;

所述隔离单元电极体21与器件第一电极金属电连接。The isolation unit electrode body 21 is electrically connected to the first electrode metal of the device.

为了能进一步降低屏蔽栅功率器件在反向恢复时的漏电流,本发明的一种实施例中,还可在有源区内设置至少一个自隔离单元,其中,自隔离单元一般可分布于类肖特基二极管的一侧,或者在类肖特基二极管的两侧均设置一个自隔离单元,图2~图4中示出了在类肖特基二极管的左侧设置一个自隔离单元的一种实施例,图5中示出了在类肖特基二极管的两侧均设置一个自隔离单元的一种实施例,自隔离单元在有源区内的分布可根据实际需要选择。此时,利用自隔离单元的隔离作用,可分散聚集在类二极管沟槽4侧壁上的电场,进一步降低类肖特基二极管处的漏电流。In order to further reduce the leakage current of the shielded gate power device during reverse recovery, in one embodiment of the present invention, at least one self-isolation unit can be set in the active area, wherein the self-isolation unit can generally be distributed on one side of the Schottky-like diode, or a self-isolation unit can be set on both sides of the Schottky-like diode. Figures 2 to 4 show an embodiment of setting a self-isolation unit on the left side of the Schottky-like diode, and Figure 5 shows an embodiment of setting a self-isolation unit on both sides of the Schottky-like diode. The distribution of the self-isolation unit in the active area can be selected according to actual needs. At this time, the isolation effect of the self-isolation unit can be used to disperse the electric field gathered on the side wall of the diode-like groove 4, further reducing the leakage current at the Schottky-like diode.

图2~图5中示出了自隔离单元的一种实施例,图中,自隔离单元包括自隔离沟槽19以及填充于所述自隔离沟槽19内的隔离单元电极体21,自隔离沟槽19的槽口位于外延层2的表面,自隔离沟槽19的槽底位于外延层2内。隔离单元电极体21可为导电多晶硅或其他的导电材料,具体的材料类型可根据需要选择。FIG2 to FIG5 show an embodiment of a self-isolation unit, in which the self-isolation unit includes a self-isolation groove 19 and an isolation unit electrode body 21 filled in the self-isolation groove 19, the notch of the self-isolation groove 19 is located on the surface of the epitaxial layer 2, and the bottom of the self-isolation groove 19 is located in the epitaxial layer 2. The isolation unit electrode body 21 can be conductive polysilicon or other conductive materials, and the specific material type can be selected according to needs.

在自隔离沟槽19内设置隔离沟槽内氧化层20,隔离沟槽内氧化层20一般为二氧化硅层,利用隔离沟槽内氧化层20能实现隔离单元电极体21与自隔离沟槽19侧壁以及底壁的隔离。一般地,隔离沟槽内氧化层20的厚度可与槽内场氧化层14的厚度相一致。An isolation trench inner oxide layer 20 is provided in the self-isolation trench 19. The isolation trench inner oxide layer 20 is generally a silicon dioxide layer. The isolation trench inner oxide layer 20 can be used to isolate the isolation unit electrode body 21 from the sidewall and bottom wall of the self-isolation trench 19. Generally, the thickness of the isolation trench inner oxide layer 20 can be consistent with the thickness of the field oxide layer 14 in the trench.

具体实施时,设置将隔离单元电极体21与器件第一电极金属电连接,其中,可采用本技术常用的技术手段将隔离单元电极体21与器件第一电极金属电连接,图1~图3中未示出将隔离单元电极体21引出并与器件第一电极金属的连接方式;图4~图5中示出了将隔离单元电极体21引出连接的一种实施例,图中,在自隔离沟槽19的槽口设置隔离单元内接触孔26,隔离单元内接触孔26从自隔离沟槽19的槽口垂直向所述自隔离沟槽19的槽底方向开设,通过隔离单元内接触孔26可使得隔离单元电极体21露出,此后,器件第一电极金属可填充在隔离单元内接触孔26内,即能实现器件第一电极金属与隔离单元电极体21间的接触,以及接触后的电连接。During specific implementation, it is provided to electrically connect the isolation unit electrode body 21 with the first electrode metal of the device, wherein the isolation unit electrode body 21 can be electrically connected with the first electrode metal of the device by using the commonly used technical means in the present technology, and the method of leading out the isolation unit electrode body 21 and connecting it with the first electrode metal of the device is not shown in FIGS. 1 to 3 ; FIGS. 4 to 5 show an embodiment of leading out and connecting the isolation unit electrode body 21, in which an isolation unit internal contact hole 26 is provided at the notch of the self-isolation groove 19, and the isolation unit internal contact hole 26 is opened from the notch of the self-isolation groove 19 vertically toward the groove bottom direction of the self-isolation groove 19, and the isolation unit electrode body 21 can be exposed through the isolation unit internal contact hole 26, and thereafter, the first electrode metal of the device can be filled in the isolation unit internal contact hole 26, that is, the contact between the first electrode metal of the device and the isolation unit electrode body 21, as well as the electrical connection after the contact can be realized.

需要说明的是,将自隔离单元设置在类肖特基二极管的一侧后,由于自隔离单元内的隔离单元电极体21也与器件第一电极金属电连接,从而,屏蔽栅功率器件在反向恢复状态时,可分散电场,实现对类肖特基二极管保护,使得漏电发生击穿的区域由类肖特基二极管移至自隔离单元所在区域,甚至移至自隔离单元外侧的区域,从而避免电场在类二极管沟槽与槽内栅氧化层16对应侧壁区域的聚集,由此可知,在保持屏蔽栅功率器件的快恢复能力情况下,能进一步降低漏电,增强屏蔽栅功率器件的雪崩能力。It should be noted that after the self-isolation unit is set on one side of the Schottky-like diode, since the isolation unit electrode body 21 in the self-isolation unit is also electrically connected to the first electrode metal of the device, the shielded gate power device can disperse the electric field in the reverse recovery state to protect the Schottky-like diode, so that the area where leakage breakdown occurs is moved from the Schottky-like diode to the area where the self-isolation unit is located, or even to the area outside the self-isolation unit, thereby avoiding the electric field from gathering in the side wall area corresponding to the diode-like groove and the gate oxide layer 16 in the groove. It can be seen that while maintaining the fast recovery capability of the shielded gate power device, the leakage can be further reduced and the avalanche capability of the shielded gate power device can be enhanced.

图2~图4中,在类肖特基二极管的左侧设置一个自隔离单元,此时,可将漏电发生击穿的区域至少移至自隔离单元所在的区域;图5中,在类肖特基二极管的两侧均设置一个自隔离单元后,可将漏电发生击穿的区域均至少移至自隔离单元所在的区域,降低漏电,增强屏蔽栅功率器件的雪崩能力。In Figures 2 to 4, a self-isolation unit is set on the left side of the Schottky-like diode. At this time, the area where leakage breakdown occurs can be moved at least to the area where the self-isolation unit is located; in Figure 5, after a self-isolation unit is set on both sides of the Schottky-like diode, the area where leakage breakdown occurs can be moved at least to the area where the self-isolation unit is located, thereby reducing leakage and enhancing the avalanche capability of the shielded gate power device.

本发明的一种实施例中,在有源区内,自隔离沟槽19的槽深与类二极管沟槽4的槽深相一致;In one embodiment of the present invention, in the active region, the trench depth of the self-isolation trench 19 is consistent with the trench depth of the diode-like trench 4;

隔离单元电极体21的高度与槽内第一电极体15的高度相一致,且隔离单元电极体21的第二端端部与槽内第一电极体第一区域的端部平齐;The height of the isolation unit electrode body 21 is consistent with the height of the first electrode body 15 in the groove, and the second end of the isolation unit electrode body 21 is flush with the end of the first region of the first electrode body in the groove;

隔离单元电极体21的第一端邻近所在自隔离沟槽19的槽底。The first end of the isolation unit electrode body 21 is adjacent to the bottom of the self-isolation trench 19 .

由图2~图5以及上述说明可知,自隔离沟槽19的槽口与外延层2的表面对应,当自隔离沟槽19的槽深与类二极管沟槽4的槽深相一致时,自隔离沟槽19的槽底与类二极管沟槽4的槽底在外延层2内平齐,此时,自隔离沟槽19与类二极管沟槽4可基于同一沟槽工艺制备形成。当自隔离沟槽19的槽深与类二极管沟槽的槽深相一致时,则自隔离沟槽19的槽深较大,此时,可利用自隔离沟槽19的槽深能进一步增加自隔离单元的耐压,此时,可把类肖特基二极管的雪崩击穿点转向耐压相对较低的SGT元胞区域,能有效降低类肖特基二极管的电场,降低类肖特基二极管的漏电,提高雪屏蔽栅功率器件的崩击穿能力。As can be seen from FIG. 2 to FIG. 5 and the above description, the notch of the self-isolation groove 19 corresponds to the surface of the epitaxial layer 2. When the groove depth of the self-isolation groove 19 is consistent with the groove depth of the diode-like groove 4, the groove bottom of the self-isolation groove 19 and the groove bottom of the diode-like groove 4 are flush in the epitaxial layer 2. At this time, the self-isolation groove 19 and the diode-like groove 4 can be prepared and formed based on the same groove process. When the groove depth of the self-isolation groove 19 is consistent with the groove depth of the diode-like groove, the groove depth of the self-isolation groove 19 is larger. At this time, the groove depth of the self-isolation groove 19 can be used to further increase the withstand voltage of the self-isolation unit. At this time, the avalanche breakdown point of the Schottky-like diode can be turned to the SGT cell area with relatively low withstand voltage, which can effectively reduce the electric field of the Schottky-like diode, reduce the leakage of the Schottky-like diode, and improve the avalanche breakdown capability of the snow shielded gate power device.

图1~图5中,隔离单元电极体21的长度方向与自隔离沟槽19的长度方向相一致,隔离单元电极体21具有第一端以及与第一端对应的第二端,其中,隔离单元电极体21的第一端邻近所在自隔离沟槽19的槽底,此时则有:隔离单元电极体21的第二端邻近所在自隔离沟槽19的槽口。本发明的一种实施例中,隔离单元电极体21的高度与槽内第一电极体15的高度相一致,所述高度即为沿自隔离沟槽19以及类二极管沟槽4长度方向的尺寸。In FIG. 1 to FIG. 5 , the length direction of the isolation unit electrode body 21 is consistent with the length direction of the self-isolation groove 19, and the isolation unit electrode body 21 has a first end and a second end corresponding to the first end, wherein the first end of the isolation unit electrode body 21 is adjacent to the bottom of the self-isolation groove 19, and in this case: the second end of the isolation unit electrode body 21 is adjacent to the notch of the self-isolation groove 19. In one embodiment of the present invention, the height of the isolation unit electrode body 21 is consistent with the height of the first electrode body 15 in the groove, and the height is the dimension along the length direction of the self-isolation groove 19 and the diode-like groove 4.

此外,将隔离单元电极体21的第二端端部与槽内第一电极体第一区域的端部平齐,由上述说明可知,此时,隔离单元电极体21的第二端位于P型基区7底面的上方。将隔离单元电极体21的第二端设置位于P型基区7底面的上方时,可进一步增强屏蔽栅功率器件第一电极的场板效应,提高耐压,降低漏电。In addition, the second end of the isolation unit electrode body 21 is flush with the end of the first region of the first electrode body in the groove. As can be seen from the above description, at this time, the second end of the isolation unit electrode body 21 is located above the bottom surface of the P-type base region 7. When the second end of the isolation unit electrode body 21 is set above the bottom surface of the P-type base region 7, the field plate effect of the first electrode of the shielded gate power device can be further enhanced, the withstand voltage can be improved, and the leakage can be reduced.

具体实施时,还可在自隔离沟槽19和/或类二极管沟槽4的槽底设置沟槽P+注入区,利用沟槽P+注入区包覆自隔离沟槽19、类二极管沟槽4的槽底,利用沟槽P+注入区可进一步避免电场在类二极管沟槽4、自隔离沟槽19底部的聚集,进一步提高类肖特基二极管以及自隔离单元的耐压,由此,可进一步提高屏蔽栅器件的耐压,增强屏蔽栅功率器件的雪崩能力。During specific implementation, a trench P+ injection region can also be set at the bottom of the self-isolation trench 19 and/or the diode-like trench 4, and the trench P+ injection region can be used to cover the bottom of the self-isolation trench 19 and the diode-like trench 4. The trench P+ injection region can be used to further avoid the accumulation of the electric field at the bottom of the diode-like trench 4 and the self-isolation trench 19, thereby further improving the withstand voltage of the Schottky-like diode and the self-isolation unit. As a result, the withstand voltage of the shielded gate device can be further improved, and the avalanche capability of the shielded gate power device can be enhanced.

本发明的一种实施例中,对自隔离单元,还包括位于自隔离沟槽19外侧的隔离单元N+源区29,其中,In one embodiment of the present invention, the self-isolation unit further includes an isolation unit N+ source region 29 located outside the self-isolation trench 19, wherein:

隔离单元N+源区29位于自隔离沟槽19外侧的P型基区7内,且隔离单元N+源区29、P型基区7均与自隔离沟槽19的外侧壁接触;The isolation unit N+ source region 29 is located in the P-type base region 7 outside the self-isolation trench 19, and the isolation unit N+ source region 29 and the P-type base region 7 are both in contact with the outer side wall of the self-isolation trench 19;

器件第一电极金属还与隔离单元N+源区29以及P型基区7电连接。The first electrode metal of the device is also electrically connected to the isolation unit N+ source region 29 and the P-type base region 7 .

图2~图3中,示出了在自隔离沟槽19的外侧均设置隔离单元N+源区29的一种实施例,隔离单元N+源区29位于与自隔离沟槽19接触的P型基区7内,隔离单元N+源区29与自隔离沟槽19的外侧壁接触。当器件第一电极金属与隔离单元N+源区29以及P型基区7电连接后,则屏蔽栅功率器件在工作时,可在自隔离沟槽19的外侧壁形成导电沟道,此时,可降低屏蔽栅功率器件的导通电阻。FIG. 2 and FIG. 3 show an embodiment in which an isolation unit N+ source region 29 is disposed on the outer side of the self-isolation trench 19. The isolation unit N+ source region 29 is located in the P-type base region 7 in contact with the self-isolation trench 19, and the isolation unit N+ source region 29 is in contact with the outer side wall of the self-isolation trench 19. When the first electrode metal of the device is electrically connected to the isolation unit N+ source region 29 and the P-type base region 7, a conductive channel can be formed on the outer side wall of the self-isolation trench 19 when the shielded gate power device is in operation, and at this time, the on-resistance of the shielded gate power device can be reduced.

本发明的一种实施例中,对自隔离单元,还包括设置于自隔离沟槽19外侧的隔离单元P+注入区24以及与所述隔离单元P+注入区24对应的隔离单元外接触孔25,其中,In one embodiment of the present invention, the self-isolation unit further includes an isolation unit P+ injection region 24 disposed outside the self-isolation trench 19 and an isolation unit external contact hole 25 corresponding to the isolation unit P+ injection region 24, wherein:

所述隔离单元P+注入区24贯穿自隔离沟槽19外侧的P型基区7,隔离单元P+注入区24的掺杂浓度大于P型基区7的掺杂浓度,且隔离单元P+注入区24的底部位于P型基区7底面的下方;The isolation unit P+ injection region 24 penetrates the P-type base region 7 outside the isolation trench 19, the doping concentration of the isolation unit P+ injection region 24 is greater than the doping concentration of the P-type base region 7, and the bottom of the isolation unit P+ injection region 24 is located below the bottom surface of the P-type base region 7;

隔离单元P+注入区24与自隔离沟槽19相应的外侧壁接触,且隔离单元P+注入区24与填充在隔离单元外接触孔25内的器件第一电极金属欧姆接触。The isolation unit P+ implantation region 24 contacts the corresponding outer sidewall of the self-isolation trench 19 , and the isolation unit P+ implantation region 24 makes ohmic contact with the first electrode metal of the device filled in the isolation unit external contact hole 25 .

由图2~图3以及上述说明可知,当在自隔离沟槽19的外侧设置隔离单元N+源区29时,可在自隔离沟槽19的外侧形成导电沟道。为了减少导电沟道的影响,进一步提升屏蔽栅功率器件的耐压,图4~图5中,在自隔离沟槽19的外侧设置隔离单元P+注入区24以及与隔离单元P+注入区24对应的隔离单元外接触孔25,也即隔离单元外接触孔25与隔离单元P+注入区24呈一一对应。具体地,隔离单元P+注入区24贯穿P型基区7,隔离单元P+注入区24的结深大于P型基区7的结深,也即隔离单元P+注入区24的底部位于P型基区7的下方,隔离单元P+注入区24与P型基区7接触。As can be seen from FIG. 2 to FIG. 3 and the above description, when the isolation unit N+ source region 29 is set on the outside of the self-isolation groove 19, a conductive channel can be formed on the outside of the self-isolation groove 19. In order to reduce the influence of the conductive channel and further improve the withstand voltage of the shielded gate power device, in FIG. 4 to FIG. 5, an isolation unit P+ injection region 24 and an isolation unit external contact hole 25 corresponding to the isolation unit P+ injection region 24 are set on the outside of the self-isolation groove 19, that is, the isolation unit external contact hole 25 is in one-to-one correspondence with the isolation unit P+ injection region 24. Specifically, the isolation unit P+ injection region 24 penetrates the P-type base region 7, and the junction depth of the isolation unit P+ injection region 24 is greater than the junction depth of the P-type base region 7, that is, the bottom of the isolation unit P+ injection region 24 is located below the P-type base region 7, and the isolation unit P+ injection region 24 is in contact with the P-type base region 7.

图4~图5中,隔离单元P+注入区24与自隔离沟槽19相应的外侧壁接触,隔离单元外接触孔25至少沿自隔离沟槽19的外侧壁分布,当在自隔离沟槽19的外侧壁设置隔离单元外接触孔25后,则在自隔离沟槽19的外侧壁没有上述的隔离单元N+源区29,也即在自隔离沟槽19的外壁无法形成导电沟道。In Figures 4 and 5, the isolation unit P+ injection region 24 contacts the corresponding outer side wall of the self-isolation trench 19, and the isolation unit external contact hole 25 is distributed at least along the outer side wall of the self-isolation trench 19. When the isolation unit external contact hole 25 is set on the outer side wall of the self-isolation trench 19, there is no above-mentioned isolation unit N+ source region 29 on the outer side wall of the self-isolation trench 19, that is, a conductive channel cannot be formed on the outer wall of the self-isolation trench 19.

具体地,隔离单元P+注入区24可有效降低所接触P型基区7的电场,由于隔离单元P+注入区24邻近类肖特基二极管,从而可进一步缓解类肖特基管二极管的槽内栅氧化层16处电场集中,降低漏电。此外,通过隔离单元P+注入区24还可形成热载流子的抽取通道,进一步增强屏蔽栅功率器件的雪崩能力。Specifically, the isolation unit P+ injection region 24 can effectively reduce the electric field of the contacted P-type base region 7. Since the isolation unit P+ injection region 24 is adjacent to the Schottky-like diode, the electric field concentration at the gate oxide layer 16 in the trench of the Schottky-like diode can be further alleviated, thereby reducing leakage. In addition, a hot carrier extraction channel can be formed through the isolation unit P+ injection region 24, further enhancing the avalanche capability of the shielded gate power device.

隔离单元外接触孔25的深度要小于隔离单元P+注入区24的深度。具体实施时,器件第一电极金属可填充在隔离单元外接触孔25内,此时,器件第一电极金属与隔离单元P+注入区24欧姆接触,并通过隔离单元P+注入区24可与P型基区7电连接。The depth of the isolation unit external contact hole 25 is smaller than the depth of the isolation unit P+ injection region 24. In a specific implementation, the device first electrode metal can be filled in the isolation unit external contact hole 25. At this time, the device first electrode metal is in ohmic contact with the isolation unit P+ injection region 24, and can be electrically connected to the P-type base region 7 through the isolation unit P+ injection region 24.

本发明的一种实施例中,在所述屏蔽栅功率器件的截面上,隔离单元外接触孔25呈梯形状,其中,In one embodiment of the present invention, in the cross section of the shielded gate power device, the isolation unit external contact hole 25 is in a trapezoidal shape, wherein:

隔离单元外接触孔25第一端的宽度小于所述隔离单元外接触孔25第二端的宽度,其中,隔离单元外接触孔25第一端位于自隔离沟槽19槽口的下方;The width of the first end of the isolation unit external contact hole 25 is smaller than the width of the second end of the isolation unit external contact hole 25, wherein the first end of the isolation unit external contact hole 25 is located below the notch of the self-isolation trench 19;

隔离单元外接触孔25第二端的宽度大于隔离单元P+注入区24的宽度,以使得隔离单元外接触孔25的第二端进入自隔离沟槽19的槽口区域。The width of the second end of the isolation unit external contact hole 25 is greater than the width of the isolation unit P+ implantation region 24 , so that the second end of the isolation unit external contact hole 25 enters the notch region of the self-isolation trench 19 .

图4~图5中,隔离单元外接触孔25可呈梯形状,隔离单元外接触孔25具有第一端以及与所述第一端对应的第二端,其中,隔离单元外接触孔25第一端位于自隔离沟槽19槽口的下方,且隔离单元外接触孔25的第一端邻近自隔离沟槽19的槽底,此时,隔离单元外接触孔25的第二端与自隔离沟槽19的槽口对应。In Figures 4 to 5, the isolation unit external contact hole 25 may be trapezoidal in shape, and the isolation unit external contact hole 25 has a first end and a second end corresponding to the first end, wherein the first end of the isolation unit external contact hole 25 is located below the notch of the self-isolation groove 19, and the first end of the isolation unit external contact hole 25 is adjacent to the bottom of the self-isolation groove 19, at this time, the second end of the isolation unit external contact hole 25 corresponds to the notch of the self-isolation groove 19.

本发明的一种实施例中,隔离单元外接触孔25第一端的宽度小于所述隔离单元外接触孔25第二端的宽度,且隔离单元外接触孔25第二端的宽度大于隔离单元P+注入区24的宽度,以使得隔离单元外接触孔25的第二端进入自隔离沟槽19的槽口区域,如图4~图5所示,此时,刻蚀形成隔离单元外接触孔25时,会对自隔离沟槽19槽口的隔离沟槽内氧化层20进行部分刻蚀掉,可增大隔离单元外接触孔25的宽度。In one embodiment of the present invention, the width of the first end of the isolation unit external contact hole 25 is smaller than the width of the second end of the isolation unit external contact hole 25, and the width of the second end of the isolation unit external contact hole 25 is larger than the width of the isolation unit P+ injection region 24, so that the second end of the isolation unit external contact hole 25 enters the notch area of the self-isolation groove 19, as shown in Figures 4 and 5. At this time, when etching to form the isolation unit external contact hole 25, the oxide layer 20 in the isolation trench of the notch of the self-isolation groove 19 will be partially etched away, which can increase the width of the isolation unit external contact hole 25.

增大隔离单元外接触孔25的宽度后,可进一步增强隔离单元P+注入区24的注入深度,由上述说明可知,增强隔离单元P+注入区24的注入深度后,利用隔离单元P+注入区24可进一步增加对槽内栅氧化层16的保护,也即可进一步缓解类肖特基二极管的槽内栅氧化层16处电场集中,降低发生在类肖特基二极管的槽内栅氧化层16处的漏电。具体实施时,可先自隔离沟槽19的外侧刻蚀形成隔离单元外接触孔25,在制备得到隔离单元外接触孔25后,再进行P型杂质离子注入,以形成隔离单元P+注入区24。After increasing the width of the isolation unit external contact hole 25, the injection depth of the isolation unit P+ injection region 24 can be further enhanced. As can be seen from the above description, after enhancing the injection depth of the isolation unit P+ injection region 24, the isolation unit P+ injection region 24 can be used to further increase the protection of the gate oxide layer 16 in the trench, which can further alleviate the electric field concentration at the gate oxide layer 16 in the trench of the Schottky-like diode, and reduce the leakage at the gate oxide layer 16 in the trench of the Schottky-like diode. In specific implementation, the isolation unit external contact hole 25 can be first etched from the outside of the isolation trench 19 to form the isolation unit external contact hole 25. After the isolation unit external contact hole 25 is prepared, P-type impurity ions are implanted to form the isolation unit P+ injection region 24.

本发明的一种实施例中,对任一SGT元胞,在所述SGT元胞的元胞沟槽3内设置SGT结构,其中,In one embodiment of the present invention, for any SGT cell, an SGT structure is provided in the cell groove 3 of the SGT cell, wherein:

所述SGT结构采用上下结构时,所述SGT结构包括元胞下电极体6以及元胞上电极体8,元胞上电极体8位于元胞下电极体6的上方,且元胞上电极体8与元胞下电极体6间绝缘隔离;When the SGT structure adopts a top-bottom structure, the SGT structure includes a cell bottom electrode body 6 and a cell top electrode body 8, the cell top electrode body 8 is located above the cell bottom electrode body 6, and the cell top electrode body 8 is insulated and isolated from the cell bottom electrode body 6;

所述元胞上电极体8通过元胞栅氧化层10与所在元胞沟槽3的侧壁绝缘隔离;The cell upper electrode body 8 is insulated and isolated from the sidewall of the cell trench 3 by the cell gate oxide layer 10;

元胞栅氧化层10的厚度大于槽内栅氧化层16的厚度;The thickness of the cell gate oxide layer 10 is greater than the thickness of the in-groove gate oxide layer 16;

所述元胞上电极体8与半导体基板上方的器件第二电极金属电连接,元胞下电极体6与器件第一电极金属电连接。The cell upper electrode body 8 is electrically connected to the second electrode metal of the device above the semiconductor substrate, and the cell lower electrode body 6 is electrically connected to the first electrode metal of the device.

图1~图5中示出了在元胞沟槽3内设置SGT结构,且SGT结构采用上下结构的一种实施例,其中,SGT结构包括元胞下电极体6以及元胞上电极体8,由上述说明可知,元胞下电极体6以及元胞上电极体8一般可采用导电多晶硅,当然,也可以采用其他的导电材料,具体材料的类型可根据需要选择。图1~图5中,元胞上电极体8位于元胞下电极体6的上方,此时,在元胞沟槽3内,元胞上电极体8邻近元胞沟槽3的槽口,而元胞下电极体6更邻近元胞沟槽3的槽底。FIG. 1 to FIG. 5 show an embodiment in which an SGT structure is arranged in a cell groove 3, and the SGT structure adopts an upper and lower structure, wherein the SGT structure includes a cell lower electrode body 6 and a cell upper electrode body 8. As can be seen from the above description, the cell lower electrode body 6 and the cell upper electrode body 8 can generally be made of conductive polysilicon. Of course, other conductive materials can also be used, and the type of specific material can be selected as needed. In FIG. 1 to FIG. 5, the cell upper electrode body 8 is located above the cell lower electrode body 6. At this time, in the cell groove 3, the cell upper electrode body 8 is adjacent to the notch of the cell groove 3, and the cell lower electrode body 6 is closer to the groove bottom of the cell groove 3.

由SGT元胞原理可知,在元胞沟槽3内,元胞上电极体8与元胞下电极体6间需绝缘隔离,且元胞上电极体8与器件第二电极金属电连接,元胞下电极体6与器件第一电极金属电连接,由上述说明可知,器件第一电极金属可形成屏蔽栅功率器件的第一电极;此时,利用器件第二电极金属可形成屏蔽栅功率器件的第二电极,当屏蔽栅功率器件为SGT MOSFET器件时,则第二电极为SGT MOSFET器件的栅电极,当屏蔽栅功率器件为SGT IGBT器件时,则第二电极为SGT IGBT器件的门极,当屏蔽栅功率器件为其他类型的功率器件时,则能得到基于器件第二电极金属形成第二电极的类型,此处不再赘述。It can be known from the SGT cell principle that in the cell groove 3, the cell upper electrode body 8 and the cell lower electrode body 6 need to be insulated and isolated, and the cell upper electrode body 8 is electrically connected to the second electrode metal of the device, and the cell lower electrode body 6 is electrically connected to the first electrode metal of the device. It can be seen from the above description that the first electrode metal of the device can form the first electrode of the shielded gate power device; at this time, the second electrode of the shielded gate power device can be formed by using the second electrode metal of the device. When the shielded gate power device is an SGT MOSFET device, the second electrode is the gate electrode of the SGT MOSFET device. When the shielded gate power device is an SGT IGBT device, the second electrode is the gate of the SGT IGBT device. When the shielded gate power device is other types of power devices, the type of second electrode formed based on the second electrode metal of the device can be obtained, which will not be repeated here.

为了能实现元胞上电极体8与元胞下电极体6之间的绝缘隔离,在元胞沟槽3内设置层间氧化层9,利用层间氧化层9可实现元胞上电极体8与元胞下电极体6之间的绝缘隔离。此外,在元胞沟槽3内设置元胞场氧化层5,元胞场氧化层5与元胞下电极体6对应,元胞场氧化层5覆盖在元胞沟槽3的侧壁以及底壁,因此,元胞下电极体6可利用元胞场氧化层5可与所在元胞沟槽3的侧壁以及底壁绝缘隔离,当然,层间氧化层9与元胞场氧化层5接触连接。In order to achieve insulation isolation between the cell upper electrode body 8 and the cell lower electrode body 6, an interlayer oxide layer 9 is provided in the cell groove 3, and insulation isolation between the cell upper electrode body 8 and the cell lower electrode body 6 can be achieved by using the interlayer oxide layer 9. In addition, a cell field oxide layer 5 is provided in the cell groove 3, the cell field oxide layer 5 corresponds to the cell lower electrode body 6, and the cell field oxide layer 5 covers the side wall and the bottom wall of the cell groove 3, so the cell lower electrode body 6 can be insulated and isolated from the side wall and the bottom wall of the cell groove 3 by using the cell field oxide layer 5, and of course, the interlayer oxide layer 9 is in contact with the cell field oxide layer 5.

元胞上电极体8与所在元胞沟槽3内的元胞栅氧化层10对应接触,元胞栅氧化层10覆盖在元胞沟槽3相应的侧壁。需要说明的是,元胞栅氧化层10、元胞场氧化层5以及层间氧化层9均为二氧化硅层,可通过热氧化工艺制备形成;元胞栅氧化层10的厚度要小于元胞场氧化层5的厚度,此外,元胞栅氧化层10的厚度,要小于槽内栅氧化层16的厚度,由此可知,类肖特基二极管的开启电压要小于SGT元胞的开启电压。The cell upper electrode body 8 is in corresponding contact with the cell gate oxide layer 10 in the cell trench 3, and the cell gate oxide layer 10 covers the corresponding side wall of the cell trench 3. It should be noted that the cell gate oxide layer 10, the cell field oxide layer 5 and the interlayer oxide layer 9 are all silicon dioxide layers, which can be prepared by thermal oxidation process; the thickness of the cell gate oxide layer 10 is less than the thickness of the cell field oxide layer 5, and in addition, the thickness of the cell gate oxide layer 10 is less than the thickness of the gate oxide layer 16 in the groove, so it can be seen that the turn-on voltage of the Schottky-like diode is less than the turn-on voltage of the SGT cell.

当元胞栅氧化层10的厚度小于元胞场氧化层5的厚度时,则元胞上电极体8的宽度应大于元胞下电极体6的宽度;此外,图1~图5中,在元胞沟槽3内还设置槽口氧化层11,利用槽口氧化层11可对元胞上电极体8进行覆盖,以能实现元胞上电极体8与器件第一电极金属间的绝缘隔离。进一步地,元胞上电极体8邻近元胞沟槽3槽底的一端表面位于P型基区7底面的下方。When the thickness of the cell gate oxide layer 10 is less than the thickness of the cell field oxide layer 5, the width of the cell upper electrode body 8 should be greater than the width of the cell lower electrode body 6; in addition, in Figures 1 to 5, a notch oxide layer 11 is also provided in the cell groove 3, and the notch oxide layer 11 can be used to cover the cell upper electrode body 8, so as to achieve insulation isolation between the cell upper electrode body 8 and the first electrode metal of the device. Further, the end surface of the cell upper electrode body 8 adjacent to the bottom of the cell groove 3 is located below the bottom surface of the P-type base region 7.

为了能形成SGT元胞的导电沟道,在元胞沟槽3的外侧壁应设置元胞N+源区12,元胞N+源区12位于与元胞沟槽3接触的P型基区7内,且元胞N+源区12与对应的元胞沟槽3的外侧壁接触,同时,元胞N+源区12以及所在的P型基区7均需与器件第一电极金属欧姆接触。为了能实现与器件第一电极金属间的欧姆接触,图1~图3中,在P型基区7内设置接触P+注入区13,接触P+注入区13的掺杂浓度大于P型基区7的掺杂浓度,接触P+注入区13与元胞N+源区12接触,此时,器件第一电极金属可与元胞N+源区12欧姆接触,并通过接触P+注入区13实现与相应P型基区7的电连接。In order to form a conductive channel of the SGT cell, a cell N+ source region 12 should be set on the outer side wall of the cell trench 3. The cell N+ source region 12 is located in the P-type base region 7 in contact with the cell trench 3, and the cell N+ source region 12 contacts the outer side wall of the corresponding cell trench 3. At the same time, the cell N+ source region 12 and the P-type base region 7 in which it is located need to be in ohmic contact with the first electrode metal of the device. In order to achieve ohmic contact with the first electrode metal of the device, in Figures 1 to 3, a contact P+ injection region 13 is set in the P-type base region 7, and the doping concentration of the contact P+ injection region 13 is greater than the doping concentration of the P-type base region 7. The contact P+ injection region 13 contacts the cell N+ source region 12. At this time, the first electrode metal of the device can be in ohmic contact with the cell N+ source region 12, and the electrical connection with the corresponding P-type base region 7 is achieved through the contact P+ injection region 13.

需要说明的是,接触P+注入区13可通过在P型基区7内进行离子注入形成,图1~图3中示出了直接在P型基区7内进行离子注入,并形成接触P+注入区13的实施例。It should be noted that the contact P+ implantation region 13 can be formed by ion implantation in the P-type base region 7 . FIGS. 1 to 3 show an embodiment of directly performing ion implantation in the P-type base region 7 to form the contact P+ implantation region 13 .

具体实施时,元胞沟槽3、类二极管沟槽4以及自隔离沟槽19均呈长条状,且元胞沟槽3、类二极管沟槽4以及自隔离沟槽19间相互平行。In a specific implementation, the cell trench 3 , the diode-like trench 4 , and the self-isolation trench 19 are all in the shape of long strips, and the cell trench 3 , the diode-like trench 4 , and the self-isolation trench 19 are parallel to each other.

下面对有源区内设置类肖特基二极管可提升屏蔽栅功率器件的恢复能力进行说明,具体地:The following is an explanation of how the Schottky-like diodes in the active region can improve the recovery capability of the shielded gate power device, specifically:

当屏蔽栅功率器件的器件第一电极金属处流过反向恢复电流时,电流流过类肖特基二极管处会产生压降,进而类肖特基二极管处为正电压。由于槽内栅氧化层16的厚度小于元胞栅氧化层10的厚度,因此,P型基区7与外延层2间的PN结正向偏压增加到0.7v之前,槽内栅氧化层16处的沟道便能够比元胞栅氧化层10处的沟道先导通,进而使得P型基区7与外延层2间的PN结正向偏压小于0.7v。也即PN结导通之前,类肖特基二极管处的沟道便已经导通,造成了PN结内部的移动电荷流失消耗,使得PN结内部的移动电荷无法累积,导致PN结的电压无法升到0.7v,借此PN结的耗尽区受电压影响产生的变化量减小,PN结能够更快速的恢复,由此实现了减小屏蔽栅功率器件的反向恢复电荷Qrr和反向恢复时间Trr,提高屏蔽栅功率器件的反向恢复特性。When a reverse recovery current flows through the first electrode metal of the shielded gate power device, a voltage drop will be generated when the current flows through the Schottky-like diode, and then the Schottky-like diode is at a positive voltage. Since the thickness of the gate oxide layer 16 in the groove is less than the thickness of the cell gate oxide layer 10, before the forward bias voltage of the PN junction between the P-type base region 7 and the epitaxial layer 2 increases to 0.7v, the channel at the gate oxide layer 16 in the groove can be turned on before the channel at the cell gate oxide layer 10, thereby making the forward bias voltage of the PN junction between the P-type base region 7 and the epitaxial layer 2 less than 0.7v. That is, before the PN junction is turned on, the channel at the Schottky-like diode has already been turned on, causing the mobile charge inside the PN junction to be lost and consumed, making it impossible for the mobile charge inside the PN junction to accumulate, resulting in the voltage of the PN junction unable to rise to 0.7V. As a result, the change in the depletion region of the PN junction affected by the voltage is reduced, and the PN junction can recover more quickly, thereby reducing the reverse recovery charge Qrr and reverse recovery time Trr of the shielded gate power device and improving the reverse recovery characteristics of the shielded gate power device.

本发明的一种实施例中,在有源区内,设置若干源区接触孔单元,其中,In one embodiment of the present invention, a plurality of source region contact hole units are arranged in the active region, wherein:

所述源区接触孔单元至少分布于相邻的两个SGT元胞之间;The source region contact hole unit is distributed at least between two adjacent SGT cells;

所述源区接触孔单元包括源区接触孔27以及位于所述源区接触孔27正下方的接触孔下P+注入区23,其中,The source contact hole unit includes a source contact hole 27 and a contact hole P+ implantation region 23 located directly below the source contact hole 27, wherein:

接触孔下P+注入区23的掺杂浓度大于P型基区7的掺杂浓度,接触孔下P+注入区23位于P型基区7的下方,且与对应的P型基区7接触;The doping concentration of the P+ injection region 23 under the contact hole is greater than the doping concentration of the P-type base region 7. The P+ injection region 23 under the contact hole is located below the P-type base region 7 and contacts the corresponding P-type base region 7.

器件第一电极金属填充在源区接触孔27内,且器件第一电极金属与接触孔下P+注入区23、P型基区7以及所填充源区接触孔两侧的元胞N+源区12欧姆接触;The first electrode metal of the device is filled in the source contact hole 27, and the first electrode metal of the device is in ohmic contact with the P+ injection region 23 under the contact hole, the P-type base region 7, and the cell N+ source region 12 on both sides of the filled source contact hole;

元胞N+源区12与对应元胞沟槽3的外侧壁接触。The cell N+ source region 12 contacts the outer sidewall of the corresponding cell trench 3 .

为了能进一步保护类肖特基二极管,在有源区内还可设置源区接触孔单元,其中,源区接触孔单元至少分布于相邻的两个SGT元胞之间,如图4所示,当然,源区接触孔单元还可以分布于类肖特基二极管与SGT元胞之间,如图4和图5所示,源极接触孔单元分布于类肖特基二极管与SGT元胞之间时,具体可根据类肖特基二极管的分布位置相关;具体地,源区接触孔单元与上述的接触P+注入区13对应,也即通过对接触P+注入区13所在的位置进行改进,以能进一步提升屏蔽栅功率器件的耐压,达到对类肖特基二极管保护的目的。In order to further protect the Schottky-like diode, a source contact hole unit may be provided in the active region, wherein the source contact hole unit is distributed between at least two adjacent SGT cells, as shown in FIG4 . Of course, the source contact hole unit may also be distributed between the Schottky-like diode and the SGT cell, as shown in FIG4 and FIG5 . When the source contact hole unit is distributed between the Schottky-like diode and the SGT cell, it may be specifically related to the distribution position of the Schottky-like diode; specifically, the source contact hole unit corresponds to the above-mentioned contact P+ injection region 13, that is, by improving the position of the contact P+ injection region 13, the withstand voltage of the shielded gate power device can be further improved, thereby achieving the purpose of protecting the Schottky-like diode.

图4和图5中示出了源区接触孔单元的一种实施例,图中,源区接触孔单元包括源区接触孔27以及位于所述源区接触孔27正下方的接触孔下P+注入区23,由上述说明可知,源区接触孔27所在的位置可与上述接触P+注入区13所在的位置,不同的是,源区接触孔27的宽度要大于接触P+注入区13的宽度,可以理解的时,当设置图1~图3所示的接触P+注入区13时,在满足器件第一电极金属的连接情况下,可省去开设接触孔的步骤。而在有源区内设置源区接触孔27时,则必须在元胞沟槽3的外侧和/或类二极管沟槽4的外侧设置源区接触孔27,源区接触孔27可采用本技术领域常用的接触孔工艺制备形成。FIG. 4 and FIG. 5 show an embodiment of a source contact hole unit. In the figure, the source contact hole unit includes a source contact hole 27 and a contact hole P+ injection area 23 located directly below the source contact hole 27. As can be seen from the above description, the location of the source contact hole 27 can be the same as the location of the contact P+ injection area 13. The difference is that the width of the source contact hole 27 is greater than the width of the contact P+ injection area 13. It can be understood that when the contact P+ injection area 13 shown in FIG. 1 to FIG. 3 is set, the step of opening the contact hole can be omitted under the condition that the connection of the first electrode metal of the device is met. When the source contact hole 27 is set in the active area, the source contact hole 27 must be set outside the cell trench 3 and/or outside the diode-like trench 4. The source contact hole 27 can be prepared and formed using the contact hole process commonly used in the technical field.

本发明的一种实施例中,源区接触孔27的深度至少与P型基区7的厚度相一致,此时,源区接触孔27的孔口位于外延层2的表面,源区接触孔27的孔底与P型基区7的底面平齐,或者,源区接触孔27的孔底位于P型基区7的下方,此时,源区接触孔27与两侧的元胞N+源区12接触。具体实施时,在开设源区接触孔27后,可通过离子注入工艺,在源区接触孔27的下方形成接触孔下P+注入区23,接触孔下P+注入区23的掺杂浓度大于P型基区7的掺杂浓度,接触孔下P+注入区23与对应的P型基区7接触,如图4和图5所示。In one embodiment of the present invention, the depth of the source contact hole 27 is at least consistent with the thickness of the P-type base region 7. At this time, the opening of the source contact hole 27 is located on the surface of the epitaxial layer 2, and the bottom of the source contact hole 27 is flush with the bottom surface of the P-type base region 7, or the bottom of the source contact hole 27 is located below the P-type base region 7. At this time, the source contact hole 27 contacts the cell N+ source regions 12 on both sides. In specific implementation, after the source contact hole 27 is opened, an ion implantation process can be used to form a P+ implantation region 23 below the source contact hole 27. The doping concentration of the P+ implantation region 23 below the contact hole is greater than the doping concentration of the P-type base region 7, and the P+ implantation region 23 below the contact hole contacts the corresponding P-type base region 7, as shown in Figures 4 and 5.

当在源区接触孔27内填充器件第一电极金属后,器件第一电极金属会与源区接触孔27两侧的元胞N+源区12、P型基区7以及接触孔下P+注入区23欧姆接触;此时,可利用接触孔下P+注入区23实现分散电场,也即可进一步减少电场在类肖特基二极管内槽内栅氧化层16的聚集,降低在类肖特基二极管内槽内栅氧化层16处发生漏电的可能性。After the first electrode metal of the device is filled in the source contact hole 27, the first electrode metal of the device will make ohmic contact with the cell N+ source region 12, the P-type base region 7 and the P+ injection region 23 under the contact hole on both sides of the source contact hole 27; at this time, the P+ injection region 23 under the contact hole can be used to achieve a dispersed electric field, which can further reduce the concentration of the electric field in the gate oxide layer 16 in the inner groove of the Schottky-like diode, thereby reducing the possibility of leakage at the gate oxide layer 16 in the inner groove of the Schottky-like diode.

Claims (9)

1. A shielded gate power device with low leakage and fast recovery capability, the shielded gate power device comprising:
a semiconductor substrate of a first conductivity type;
An active region distributed in a central region of the semiconductor substrate and comprising a plurality of SGT cells and at least one Schottky-like diode, wherein,
The schottky-like diode is a trench schottky-like diode, and comprises a diode-like trench located in the active region;
in the active region, the groove depth of the diode-like groove is larger than the groove depth of a cell groove of any SGT cell;
For the schottky-like diode, comprising a diode electrode body filled in the diode-like trench, wherein,
The diode electrode body comprises a first electrode body in a groove and a second electrode body in the groove corresponding to the first electrode body in the groove, and the second electrode body in the groove is adjacent to a notch of the diode-like groove;
The first electrode body in the groove comprises a first area of the first electrode body in the groove entering the second electrode body in the groove and a second area of the first electrode body in the groove below the second electrode body in the groove, wherein,
The first region of the first electrode body in the groove is separated from the second electrode body in the groove by an electrode body isolation medium layer, and the second region of the first electrode body in the groove is isolated from the bottom wall and the corresponding side wall of the diode-like groove by using a field oxide layer in the groove;
The second electrode body in the groove is insulated and isolated from the side wall of the diode-like groove by the gate oxide layer in the groove, the thickness of the gate oxide layer in the groove is smaller than that of the field oxide layer in the groove, and the gate oxide layer in the groove is contacted with the field oxide layer in the groove;
the first electrode body in the groove and the second electrode body in the groove are electrically connected with the first electrode metal of the device above the semiconductor substrate, wherein,
The device first electrode metal is also in ohmic contact with the diode first conductivity type source region corresponding to the outside of the diode-like trench and the second conductivity type base region traversing the active region,
The diode first conduction type source region and the second conduction type base region are both in contact with the outer side wall of the diode-like groove.
2. The shielded gate power device with low leakage and fast recovery capability of claim 1, wherein a width of the second electrode body in the trench is greater than a width of the first electrode body in the trench in the diode-like trench;
the width of the first area of the first electrode body in the groove is smaller than that of the second area of the first electrode body in the groove;
the end face of the first region of the first electrode body in the groove is positioned above the bottom face of the second conductive type base region;
the end face of the second electrode body in the groove, which is adjacent to the bottom of the diode-like groove, is not higher than the bottom face of the second conductive type base region.
3. The shielded gate power device with low leakage and fast recovery capability according to claim 1, wherein a self-isolation cell is provided in the active region at least on one side of the schottky-like diode, wherein,
The self-isolation unit comprises a self-isolation groove and an isolation unit electrode body filled in the self-isolation groove;
The isolation unit electrode body is isolated from the side wall and the bottom wall of the self-isolation groove through an oxide layer in the isolation groove;
the isolation unit electrode body is electrically connected with the first electrode metal of the device.
4. A shielded gate power device with low leakage and fast recovery capability according to claim 3, wherein the self-isolation trench has a trench depth in the active region that corresponds to the trench depth of the diode-like trench;
the height of the isolation unit electrode body is consistent with that of the first electrode body in the groove, and the second end part of the isolation unit electrode body is level with the end part of the first area of the first electrode body in the groove;
The first end of the isolation unit electrode body is adjacent to the bottom of the self-isolation trench.
5. The shielded gate power device with low leakage and fast recovery capability according to claim 3, further comprising an isolation cell source region of a first conductivity type outside the self-isolation trench for the self-isolation cell, wherein,
The isolation unit first conductive type source region is positioned in the second conductive type base region outside the self-isolation trench, and the isolation unit first conductive type source region and the second conductive type base region are both in contact with the outer side wall of the self-isolation trench;
the first electrode metal of the device is also electrically connected with the first conductive type source region and the second conductive type base region of the isolation unit.
6. The device of claim 3, further comprising an isolation cell second conductivity type injection region disposed outside the self-isolation trench and an isolation cell external contact hole corresponding to the isolation cell second conductivity type injection region for the self-isolation cell,
The second conductive type injection region of the isolation unit penetrates through the second conductive type base region outside the isolation groove, the doping concentration of the second conductive type injection region of the isolation unit is larger than that of the second conductive type base region, and the bottom of the second conductive type injection region of the isolation unit is positioned below the bottom surface of the second conductive type base region;
The isolation unit second conductivity type injection region is in contact with the corresponding outer side wall of the self-isolation trench, and the isolation unit second conductivity type injection region is in ohmic contact with the device first electrode metal filled in the isolation unit outer contact hole.
7. The shielded gate power device with low leakage and fast recovery capability according to claim 6, wherein the isolation cell outer contact hole has a trapezoid shape in a cross section of the shielded gate power device, wherein,
The width of the first end of the outer contact hole of the isolation unit is smaller than that of the second end of the outer contact hole of the isolation unit, wherein the first end of the outer contact hole of the isolation unit is positioned below a notch of the self-isolation groove;
The width of the second end of the isolation unit outer contact hole is greater than the width of the isolation unit second conductivity type injection region, so that the second end of the isolation unit outer contact hole enters the notch region of the self-isolation trench.
8. The shielded gate power device with low leakage and fast recovery capability according to any one of claims 1 to 7, wherein for any one SGT cell, an SGT structure is provided in a cell trench of said SGT cell, wherein,
When the SGT structure adopts an up-down structure, the SGT structure comprises a cell lower electrode body and a cell upper electrode body, wherein the cell upper electrode body is positioned above the cell lower electrode body, and the cell upper electrode body is insulated and isolated from the cell lower electrode body;
the upper electrode body of the cell is insulated and isolated from the side wall of the cell groove through the cell gate oxide layer;
The thickness of the cellular gate oxide layer is larger than that of the gate oxide layer in the groove;
the upper electrode body of the cell is electrically connected with the second electrode metal of the device above the semiconductor substrate, and the lower electrode body of the cell is electrically connected with the first electrode metal of the device.
9. The shielded gate power device with low leakage and fast recovery capability according to claim 8, wherein a plurality of source contact hole cells are disposed in the active region, wherein,
The source region contact hole units are at least distributed between two adjacent SGT unit cells;
The source region contact hole unit comprises a source region contact hole and a contact Kong Xiadi two conductivity type injection region positioned right below the source region contact hole, wherein,
The doping concentration of the contact Kong Xiadi second conductive type injection region is larger than that of the second conductive type base region, and the contact Kong Xiadi second conductive type injection region is positioned below the second conductive type base region and is in contact with the corresponding second conductive type base region;
The first electrode metal of the device is filled in the contact hole of the source region, and is in ohmic contact with the two conductive type injection regions of the contact Kong Xiadi, the second conductive type base region and the cell first conductive type source regions at two sides of the contact hole of the filled source region;
The first conductivity type source region of the cell is in contact with the outer sidewall of the corresponding cell trench.
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