CN118412023A - Integrated unit structure for storage and calculation - Google Patents

Abstract

The invention discloses a storage and calculation integrated unit structure, which comprises: an SRAM memory cell and a function switching cell. The function switching unit includes: first and second storage data control tubes connected between two bit lines, and row and column signal control tubes connected between the intermediate node and the second row signal line in series, the gate connections of the 4 control tubes being connected to the first and second storage nodes and the first row and column signal lines, respectively. The row and column signal control tubes are in a memory configuration state when they are off. The configuration state of the multi-Boolean logic operator is in a pre-charge and discharge state, the row signal control tube is cut off, the column signal control tube is conducted, and the level of the first bit line is the same as that of the second bit line and is opposite to that of the second row signal line; in the operation state, the row signal control tubes of the two rows of units for operation are conducted, and the first and second logic operation results of the two rows of storage signals are respectively output on the two bit lines. The invention can realize the storage and the multi-Boolean logic operation and can also realize the CAM searching function.

Description

Storage and computing integrated unit structure

Technical Field

The present invention relates to a semiconductor integrated circuit, and in particular to a storage-computing integrated unit structure.

Background technique

With the information age, the development of information technology such as AI has led to the expansion of computing needs. Traditional computer architecture has gradually been unable to meet computing needs. The traditional computer architecture adopts the von Neumann system, which separates the processor and the memory, resulting in the frequent transportation of data between the memory and the processor during multiple calculations, which consumes a lot of useless power and limits computing efficiency and speed. This is what we call the von Neumann bottleneck. The static storage unit designed in the present invention uses storage-computing integrated technology to give the memory the ability to calculate, thereby realizing in-memory computing. The SRAM unit currently used in the field of in-memory computing can only realize a single computing function, and cannot realize bidirectional operations of rows and columns, and has poor flexibility and reconfigurability.

Summary of the invention

The technical problem to be solved by the present invention is to provide a storage-computation integrated unit structure, which can realize storage, multiple Boolean logic operations and then realize full Boolean logic operations, and can also realize column CAM search and row CAM search and then realize row and column bidirectional search functions, and can also significantly improve circuit integration to reduce circuit area, and can also improve sensing efficiency.

In order to solve the above technical problems, the storage and computing integrated unit structure provided by the present invention includes: an SRAM storage unit and a function switching unit.

The SRAM storage cell is connected between a first bit line and a second bit line and has a first storage node and a second storage node. A first storage signal of the first storage node and a second storage signal of the second storage node are inverted.

The function switching unit comprises:

A first storage data control tube is connected between the first bit line and the middle node.

A second storage data control transistor is connected between the second bit line and the intermediate node, and the first storage data control transistor and the second storage data control transistor have the same channel conductivity type.

A row signal control tube and a column signal control tube are connected in series between the middle node and the second row signal line.

The gate of the first storage data control transistor is connected to the first storage node.

The gate of the second storage data control transistor is connected to the second storage node.

The gate of the row signal control tube is connected to the first row signal line.

The gate of the column signal control tube is connected to the column signal line.

The storage-computation-in-one unit structure includes a memory configuration state and a multi-Boolean logic operator configuration state.

The signal setting of the memory configuration state includes:

The first row signal of the first row signal line turns off the row signal control tube.

The column signal of the column signal line turns off the column signal control tube.

The signal setting of the multi-Boolean logic operator configuration state includes:

In the pre-charge state, the first row signal of the first row signal line turns off the row signal control tube.

The column signal of the column signal line turns on the column signal control tube.

The first bit line and the second bit line have the same level and are opposite to the level of the second row signal of the second row signal line.

In the operation state, the address signal selects the two rows of the storage-operation-in-one unit structure on the same column that need to perform logic operations.

The first row signals of the first row signal lines of the two rows of the integrated storage and computing unit structures are switched to turn on the row signal control tubes.

The first logic operation result of the first storage signal of the two rows of the integrated storage and calculation unit structures is output on the first bit line.

The second logic operation result of the first storage signal of the two rows of the integrated storage and calculation unit structure is output on the second bit line.

A further improvement is that the integrated storage and computing unit structure also includes a column-wise CAM searcher configuration state.

The signal setting of the column to the CAM searcher configuration state includes:

In the pre-charge state, the first row signal of the first row signal line turns off the row signal control tube.

The column signal of the column signal line turns on the column signal control tube.

The first bit line and the second bit line have opposite voltage levels.

The second row signal of the second row signal line is loaded with data to be matched.

In the column-direction CAM search state, the first row signal of the first row signal line of each row is switched in sequence to turn on the row signal control tube.

A column search matching result signal for judging whether the first storage signal and the to-be-matched data of the corresponding row match is obtained through the logic states of the first bit line signal of the first bit line and the second bit line signal of the second bit line.

A further improvement is that the integrated storage and computing unit structure also includes a row-wise CAM searcher configuration state.

The signal setting of the row-direction CAM searcher configuration state includes:

In the pre-charge state, the first row signal of the first row signal line turns on the row signal control tube.

The column signal of the column signal line turns off the column signal control tube.

The first bit line signal of the first bit line is loaded with data to be matched, and the level of the second bit line is opposite to that of the first bit line.

The second row signal of the second row signal line is set to a high level or a low level.

In the row-direction CAM search state, the column signal of the column signal line of each column is switched in turn to turn on the column signal control tube.

A row search matching result signal for judging whether the first storage signal and the to-be-matched data of the corresponding column match is obtained through the logic state of the second row signal of the second row signal line.

A further improvement is that both the first storage data control tube and the second storage data control tube are NMOS tubes. When the first storage signal is high level and the second storage signal is low level, the first storage data control tube is turned on and the second storage data control tube is turned off.

Alternatively, the first storage data control tube and the second storage data control tube are both PMOS tubes, and when the first storage signal is high level and the second storage signal is low level, the first storage data control tube is turned off and the second storage data control tube is turned on.

A further improvement is that the row signal control tube is an NMOS tube, the row signal control tube is turned on when the first row signal is at a high level, and the row signal control tube is turned off when the first row signal is at a low level.

Alternatively, the row signal control tube is a PMOS tube, and the row signal control tube is turned on when the first row signal is at a low level, and the row signal control tube is turned off when the first row signal is at a high level.

A further improvement is that the column signal control tube adopts an NMOS tube, and the column signal control tube is turned on when the column signal is at a high level, and the column signal control tube is turned off when the column signal is at a low level.

Alternatively, the column signal control tube is a PMOS tube, and the column signal control tube is turned on when the column signal is at a low level, and the column signal control tube is turned off when the column signal is at a high level.

A further improvement is that, when the storage-computation-in-one unit structure is in the operation state of the multi-Boolean logic operator configuration state, the first logic operation result outputs the OR signal or the NOR signal of the first storage signal of two rows of the storage-computation-in-one unit structure through a corresponding number of NOT gates, and the second logic operation result outputs the NAND signal or the AND signal of the first storage signal of two rows of the storage-computation-in-one unit structure through a corresponding number of NOT gates.

Alternatively, when the storage-computation-in-one unit structure is in the operation state of the multi-Boolean logic operator configuration state, the first logic operation result outputs the NAND signal or AND signal of the first storage signal of two rows of the storage-computation-in-one unit structure through a corresponding number of NOT gates, and the second logic operation result outputs the OR signal or NOR signal of the first storage signal of two rows of the storage-computation-in-one unit structure through a corresponding number of NOT gates.

A further improvement is that the function switching unit further includes:

A first NAND gate, wherein a first input terminal of the first NAND gate is respectively connected to the OR signal and a second input terminal is respectively connected to the NAND signal.

The output terminal of the first NAND gate outputs an XENO signal.

A further improvement is that the output end of the first NAND gate also outputs an XOR signal through a NOT gate.

A further improvement is that, when the first storage data control transistor and the second storage data control transistor are both NMOS transistors:

When the storage-computing integrated unit structure is in the column-oriented CAM searcher configuration state, in the pre-charge state, the first bit line is at a high level and the second bit line is at a low level; in the column-oriented CAM search state, when the first bit line or the second bit line has a state change, it indicates that the first storage signal and the data to be matched do not match.

A further improvement is that the integrated storage and computing unit structure also includes a column search matching output circuit.

The column search matching output circuit includes: a first NOR gate, the first bit line is connected to the first input terminal of the first NOR gate through a first-level NOR gate, and the second bit line is connected to the second input terminal of the first NOR gate through two-level NOR gates; when the first NOR gate outputs a high level, it indicates a successful match, and when the first NOR gate outputs a low level, it indicates a failed match.

A further improvement is that, when the first storage data control transistor and the second storage data control transistor are both NMOS transistors:

When the storage-computing integrated unit structure is in the column-oriented CAM searcher configuration state, in the pre-charge state, the first bit line is at a low level and the second bit line is at a high level; in the column-oriented CAM search state, when the first bit line or the second bit line has a state change, it indicates that the first storage signal matches the data to be matched.

A further improvement is that, when both the first storage data control transistor and the second storage data control transistor are PMOS transistors:

When the storage-computing integrated unit structure is in the column-oriented CAM searcher configuration state, in the pre-charge state, the first bit line is at a high level and the second bit line is at a low level; in the column-oriented CAM search state, when the first bit line or the second bit line has a state change, it indicates that the first storage signal matches the data to be matched.

Alternatively, when the storage-computing integrated unit structure is in the column-oriented CAM searcher configuration state, in the pre-charge state, the first bit line is at a low level and the second bit line is at a high level; in the column-oriented CAM search state, when the first bit line or the second bit line has a state change, it indicates that the first storage signal and the data to be matched do not match.

A further improvement is that, when the first storage data control transistor and the second storage data control transistor are both NMOS transistors:

When the storage-computing integrated unit structure is in the row-directed CAM searcher configuration state, in the row-directed CAM search state, when the second row signal is at a high level, the first storage signal and the data to be matched match, and when the second row signal is at a low level, the first storage signal and the data to be matched do not match.

A further improvement is that the second row signal line also outputs the row search matching result signal through a NOT gate.

A further improvement is that, when both the first storage data control transistor and the second storage data control transistor are PMOS transistors:

When the storage-computing integrated unit structure is in the row-directed CAM searcher configuration state, in the row-directed CAM search state, when the second row signal is at a high level, the first storage signal and the data to be matched do not match, and when the second row signal is at a low level, the first storage signal and the data to be matched match.

A further improvement is that the SRAM memory cell comprises a 6T SRAM memory cell.

The present invention sets a function switching unit on the basis of an SRAM storage unit. The function switching unit can realize a first storage data control tube, a second storage data control tube, a row signal control tube and a column signal control tube through four transistors. The present invention also makes a special setting for the control signal of each transistor of the function switching unit, that is, the signal connected to the gate. Combined with the signal setting, the storage-calculation integrated unit structure can be set in a memory configuration state and a multi-Boolean logic operator configuration state. Combined with the peripheral logic circuit, full Boolean logic operation can also be realized.

The present invention can further enable the storage-computation integrated unit structure to be in a column-oriented CAM searcher configuration state and a row-oriented CAM searcher configuration state, thereby realizing a row-column bidirectional search function.

Since the present invention can realize full Boolean operations and realize bidirectional operations of rows and columns, the present invention has the characteristics of high flexibility and good reconfigurability.

In addition, the present invention does not need to use a sensitive amplifier to sense the signal line, but uses a logic gate instead of a sensitive amplifier to sense the signal line, which can significantly improve the circuit integration and thus reduce the circuit area, and can also improve the sensing efficiency.

In addition, when the SRAM storage unit of the present invention adopts a standard 6T SRAM storage unit, combined with the 4 transistors of the function switching unit, it can be known that the storage and computing integrated unit structure of the present invention can realize a 10T unit structure, that is, it can be realized with 10 transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

FIG1 is a circuit diagram of a storage-computation-in-one unit structure according to an embodiment of the present invention;

2 is a circuit diagram of a storage-computation-in-one unit structure in a memory configuration state according to an embodiment of the present invention;

3 is a circuit diagram of a storage-computation-in-one unit structure in a multi-Boolean logic operator configuration state according to an embodiment of the present invention;

4 is a circuit diagram of a storage-computation-in-one unit structure in a column-oriented CAM searcher configuration state according to an embodiment of the present invention;

5 is a circuit diagram of the storage-computation-in-one unit structure in the row-direction CAM searcher configuration state according to an embodiment of the present invention.

Detailed ways

As shown in FIG. 1 , it is a circuit diagram of a storage-computing integrated unit structure 101 according to an embodiment of the present invention; the storage-computing integrated unit structure 101 according to an embodiment of the present invention includes: an SRAM storage unit 102 and a function switching unit 103 .

The SRAM storage cell 102 is connected between a first bit line BL and a second bit line BLB and has a first storage node and a second storage node. A first storage signal Q of the first storage node and a second storage signal QB of the second storage node are inverted.

In the embodiment of the present invention, the SRAM storage unit 102 is a 6T SRAM storage unit, which is a standard SRAM storage unit.

As shown in FIG. 1 , the SRAM storage unit 102 includes:

A first CMOS inverter formed by connecting the PMOS tube P1 and the NMOS tube N1, and a second CMOS inverter formed by connecting the PMOS tube P2 and the NMOS tube N2, the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected to the first storage node, and the input end of the first CMOS inverter and the output end of the second CMOS inverter are connected to the second storage node.

The first bit line BL is connected to the first storage node via an NMOS transistor N3, the second bit line BLB is connected to the second storage node via an NMOS transistor N4, and gates of the NMOS transistors N3 and N4 are both connected to a word line WL.

PMOS tubes P1 and P2 are both pull-up tubes (PU), NMOS tubes N1 and N2 are both pull-down tubes (PD), and NMOS tubes N3 and N4 are both transmission tubes (PG).

In other embodiments, the SRAM memory cell 102 can also be a SRAM memory cell formed by further improving a 6T SRAM memory cell or any other suitable SRAM memory cell.

The function switching unit 103 includes:

A first storage data control transistor 104 is connected between the first bit line BL and the middle node.

The second storage data control transistor 105 is connected between the second bit line BLB and the middle node, and the first storage data control transistor 104 and the second storage data control transistor 105 have the same channel conductivity type.

A row signal control transistor 106 and a column signal control transistor 107 are connected in series between the middle node and the second row signal line OP.

A gate of the first storage data control transistor 104 is connected to the first storage node.

A gate of the second storage data control transistor 105 is connected to the second storage node.

The gate of the row signal control transistor 106 is connected to the first row signal line OP1 .

The gate of the column signal control transistor 107 is connected to the column signal line OP2.

In the embodiment of the present invention, both the first storage data control transistor 104 and the second storage data control transistor 105 are NMOS transistors. When the first storage signal Q is at a high level and the second storage signal QB is at a low level, the first storage data control transistor 104 is turned on and the second storage data control transistor 105 is turned off. FIG. 1 also shows that the first storage data control transistor 104 is an NMOS transistor N7 and the second storage data control transistor 105 is an NMOS transistor N8.

In other embodiments, the first storage data control tube 104 and the second storage data control tube 105 are both PMOS tubes, when the first storage signal Q is at a high level, the second storage signal QB is at a low level, the first storage data control tube 104 is turned off, and the second storage data control tube 105 is turned on. At this time, the control of the corresponding logic signal only needs to be adjusted accordingly, but the storage, multi-Boolean logic operation and row and column bidirectional search functions can also be realized.

In the embodiment of the present invention, the row signal control tube 106 is an NMOS tube, which is turned on when the first row signal is high level and turned off when the first row signal is low level. FIG1 also shows that the row signal control tube 106 is an NMOS tube N5.

In other embodiments, the row signal control tube 106 may be a PMOS tube, and the row signal control tube 106 is turned on when the first row signal is at a low level, and the row signal control tube 106 is turned off when the first row signal is at a high level.

In the embodiment of the present invention, the column signal control tube 107 is an NMOS tube. When the column signal is high, the column signal control tube 107 is turned on. When the column signal is low, the column signal control tube 107 is turned off. FIG1 also shows that the column signal control tube 107 is an NMOS tube N6.

In other embodiments, the column signal control tube 107 may be a PMOS tube, and the column signal control tube 107 is turned on when the column signal is at a low level, and the column signal control tube 107 is turned off when the column signal is at a high level.

The storage-computation-in-one unit structure 101 includes a memory configuration state and a multi-Boolean logic operator configuration state.

As shown in FIG. 2 , it is a circuit diagram of the storage-computation-in-one unit structure in the memory configuration state according to an embodiment of the present invention; the signal setting of the memory configuration state includes:

The first row signal of the first row signal line OP1 turns off the row signal control transistor 106 .

The column signal of the column signal line OP2 turns off the column signal control tube 107 .

Since the row signal control tube 106 and the column signal control tube 107 are both turned off, the signals of the first bit line BL and the second bit line BLB will not be affected by the second row signal line OP.

At the same time, since the first storage signal Q and the second storage signal QB are inverted to each other, one of the first storage data control tube 104 and the second storage data control tube 105 with the same channel conductivity type always remains in the cut-off state, so the first bit line BL and the second bit line BLB will not interfere with each other, making the entire storage and computing integrated unit structure equivalent to one SRAM storage unit 102.

As shown in FIG3 , it is a circuit diagram of the storage-computation-in-one unit structure of an embodiment of the present invention when it is in a multi-Boolean logic operator configuration state; the signal setting of the multi-Boolean logic operator configuration state includes:

In the pre-charge state, the first row signal of the first row signal line OP1 turns off the row signal control transistor 106 .

The column signal of the column signal line OP2 turns on the column signal control transistor 107 .

The levels of the first bit line BL and the second bit line BLB are the same and opposite to the level of the second row signal of the second row signal line OP.

Generally, in the pre-charge and discharge state, the high-level signal line needs to be pre-charged, while the low-level signal line needs to be pre-discharged.

In the pre-charge state, since the row signal control tube 106 is turned off, the second row signal of the second row signal line OP will not affect the levels of the first bit line BL and the second bit line BLB.

In the operation state, the address signal selects the two rows of the storage-operation integrated unit structure 101 on the same column that need to perform logic operations.

The first row signals of the first row signal lines OP1 of the two rows of the integrated storage and computing unit structures 101 are switched to turn on the row signal control tubes 106 .

After the row signal control tube 106 is turned on, the conduction relationship between the first bit line BL and the second bit line BLB and the corresponding second row signal line OP is completely related to the storage information in the two rows of the storage and computing integrated unit structure 101, namely, the first storage signal Q and the second storage signal QB. Different storage information has different conduction relationships. Finally, the potential of the first bit line BL and the second bit line BLB can reflect the storage information in the two rows of the storage and computing integrated unit structure 101, thereby realizing the logical operation of the storage information in the two rows of the storage and computing integrated unit structure 101.

The first logic operation result of the first storage signal Q of the two rows of the integrated storage and calculation unit structure 101 is output on the first bit line BL.

The second bit line BLB outputs the second logic operation result of the first storage signal Q of the two rows of the integrated storage and calculation unit structure 101.

In the embodiment of the present invention shown in FIG3 , the first bit line BL is inverted by the NOT gate 201a to output an OR signal OR, and the OR signal OR is inverted by the NOT gate 201b to output an OR signal NOR; the first bit line BL is inverted by the NOT gate 201c to output a NAND signal NAND, and the NAND signal NAND is inverted by the NOT gate 201d to output an AND signal AND. The control signal corresponding to the logic signal output shown in FIG3 is set as:

In the pre-charge state, the first bit line BL and the second bit line BLB are both pre-charged and will be at a high level after pre-charging; the second row signal of the second row signal line OP is connected to a low level or ground (VSS/GND). In combination with the first storage data control tube 104 and the second storage data control tube 105 both being NMOS tubes, the logical operation result shown in FIG. 3 can be obtained.

At this time, when the storage-computation integrated unit structure 101 is in the operation state of the multi-Boolean logic operator configuration state, the first logic operation result outputs the OR signal or the NOR signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates, and the second logic operation result outputs the NAND signal or the AND signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates.

In the embodiment of the present invention, the function switching unit 103 further includes:

A first NAND gate 202 , wherein a first input terminal of the first NAND gate 202 is connected to the OR signal OR and a second input terminal of the first NAND gate 202 is connected to the NAND signal NAND.

The output terminal of the first NAND gate 202 outputs an exclusive OR signal XNOR.

The output end of the first NAND gate 202 further outputs an exclusive OR signal NOR through a NOT gate 201e.

The following further describes the working process of the storage-computation-in-one unit structure of the embodiment of the present invention shown in FIG3 when the column is in the multi-Boolean logic operator configuration state in conjunction with the truth table corresponding to Table 1:

Table I

Q<i1,j> Q<i2,j> BL BLB 0 0 1 (keep high level) 0 (discharge to OP) 0 1 0 (discharge to OP) 0 (discharge to OP) 1 0 0 (discharge to OP) 0 (discharge to OP) 1 1 0 (discharge to OP) 1 (keep high level)

In Table 1, Q<i1,j> represents the first storage signal of address <i1,j>, Q<i2,j> represents the first storage signal of address <i1,j>, BL represents the first bit line signal of the first bit line BL, BLB represents the second bit line signal of the second bit line BLB, and OP represents the second row signal line OP.

In the following, the first bit line BL is directly represented by BL, the second bit line BLB is directly represented by BLB, the second row signal line OP is directly represented by OP, the first row signal line OP1 is directly represented by OP1, the first storage signal Q is directly represented by Q, and the second storage signal QB is directly represented by QB; in Figure 3, the address of the i1th row and jth column is represented by <i1,j>, the address of the i2th row and jth column is represented by <i2,j>, the storage and computing integrated unit structure 101 is directly represented by Cell, and the Cells of the two addresses are represented by Cell<i1,j> and Cell<i2,j> respectively, the OP1 of the i1th row is represented by OP1<i1>, the OP1 of the i2th row is represented by OP1<i2>, the OP of the i1th row is represented by OP<i1>, the OP of the i2th row is represented by OP<i2>, the OP2 of the jth column is represented by OP2<j>, the BL of the jth column is represented by Bl<j>, and the BLB of the jth column is represented by BLB<j>. The first storage data control tube 104 is represented by an NMOS tube N7, the second storage data control tube 105 is represented by an NMOS tube N8, the row signal control tube 106 is represented by an NMOS tube N5, and the column signal control tube 107 is represented by an NMOS tube N6.

In the multi-Boolean logic operator configuration state:

First, each row OP1 is pre-discharged, each column OP2 is pre-charged, each row OP is connected to low level (VSS)/ground (GND), and all bit lines BL/BLB are pre-charged. At this time, the address signal decoding obtains two unit addresses that need to be Boolean logic, namely row i1, column j, and row i2, column j. Then OP1 of row i1 and row i2 is charged. At this time, the path formation between OP and BL, OP and BLB depends on the Q and QB level values stored in the two units.

If the Q values stored in the two cells are both 0, the NMOS tubes N7 in the two cells are both turned off, BL maintains a high level, the NMOS tubes N8 are both turned on, and BLB discharges to OP through the NMOS tubes N8, NMOS tubes N5, and NMOS tubes N6.

If the Q values stored in the two cells are both 1, the NMOS tubes N8 in the two cells are both turned off, BLB maintains a high level, the NMOS tubes N7 are both turned on, and BL discharges to OP through the NMOS tubes N7, NMOS tubes N5, and NMOS tubes N6.

If cell<i1,j> stores Q as 0 and cell<i2,j> stores Q as 1, then the NMOS tube N7 of cell<i1,j> is turned off and the NMOS tube N8 is turned on; the NMOS tube N7 of cell<i2,j> is turned on and the NMOS tube N8 is turned off; BL discharges to OP through the NMOS tube N7, NMOS tube N5 and NMOS tube N6 of cell<i2,j>; BLB discharges to OP through the NMOS tube N8, NMOS tube N5 and NMOS tube N6 of cell<i2,j>.

In this way, the truth table shown in Table 1 is obtained. Combined with FIG3, it can be seen that the output of BL passes through the first-level NOT gate 201a to obtain the OR signal result, and passes through the two-level NOT gates 201a and 201b to obtain the NOR signal result; the output of BLB passes through the first-level NOT gate 201c to obtain the NAND signal result, and passes through the two-level NOT gates 201c and 201d to obtain the AND signal result. The OR signal and the NAND signal are output through the first NAND gate 202 to obtain the XNOR signal result, and then pass through the first-level NOT gate 201e to obtain the XOR signal result, thereby realizing the simultaneous output of multiple Boolean logic operations.

The embodiment of the present invention can also make corresponding changes based on FIG. 3 to obtain other embodiments, which are described as follows:

In some embodiments, the first storage data control tube 104 and the second storage data control tube 105 are both NMOS tubes. In the pre-charge state, the first bit line BL and the second bit line BLB are both pre-discharged and will be at a low level after pre-discharge; the second row signal of the second row signal line OP is connected to a high level.

In the operation state where the storage-computation integrated unit structure 101 is the multi-Boolean logic operator configuration state, the first logic operation result outputs the OR signal or the NOR signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates, and the second logic operation result outputs the NAND signal or the AND signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates. The specific truth table can also be obtained by deduction, and the process is similar to obtaining the truth table of Table 1.

In some embodiments, the first storage data control tube 104 and the second storage data control tube 105 are both PMOS tubes, the first bit line BL and the second bit line BLB are both pre-charged and will be high level after pre-charging; the second row signal of the second row signal line OP is connected to a low level or ground (VSS/GND).

In the operation state where the storage-computation integrated unit structure 101 is the multi-Boolean logic operator configuration state, the first logic operation result outputs the NAND signal or AND signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates, and the second logic operation result outputs the OR signal or NOR signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates. The specific truth table can also be obtained by deduction, and the process is similar to obtaining the truth table of Table 1.

In some embodiments, the first storage data control tube 104 and the second storage data control tube 105 are both PMOS tubes. In the pre-charge state, the first bit line BL and the second bit line BLB are both pre-discharged and will be at a low level after pre-discharge; the second row signal of the second row signal line OP is connected to a high level.

In the operation state where the storage-computation integrated unit structure 101 is the multi-Boolean logic operator configuration state, the first logic operation result outputs the NAND signal or AND signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates, and the second logic operation result outputs the OR signal or NOR signal of the first storage signal Q of two rows of the storage-computation integrated unit structure 101 through a corresponding number of NOT gates. The specific truth table can also be obtained by deduction, and the process is similar to obtaining the truth table of Table 1.

Therefore, in the above embodiments, four logic operation result signals, namely, an OR signal, a NOR signal, a NAND signal, a NAND signal, and an AND signal, can be obtained from the first logic operation result and the second logic operation result.

As shown in FIG4 , it is a circuit diagram of the storage-computation-in-one unit structure in an embodiment of the present invention when it is in a column-oriented CAM searcher configuration state; in the embodiment of the present invention, the storage-computation-in-one unit structure 101 also includes a column-oriented CAM searcher configuration state.

The signal setting of the column to the CAM searcher configuration state includes:

In the pre-charge state, the first row signal of the first row signal line OP1 turns off the row signal control transistor 106 .

The column signal of the column signal line OP2 turns on the column signal control transistor 107 .

The first bit line BL and the second bit line BLB have opposite levels.

The second row signal of the second row signal line OP carries the data to be matched.

In the column-direction CAM search state, the first row signal of the first row signal line OP1 of each row is switched in turn to turn on the row signal control tube 106. The column search matching result signal for judging whether the first storage signal Q of the corresponding row matches the data to be matched is obtained through the logic state of the first bit line signal of the first bit line BL and the second bit line signal of the second bit line BLB. Among them, after the row signal control tube 106 of the corresponding row is turned on, the first bit line BL and the second bit line BLB will be affected by the second row signal of the second row signal line OP, and the influence relationship between the two is related to the matching state of the first storage signal Q of the corresponding row and the data to be matched. Therefore, finally, the logic state of the first bit line signal of the first bit line BL and the second bit line signal of the second bit line BLB can be used to judge whether the first storage signal Q of the corresponding row matches the data to be matched and output the corresponding column search matching result signal.

In the embodiment of the present invention, both the first storage data control transistor 104 and the second storage data control transistor 105 are NMOS transistors. In this case:

When the storage-computing integrated unit structure 101 is in the column-oriented CAM searcher configuration state, in the pre-charge and discharge state, the first bit line BL is at a high level, that is, the first bit line BL is pre-charged, and the second bit line BLB is at a low level, that is, the second bit line BL is pre-discharged. In the column-oriented CAM search state, when the first bit line BL or the second bit line BLB changes state, it indicates that the first storage signal Q does not match the data to be matched.

As shown in FIG. 4 , the integrated storage and computing unit structure 101 further includes a column search and matching output circuit.

The column search matching output circuit includes: a first NOR gate 203, the first bit line BL is connected to the first input terminal of the first NOR gate 203 through a first-level NOR gate 201f, and the second bit line BLB is connected to the second input terminal of the first NOR gate 203 through two-level NOR gates 201g and 201h; when the first NOR gate 203 outputs a high level, it indicates a successful match, and when the first NOR gate 203 outputs a low level, it indicates a failed match.

The following further describes the working process of the storage-computation-in-one unit structure of the embodiment of the present invention shown in FIG. 4 when the column is in the column-directed CAM searcher configuration state in conjunction with the truth table corresponding to Table 2:

Table II

In Table 2, Q represents the first storage signal, OP represents the second row signal of the second row signal line OP, BL represents the first bit line signal of the first bit line BL, and BLB represents the second bit line signal of the second bit line BLB.

In the following, the first bit line BL is directly represented by BL, the second bit line BLB is directly represented by BLB, the second row signal line OP is directly represented by OP, the first row signal line OP1 is directly represented by OP1, the first storage signal Q is directly represented by Q, and the second storage signal QB is directly represented by QB; in FIG4, the address of the i1th row and jth column is represented by <i1,j>, the address of the inth row and jth column is represented by <in,j>, the storage-computation integrated unit structure 101 is directly represented by Cell, and the Cells of the two addresses are respectively represented by Ce. ll<i1,j> and Cell<in,j> are represented, and the dotted line between Cell<i1,j> and Cell<in,j> indicates that the cells corresponding to the middle rows on the same column are omitted; OP1 of the i1th row is represented by OP1<i1>, OP1 of the inth row is represented by OP1<in>, OP of the i1th row is represented by OP<i1>, OP of the inth row is represented by OP<in>, OP2 of the jth column is represented by OP2<j>, BL of the jth column is represented by Bl<j>, and BLB of the jth column is represented by BLB<j>. The first storage data control tube 104 is represented by NMOS tube N7, and the second storage data control tube 105 is represented by NMOS tube N8.

In the column-oriented CAM configuration, the function of simultaneously detecting whether the data in each column is the same as the data to be matched is realized. First, each column OP2 is precharged and each row OP1 is pre-discharged. Then OP loads the data to be matched, BL is precharged, and BLB is pre-discharged. After the configuration is completed, each row OP1 is charged and the column-oriented CAM search begins. By sensing whether there is charging and discharging on BL and BLB, it is determined whether there is a match.

If the Q value stored in the corresponding Cell is 0 and the data to be matched is also 0 (i.e., OP is loaded with a low level), the NMOS tube N7 of the Cell is turned off, the NMOS tube N8 is turned on, BL remains at a high level, and BLB is originally at a low level, and remains at a low level after connecting to OP;

If the Q value stored in the Cell is 1 and the data to be matched is also 1 (i.e., OP is loaded with a high level), the NMOS tube N7 of the Cell is turned on, and the NMOS tube N8 is turned off. BL is originally at a high level, but remains at a high level after connecting to OP. Since the NMOS tube N8 is turned off, no charging circuit can be generated between BLB and OP, and BLB remains at a low level.

If the Q value stored in the Cell is 0 and the data to be matched is 1 (i.e., OP is loaded with a high level), the NMOS tube N7 of the Cell is turned off, the NMOS tube N8 is turned on, BL maintains a high level, OP charges BLB, and BLB becomes a high level, i.e., ‘1’, which is ‘1 (charge exists)’ shown in Table 2.

If the Q value stored in the Cell is 1 and the data to be matched is 0 (i.e., OP is loaded with a low level), the NMOS tube N7 of the Cell is turned on, the NMOS tube N8 is turned off, BL discharges to OP, and BL becomes a low level, i.e., ‘0’, which is ‘0 (discharge exists)’ shown in Table 2, and BLB remains at a low level.

From the above four cases, we get the truth table shown in Table 2.

It can be seen from Table 2 that as long as BL is discharged or BLB is charged, there is no match. Discharging of BL or charging of BLB is equivalent to BL being 1 through a first-level NOT gate 201f or BLB being 1 through two-level NOT gates 201g and 201h. Whether the match is successful can be detected through three NOT gates 201f, 201g and 201h and one NOR gate, namely the first NOR gate 203. Finally, the NOR gate output is 1, indicating a successful match, and the NOR gate output is 0, indicating a failed match.

The embodiment of the present invention can also make corresponding transformations based on FIG. 4 to obtain other embodiments, which are described as follows:

In some embodiments, when the first storage data control transistor 104 and the second storage data control transistor 105 are both NMOS transistors:

When the storage-computing integrated unit structure 101 is in the column-oriented CAM searcher configuration state, in the pre-charge and discharge state, the first bit line BL is at a low level and the second bit line BLB is at a high level, that is, compared with the corresponding embodiment of Figure 4, the charge and discharge states of the first bit line BL and the second bit line BLB are switched; in the column-oriented CAM search state, when the state of the first bit line BL or the second bit line BLB changes, it indicates that the first storage signal Q matches the data to be matched, and finally, the corresponding column search matching result signal can also be output through the corresponding column search matching output circuit according to the signals of the first bit line BL and the second bit line BLB.

In some embodiments, when the first storage data control transistor 104 and the second storage data control transistor 105 are both PMOS transistors:

When the storage-computation integrated unit structure 101 is in the column-directed CAM searcher configuration state, in the pre-charge state, the first bit line BL is at a high level and the second bit line BLB is at a low level; in the column-directed CAM search state, when the first bit line BL or the second bit line BLB has a state change, it indicates that the first storage signal Q matches the to-be-matched data. Finally, the corresponding column search match result signal can also be output through the corresponding column search match output circuit according to the signals of the first bit line BL and the second bit line BLB.

In some embodiments, when the first storage data control transistor 104 and the second storage data control transistor 105 are both PMOS transistors:

When the storage-computation integrated unit structure 101 is in the column-oriented CAM searcher configuration state, in the pre-charge state, the first bit line BL is at a low level and the second bit line BLB is at a high level; in the column-oriented CAM search state, when the first bit line BL or the second bit line BLB has a state change, it indicates that the first storage signal Q does not match the data to be matched. Finally, the corresponding column search match result signal can also be output through the corresponding column search match output circuit according to the signals of the first bit line BL and the second bit line BLB.

As shown in FIG5 , it is a circuit diagram of the storage-computation integrated unit structure in the embodiment of the present invention when it is in the row-direction CAM searcher configuration state. In the embodiment of the present invention, the storage-computation integrated unit structure 101 also includes the row-direction CAM searcher configuration state. The signal setting of the row-direction CAM searcher configuration state includes:

In the pre-charge state, the first row signal of the first row signal line OP1 turns on the row signal control transistor 106 .

The column signal of the column signal line OP2 turns off the column signal control tube 107 .

The first bit line signal of the first bit line BL is loaded with data to be matched, and the level of the second bit line BLB is opposite to that of the first bit line BL.

The second row signal of the second row signal line OP is set to a high level or a low level.

In the row CAM search state, the column signal of the column signal line OP2 of each column is switched in turn to turn on the column signal control tube 107. The row search matching result signal for judging whether the first storage signal Q of the corresponding column matches the to-be-matched data is obtained through the logic state of the second row signal of the second row signal line OP.

Among them, after the column signal control tube 107 of the corresponding column is turned on, the second row signal of the second row signal line OP will be affected by the signals of the first bit line BL and the second bit line BLB, and the influence relationship between the two is related to the matching state of the first storage signal Q of the corresponding column and the data to be matched. Therefore, finally, the row search matching result signal for judging whether the first storage signal Q of the corresponding column and the data to be matched matches is obtained through the logical state of the second row signal of the second row signal line OP.

In the embodiment of the present invention, as shown in FIG5 , the first storage data control transistor 104 and the second storage data control transistor 105 are both NMOS transistors. In this case:

When the storage and computing integrated unit structure 101 is in the row-directed CAM searcher configuration state, in the row-directed CAM search state, when the second row signal is at a high level, the first storage signal Q and the data to be matched match, and when the second row signal is at a low level, the first storage signal Q and the data to be matched do not match.

When in the pre-charge state, the second row signal is at a high level, i.e., pre-charged, then when the first storage signal Q and the data to be matched do not match, the second row signal will be discharged to a low level; when the first storage signal Q and the data to be matched match, the second row signal remains at a high level.

Corresponding transformation is performed. When the second row signal is at a low level, i.e., pre-discharge, when the first storage signal Q and the data to be matched do not match, the second row signal will remain at a low level; when the first storage signal Q and the data to be matched match, the second row signal will be charged to a high level.

As shown in FIG. 5 , in the embodiment of the present invention, the second row signal line OP further outputs the row search matching result signal through a NOT gate 201 i.

The following further describes the working process of the storage-computation-in-one unit structure of the embodiment of the present invention shown in FIG5 when the column is in the row-direction CAM searcher configuration state in conjunction with the truth table corresponding to Table 3:

Table 3

Q BL BLB OP 0 0 1 1 0 1 0 0 (discharge present) 1 0 1 0 (discharge present) 1 1 0 1

In Table 3, Q represents the first storage signal, OP represents the second row signal of the second row signal line OP, BL represents the first bit line signal of the first bit line BL, and BLB represents the second bit line signal of the second bit line BLB.

In the following, the first bit line BL is directly represented by BL, the second bit line BLB is directly represented by BLB, the second row signal line OP is directly represented by OP, the first row signal line OP1 is directly represented by OP1, the first storage signal Q is directly represented by Q, and the second storage signal QB is directly represented by QB; in FIG5, the address of the i-th row and j1-th column is represented by <i, j1>, the address of the i-th row and j2-th column is represented by <i, j2>, the storage-computation integrated unit structure 101 is directly represented by Cell, and the two The cells of the addresses are represented by Cell<i,j1> and Cell<i,j2> respectively; OP1 of the i-th row is represented by OP1<i>, OP of the i-th row is represented by OP<i>, OP2 of the j1-th column is represented by OP2<j1>, OP2 of the j2-th column is represented by OP2<j2>, BL of the j1-th column is represented by Bl<j1>, BL of the j2-th column is represented by Bl<j2>, BLB of the j1-th column is represented by BLB<j1>, and BLB of the j2-th column is represented by BLB<j2>. The first storage data control tube 104 is represented by NMOS tube N7, and the second storage data control tube 105 is represented by NMOS tube N8.

The external signal configuration shown in FIG5 is a row-directed CAM searcher configuration: In the row-directed CAM configuration, the function of simultaneously detecting whether the data in each row is the same as the data to be matched is realized. First, each row OP1 is precharged and each column OP2 is pre-discharged. Then BL and BLB load the data to be matched, and OP is precharged. After the configuration is completed, each column OP2 is charged and the row-directed CAM search begins. By sensing whether there is a discharge phenomenon on OP, it is determined whether it matches.

If the Q value stored in the Cell is 0 and the data to be matched is also 0 (i.e., BL is loaded with a low level and BLB is loaded with a high level), the NMOS tube N7 of the Cell is turned off, the NMOS tube N8 is turned on, and OP is at a high level;

If the Q value stored in the Cell is 1 and the data to be matched is also 1 (i.e., BL is loaded with a high level and BLB is loaded with a low level), the NMOS tube N7 of the Cell is turned on, the NMOS tube N8 is turned off, and OP is at a high level;

If the Q value stored in the Cell is 0 and the data to be matched is 1 (i.e., BL is loaded with a high level and BLB is loaded with a low level), the NMOS tube N7 of the Cell is turned off, the NMOS tube N8 is turned on, and OP discharges to BLB;

If the Q value stored in the Cell is 1 and the data to be matched is 0 (ie, BL is loaded with a low level and BLB is loaded with a high level), the NMOS tube N7 of the Cell is turned on, the NMOS tube N8 is turned off, and OP discharges to BL.

The above four situations can finally get the truth table shown in Table 3.

Therefore, if there is discharge in a row OP, there is no match. OP passes through a first-stage NOT gate 201i. If the output of the NOT gate 201i is 1, there is no match. If the output is 0, there is a match.

Other embodiments can also be obtained by performing changes based on the embodiment of the present invention shown in FIG. 5 . In some embodiments, it can also be:

The first storage data control transistor 104 and the second storage data control transistor 105 are both PMOS transistors. In this case:

When the storage and computing integrated unit structure 101 is in the row-directed CAM searcher configuration state, in the row-directed CAM search state, when the second row signal is at a high level, the first storage signal Q and the data to be matched do not match, and when the second row signal is at a low level, the first storage signal Q and the data to be matched match.

The embodiment of the present invention sets a function switching unit 103 on the basis of the SRAM storage unit 102. The function switching unit 103 can realize the first storage data control tube 104, the second storage data control tube 105, the row signal control tube 106 and the column signal control tube 107 through 4 transistors; the embodiment of the present invention also makes special settings for the control signals of each transistor of the function switching unit 103, that is, the signals connected to the gate. Combined with the signal settings, the storage and calculation integrated unit structure 101 can be set in the memory configuration state and the multi-Boolean logic operator configuration state, and combined with the peripheral logic circuit, it can also realize full Boolean logic operations.

The embodiment of the present invention can further enable the storage-computing integrated unit structure 101 to be in a column-oriented CAM searcher configuration state and a row-oriented CAM searcher configuration state, thereby realizing a bidirectional row-column search function.

Since the embodiment of the present invention can realize full Boolean operations and realize bidirectional operations of rows and columns, the embodiment of the present invention has the characteristics of high flexibility and good reconfigurability.

In addition, the embodiment of the present invention does not need to use a sense amplifier to sense the signal line, but uses a logic gate instead of a sense amplifier to sense the signal line, which can significantly improve the circuit integration and thus reduce the circuit area, and can also improve the sensing efficiency.

In addition, when the SRAM storage unit 102 of the embodiment of the present invention adopts a standard 6T SRAM storage unit, combined with the 4 transistors of the function switching unit 103, it can be known that the storage and computing integrated unit structure 101 of the embodiment of the present invention can realize a 10T unit structure, that is, it can be realized with 10 transistors.

The embodiment of the present invention realizes a storage-computation integrated circuit that multiplexes storage, multi-Boolean logic operators, and row-column bidirectional content-addressable memory. By using in-memory computing technology and giving different signal configurations, storage-computation multiplexing of the memory, multi-Boolean logic operators, and content-addressable memory is realized, thereby improving the data processing capability and computing efficiency of the storage-computation integrated system. In addition, multi-Boolean logic realizes array parallel computing to improve computing efficiency, and the addressing function realizes full-array bidirectional addressing to adapt to different application requirements.

The embodiments of the present invention can realize a highly flexible and reconfigurable in-memory computing SRAM unit, which is applied to the field of in-memory computing, realizes full Boolean logic parallel operation and row and column bidirectional addressing functions, and performs signal line sensing by replacing sensitive amplifiers with logic gates, thereby improving circuit integration and sensing efficiency.

The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims (17)

1. A computationally integrated unit structure, comprising: an SRAM memory unit and a function switching unit;

The SRAM memory cell is connected between a first bit line and a second bit line and is provided with a first memory node and a second memory node, and a first memory signal of the first memory node and a second memory signal of the second memory node are opposite;

the function switching unit includes:

a first storage data control pipe connected between the first bit line and an intermediate node;

A second storage data control pipe connected between the second bit line and the intermediate node, the first storage data control pipe and the second storage data control pipe having the same channel conductivity type;

a row signal control tube and a column signal control tube connected in series between the intermediate node and the second row signal line;

the grid electrode of the first storage data control tube is connected with the first storage node;

The grid electrode of the second storage data control tube is connected with the second storage node;

The grid electrode of the row signal control tube is connected with a first row signal line;

the grid electrode of the column signal control tube is connected with a column signal line;

the memory and calculation integrated unit structure comprises a memory configuration state and a multi-Boolean logic operator configuration state;

the signal setting of the memory configuration state includes:

The first row signal of the first row signal line cuts off the row signal control tube;

The column signal of the column signal line cuts off the column signal control tube;

The signal setting of the configuration state of the multi-boolean logic operator comprises:

in a pre-charge and discharge state, the first row signal of the first row signal line cuts off the row signal control tube;

column signals of the column signal lines enable the column signal control tubes to be conducted;

The first bit line and the second bit line have the same level and are opposite to the level of the second row signal line;

in the operation state, the address signal selects two rows of the integrated memory unit structures needing logic operation on the same column;

the first row signals of the first row signal lines of the two rows of integrated memory unit structures are switched to conduct the row signal control tubes;

Outputting first logic operation results of the first storage signals of the two rows of the integrated storage unit structures on the first bit line;

and outputting second logic operation results of the first storage signals of the two rows of the integrated storage unit structures on the second bit line.

2. The computationally intensive unit structure as claimed in claim 1, wherein: the integrated memory cell structure further comprises a column CAM searcher configuration state;

the signal setting of the column CAM searcher configuration state includes:

in a pre-charge and discharge state, the first row signal of the first row signal line cuts off the row signal control tube;

column signals of the column signal lines enable the column signal control tubes to be conducted;

the first bit line and the second bit line are opposite in level;

loading data to be matched by a second row signal of the second row signal line;

In a column CAM search state, switching a first row signal of the first row signal line of each row to conduct the row signal control tube in sequence;

And obtaining a column search matching result signal for judging whether the first storage signal of the corresponding row and the data to be matched are matched or not according to the logic states of the first bit line signal of the first bit line and the second bit line signal of the second bit line.

3. The computationally intensive unit structure as claimed in claim 2, wherein: the memory integrated unit structure further comprises a row CAM searcher configuration state;

the signal setting of the configuration state of the row-wise CAM searcher comprises:

in a pre-charge and discharge state, a first row signal of the first row signal line enables the row signal control tube to be conducted;

The column signal of the column signal line cuts off the column signal control tube;

Loading data to be matched by a first bit line signal of the first bit line, wherein the level of the second bit line is opposite to that of the first bit line;

the second row signal of the second row signal line is set to a high level or a low level;

In a row CAM search state, sequentially switching the column signals of the column signal lines of each column to turn on the column signal control tube;

And obtaining a row search matching result signal for judging whether the first storage signal of the corresponding column and the data to be matched are matched or not according to the logic state of the second row signal line.

4. The computationally intensive unit structure as claimed in claim 3, characterized in that: the first storage data control tube and the second storage data control tube are NMOS tubes, when the first storage signal is at a high level, the second storage signal is at a low level, the first storage data control tube is conducted, and the second storage data control tube is cut off;

or the first storage data control tube and the second storage data control tube are PMOS tubes, when the first storage signal is at a high level, the second storage signal is at a low level, the first storage data control tube is cut off, and the second storage data control tube is conducted.

5. The computationally intensive unit structure as claimed in claim 4, wherein: the row signal control tube adopts an NMOS tube, the row signal control tube is conducted when the first row signal is at a high level, and the row signal control tube is cut off when the first row signal is at a low level;

Or the row signal control tube adopts a PMOS tube, the row signal control tube is conducted when the first row signal is at a low level, and the row signal control tube is cut off when the first row signal is at a high level.

6. The computationally intensive unit structure as claimed in claim 5, wherein: the column signal control tube adopts an NMOS tube, the column signal control tube is conducted when the column signal is in a high level, and the column signal control tube is cut off when the column signal is in a low level;

Or the column signal control tube adopts a PMOS tube, the column signal control tube is conducted when the column signal is at a low level, and the column signal control tube is cut off when the column signal is at a high level.

7. The computationally intensive unit structure as defined in claim 6, wherein: in the operation state that the integrated memory unit structure is the configuration state of the multi-boolean logic operator, the first logic operation result outputs the or signal or the nor signal of the first storage signals of the two rows of integrated memory unit structures through a corresponding number of not gates, and the second logic operation result outputs the nand signal or the and signal of the first storage signals of the two rows of integrated memory unit structures through a corresponding number of not gates;

or in the operation state that the integrated memory unit structure is the configuration state of the multi-boolean logic operator, the first logic operation result outputs nand signals or and signals of the first storage signals of the two rows of integrated memory unit structures through a corresponding number of not gates, and the second logic operation result outputs nor signals or nor signals of the first storage signals of the two rows of integrated memory unit structures through a corresponding number of not gates.

8. The computationally intensive unit structure as claimed in claim 7, wherein: the function switching unit further includes:

the first input end of the first NAND gate is connected with the OR signal respectively, and the second input end of the first NAND gate is connected with the NAND signal;

And the output end of the first NAND gate outputs an exclusive nor signal.

9. The computationally intensive unit structure as claimed in claim 8, wherein: the output end of the first NAND gate outputs an exclusive OR signal through an NOT gate.

10. The computationally intensive unit structure as defined in claim 6, wherein: when the first storage data control pipe and the second storage data control pipe are NMOS pipes:

When the integrated memory cell structure is in a configuration state of the column CAM searcher, in a pre-charge and discharge state, when the first bit line is in a high level and the second bit line is in a low level; in a column-wise CAM search state, when there is a change in state of the first bit line or the second bit line, it is indicated that the first storage signal and the data to be matched do not match.

11. The computationally intensive unit structure as claimed in claim 10, wherein: the integrated memory unit structure further comprises a column search matching output circuit;

The column search matching output circuit includes: a first nor gate, the first bit line being connected to a first input of the first nor gate through a one-stage nor gate, the second bit line being connected to a second input of the first nor gate through a two-stage nor gate; the first nor gate indicates successful matching when outputting high level and indicates failed matching when outputting low level.

12. The computationally intensive unit structure as defined in claim 6, wherein: when the first storage data control pipe and the second storage data control pipe are NMOS pipes:

When the integrated memory cell structure is in a configuration state of the column CAM searcher, in a pre-charge and discharge state, when the first bit line is in a low level and the second bit line is in a high level; in a column-wise CAM search state, when there is a change in state of the first bit line or the second bit line, it is indicative that the first storage signal and the data to be matched match.

13. The computationally intensive unit structure as defined in claim 6, wherein: when the first storage data control pipe and the second storage data control pipe are PMOS pipes:

When the integrated memory cell structure is in a configuration state of the column CAM searcher, in a pre-charge and discharge state, when the first bit line is in a high level and the second bit line is in a low level; in a column-wise CAM search state, when there is a change in state of the first bit line or the second bit line, indicating that the first storage signal and the data to be matched match;

Or when the integrated memory cell structure is in a configuration state of the column CAM searcher, in a pre-charge and discharge state, when the first bit line is in a low level and the second bit line is in a high level; in a column-wise CAM search state, when there is a change in state of the first bit line or the second bit line, it is indicated that the first storage signal and the data to be matched do not match.

14. The computationally intensive unit structure as defined in claim 6, wherein: when the first storage data control pipe and the second storage data control pipe are NMOS pipes:

when the integrated memory cell structure is in a configuration state of a row-wise CAM searcher, in the row-wise CAM searching state, the first memory signal is matched with the data to be matched when the second row signal is in a high level, and the first memory signal is not matched with the data to be matched when the second row signal is in a low level.

15. The computationally intensive unit structure as claimed in claim 14, wherein: the second row signal line also outputs the row search match result signal through a not gate.

16. The computationally intensive unit structure as defined in claim 6, wherein: when the first storage data control pipe and the second storage data control pipe are PMOS pipes:

When the integrated memory cell structure is in a configuration state of a row-wise CAM searcher, in the row-wise CAM searching state, the first memory signal is not matched with the data to be matched when the second row signal is in a high level, and the first memory signal is matched with the data to be matched when the second row signal is in a low level.

17. The computationally intensive unit structure as claimed in claim 1, wherein: the SRAM memory cells include 6T SRAM memory cells.