CN118431189A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN118431189A CN118431189A CN202310219527.2A CN202310219527A CN118431189A CN 118431189 A CN118431189 A CN 118431189A CN 202310219527 A CN202310219527 A CN 202310219527A CN 118431189 A CN118431189 A CN 118431189A
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- layer
- functional surface
- rewiring layer
- chip
- isolation
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 31
- 238000002955 isolation Methods 0.000 claims abstract description 133
- 239000010408 film Substances 0.000 claims description 44
- 239000004033 plastic Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 13
- 239000005022 packaging material Substances 0.000 claims description 12
- 239000002861 polymer material Substances 0.000 claims description 11
- 230000000712 assembly Effects 0.000 claims description 10
- 238000000429 assembly Methods 0.000 claims description 10
- 229920001721 polyimide Polymers 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 239000009719 polyimide resin Substances 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims description 5
- 230000006872 improvement Effects 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 150000001875 compounds Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000002585 base Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011038 discontinuous diafiltration by volume reduction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- -1 is provided Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5225—Shielding layers formed together with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a chip packaging structure and a manufacturing method thereof, comprising the following steps: the first chip is provided with a first functional surface; the second chip is provided with a second functional surface which is close to the first functional surface; the rewiring layer is arranged between the first functional surface and the second functional surface and comprises a first rewiring layer and a second rewiring layer which are close to each other, the first rewiring layer is electrically connected with the first functional surface, and the second rewiring layer is electrically connected with the second functional surface; and the isolation voltage-resistant layer is at least partially arranged between the first rewiring layer and the second rewiring layer and is used for forming an isolation voltage-resistant structure between the first rewiring layer and the second rewiring layer. An isolation voltage-resistant layer is arranged between the first rewiring layer and the second rewiring layer to form an isolation voltage-resistant structure, and the first chip and the second chip can effectively reduce the volume of the packaged product while meeting the isolation voltage-resistant requirement of the packaged product without the need of having isolation capacitance characteristics.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a manufacturing method thereof.
Background
Fig. 1 is a schematic diagram of a conventional isolation packaging scheme, and the basic isolation packaging requirement of a chip is mainly met through the structural design of a frame. In order to meet the isolation withstand voltage requirement, the traditional isolation consists of two withstand voltage structures. Structure one: the isolation capacitors of the chip A and the chip B on the two sides are interconnected to form a pressure-resistant structure, and the isolation capacitors are filled with silicon dioxide which is a good pressure-resistant material; and (2) a structure II: the islands 1' on the two sides of the frame are independent, plastic packaging materials are filled in the middle, the pressure resistance characteristics of the plastic packaging materials and the distance between the islands are determined by pressure resistance requirements, and high-pressure resistant plastic packaging materials are generally adopted, wherein the distance is more than 300 um.
To meet the requirement of isolation withstand voltage, both isolation withstand voltage structures have some drawbacks: 1. the isolation capacitors are arranged in the chip, so that thick silicon dioxide (the thickness of the silicon dioxide of a conventional wafer is only 3-4 mu m, and the thickness of the silicon dioxide of the isolation wafer is about 20 mu m) is needed between the capacitors, the wafer is difficult to cut due to hard silicon dioxide texture, and defects such as cracks of a product are easy to cut, so that the quality of the product is affected. 2. The isolated withstand voltage structure is independently made to the base island, often is planar structure to because the withstand voltage of conventional plastic envelope material is only 20V/um, the interval of base island needs to enlarge, in order to satisfy withstand voltage demand, this will lead to isolating device encapsulation appearance increase, the consumptive material increases, product cost risees. 3. The different pressure-resistant requirements lead to large differences in structures, each structure needs to develop a corresponding frame, and the frame development period is long, which also seriously affects project progress.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof, which are used for solving the problem that the prior art cannot meet the requirements of isolation pressure resistance and the requirement of volume reduction of packaging products.
In order to achieve the above object, the present invention provides a chip package structure, comprising:
The first chip is provided with a first functional surface;
the second chip is provided with a second functional surface which is arranged close to the first functional surface;
the rewiring layer is arranged between the first functional surface and the second functional surface and comprises a first rewiring layer and a second rewiring layer which are close to each other, wherein the first rewiring layer is electrically connected with the first functional surface, and the second rewiring layer is electrically connected with the second functional surface;
And the isolation voltage-resistant layer is at least partially arranged between the first rewiring layer and the second rewiring layer and is used for forming an isolation voltage-resistant structure between the first rewiring layer and the second rewiring layer.
As a further improvement of an embodiment of the present invention, the isolating voltage-resistant layer is made of a polymer material.
As a further improvement of an embodiment of the present invention, the isolating voltage-resistant layer material is polyimide and/or epoxy resin.
As a further improvement of an embodiment of the present invention, the chip packaging structure further includes a plastic package body, where the plastic package body is used to encapsulate the first chip, the second chip, the rewiring layer and the isolation voltage-resistant layer; the voltage withstand value of the isolation voltage withstand layer is larger than that of the plastic package body.
As a further improvement of an embodiment of the present invention, the chip packaging structure further includes a first film layer that is attached to the first functional surface, and a second film layer that is attached to the second functional surface;
The first film layer is provided with a first groove exposing the electrical bonding pad of the first functional surface, and the first groove is filled with the first rewiring layer; the second film layer is provided with a second groove exposing the electrical bonding pad of the second functional surface, and the second groove is filled with the second rewiring layer.
As a further improvement of an embodiment of the present invention, the isolation withstand voltage value of the isolation withstand voltage layer is 300V/μm, and a space between the first rewiring layer and the second rewiring layer is 25 μm.
As a further improvement of an embodiment of the present invention, the isolating voltage-resistant layer is provided with at least two layers between the first functional surface and the second functional surface, each layer having a thickness of 45 μm;
the first rewiring layer extends into at least one of the isolation voltage resistant layers, and/or the second rewiring layer extends into at least one of the isolation voltage resistant layers.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps:
Manufacturing rewiring layers on the functional surfaces of at least two chips to form at least two packaging bodies; the package body comprises a first package body and a second package body, wherein the first package body comprises a first chip, a first functional surface and a first rewiring layer, and the second package body comprises a second chip, a second functional surface and a second rewiring layer;
Manufacturing an isolation pressure-resistant layer on one side of a first functional surface of the first packaging body;
the second package is connected to the isolation withstand voltage layer through the second rewiring layer, and the second rewiring layer is disposed close to the first rewiring layer.
As a further improvement of an embodiment of the present invention, the "forming a rewiring layer on the functional surfaces of at least two chips to form at least two packages" specifically includes:
and encapsulating the other side surfaces except one side of the functional surface on the chip by using the plastic packaging material, and manufacturing a rewiring layer on the functional surface to form at least two packaging bodies.
As a further improvement of an embodiment of the present invention, the "encapsulating the plastic package material on the other side surface of the chip except for the side of the functional surface, and making a rewiring layer on the functional surface, to form at least two packages" specifically includes:
Film pressing is carried out on the functional surfaces of at least two chips, grooves are formed in the formed film layers, and the electric bonding pads on the functional surfaces are exposed, so that at least two assemblies are formed;
and encapsulating the other side surfaces except one side of the functional surface on the assembly body by using plastic packaging material, and filling the rewiring layer in the groove at the functional surface to form at least two packaging bodies.
As a further improvement of an embodiment of the present invention, the "forming a rewiring layer on the functional surfaces of at least two chips to form at least two assemblies" specifically includes:
providing a carrier plate, arranging an assembly body on the carrier plate, and enabling one side of a functional surface of the assembly body to be abutted against the surface of the carrier plate;
Encapsulating other surfaces of the assembly body, which are not abutted against the carrier plate, by using plastic packaging materials;
And removing the carrier plate, and manufacturing a rewiring layer on the functional surface to form at least two packaging bodies.
As a further improvement of an embodiment of the present invention, the assembly includes a first assembly corresponding to the first chip, and the film layer includes a first film layer corresponding to the first chip; the step of encapsulating the plastic package material on the other sides of the assembly body except the side of the functional surface, and filling the rewiring layer in the groove at the functional surface to form at least two package bodies comprises the following steps:
Encapsulating other side surfaces except one side of the first functional surface on the first assembly body by using plastic packaging material, filling the first rewiring layer in a first groove at the first functional surface, and enabling the first rewiring layer to extend away from a plane where the first film layer is located;
the step of manufacturing the isolation voltage-resistant layer on the first functional surface side of the first package body specifically includes:
and laminating the first film layer and the first rewiring layer at one side away from the first functional surface to form the isolation pressure-resistant layer.
As a further improvement of an embodiment of the present invention, the "forming the isolation voltage-resistant layer by laminating the first thin film layer and the first rewiring layer on a side facing away from the first functional surface" specifically includes: at least twice film pressing is carried out on one side, away from the first functional surface, of the first film layer and the first rewiring layer, so that a plurality of isolation pressure-resistant layers are formed; wherein the thickness of each isolation pressure-resistant layer is 45 μm.
As a further improvement of an embodiment of the present invention, after the "forming the isolation pressure-resistant layer by laminating the first thin film layer and the first rewiring layer on a side facing away from the first functional surface", the method for manufacturing the chip structure specifically includes:
a third groove is formed in one side, away from the first packaging body, of the isolation pressure-resistant layer;
forming a second extension corresponding to the second rewiring layer in the third groove;
the "connecting the second package to the isolation voltage-resistant layer through the second rewiring layer" specifically includes: the second rewiring layer is connected with the second extension.
As a further improvement of one embodiment of the present invention, the isolation voltage-resistant layer is made of a polymer material, the voltage-resistant value of the isolation voltage-resistant layer is 300V/μm, and the interval between the first rewiring layer and the second rewiring layer is set to 25 μm.
The invention has the beneficial effects that: through carrying out rewiring between first chip and second chip to and set up the isolation withstand voltage layer between the first rewiring layer of electric connection in first chip and the second rewiring layer of electric connection in second chip in order to form the isolation withstand voltage structure, need not first chip and second chip and possess isolation capacitance characteristic, can effectively reduce the volume of encapsulation product when can satisfying encapsulation product isolation withstand voltage requirement.
Drawings
FIG. 1 is a schematic diagram of a chip package structure according to the prior art;
FIG. 2 is a schematic diagram of a chip package structure according to an embodiment of the invention;
FIG. 3 is a flow chart of a method for fabricating a package structure according to an embodiment of the invention;
fig. 4a to 4f, fig. 5a to 5f, and fig. 6 are process step diagrams of a method for manufacturing a corresponding chip package structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below in conjunction with the detailed description of the present invention and the corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
For purposes of illustration, terms that indicate relative spatial locations are used herein, such as "upper," "lower," and the like, to describe one element or feature's relationship to another element or feature's relationship shown in the figures. The term spatially relative position may include different orientations of the device in use or operation than that illustrated in the figures. For example, if the device in the figures is turned over, elements described as "below" or "over" other elements or features would then be oriented "below" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 2, an embodiment of the present invention provides a chip package structure, which includes a first chip 1, a second chip 2, a rewiring layer 3, and an isolation voltage-resistant layer 4.
The first chip 1 has a first functional surface 11 and a first nonfunctional surface opposite to the first functional surface 11, and a plurality of electrical pads are disposed on the first functional surface 11.
The second chip 2 has a second functional surface 21 disposed near the first functional surface 11, and a second non-functional surface opposite to the second functional surface 21, and a plurality of electrical pads are disposed on the second functional surface 21. Specifically, the second functional surface 21 is disposed toward the first functional surface 11.
The rewiring layer 3 is disposed between the first functional surface 11 and the second functional surface 21, and includes a first rewiring layer 31 and a second rewiring layer 32 that are close to each other, the first rewiring layer 31 is electrically connected to the first functional surface 11, and the second rewiring layer 32 is electrically connected to the second functional surface 21. Specifically, the first rewiring layer 31 is electrically connected to the electrical pads on the first functional surface 11, and the second rewiring layer 32 is electrically connected to the electrical pads on the second functional surface 21.
Preferably, the rewiring layer 3 material is copper.
Of course, in other embodiments, the rewiring layer 3 material may be other materials that are useful for electrical conductivity, such as tin, silver, and the like.
The isolation withstand voltage layer 4 is at least partially disposed between the first rewiring layer 31 and the second rewiring layer 32 for forming an isolation withstand voltage structure between the first rewiring layer 31 and the second rewiring layer 32.
In the present embodiment, the first rewiring layer 31 and the second rewiring layer 32 are provided in isolation in the normal direction of the first functional surface 11, and the isolation voltage-resistant layer 4 is entirely filled in the region between the first rewiring layer 31 and the second rewiring layer 32, thereby forming a vertical isolation structure between the first rewiring layer 31 and the second rewiring layer 32.
Specifically, the insulating pressure-resistant layer 4 is a polymer material having pressure-resistant performance, and may be a material such as polyimide and/or epoxy resin. By providing the polymer material having the voltage-resistant property between the first rewiring layer 31 and the second rewiring layer 32, the isolation capacitor does not need to be formed in the first chip 1 and the second chip 2, and the problems of unstable isolation voltage-resistant property, high processing cost, thick isolation device structure, low isolation voltage-resistant property and the like when the silicon dioxide material is used as the isolation structure are solved.
Preferably, the isolation voltage-resistant layer 4 is polyimide, and is a high voltage-resistant material, and the voltage-resistant value of the material can reach 300V/μm, so that compared with the isolation (20V/μm) with plastic packaging materials in the prior art, the voltage-resistant performance of the packaged product can be greatly improved, and meanwhile, the voltage-resistant distance can be greatly shortened, namely, in the embodiment, the interval distance between the first rewiring layer 31 and the second rewiring layer 32 can be greatly reduced.
The specific thickness of the isolation pressure-resistant layer 4 is not limited, the thickness can be adjusted according to the actual product requirement, and the isolation pressure-resistant requirement between the first chip 1 and the second chip 2 can be met only by ensuring that the interval distance between the first rewiring layer 31 and the second rewiring layer 32 is matched with the isolation performance of the isolation pressure-resistant layer 4 material.
Therefore, in the present invention, the isolation performance between the first chip 1 and the second chip 2 is related to the material specificity of the isolation withstand voltage layer 4 and the vertical distance between the first rewiring layer 31 and the second rewiring layer 32, and the higher the withstand voltage performance of the isolation withstand voltage layer 4 material, the larger the vertical distance between the first rewiring layer 31 and the second rewiring layer 32, the better the isolation performance between the first chip 1 and the second chip 2.
Illustratively, when the isolation withstand voltage layer 4 is polyimide, its withstand voltage value is 300V/μm, i.e., the vertical distance between the first rewiring layer 31 and the second rewiring layer 32 is set to 25 μm, the most basic isolation performance of the packaged product can be satisfied.
In addition, the polyimide material has heat-fixing property, low mechanical strength before solidification, convenient processing and molding, and good mechanical strength after subsequent baking and solidification, and can play a certain supporting role on the first rewiring layer 31, the second rewiring layer 32, the first chip 1 and the second chip 2. In addition, the material has stable chemical property, acid and alkali corrosion resistance and excellent thermal stability.
Of course, in other embodiments of the present invention, the material of the isolation voltage-resistant layer 4 may be other polymer materials besides polyimide and epoxy resin, and for the voltage-resistant characteristics of the different polymer materials (i.e. the voltage-resistant values of the different polymer materials), the vertical distance between the first rewiring layer 31 and the second rewiring layer 32 may be adaptively adjusted according to the voltage-resistant requirements of the packaging product, in combination with the voltage-resistant value of the isolation voltage-resistant layer 4.
Further, the chip package structure further includes a first film layer 51 that is abutted against the first functional surface 11, and a second film layer 52 that is abutted against the second functional surface 21.
Here, the first thin film layer 51 and the second thin film layer 52 may be made of the same material as the isolation pressure-resistant layer 4, or may be made of a thin film material having low isolation pressure-resistant performance, which is not limited in the present invention.
The thicknesses of the first film layer 51 and the second film layer 52 are not limited, and may be adjusted according to practical needs.
Specifically, the first film layer 51 is provided with a first groove 511 exposing the electrical pad of the first functional surface 11, and the first rewiring layer 31 is filled in the first groove 511. The second thin film layer 52 is provided with a second groove 521 exposing the electrical pad of the second functional surface 21, and the second groove 521 is filled with the second rewiring layer 32.
Further, the isolation voltage-resistant layer 4 is provided with at least two layers between the first functional surface 11 and the second functional surface 21, each layer having a thickness of 45 μm, the first rewiring layer 31 extending into at least one isolation voltage-resistant layer 4, and/or the second rewiring layer 32 extending into at least one isolation voltage-resistant layer 4.
In the embodiment of the present invention, the isolation pressure-resistant layer 4 is provided with two layers between the first functional surface 11 and the second functional surface 21, each layer being set to 45 μm. The first rewiring layer 31 extends into the isolation withstand voltage layer 4 on the side close to the first chip 1, and the second rewiring layer 32 also extends into the isolation withstand voltage layer 4 on the side close to the first chip 1. Or to enhance the isolation performance, the first rewiring layer 31 extends into the isolation withstand voltage layer 4 on the side close to the first chip 1, and the second rewiring layer 32 extends into the isolation withstand voltage layer 4 on the side close to the second chip 2.
Of course, the invention is not limited herein with respect to the number of layers of the isolation withstand voltage layer 4, the thickness of each isolation withstand voltage layer 4, and the extent to which the first rewiring layer 31 and the second rewiring layer 32 extend into the isolation withstand voltage layer 4, the greater the number of layers of the isolation withstand voltage layer 4, the greater the thickness of each isolation withstand voltage layer 4, and the greater the relative distance after the first rewiring layer 31 and the second rewiring layer 32 extend, the better the isolation performance, the multilayer wiring may correspond to different product requirements, and how the wiring may be adjusted correspondingly according to the different product requirements.
Further, the chip package structure further includes a plastic package body 6, where the plastic package body 6 is used to encapsulate the first chip 1, the second chip 2, the rewiring layer 3 and the isolation voltage-resistant layer 4.
Specifically, the plastic package 6 completely covers the side surface of the first chip 1 and a side surface away from the first functional surface 11, the side surface of the first thin film layer 51, the side surface of the second chip 2 and a side surface away from the second functional surface 21, the side surface of the second thin film layer 52, and the unmasked surfaces of the rewiring layer 3 and the isolation pressure-resistant layer 4.
Here, the molding compound 6 refers to a solid state that is present after curing the molding compound.
In the embodiment of the present invention, the voltage withstand value of the isolation voltage withstand layer 4 is larger than that of the plastic package 6.
Still further, in the subsequent process of soldering the package structure in fig. 2 to the external circuit board, the plastic package body 6 may be routed through the openings, so that the first rewiring layer 31 and the second rewiring layer 32 are electrically connected to the external circuit board respectively, thereby implementing signal transmission between the first chip 1 and the second chip 2 and the external circuit board.
As shown in fig. 3, an embodiment of the present invention provides a method for manufacturing a chip package structure, including the steps of:
S1: manufacturing rewiring layers on the functional surfaces of at least two chips to form at least two packaging bodies; the package body comprises a first package body and a second package body, wherein the first package body comprises a first chip, a first functional surface and a first rewiring layer, and the second package body comprises a second chip, a second functional surface and a second rewiring layer;
s2: manufacturing an isolation pressure-resistant layer on one side of a first functional surface of a first packaging body;
s3: the second package is connected to the isolation voltage-resistant layer through the second rewiring layer, and the second rewiring layer is arranged close to the first rewiring layer.
The manufacturing method in the specific embodiment of the invention specifically comprises three process manufacturing steps: chip pretreatment, rewiring, isolating voltage-resistant layer rewiring and flip-chip technology.
Corresponding to step S1, the chip preprocessing and rewiring process steps are adopted.
Specifically, film pressing is performed on the functional surfaces of at least two chips, grooves are formed in the formed film layer, and the electric bonding pads on the functional surfaces are exposed, so that at least two assemblies are formed.
As shown in fig. 4a, a film is pressed on the functional surface of the chip.
As shown in fig. 4b, a groove is formed in the formed thin film layer, so that the groove exposes the electrical pads on the functional surface of the chip for subsequent wiring.
As shown in fig. 4c, at least two assemblies 7 are formed by cutting.
Specifically, the assembly 7 includes a first assembly 71 corresponding to the first chip 1 and a second assembly 72 corresponding to the second chip 2, the film layer includes a first film layer 51 corresponding to the first chip 1 and a second film layer 52 corresponding to the second chip 2, and the groove formed on the film layer includes a first groove 511 corresponding to the first chip 1 and a second groove 521 corresponding to the second chip 2.
Further, the plastic package material is used for encapsulating other side surfaces except one side of the functional surface on the chip, and a rewiring layer is manufactured on the functional surface to form at least two packages.
Specifically, the plastic package material is used for encapsulating other side surfaces except one side of the functional surface on the assembly body 7, and a rewiring layer is filled in the groove at the functional surface to form at least two package bodies.
As shown in fig. 4d, a carrier 8 is provided, at least two assemblies 7 are respectively disposed on the carrier 8, and one side of the functional surface of the assemblies 7 is abutted against the surface of the carrier 8.
As shown in fig. 4e, a molding compound is provided, and encapsulates the other surface of the assembly 7 not abutted against the carrier plate 8.
Specifically, the two assemblies 7 manufactured in the above steps are respectively attached to different carrier plates 8, and one side of the functional surface of the assembly 7 is attached to the surface of the carrier plate 8. Of course, in other embodiments, the two assemblies 7 may be respectively attached to different surfaces of the same carrier 8, and the plastic packaging process may be performed at the same time, so as to improve the manufacturing efficiency.
As shown in fig. 4f, the carrier 8 is removed, and the rewiring layer 3 is fabricated on the functional surface, so as to form at least two packages 9.
Fig. 4d to fig. 4f illustrate an exemplary process performed on the first assembly 71, specifically, the plastic molding compound is encapsulated on the other side surface of the first assembly 71 except for the side of the first functional surface 11, the first rewiring layer 31 is filled in the first groove 511 at the first functional surface 11, and the first rewiring layer 31 extends away from the plane of the first film layer 51.
Of course, as shown in fig. 4d to 4f, the process flow of the second assembly 72 is also more specifically that rewiring is performed in the first film layer 51 and the first groove 511, the second film layer and the second groove, respectively, and the rewiring layer 3 formed by the manufacture extends to the thickness of the surfaces of the first film layer 51 and the second film layer and the extension length of the surfaces of the first film layer 51 and the second film layer, which is not limited in this aspect of the invention, and can be adjusted according to the wiring requirements of actual requirements of products.
The package 9 formed by the fabrication includes a first package 91 and a second package, the first package 91 including the first chip 1, the first functional surface 11, and the first rewiring layer 31, and the second package including the second chip, the second functional surface, and the second rewiring layer.
Corresponding to step S2, a process step of rewiring the isolation voltage-resistant layer is performed.
The isolation voltage-resistant layer is rewiring on one of the packages 9, for example, a first package 91 is selected, as shown in fig. 5a, a polymer material, preferably polyimide, is provided, and a film is laminated on the first thin film layer 51 and the first rewiring layer back 31 side away from the first functional surface 11 to form the isolation voltage-resistant layer 4.
Of course, in this step, the second package may be selected to manufacture the isolation voltage-resistant layer, which is not limited in the present invention.
Further, as shown in fig. 5b, a third groove 531 is formed on a side of the isolation voltage-resistant layer 4 away from the first package 91.
As shown in fig. 5c, the second extension 321 corresponding to the second rewiring layer is formed in the third groove 531, i.e., the third groove 531 is filled with a conductive material.
Further, the first thin film layer 51 and the first rewiring layer 31 are laminated at least twice on the side facing away from the first functional surface 11, so as to form a plurality of isolation voltage-resistant layers 4. Wherein the thickness of each isolation withstand voltage layer 4 is 45 μm.
As shown in fig. 5d, the second isolation withstand voltage layer 4 is formed by laminating the insulating withstand voltage layer 4 again after the first formation.
As shown in fig. 5e to 5f, a groove is formed on the side of the second isolation voltage-resistant layer 4 away from the first functional surface 11, and conductive material is filled in the groove again, so that the second package is flip-chip bonded to the structure in fig. 5f, and the conductive material filled in the groove in this step may also be the second extension 321 corresponding to the second rewiring layer.
Corresponding to step S3, the flip-chip process step is adopted.
As shown in fig. 6, the second package 92 is connected to the isolation withstand voltage layer 4 through the second rewiring layer 32, and the second rewiring layer 32 is disposed close to the first rewiring layer 31.
Specifically, the second rewiring layer 32 is connected to the second extension 321.
In the package structure shown in fig. 6, the isolation voltage-resistant layer 4 is made of a polymer material, preferably polyimide, and has a voltage-resistant value of 300V/μm, and the isolation performance of the package product, which is the most basic, can be satisfied by setting the interval between the first rewiring layer 31 and the second rewiring layer 32 to 25 μm.
Of course, the invention is not limited herein with respect to the arrangement of the number of layers of the isolation voltage-resistant layer 4 and with respect to the extent to which the first rewiring layer 31 and the second rewiring layer 32 extend into the isolation voltage-resistant layer 4, and the greater the number of layers of the isolation voltage-resistant layer 4 and the greater the relative distance after the first rewiring layer 31 and the second rewiring layer 32 extend, the better the isolation performance, the multilayer wiring can correspond to different product requirements, and how the wiring can be correspondingly adjusted according to the different product requirements.
In summary, in the invention, through rewiring between the first chip and the second chip and arranging the isolation voltage-resistant layer between the first rewiring layer electrically connected to the first chip and the second rewiring layer electrically connected to the second chip, a vertical isolation voltage-resistant structure is formed, and the first chip and the second chip do not need to have isolation capacitance characteristics, so that the volume of the packaged product can be effectively reduced while the isolation voltage-resistant requirement of the packaged product can be met. Meanwhile, compared with the prior art, the vertical isolation pressure-resistant structure is formed by adopting a panel-level packaging process without frame packaging and adopting a rewiring process, and the middle isolation pressure-resistant layer can be made of high-molecular pressure-resistant materials such as polyimide and/or epoxy resin, so that the spacing of the isolation layers can be greatly reduced, the isolation performance is improved, and the volume of the package body is reduced.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (15)
1. A chip package structure, comprising:
The first chip is provided with a first functional surface;
the second chip is provided with a second functional surface which is arranged close to the first functional surface;
the rewiring layer is arranged between the first functional surface and the second functional surface and comprises a first rewiring layer and a second rewiring layer which are close to each other, wherein the first rewiring layer is electrically connected with the first functional surface, and the second rewiring layer is electrically connected with the second functional surface;
And the isolation voltage-resistant layer is at least partially arranged between the first rewiring layer and the second rewiring layer and is used for forming an isolation voltage-resistant structure between the first rewiring layer and the second rewiring layer.
2. The chip package structure of claim 1, wherein the isolation voltage-resistant layer is a polymer material.
3. The chip packaging structure according to claim 2, wherein the isolating voltage-resistant layer material is polyimide and/or epoxy resin.
4. The chip package structure of claim 1, further comprising a plastic package for encapsulating the first chip, the second chip, the rewiring layer, and the isolation voltage resistant layer; the voltage withstand value of the isolation voltage withstand layer is larger than that of the plastic package body.
5. The chip package structure of claim 1, further comprising a first film layer that is attached to the first functional surface and a second film layer that is attached to the second functional surface;
The first film layer is provided with a first groove exposing the electrical bonding pad of the first functional surface, and the first groove is filled with the first rewiring layer; the second film layer is provided with a second groove exposing the electrical bonding pad of the second functional surface, and the second groove is filled with the second rewiring layer.
6. The chip package structure according to claim 3, wherein the isolation voltage-resistant layer has a voltage-resistant value of 300V/μm, and a space between the first rewiring layer and the second rewiring layer is 25 μm.
7. The chip packaging structure according to claim 1, wherein the isolation pressure-resistant layer is provided with at least two layers between the first functional surface and the second functional surface, each layer having a thickness of 45 μm;
the first rewiring layer extends into at least one of the isolation voltage resistant layers, and/or the second rewiring layer extends into at least one of the isolation voltage resistant layers.
8. The manufacturing method of the chip packaging structure is characterized by comprising the following steps:
Manufacturing rewiring layers on the functional surfaces of at least two chips to form at least two packaging bodies; the package body comprises a first package body and a second package body, wherein the first package body comprises a first chip, a first functional surface and a first rewiring layer, and the second package body comprises a second chip, a second functional surface and a second rewiring layer;
Manufacturing an isolation pressure-resistant layer on one side of a first functional surface of the first packaging body;
the second package is connected to the isolation withstand voltage layer through the second rewiring layer, and the second rewiring layer is disposed close to the first rewiring layer.
9. The method of manufacturing a chip package structure according to claim 8, wherein the step of manufacturing a rewiring layer on the functional surfaces of the at least two chips to form the at least two packages specifically comprises:
and encapsulating the other side surfaces except one side of the functional surface on the chip by using the plastic packaging material, and manufacturing a rewiring layer on the functional surface to form at least two packaging bodies.
10. The method of manufacturing a chip package according to claim 9, wherein the encapsulating the plastic material on the other sides of the chip except the functional surface side, and manufacturing a rewiring layer on the functional surface, to form at least two packages, specifically comprises:
Film pressing is carried out on the functional surfaces of at least two chips, grooves are formed in the formed film layers, and the electric bonding pads on the functional surfaces are exposed, so that at least two assemblies are formed;
and encapsulating the other side surfaces except one side of the functional surface on the assembly body by using plastic packaging material, and filling the rewiring layer in the groove at the functional surface to form at least two packaging bodies.
11. The method of manufacturing a chip package structure according to claim 10, wherein the step of manufacturing a rewiring layer on the functional surfaces of the at least two chips to form the at least two assemblies specifically comprises:
providing a carrier plate, arranging an assembly body on the carrier plate, and enabling one side of a functional surface of the assembly body to be abutted against the surface of the carrier plate;
Encapsulating other surfaces of the assembly body, which are not abutted against the carrier plate, by using plastic packaging materials;
And removing the carrier plate, and manufacturing a rewiring layer on the functional surface to form at least two packaging bodies.
12. The method of claim 10, wherein the assembly comprises a first assembly corresponding to the first chip, and the film layer comprises a first film layer corresponding to the first chip; the step of encapsulating the plastic package material on the other sides of the assembly body except the side of the functional surface, and filling the rewiring layer in the groove at the functional surface to form at least two package bodies comprises the following steps:
Encapsulating other side surfaces except one side of the first functional surface on the first assembly body by using plastic packaging material, filling the first rewiring layer in a first groove at the first functional surface, and enabling the first rewiring layer to extend away from a plane where the first film layer is located;
the step of manufacturing the isolation voltage-resistant layer on the first functional surface side of the first package body specifically includes:
and laminating the first film layer and the first rewiring layer at one side away from the first functional surface to form the isolation pressure-resistant layer.
13. The method for manufacturing a chip package structure according to claim 12, wherein the forming the isolation voltage-resistant layer by laminating the first thin film layer and the first rewiring layer on a side facing away from the first functional surface specifically includes: at least twice film pressing is carried out on one side, away from the first functional surface, of the first film layer and the first rewiring layer, so that a plurality of isolation pressure-resistant layers are formed; wherein the thickness of each isolation pressure-resistant layer is 45 μm.
14. The method for manufacturing a chip package according to claim 12, wherein after the step of forming the isolation pressure-resistant layer by laminating the first thin film layer and the first rewiring layer on a side facing away from the first functional surface, the method for manufacturing a chip package specifically comprises:
a third groove is formed in one side, away from the first packaging body, of the isolation pressure-resistant layer;
forming a second extension corresponding to the second rewiring layer in the third groove;
the "connecting the second package to the isolation voltage-resistant layer through the second rewiring layer" specifically includes: the second rewiring layer is connected with the second extension.
15. The method of manufacturing a chip package according to claim 8, wherein the isolation voltage-resistant layer is made of a polymer material, a voltage-resistant value of the isolation voltage-resistant layer is 300V/μm, and a space between the first rewiring layer and the second rewiring layer is set to 25 μm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310219527.2A CN118431189A (en) | 2023-01-31 | 2023-01-31 | Chip packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310219527.2A CN118431189A (en) | 2023-01-31 | 2023-01-31 | Chip packaging structure and manufacturing method thereof |
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| CN118431189A true CN118431189A (en) | 2024-08-02 |
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| CN202310219527.2A Pending CN118431189A (en) | 2023-01-31 | 2023-01-31 | Chip packaging structure and manufacturing method thereof |
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- 2023-01-31 CN CN202310219527.2A patent/CN118431189A/en active Pending
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