CN118447796A - Timing control device and driving method thereof, display panel, and display device - Google Patents

Abstract

A time sequence control device and a driving method thereof, a display panel and a display device are provided, wherein the time sequence control device is suitable for the display panel to dynamically adjust the time sequence of the luminous initial signal pulse width; the content displayed on the display panel includes: a plurality of display frames, the display panel comprising: the light-emitting initial signal line, the timing of at least one display frame includes: a display phase, the display phase comprising: refreshing the frame and maintaining the frame; the timing control device is configured to supply a first pulse signal to the light emission initial signal line in a refresh frame and a plurality of second pulse signals to the light emission initial signal line in a hold frame, the first pulse signal having a pulse width greater than a pulse width of at least one of the second pulse signals.

Description

Timing control device and driving method thereof, display panel, and display device

Technical Field

The present disclosure relates to but is not limited to display technology, and in particular to a timing control device and a driving method thereof, a display panel, and a display device.

Background technique

Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

Summary of the invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

In a first aspect, an embodiment of the present disclosure provides a timing control device, which is applicable to a display panel to dynamically adjust the timing of a pulse width of an initial light-emitting signal, wherein the content displayed by the display panel includes: a plurality of display frames, the display panel includes: an initial light-emitting signal line, and the timing of at least one display frame includes: a display stage, and the display stage includes: a refresh frame and a hold frame;

The timing control device is configured to provide a first pulse signal to the light-emitting initial signal line in a refresh frame and provide multiple second pulse signals to the light-emitting initial signal line in a hold frame, wherein the pulse width of the first pulse signal is greater than the pulse width of at least one second pulse signal.

In some possible implementations, the timing of at least one display frame includes: a first blanking period and a second blanking period, wherein the first blanking period occurs before the display phase, and the second blanking period occurs after the display phase;

The first pulse signal and the plurality of second pulse signals satisfy the following conditions:

1-((A1+A2+A3+…+An)/(H+VFP+VBP))=EM_DUTY%, wherein EM_DUTY% is a preset luminous duty cycle, A1 is a pulse width of the first pulse signal, A2 is a pulse width of the first second pulse signal, An is a pulse width of the n-1th second pulse signal, H is the number of rows driven in a display stage, VFP is the number of rows driven in the first blanking period, VBF is the number of rows driven in the second blanking period, and (H+VFP+VBP) is divisible by n.

In some possible implementations, EM_DUTY% ≥ 90%.

In some possible implementations, the minimum width of A1 is 96H.

In some possible implementations, the minimum width of Ai is 4H, i=2, 3...n.

In some possible implementations, it is characterized in that n≥1.

In a second aspect, an embodiment of the present disclosure provides a display panel, comprising: a timing control device as described in any embodiment of the first aspect;

The display panel also includes: sub-pixels arranged in an array in the display area and a first driving circuit in the non-display area, at least one sub-pixel includes: a pixel circuit, the pixel circuit includes: a light-emitting transistor, the first driving circuit is electrically connected to the light-emitting transistor and the light-emitting initial signal line, respectively, and the light-emitting initial signal line is configured to provide a light-emitting initial signal to the first driving circuit.

In some possible implementations, the display panel further includes: a second driving circuit and a compensation initial signal line, the pixel circuit further includes: a compensation transistor, the second driving circuit is electrically connected to the compensation transistor and the compensation initial signal line, respectively, and the compensation initial signal line is configured to provide a compensation initial signal to the second driving circuit;

The timing control device provides a third pulse signal to the compensation initial signal line in a refresh frame, and a time period of the third pulse signal at least partially overlaps with a time period of the first pulse signal.

In some possible implementations, the time period of the third pulse signal is within the time period of the first pulse signal, and the duration of the third pulse signal is shorter than the duration of the first pulse signal.

In some possible implementations, the display panel further includes a third driving circuit and a first reset initial signal line, the pixel circuit further includes: a first node reset transistor, the third driving circuit is electrically connected to the first node reset transistor and the first reset initial signal line, respectively, and the first reset initial signal line is configured to provide a first reset initial signal to the third driving circuit;

The timing control device provides a fourth pulse signal to the first reset initial signal line in a refresh frame, and a time period of the fourth pulse signal at least partially overlaps with a time period of the first pulse signal.

In some possible implementations, the time period of the fourth pulse signal is partially located within the time period of the first pulse signal, and the duration of the fourth pulse signal is shorter than the duration of the first pulse signal.

In some possible implementations, the display panel further includes a fourth drive circuit and a second reset initial signal line, the pixel circuit further includes: an anode reset transistor and a second node reset transistor, the fourth drive circuit is electrically connected to the anode reset transistor, the second node reset transistor and the second reset initial signal line, respectively, and the second reset initial signal line is configured to provide a second reset initial signal to the fourth drive circuit;

The timing control device provides a fifth pulse signal to the second reset initial signal line in a refresh frame, and a time period of the fifth pulse signal at least partially overlaps with a time period of the first pulse signal.

In some possible implementations, the time period of the fifth pulse signal is within the time period of the first pulse signal, and the duration of the fifth pulse signal is shorter than the duration of the first pulse signal.

In some possible implementations, the display panel further includes a fifth driving circuit and a data initial signal line, the pixel circuit further includes: a data writing transistor, the fifth driving circuit is electrically connected to the data writing transistor and the data initial signal line, respectively, and the data initial signal line is configured to provide a data initial signal to the fifth driving circuit;

The timing control device provides a sixth pulse signal to the data initial signal line in a refresh frame, and a time period of the sixth pulse signal at least partially overlaps with a time period of the first pulse signal.

In some possible implementations, the time period in which the sixth pulse signal is located is partially within the time period in which the first pulse signal is located, and the duration of the sixth pulse signal is shorter than the duration of the first pulse signal.

In some possible implementations, the display panel further includes: a first reset signal line, a second reset signal line, a data signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first scan signal line, a second scan signal line, and a first power line; the light emitting transistor includes a first light emitting transistor and a second light emitting transistor; and the pixel circuit further includes: a compensation transistor, a first node reset transistor, an anode reset transistor, a second node reset transistor, a data write transistor, a drive transistor, and a capacitor;

The control electrode of the compensation transistor is electrically connected to the second scanning signal line, the first electrode of the compensation transistor is electrically connected to the first node, and the second electrode of the compensation transistor is electrically connected to the third node;

The control electrode of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

The control electrode of the data writing transistor is electrically connected to the first scanning signal line, the first electrode of the data writing transistor is electrically connected to the data signal line, and the second electrode of the data writing transistor is electrically connected to the second node;

The control electrode of the first node reset transistor is electrically connected to the first reset signal line, the first electrode of the first node reset transistor is electrically connected to the first initial signal line, and the second electrode of the first node reset transistor is electrically connected to the third node;

The control electrode of the anode reset transistor is electrically connected to the second reset signal line, the first electrode of the anode reset transistor is electrically connected to the second initial signal line, and the second electrode of the anode reset transistor is electrically connected to the fourth node;

The control electrode of the second node reset transistor is electrically connected to the second reset signal line, the first electrode of the second node reset transistor is electrically connected to the third initial signal line, and the second electrode of the second node reset transistor is electrically connected to the second node;

The control electrode of the first light emitting transistor is electrically connected to the light emitting signal line, the first electrode of the first light emitting transistor is electrically connected to the first power line, and the second electrode of the first light emitting transistor is electrically connected to the second node;

The control electrode of the second light emitting transistor is electrically connected to the light emitting signal line, the first electrode of the second light emitting transistor is electrically connected to the third node, and the second electrode of the second light emitting transistor is electrically connected to the fourth node;

The capacitor includes a first plate and a second plate. The first plate of the capacitor is electrically connected to the first power line, and the second plate of the capacitor is electrically connected to the first node.

In some possible implementations, at least one transistor in the pixel circuit is a P-type transistor or an N-type transistor, the first light-emitting transistor and the second light-emitting transistor are of the same transistor type, and the anode reset transistor and the second node reset transistor are of the same transistor type.

In a third aspect, an embodiment of the present disclosure provides a display device, comprising: a display panel as described in any one of the second aspects.

In a fourth aspect, an embodiment of the present disclosure provides a method for driving a timing control device, which is configured to drive the timing control device as described in any one of the first aspects, and the method includes:

A first pulse signal is provided to the light-emitting initial signal line in a refresh frame, and a plurality of second pulse signals are provided to the light-emitting initial signal line in a hold frame, wherein a pulse width of the first pulse signal is greater than a pulse width of at least one second pulse signal.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

FIG1 is a schematic diagram of the structure of a display panel;

FIG2A is a schematic diagram of a planar structure of a display panel;

FIG2B is a second schematic diagram of a planar structure of a display panel;

FIG2C is a third schematic diagram of a planar structure of a display panel;

FIG3 is a schematic diagram of a cross-sectional structure of a display panel;

FIG4 is a timing diagram of at least one display frame;

FIG5A is a schematic diagram of a pulse signal before adjustment;

FIG5B is a schematic diagram of a pulse signal after adjustment;

FIG6 is a schematic diagram of a display panel;

FIG7 is a schematic diagram of an equivalent circuit of a pixel circuit in a display panel;

FIG. 8 is a working timing diagram of the pixel circuit provided in FIG. 7 .

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values shown in the drawings.

In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

In this specification, for the sake of convenience, words and phrases indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the materials of the precursors forming the multiple structures arranged in the same layer are the same, and the materials finally formed may be the same or different.

The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

FIG. 1 is a schematic diagram of the structure of a display panel. As shown in FIG. 1 , the display panel may include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, wherein the timing controller is respectively connected to the data driver, the scan driver, and the light emitting driver, wherein the data driver is respectively connected to a plurality of data signal lines, the scan driver is respectively connected to a plurality of scan signal lines, and the light emitting driver is respectively connected to a plurality of light emitting signal lines. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel circuit, and the pixel circuit may be respectively connected to the scan signal line, the light emitting signal line, and the data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emitting driver to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal line using the grayscale value and the control signal received from the timing controller. For example, the data driver can sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal line in units of pixel rows. The scan driver can generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver can sequentially provide a scan signal with a conduction level pulse to the scan signal line. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit to generate the scan signal under the control of the clock signal. The light-emitting driver can generate an emission signal to be provided to the light-emitting signal line by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide an emission signal with a cut-off level pulse to the light-emitting signal line. For example, the light-emitting driver can be constructed in the form of a shift register, and can sequentially transmit the emission stop signal provided in the form of a cut-off level pulse to the next level circuit to generate the emission signal under the control of the clock signal.

FIG. 2A is a schematic diagram of a planar structure of a display panel, FIG. 2B is a schematic diagram of a planar structure of a display panel, and FIG. 2C is a schematic diagram of a planar structure of a display panel. As shown in FIG. 2A to FIG. 2C, the display panel may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel circuit and a light-emitting device. The pixel circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel circuit of the sub-pixel in which they are located.

In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.

In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or in a herringbone manner, which is not limited in the present disclosure. FIG. 2A is an example in which a pixel unit includes three sub-pixels, and the three sub-pixels are arranged in a horizontal parallel manner, and FIG. 2B is an example in which a pixel unit includes three sub-pixels, and the three sub-pixels are arranged in a herringbone manner.

In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, square or diamond shape, etc., which is not limited in the present disclosure. FIG. 2C is an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square shape.

In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged horizontally, vertically or in a herringbone pattern, which is not limited in the present disclosure.

FIG3 is a schematic diagram of a cross-sectional structure of a display panel, illustrating the structure of three sub-pixels of the display panel. As shown in FIG3, on a plane perpendicular to the display panel, the display panel may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display panel may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit, and FIG3 only takes one transistor 101 and one capacitor 101A as an example. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of corresponding colors under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

In an exemplary embodiment, the organic light emitting layer 303 may include a light emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In an exemplary embodiment, the touch structure layer of each sub-pixel may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer; the first touch metal layer may include a plurality of bridging electrodes; the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes; the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

The brightness adjustment of the display panel is usually driven by the dimming method of light control. When the pulse signal of the light control is set to a pulse number, the brightness drop is relatively large. The brightness drop refers to the brightness from the light-emitting stage to the non-light-emitting stage after the light-emitting stage.

An embodiment of the present disclosure provides a timing control device, which is applicable to a display panel to dynamically adjust the timing of the pulse width of an initial light-emitting signal. The content displayed by the display panel includes: multiple display frames, and the display panel includes: an initial light-emitting signal line. The timing of at least one display frame may include: a display stage, and the display stage may include: a refresh frame and a hold frame.

The timing control device is configured to provide a first pulse signal to the light-emitting initial signal line in a refresh frame and provide multiple second pulse signals to the light-emitting initial signal line in a hold frame, wherein the pulse width of the first pulse signal is greater than the pulse width of at least one second pulse signal.

The timing control device provides a first pulse signal to the initial light-emitting signal line in the refresh frame to write the data signal, and the light-emitting device emits light. The timing control device provides multiple second pulse signals to the initial light-emitting signal line in the hold frame to write the data signal, and the light-emitting device maintains the brightness of the refresh frame.

In an exemplary embodiment, the first pulse signal and the second pulse signal may be light-emitting initial signals.

The pulse width of at least one second pulse signal is smaller than the pulse width of the first pulse signal, that is, the pulse width of the second pulse signal in the holding frame is reduced. In the case of multiple pulses, a high luminous duty cycle can be achieved and brightness drop can be reduced.

In an exemplary embodiment, the timing of at least one display frame may include: a first blanking period and a second blanking period, the first blanking period occurs before the display phase, and the second blanking period occurs after the display phase. FIG4 is a timing diagram of at least one display frame. As shown in FIG4, the first pulse signal and the plurality of second pulse signals may meet the following conditions:

1-((A1+A2+A3+…+An)/(H+VFP+VBP))=EM_DUTY%,

Among them, EM_DUTY% is the preset luminous duty cycle, A1 is the pulse width of the first pulse signal, A2 is the pulse width of the first second pulse signal, An is the width of the pulse signal of the n-1th second pulse signal, H is the number of rows driven in a display stage, VFP is the number of rows driven in the first blanking period, VBF is the number of rows driven in the second blanking period, and (H+VFP+VBP) is divisible by n.

In an exemplary embodiment, EM_DUTY%≥90%, the preset luminous duty cycle EM_DUTY% is greater than or equal to 90%, and a high luminous duty cycle can be achieved under multi-pulse conditions by reducing the pulse width of the second pulse signal in the holding frame.

In an exemplary embodiment, the minimum width of A1 is 96H.

In an exemplary embodiment, the minimum width of Ai is 4H, i=2, 3...n.

In an exemplary embodiment, n≥1.

In an exemplary embodiment, as shown in Figure 4, n=4, A1 is the width of the first pulse signal B1, A2 is the width of the first second pulse signal B2, A3 is the width of the second second pulse signal B3, and A4 is the width of the third second pulse signal B4.

An embodiment of the present disclosure provides a display panel, including: a timing control device, the timing control device is the timing control device provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

The display panel may further include: array-arranged sub-pixels located in the display area and a first driving circuit located in the non-display area, at least one sub-pixel including: a pixel circuit. The pixel circuit may include: a light-emitting transistor, a first driving circuit, electrically connected to the light-emitting transistor and a light-emitting initial signal line, respectively, and the light-emitting initial signal line is configured to provide a light-emitting initial signal to the first driving circuit.

In an exemplary embodiment, the display panel may further include: a second driving circuit and a compensation initial signal line, and the pixel circuit may further include: a compensation transistor, a second driving circuit, electrically connected to the compensation transistor and the compensation initial signal line, respectively, and the compensation initial signal line is configured to provide a compensation initial signal to the second driving circuit.

The timing control device provides a third pulse signal NSTV to the compensation initial signal line in a refresh frame, and a time period of the third pulse signal at least partially overlaps with a time period of the first pulse signal.

In an exemplary embodiment, as shown in FIG. 4 , the time period of the third pulse signal is within the time period of the first pulse signal, and the duration of the third pulse signal is shorter than the duration of the first pulse signal.

In an exemplary embodiment, the third pulse signal may be a compensated initial signal.

In an exemplary embodiment, the display panel may further include a third driving circuit and a first reset initial signal line, and the pixel circuit may further include: a first node reset transistor, a third driving circuit, electrically connected to the first node reset transistor and the first reset initial signal line, respectively, and the first reset initial signal line is configured to provide a first reset initial signal to the third driving circuit.

The timing control device provides a fourth pulse signal PSTV to the first reset initial signal line in a refresh frame, and a time period of the fourth pulse signal at least partially overlaps a time period of the first pulse signal.

In an exemplary embodiment, as shown in FIG. 4 , the time period in which the fourth pulse signal is located is partially within the time period in which the first pulse signal is located, and the duration of the fourth pulse signal is shorter than the duration of the first pulse signal.

In an exemplary embodiment, the fourth pulse signal may be a first reset initial signal.

In an exemplary embodiment, the display panel may further include a fourth driving circuit and a second reset initial signal line, and the pixel circuit may further include: an anode reset transistor and a second node reset transistor, the fourth driving circuit being electrically connected to the anode reset transistor, the second node reset transistor and the second reset initial signal line, respectively, and the second reset initial signal line being configured to provide a second reset initial signal to the fourth driving circuit.

The timing control device provides a fifth pulse signal HSTV to the second reset initial signal line in a refresh frame, and a time period of the fifth pulse signal at least partially overlaps a time period of the first pulse signal.

In an exemplary embodiment, as shown in FIG. 4 , the time period of the fifth pulse signal is within the time period of the first pulse signal, and the duration of the fifth pulse signal is shorter than the duration of the first pulse signal.

In an exemplary embodiment, the fifth pulse signal may be a second reset initial signal.

In an exemplary embodiment, the display panel may further include a fifth driving circuit and a data initial signal line, and the pixel circuit may further include: a data write transistor, a fifth driving circuit, electrically connected to the data write transistor and the data initial signal line, respectively, and the data initial signal line is configured to provide a data initial signal to the fifth driving circuit.

The timing control device provides a sixth pulse signal GSTV to the data initial signal line in a refresh frame, and a time period of the sixth pulse signal at least partially overlaps a time period of the first pulse signal.

In an exemplary embodiment, as shown in FIG. 4 , the time period in which the sixth pulse signal is located is partially within the time period in which the first pulse signal is located, and the duration of the sixth pulse signal is shorter than the duration of the first pulse signal.

In an exemplary embodiment, the sixth pulse signal may be a data initial signal.

In an exemplary embodiment, FIG. 5A is a schematic diagram of a pulse signal before adjustment, and FIG. 5B is a schematic diagram of a pulse signal after adjustment. As shown in FIG. 5A, within a display cycle, the pulse signal of the luminous initial signal ESTV is evenly distributed, that is, the pulse width of the first pulse signal written in the refresh frame is consistent with the pulse width of each second pulse signal written in the holding frame, resulting in the maximum luminous duty cycle EM_DUTY being limited by the pulse and being less than or equal to 60%. As shown in FIG. 5B, under the condition that the minimum pulse width of the first pulse signal (its minimum high level width is 96H) of the five groups of initial signals (luminous initial signal ESTV, compensation initial signal NSTV, first reset initial signal PSTV, second reset initial signal HSTV and data initial signal GSTV) is met, the high level width of the second pulse signal is minimized, that is, the high level width of the second pulse signal in the holding frame is dynamically adjusted, and a higher luminous duty cycle EM_DUTY (≥90%) is achieved in the case of multiple pulses.

In an exemplary embodiment, FIG6 is a schematic diagram of a display panel. As shown in FIG6, the display panel is provided with a fingerprint unlocking identification area, and an optical fingerprint unlocking screen can be used. When the pulse signal of the light emitting control is set to one pulse number, the brightness drop is relatively large. In order to reduce the brightness drop, it is necessary to increase the number of pulses of the light emitting control signal. When the number of pulses of the light emitting control signal is increased, the light emitting duty cycle will be reduced synchronously. Then, the pulse width of the fingerprint unlocking identification area that is not displayed on the display panel per unit time increases, resulting in fingerprint unlocking failure.

Figure 6 (a) is a schematic diagram of the display state of the fingerprint unlocking identification area before the pulse width of the second pulse signal is adjusted. When the fingerprint is unlocked, the interval in which the fingerprint unlocking identification area is not displayed is large, and each width is equal. Figure 6 (b) is a schematic diagram of the display state of the fingerprint unlocking identification area after the pulse width of the second pulse signal is adjusted. As shown in Figure 6, the embodiment of the present disclosure provides a first pulse signal to the initial light-emitting signal line in the refresh frame through a timing control device, and provides multiple second pulse signals to the initial light-emitting signal line in the hold frame. The pulse width of the first pulse signal is greater than the pulse width of at least one second pulse signal. The pulse width of at least one second pulse signal is less than the pulse width of the first pulse signal, and the high level width of the second pulse signal is minimized, that is, the high level width of the second pulse signal in the hold frame is dynamically adjusted. In the case of multiple pulses, a high light-emitting duty cycle can be achieved and the brightness drop can be reduced, thereby improving the fingerprint unlocking success rate.

In an exemplary embodiment, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 7 is a schematic diagram of an equivalent circuit of a pixel circuit in a display panel. As shown in Figure 7, the display panel also includes: a first reset signal line Reset-P, a second reset signal line Reset-H, a data signal line Data, a first initial signal line Vint1, a second initial signal line Vint2, a third initial signal line Vint3, a first scan signal line Gate-P, a second scan signal line Gate-N and a first power line VDD, the light-emitting transistor includes a first light-emitting transistor T5 and a second light-emitting transistor T6, and the pixel circuit also includes: a compensation transistor T2, a first node reset transistor T1, an anode reset transistor T7, a second node reset transistor T8, a data write transistor T4, a drive transistor T3 and a capacitor C.

As shown in FIG7 , the control electrode of the compensation transistor T2 is electrically connected to the second scanning signal line Gate-N, the first electrode of the compensation transistor T2 is electrically connected to the first node N1, and the second electrode of the compensation transistor T2 is electrically connected to the third node N3; the control electrode of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3; the control electrode of the data writing transistor T4 is electrically connected to the first scanning signal line Gate-P, the first electrode of the data writing transistor T4 is electrically connected to the data signal line Data, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2; the control electrode of the first node reset transistor T1 is electrically connected to the first reset signal line Reset-P, the first electrode of the first node reset transistor T1 is electrically connected to the first initial signal line Vint1, and the second electrode of the first node reset transistor T1 is electrically connected to the third node N3; the control electrode of the anode reset transistor T7 is electrically connected to the second reset signal line Reset-H, and the anode reset The first electrode of the transistor T7 is electrically connected to the second initial signal line Vint2, and the second electrode of the anode reset transistor T7 is electrically connected to the fourth node N4; the control electrode of the second node reset transistor T8 is electrically connected to the second reset signal line Reset-H, the first electrode of the second node reset transistor T8 is electrically connected to the third initial signal line Vint3, and the second electrode of the second node reset transistor T8 is electrically connected to the second node N2; the control electrode of the first light-emitting transistor T5 is electrically connected to the light-emitting signal line EM, the first electrode of the first light-emitting transistor T5 is electrically connected to the first power line VDD, and the second electrode of the first light-emitting transistor T5 is electrically connected to the second node N2; the control electrode of the second light-emitting transistor T6 is electrically connected to the light-emitting signal line EM, the first electrode of the second light-emitting transistor T6 is electrically connected to the third node N3, and the second electrode of the second light-emitting transistor T6 is electrically connected to the fourth node N4; the capacitor C includes a first plate electrode C11 and a second plate electrode C12, the first plate electrode C11 of the capacitor is electrically connected to the first power line VDD, and the second plate electrode C12 of the capacitor is electrically connected to the first node N1.

In an exemplary embodiment, the second reset signal line Reset-H connected to the anode reset transistor T7 and the second reset signal line Reset-H connected to the second node reset transistor T8 may be the same signal line, or may be different signal lines with the same signal, and the present disclosure does not make any limitation on this.

In an exemplary embodiment, as shown in Fig. 7, the display panel may further include: a second power line VSS. The light emitting device L may be electrically connected to the fourth node N4 and the second power line VSS.

In an exemplary embodiment, the light emitting element L may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED). The OLED may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), the first electrode of the OLED being connected to the fourth node N4, and the second electrode of the OLED being electrically connected to the second power line VSS.

In an exemplary embodiment, the signal of the first power line VDD is a continuously high level signal, and the signal of the second power line VSS is a low level signal.

In an exemplary embodiment, when the first reset signal line Reset-P provides an active level signal, the first node reset transistor T1 transmits the first initial signal of the first initial signal line Vinit1 to the third node N3 to initialize the charge amount of the third node N3.

In an exemplary embodiment, when the second scan signal line Gate-N provides an effective level signal, the compensation transistor T2 transmits the signal of the third node N3 to the first node N1, and can perform threshold compensation on the driving transistor T3 or initialize the charge amount of the first node N1.

In an exemplary embodiment, the driving transistor T3 determines the driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between the control electrode and the first electrode.

In an exemplary embodiment, when the first scan signal line Gate-P inputs an active level signal, the data write transistor T4 allows the data voltage of the data signal line Data to be input to the second node N2.

In an exemplary embodiment, when the light emitting signal line EM inputs an effective level signal, the first light emitting transistor T5 and the second light emitting transistor T6 enable the light emitting element to emit light by forming a driving current path between the first power line VDD and the second power line VSS.

In an exemplary embodiment, when the second reset signal line Reset-H provides an effective level signal, the anode reset transistor T7 transmits the second initial signal of the second initial signal line Vinit2 to the anode of the light emitting element L to initialize the charge amount of the anode of the light emitting element.

In an exemplary embodiment, when the second reset signal line Reset-H provides an effective level signal, the second node reset transistor T8 transmits the third initial signal of the third initial signal line Vinit3 to the second node N2, and can initialize the charge amount of the second node N2.

In an exemplary embodiment, transistors can be divided into N-type transistors and P-type transistors according to the characteristics of the transistors. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V or other suitable voltages).

In an exemplary embodiment, at least one transistor in the pixel circuit is a P-type transistor or an N-type transistor, the first light-emitting transistor T5 and the second light-emitting transistor T6 are of the same transistor type, and the anode reset transistor T7 and the second node reset transistor T8 are of the same transistor type. FIG. 7 is illustrated by taking the compensation transistor T2 as an N-type transistor and the other transistors as P-type transistors as an example.

In an exemplary embodiment, the first node reset transistor T1 may be a P-type transistor or an N-type transistor. For example, the P-type transistor may be a low temperature polysilicon transistor, and the N-type transistor may be a metal oxide transistor.

In an exemplary embodiment, the compensation transistor T2 may be an N-type transistor, which can reduce leakage current, improve the performance of the pixel circuit, and reduce the power consumption of the pixel circuit.

FIG8 is a working timing diagram of the pixel circuit provided in FIG7. The following describes an exemplary embodiment of the present disclosure through the working process of the pixel circuit in the display stage shown in FIG7. FIG8 is described by taking the compensation transistor T2 as an N-type transistor, the first node reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light emitting transistor T5, the second light emitting transistor T6, the anode reset transistor T7, and the second node reset transistor T8 as P-type transistors as an example.

In conjunction with FIG. 7 and FIG. 8 , the operation process of the pixel circuit may include:

In the first stage S11, i.e., the first initialization stage, the signals of the first scanning signal line Gate-P, the second scanning signal line Gate-N, the first reset signal line Reset-P and the light-emitting signal line EM are all high-level signals, and the signal of the second reset signal line Reset-H is a low-level signal. The signal of the second reset signal line Reset-H is a low-level signal, the anode reset transistor T7 and the second node reset transistor T8 are turned on, the second initial signal of the second initial signal line Vinit2 is written into the fourth node N4, the fourth node N4 (i.e., the first pole of the light-emitting device) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written into the second node N2 and the third node N3, the second node N2 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The signal of the second scanning signal line Gate-N is a high-level signal, the compensation transistor T2 is turned on, the signal of the third node N3 is written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. In this stage, the driving transistor T3 is turned on. The signals of the first scanning signal line Gate-P, the second reset signal line Reset-H and the light-emitting signal line EM are high-level signals, and the data writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the anode reset transistor T7 and the second node reset transistor T8 are turned off. In this stage, the light-emitting element L does not emit light.

In the second stage S12, i.e., the second initialization stage, the signals of the first scanning signal line Gate-P, the second scanning signal line Gate-N, the second reset signal line Reset-H and the light-emitting signal line EM are all high-level signals, and the signal of the first reset signal line Reset-P is a low-level signal. The signal of the first reset signal line Reset-P is a low-level signal, the first node reset transistor T1 is turned on, the first initial signal of the first initial signal line Vinit1 is written into the third node N3, the third node N3 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. Since the signal of the second scanning signal line Gate-N is a high-level signal, the compensation transistor T2 is turned on, the signal of the third node N3 is continuously written into the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The signals of the first scanning signal line Gate-P, the second reset signal line Reset-H and the light-emitting signal line EM are all high-level signals, and the data writing transistor T4, the anode reset transistor T7, the second node reset transistor T8, the first light-emitting transistor T5 and the second light-emitting transistor T6 are turned off. At this stage, the light emitting element L does not emit light.

In the third stage 13, i.e., the data writing stage, the signals of the second scanning signal line Gate-N, the first reset signal line Reset-P, the second reset signal line Reset-H and the light emitting signal line EM are all high-level signals, the signal of the first scanning signal line Gate1 is a low-level signal, and the data signal line Data writes the data voltage. The signal of the first scanning signal line Gate-P is a low-level signal, the data writing transistor T4 is turned on, the signal of the second scanning signal line Gate-N is a high-level signal, the compensation transistor T2 is turned on, and the data voltage output by the data signal line Data is written to the first node N1 through the turned-on data writing transistor T4, the second node N2, the turned-on driving transistor T3, the third node N3, and the turned-on compensation transistor T2, and the difference between the second data voltage output by the data signal line Data and the threshold voltage of the driving transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vdata-|Vth|, where Vdata is the data voltage output by the data signal line Data and Vth is the threshold voltage of the driving transistor T3. The signals of the first reset signal line Reset-P, the second reset signal line Reset-H and the light-emitting signal line EM are all high-level signals, and the first node reset transistor T1, the anode reset transistor T7, the second node reset transistor T8, the first light-emitting transistor T5 and the second light-emitting transistor T6 are turned off. At this stage, the light-emitting element L does not emit light. At this stage, the light-emitting element L does not emit light.

In the fourth stage S14, i.e., the third initialization stage, the signals of the first scanning signal line Gate-P, the first reset signal line Reset-P, and the light-emitting signal line EM are all high-level signals, and the signals of the second scanning signal line Gate-N and the second reset signal line Reset-H are low-level signals. The signal of the second reset signal line Reset-H is a low-level signal, the anode reset transistor T7 and the second node reset transistor T8 are turned on, the second initial signal of the second initial signal line Vinit2 is written into the fourth node N4, the fourth node N4 (that is, the first pole of the light-emitting device) is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written into the second node N2 and the third node N3, the second node N2 and the third node N3 are initialized (reset), the pre-stored voltage inside them is cleared, and the initialization is completed. The signals of the first reset signal line Reset-P, the first scanning signal line Gate-P and the light-emitting signal line EM are all high-level signals, the signal of the second scanning signal line Gate-N is a high-level signal, the compensation transistor T2, the data writing transistor T4, the first node reset transistor T1, the first light-emitting transistor T5 and the second light-emitting transistor T6 are disconnected. At this stage, the light-emitting element L does not emit light. At this stage, the light-emitting element L does not emit light.

In the fifth stage S15, ie the holding stage, the signals of the first scanning signal line Gate-P, the first reset signal line Reset-P, the second reset signal line Reset-H and the light-emitting signal line EM are all high-level signals, and the signal of the second scanning signal line Gate-N is a low-level signal. The signals of the first scanning signal line Gate-P, the first reset signal line Reset-P, the second reset signal line Reset-H and the light-emitting signal line EM are all high-level signals, the signal of the second scanning signal line Gate-N is a low-level signal, the first node reset transistor T1, the compensation transistor T2, the data writing transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the anode reset transistor T7 and the second node reset transistor T8 are disconnected, and in this stage, the driving transistor T3 is turned on, so that the third initial signal of the third initial signal line Vinit3 can have enough time to act on the first and second electrodes of the driving transistor T3. In this stage, the voltage value of the signal of the first node N1 is greater than the voltage value of the signal of the second node N2, so that the driving transistor T3 can be in a biased state for a long time, thereby improving the hysteresis state of the driving transistor T3, and then improving the low-frequency flicker problem of the display panel.

In the sixth stage S16, i.e., the light-emitting stage, the signals of the first scanning signal line Gate-P, the first reset signal line Reset-P, and the second reset signal line Reset-H are all high-level signals, and the signals of the second scanning signal line Gate-N and the light-emitting signal line EM are low-level signals. The signal of the light-emitting signal line EM is a low-level signal, the first light-emitting transistor T5 and the second light-emitting transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the fourth node N4 through the turned-on first light-emitting transistor T5, the driving transistor T3, and the second light-emitting transistor T6, thereby driving the light-emitting device L to emit light.

During the driving process of the pixel circuit refresh frame, the driving current flowing through the driving transistor T3 is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is:

I=K*(Vgs-Vth) ² =K*[(Vdd-Vdata+|Vth|)-Vth] ² =K*[(Vdd-Vdata] ²

Among them, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the second data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

The embodiment of the present disclosure further provides a display device, including: a display panel. The display panel is the display panel provided by any of the above embodiments, and the implementation principle and effect are similar, which will not be repeated here.

The embodiment of the present disclosure further provides a method for driving a display panel, which is configured to drive a display panel. The method for driving a display panel may include:

A first pulse signal is provided to the light-emitting initial signal line in a refresh frame, and a plurality of second pulse signals are provided to the light-emitting initial signal line in a hold frame, wherein a pulse width of the first pulse signal is greater than a pulse width of at least one second pulse signal.

The display panel is the display panel provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of the layer or microstructure are exaggerated. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intermediate elements.

Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of the present disclosure shall still be subject to the scope defined in the attached claims.

Claims (19)

1. A timing control device, adapted to a display panel to dynamically adjust the timing of the pulse width of an initial signal for light emission, the display panel displaying contents comprising: a plurality of display frames, the display panel comprising: the light-emitting initial signal line, the timing of at least one display frame includes: a display phase, the display phase comprising: refreshing the frame and maintaining the frame;

The timing control device is configured to supply a first pulse signal to the light emission initial signal line in a refresh frame and supply a plurality of second pulse signals to the light emission initial signal line in a hold frame, wherein the pulse width of the first pulse signal is larger than the pulse width of at least one second pulse signal.

2. The timing control apparatus of claim 1, wherein the timing of at least one display frame comprises: a first blanking period occurring before the display phase and a second blanking period occurring after the display phase;

the first pulse signal and the plurality of second pulse signals satisfy the following conditions:

1-((A1+A2+A3+…+An)/(H+VFP+VBP))＝EM_DUTY％，

Wherein em_duty% is a preset light emitting DUTY ratio, A1 is a pulse width of the first pulse signal, A2 is a pulse width of the first second pulse signal, an is a pulse width of the n-1 th second pulse signal, H is a line number driven in one display stage, VFP is a line number driven in the first blanking period, VBF is a line number driven in the second blanking period, and (h+vfp+vbp) is divided by n.

3. The timing control apparatus according to claim 2, wherein em_duty%. Gtoreq.90%.

4. The timing control apparatus according to claim 2, wherein A1 has a minimum width of 96H.

5. The timing control apparatus according to claim 2, wherein Ai has a minimum width of 4h, i=2, 3 … n.

6. The timing control apparatus according to claim 2, wherein n is 1 or more.

7. A display panel, comprising: the timing control apparatus according to any one of claims 1 to 6;

The display panel further includes: the display device comprises array-arranged sub-pixels positioned in a display area and a first driving circuit positioned in a non-display area, wherein at least one sub-pixel comprises: a pixel circuit, the pixel circuit comprising: and a light emitting transistor, the first driving circuit being electrically connected to the light emitting transistor and the light emitting initial signal line, respectively, the light emitting initial signal line being configured to provide a light emitting initial signal to the first driving circuit.

8. The display panel of claim 7, further comprising: the second driving circuit and the compensation initial signal line, the pixel circuit further includes: a compensation transistor, the second driving circuit being electrically connected to the compensation transistor and the compensation initial signal line, respectively, the compensation initial signal line being configured to provide a compensation initial signal to the second driving circuit;

The timing control device provides a third pulse signal to the compensation initial signal line in a refresh frame, wherein the time period of the third pulse signal at least partially overlaps with the time period of the first pulse signal.

9. The display panel according to claim 8, wherein a period of time in which the third pulse signal is located is within a period of time in which the first pulse signal is located, and a duration of the third pulse signal is smaller than a duration of the first pulse signal.

10. The display panel according to claim 7, further comprising a third driving circuit and a first reset initiation signal line, wherein the pixel circuit further comprises: a first node reset transistor, the third driving circuit being electrically connected to the first node reset transistor and the first reset initiation signal line, respectively, the first reset initiation signal line being configured to provide a first reset initiation signal to the third driving circuit;

The timing control device supplies a fourth pulse signal to the first reset initial signal line in a refresh frame, and a time period in which the fourth pulse signal is located at least partially overlaps a time period in which the first pulse signal is located.

11. The display panel according to claim 10, wherein a portion of a period of time in which the fourth pulse signal is located is within a period of time in which the first pulse signal is located, and a duration of the fourth pulse signal is smaller than a duration of the first pulse signal.

12. The display panel according to claim 7, further comprising a fourth driving circuit and a second reset initiation signal line, wherein the pixel circuit further comprises: an anode reset transistor and a second node reset transistor, the fourth driving circuit being electrically connected to the anode reset transistor, the second node reset transistor, and the second reset initiation signal line, respectively, the second reset initiation signal line being configured to provide a second reset initiation signal to the fourth driving circuit;

The timing control device supplies a fifth pulse signal to the second reset initial signal line in a refresh frame, and a period of time in which the fifth pulse signal is located at least partially overlaps a period of time in which the first pulse signal is located.

13. The display panel according to claim 12, wherein a period of time in which the fifth pulse signal is located is within a period of time in which the first pulse signal is located, and a duration of the fifth pulse signal is smaller than a duration of the first pulse signal.

14. The display panel according to claim 7, further comprising a fifth driving circuit and a data initial signal line, wherein the pixel circuit further comprises: a data writing transistor, the fifth driving circuit being electrically connected to the data writing transistor and the data initialization signal line, respectively, the data initialization signal line being configured to supply a data initialization signal to the fifth driving circuit;

The timing control device provides a sixth pulse signal to the data initial signal line in a refresh frame, wherein a time period in which the sixth pulse signal is located at least partially overlaps a time period in which the first pulse signal is located.

15. The display panel according to claim 14, wherein a portion of a period of time in which the sixth pulse signal is located is within a period of time in which the first pulse signal is located, and a duration of the sixth pulse signal is smaller than a duration of the first pulse signal.

16. The display panel of claim 7, further comprising: the pixel circuit includes a first reset signal line, a second reset signal line, a data signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first scanning signal line, a second scanning signal line, and a first power supply line, the light emitting transistor includes a first light emitting transistor and a second light emitting transistor, and the pixel circuit further includes: the device comprises a compensation transistor, a first node reset transistor, an anode reset transistor, a second node reset transistor, a data writing transistor, a driving transistor and a capacitor;

The control electrode of the compensation transistor is electrically connected with the second scanning signal line, the first electrode of the compensation transistor is electrically connected with the first node, and the second electrode of the compensation transistor is electrically connected with the third node;

The control electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node;

The control electrode of the data writing transistor is electrically connected with the first scanning signal line, the first electrode of the data writing transistor is electrically connected with the data signal line, and the second electrode of the data writing transistor is electrically connected with the second node;

The control electrode of the first node reset transistor is electrically connected with a first reset signal line, the first electrode of the first node reset transistor is electrically connected with a first initial signal line, and the second electrode of the first node reset transistor is electrically connected with a third node;

the control electrode of the anode reset transistor is electrically connected with a second reset signal line, the first electrode of the anode reset transistor is electrically connected with a second initial signal line, and the second electrode of the anode reset transistor is electrically connected with a fourth node;

the control electrode of the second node reset transistor is electrically connected with a second reset signal line, the first electrode of the second node reset transistor is electrically connected with a third initial signal line, and the second electrode of the second node reset transistor is electrically connected with a second node;

The control electrode of the first light-emitting transistor is electrically connected with the light-emitting signal line, the first electrode of the first light-emitting transistor is electrically connected with the first power line, and the second electrode of the first light-emitting transistor is electrically connected with the second node;

The control electrode of the second light emitting transistor is electrically connected with the light emitting signal line, the first electrode of the second light emitting transistor is electrically connected with the third node, and the second electrode of the second light emitting transistor is electrically connected with the fourth node;

The capacitor comprises a first plate and a second plate, the first plate of the capacitor is electrically connected with the first power line, and the second plate of the capacitor is electrically connected with the first node.

17. The display panel according to claim 16, wherein at least one transistor in the pixel circuit is a P-type transistor or an N-type transistor, the first light emitting transistor and the second light emitting transistor are the same in transistor type, and the anode reset transistor and the second node reset transistor are the same in transistor type.

18. A display device, comprising: the display panel of any one of claims 7 to 17.

19. A driving method of a timing control apparatus configured to drive the timing control apparatus according to any one of claims 1 to 6, the method comprising:

A first pulse signal is supplied to a light emission initial signal line in a refresh frame, and a plurality of second pulse signals are supplied to the light emission initial signal line in a sustain frame, the pulse width of the first pulse signal being greater than the pulse width of at least one of the second pulse signals.