CN118466864B - Satellite data storage method, device, medium and equipment - Google Patents

Abstract

The present specification provides a satellite data storage method, device, medium and equipment, firstly determining the data size of the data to be stored, secondly dividing the data to be stored according to the number of read threads of the processor to obtain each first sub-data, and determining the corresponding relationship between each first sub-data and each read thread, and writing each first sub-data into the processor cache through the read thread corresponding to each first sub-data, and finally responding to any first sub-data written completely in the cache, dividing the first sub-data written completely according to the number of write threads of the processor to obtain each second sub-data, determining the corresponding relationship between each second sub-data and each write thread, and writing each second sub-data into the memory according to the corresponding relationship, by dividing the data to be stored multiple times, avoiding the occurrence of read and write errors caused by insufficient processor memory size when the satellite stores the data to be stored, and reducing the requirements for the processor cache.

Description

Satellite data storage method, device, medium and equipment

Technical Field

The present invention relates to the field of computer technology, and in particular to a satellite data storage method, device, medium and equipment.

Background Art

In recent years, with the development of computer technology, satellite technology has also made progress. For satellites that need to store data, the total amount of data that can be stored each day is limited due to the hardware performance of the satellite itself and the battery life. Therefore, how to improve the efficiency of satellite data storage under limited conditions has become a key research direction.

In the prior art, after reading the data to be stored, the processor of the satellite generally stores the data to be stored into the memory through a preset thread pool.

However, while this method greatly improves the efficiency of data storage, it also increases the requirements for the size of the processor memory. If the processor memory size is insufficient, it will cause errors in reading and writing the data to be stored, seriously affecting the efficiency of data storage.

To this end, this specification provides a satellite data storage method.

Summary of the invention

The present application provides a satellite data storage method to partially solve the above problems existing in the prior art.

The present application provides a satellite data storage method, which is applied to a satellite, including:

Determine the data size of the data to be stored;

According to the number of reading threads of the processor of the satellite, the data to be stored is divided to obtain first sub-data, and a corresponding relationship between the first sub-data and the reading threads is determined;

Writing each first sub-data into the cache of the processor through a reading thread corresponding to each first sub-data;

In response to any first sub-data that is completely written in the cache, according to the number of write threads of the processor, the first sub-data that is completely written is divided to obtain each second sub-data, and a corresponding relationship between each second sub-data and each write thread is determined;

The second sub-data are written into the memory of the satellite through the writing threads corresponding to the second sub-data.

Optionally, the method further comprises:

When the cache space size of the processor is not greater than the data size, clearing the cache space of the cache;

When the storage space size of the memory is not greater than the data size, compressing the data in the storage space;

After writing the second sub-data into the memory, the fragmented data written by the reading threads are cleaned up, and the fragmented data written by the writing threads are cleaned up.

Optionally, writing each first sub-data into a cache of the processor specifically includes:

The addresses of the first sub-data in the cache of the processor are determined, and the first sub-data are written into the addresses in the cache.

Optionally, writing each second sub-data into a memory of the satellite specifically includes:

The addresses of the second sub-data in the memory of the satellite are determined, and the second sub-data are written into the addresses in the memory.

Optionally, writing each second sub-data into a memory of the satellite through a writing thread corresponding to each second sub-data specifically includes:

For each writing thread, determining each second sub-data corresponding to the writing thread from each first sub-data that has been completely written;

Determining the order of the second sub-data corresponding to the writing thread according to the order in which the first sub-data are completely written into the cache;

The second sub-data are written into the memory of the satellite through the writing threads according to the order of the second sub-data corresponding to the writing threads.

Optionally, the method further comprises:

When an error occurs in writing the second sub-data into the memory, recording the error and continuing to write the second sub-data;

When the second sub-data is completely written, the second sub-data in the memory is corrected according to the recorded error.

Optionally, determining the number of read threads of the multiple read threads includes:

Determining a preset target size for the first sub-data;

The number of reading threads is determined according to the target size of the first sub-data and the size of the data to be stored, and each reading thread is determined according to the number of reading threads.

This specification provides a satellite data storage device, which is applied to a satellite, including:

A preprocessing module, determining the data size of the data to be stored;

A first cutting module, which divides the data to be stored according to the number of reading threads of the processor of the satellite to obtain first sub-data, and determines the corresponding relationship between the first sub-data and the reading threads;

A reading module, which writes each first sub-data into a cache of the processor through a reading thread corresponding to each first sub-data;

A second cutting module, in response to any first sub-data that is completely written in the cache, divides the first sub-data that is completely written according to the number of writing threads of the processor to obtain each second sub-data, and determines a corresponding relationship between each second sub-data and each writing thread;

The writing module writes each second sub-data into the memory of the satellite through the writing thread corresponding to each second sub-data.

The present specification provides a computer storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, a satellite data storage method is implemented.

The present specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein a satellite data storage method is implemented when the processor executes the program.

The present specification provides a satellite data storage method, which first determines the data size of the data to be stored, and then divides the data to be stored according to the number of read threads of the processor to obtain each first sub-data, and determines the corresponding relationship between each first sub-data and each read thread, writes each first sub-data into a processor cache through the read thread corresponding to each first sub-data, and finally responds to any first sub-data written completely in the cache, divides the first sub-data written completely according to the number of write threads of the processor to obtain each second sub-data, determines the corresponding relationship between each second sub-data and each write thread, and writes each second sub-data into a memory according to the corresponding relationship.

It can be seen from the above method that by dividing the stored data multiple times, the satellite avoids read and write errors caused by insufficient processor memory size when storing the data to be stored, thereby reducing the requirements for the processor cache.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

FIG1 is a schematic diagram of a flow chart of a satellite data storage method provided in this specification;

FIG2 is a schematic diagram of a satellite structure of a satellite data storage method provided in this specification;

FIG3 is a schematic diagram of a data segmentation flow method of a satellite data storage method provided in this specification;

FIG4 is a schematic diagram of an asynchronous writing method for satellite data storage method provided in this specification;

FIG5 is a schematic diagram of a device for storing satellite data provided in this specification;

FIG. 6 is a schematic diagram of an electronic device provided in this specification corresponding to FIG. 1 .

DETAILED DESCRIPTION

In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

The technical solutions provided by the embodiments of this specification are described in detail below in conjunction with the accompanying drawings.

FIG1 is a schematic flow chart of a satellite data storage method provided in this specification, which specifically includes the following steps:

S101: Determine the data size of the data to be stored.

In existing satellites, due to the influence of satellite power supply, the time for satellites to store data is very limited. For example, within 24 hours, the satellite only has about 10 minutes to store data. Therefore, the storage efficiency of the satellite needs to be improved. In order to improve the storage efficiency of satellites, the existing satellite data storage method is often stored by the processor on the satellite. After the satellite receives the data to be stored, the method of storing the data to be stored in the satellite's disk through a preset thread pool is used to improve the data storage efficiency of the satellite. However, as the number of preset threads in the preset thread pool increases, the cache hit rate of the processor cache decreases and the threads compete for shared resources (such as the mechanism for handling concurrency control and synchronization issues), which reduces the utilization of the cache and increases the cache space requirements for the processor.

To this end, the satellite processor needs to determine the data size of the data to be stored in response to the received data to be stored, so as to determine the size of the data to be written by each thread when writing the data to be stored in the subsequent step.

It should be noted here that the satellite data storage method provided in this specification can be executed using a computer or a processor. This specification provides a schematic diagram of the satellite structure used in the data storage method, as shown in Figure 2, the satellite includes a processor and a memory, and the processor includes a cache for use by the processor. The specific subject of this execution method is not limited in this specification. And for the convenience of description in this specification, this specification takes the processor executing the satellite data storage method on the satellite as an example for description.

Specifically, the processor on the satellite determines the data to be stored from the collector, uses the data as storage data, and determines the data size of the data to be stored.

S103: dividing the data to be stored according to the number of reading threads of the processor of the satellite to obtain first sub-data, and determining the corresponding relationship between the first sub-data and the reading threads.

In order to reduce the write errors caused by the size of the data read by the processor at a single time being larger than the available size in the processor cache, address errors or excessive power, the processor first determines the number of read threads in the preset thread pool in order to determine the number of data to be divided into to be stored. Secondly, the processor divides the data to be stored according to the number of read threads to obtain the first sub-data for each read thread to write. Thirdly, the processor establishes the corresponding relationship between each first sub-data and each read thread for parallel data writing in subsequent steps.

Specifically, the processor determines a fixed number of reading threads in the thread pool, divides the data to be stored into a plurality of first sub-data, and determines a reading thread corresponding to each first sub-data.

S105: Writing each first sub-data into the cache of the processor through the reading thread corresponding to each first sub-data.

The processor writes each first sub-data into the cache of the processor through each reading thread according to the determined correspondence between each first sub-data and each reading thread, so that the processor can quickly read the data to be stored in subsequent steps.

Specifically, the processor uses a fixed number of reading threads in the thread pool to write the first sub-data corresponding to each reading thread into the cache of the processor in parallel.

S107: In response to any completely written first sub-data in the cache, split the completely written first sub-data according to the number of write threads of the processor to obtain second sub-data, and determine the corresponding relationship between the second sub-data and the write threads.

When any first sub-data is completely written, the processor starts to write the data to be stored into the memory of the satellite. The specific steps and reasons are similar to step S103, and are all to reduce the write error caused by the large data size of the data read by the processor at a single time, and the first sub-data are split again. The specific reason is that it is assumed that the processor is still writing part of the incompletely written first data at this time, so the space available for writing to the satellite memory is more limited, so it is necessary to further split each first sub-data.

Specifically,

S109: Writing each second sub-data into the memory of the satellite through the writing thread corresponding to each second sub-data.

The processor writes each second sub-data into the memory of the satellite through each writing thread according to the determined correspondence between each second sub-data and each writing thread, thereby completing the storage of the data to be stored.

Specifically, the processor writes each second sub-data corresponding to each writing thread into the memory of the satellite through each writing thread.

The satellite image storage method shown in FIG1 can achieve the following: firstly, determine the data size of the data to be stored; secondly, divide the data to be stored according to the number of read threads of the processor to obtain each first sub-data, and determine the corresponding relationship between each first sub-data and each read thread; write each first sub-data into the processor cache through the read thread corresponding to each first sub-data; finally, in response to any first sub-data written completely in the cache, divide the first sub-data written completely according to the number of write threads of the processor to obtain each second sub-data; determine the corresponding relationship between each second sub-data and each write thread; and write each second sub-data into the memory according to the corresponding relationship; by dividing the data to be stored multiple times, the read and write errors caused by insufficient processor memory size when the satellite stores the data to be stored are avoided, and the requirements for the processor cache are reduced.

Specifically, in one or more embodiments of the present specification, a schematic diagram of a data segmentation flow method in the data storage method of FIG. 1 is also provided. As shown in FIG. 3, the processor can determine the spectral data to be stored as the data to be stored through a transmission write bus under a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe), and determine that the data size of the data to be stored is 500 megabytes. The processor first determines that the number of read threads in the thread pool is 4, and then divides the 500 megabytes of data to be stored into 4 125 megabytes of first sub-data, and again determines the first sub-data corresponding to each read thread. The processor writes each first sub-data corresponding to each read thread into the processor's cache through each read thread. When the processor detects that any first sub-data has been written to 125 megabytes, it first determines that the number of write threads in the thread pool is 5, and then divides the 125 megabytes of first sub-data into 5 25 megabytes of second sub-data, and again determines the second sub-data corresponding to each write thread. The processor writes each second sub-data corresponding to each write thread into the memory of the satellite through each write thread.

It should be noted that the above embodiment uses spectral data as the data to be stored because spectral data usually contains a large amount of information and occupies a large space. This can highlight that when the method processes data that occupies a large space, it is not necessary to limit the data to be stored to spectral data. In this specification, there is no restriction on whether the data to be stored is spectral data, and it can be selected as needed.

It should be additionally explained here that the above method of dividing the data to be stored is based on the premise that the performance of each reading thread is close, and the first sub-data to be written by each reading thread is evenly distributed to achieve maximum writing efficiency. It does not mean that data division can only be performed by even distribution. For example, among each reading thread, there are unexpected reasons that cause the writing ability of individual threads to be significantly weaker than other threads. In this case, compared with other reading threads, the first sub-data with a smaller data size can be allocated to the thread to achieve maximum writing efficiency. In this manual, there is no restriction on how to divide the data to be stored, and it can be selected as needed. Based on the same principle, the method of evenly dividing each first sub-data of each complete transmission can also be changed according to the writing ability of each writing thread. In this manual, there is no restriction on how to divide each first sub-data of each complete transmission, and it can be selected as needed.

In step S103 and step S107 of Figure 1, in order to improve the efficiency of data storage, in one or more embodiments of the present specification, the method of cutting the data to be stored and the method of cutting the first sub-data after the transmission are completed can also be implemented in an independent thread respectively to achieve parallel data segmentation, data reading and data writing.

In step S103 and step S107 of Figure 1, in one or more embodiments of the present specification, the reading thread and the writing thread are not necessarily two different preset threads, but can also be a general thread. Correspondingly, to ensure the efficiency balance between the reading thread and the writing thread, the number of general threads to be used as writing threads or reading threads can be determined based on the ratio of the size of data transmitted by the preset general thread to the size of the data to be transmitted.

The method provided in this specification also includes, in order to further prevent the read and write errors of the processor caused by insufficient cache space of the satellite processor, the processor cleans up the cache space occupied by the processor's completed tasks when the cache space size of the processor is not greater than the data size. Similarly, to further prevent the read and write errors caused by insufficient storage space of the satellite memory, the processor compresses the data in the storage space when the storage space size of the memory is not greater than the data size, and further cleans up the fragmented data written by the processor write thread after writing the second sub-data to the memory, and cleans up the fragmented data generated by the read thread.

The method provided in this specification also includes, in step S105, to ensure that the order of the first sub-data written by the reading thread is the same as the order of the first sub-data in the data to be stored, the processor determines in advance the addresses of the first sub-data in the processor's cache, and then writes the first sub-data to the addresses in the cache.

The method provided in this specification also includes, in step S109, to ensure that the order of the second sub-data written by the writing thread is the same as the order of the second sub-data in the data to be stored, the processor determines in advance the addresses of the second sub-data in the satellite's memory, and then writes the second sub-data to the addresses in the memory.

The method provided in this specification also includes, in step S109, to further improve the writing efficiency of the writing thread, the processor first determines, for each writing thread, from the first sub-data that have been completely written, the second sub-data corresponding to the writing thread. Secondly, according to the order in which the first sub-data are completely written into the cache, the order of the second sub-data corresponding to the writing thread is determined. Finally, through each writing thread, according to the order of the second sub-data corresponding to each writing thread, the second sub-data is written into the memory of the satellite.

In one or more embodiments of the present specification, an asynchronous writing method for use by a writing thread is provided. As shown in FIG4 , for a reading thread in a processor, a first sub-data of 125 megabytes is completely written to the processor cache every 0.2 seconds, and the writing thread starts writing the completely written first sub-data. After any 25 megabytes of data are segmented, each second sub-data obtained by segmentation is written to the memory of the satellite. When one second sub-data is completely written, the writing of the second sub-data of the next completely written first sub-data is started according to the order in which each first sub-data is completely written.

The method provided in this specification also includes, in order to correct errors that occur during the writing process of the processor without affecting the writing efficiency, when an error occurs in the second sub-data written into the memory, the processor records the error and continues to write the second sub-data. When the second sub-data is completely written, the processor corrects the second sub-data in the memory according to the recorded error.

The method provided in this specification also includes that, in order to fully utilize the read threads in the processor to improve the utilization rate of the cache space, the processor first determines a preset target size for the first sub-data, and then determines the number of read threads according to the target size of the first sub-data and the size of the data to be stored, and determines each read thread according to the number of read threads.

In addition, the data storage method provided in this specification can also send data from the satellite's memory to the ground station in reverse. The specific method of cutting and transmitting data is the same as the method in Figure 1, specifically obtaining the data to be sent from the memory, dividing the data to be sent according to the number of reading threads to obtain each first sub-data, and then dividing the completely transmitted first sub-data according to the number of writing threads to obtain each second sub-data, and sending each second sub-data to the ground station through each writing thread.

This specification also provides a device corresponding to the flowchart of the satellite data storage method in FIG1 , as shown in FIG5 :

A preprocessing module 201 determines the first sub-data size of the data to be stored;

A first cutting module 203, which divides the data to be stored according to the number of reading threads of the processor of the satellite to obtain first sub-data, and determines the corresponding relationship between the first sub-data and the reading threads;

A reading module 205 writes each first sub-data into the cache of the processor through a reading thread corresponding to each first sub-data;

The second cutting module 207, in response to any first sub-data completely written in the cache, divides the first sub-data completely written according to the number of write threads of the processor to obtain each second sub-data, and determines the corresponding relationship between each second sub-data and each write thread;

The writing module 209 writes each second sub-data into the memory of the satellite through the writing thread corresponding to each second sub-data.

Optionally, the device further includes a sorting module 211, which is used to clean up the cache space of the cache when the cache space size of the processor is not larger than the data size. When the storage space size of the memory is not larger than the data size, compress the data in the storage space, and after writing the second sub-data into the memory, clean up the fragmented data written by each reading thread, and clean up the fragmented data written by each writing thread.

Optionally, the reading module 205 is used to determine each address of each first sub-data in the cache of the processor, and write each first sub-data into each address in the cache.

Optionally, the writing module 209 is used to determine each address of each second sub-data in the memory of the satellite, and write each second sub-data into each address in the memory.

Optionally, the writing module 209 is used to determine, for each writing thread, each second sub-data corresponding to the writing thread from each first sub-data that has been completely written. According to the order in which each first sub-data is completely written into the cache, the order of each second sub-data corresponding to the writing thread is determined. Through each writing thread, according to the order of each second sub-data corresponding to each writing thread, each second sub-data is written into the memory of the satellite.

Optionally, the device further comprises an error module 213, which is used to record the error and continue writing the second sub-data when an error occurs in writing the second sub-data into the memory, and to correct the second sub-data in the memory according to the recorded error when the second sub-data is completely written.

Optionally, the device further comprises a thread module 215, which is used to determine a preset target size for the first sub-data, determine the number of reading threads according to the target size of the first sub-data and the size of the data to be stored, and determine each reading thread according to the number of reading threads.

The present specification also provides a computer-readable storage medium, which stores a computer program, and the computer program can be used to execute the above method.

This specification also provides a schematic structural diagram of an electronic device corresponding to the satellite data storage method of Figure 1, as shown in Figure 6. As shown in Figure 6, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and of course may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the satellite data storage method of Figure 1 above. Of course, in addition to the software implementation method, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

In the 1990s, it was very clear whether the improvement of a technology was hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a sensor phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and/or hardware.

Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

This specification is described with reference to the flowcharts and/or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the processes and/or boxes in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

In a typical configuration, a computing device includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.

The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and/or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-writable media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Furthermore, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media including storage devices.

Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims (10)

1. A satellite data storage method, for use with a satellite, comprising:

determining the data size of the data to be stored;

Dividing the data to be stored according to the number of the reading threads of the processor of the satellite to obtain first sub-data, and determining the corresponding relation between the first sub-data and the reading threads;

Writing each first sub-data into a cache of the processor through a read thread corresponding to each first sub-data;

Responding to any completely written first sub-data in the cache, dividing the completely written first sub-data according to the number of writing threads of the processor to obtain second sub-data, and determining the corresponding relation between the second sub-data and the writing threads;

and writing each second sub-data into the memory of the satellite through the writing thread corresponding to each second sub-data.

2. The method of claim 1, wherein the method further comprises:

when the size of the cache space of the processor is not larger than the data size, clearing the cache space of the cache;

When the storage space size of the memory is not larger than the data size, compressing the data of the storage space;

And after the second sub data is written into the memory, clearing the fragment data written by each reading thread, and clearing the fragment data written by each writing thread.

3. The method of claim 1, wherein writing each of the first sub-data into the cache of the processor, specifically comprises:

and determining each address of each first sub-data in the cache of the processor, and writing each address of each first sub-data in the cache.

4. The method of claim 1, wherein writing each of the second sub-data to the memory of the satellite, in particular comprises:

And determining each address of each second sub-data in the memory of the satellite, and writing each address of each second sub-data into the memory.

5. The method of claim 1, wherein the writing of each second sub-data into the memory of the satellite by the corresponding writing thread of each second sub-data specifically comprises:

For each writing thread, determining each second sub-data corresponding to the writing thread from the completely written first sub-data;

Determining the sequence of each second sub data corresponding to the writing thread according to the sequence of the first sub data completely written into the cache;

and writing the second sub-data into the memory of the satellite according to the sequence of the second sub-data corresponding to the writing threads through the writing threads.

6. The method of claim 1, wherein the method further comprises:

When the second sub data written into the memory has errors, recording the errors, and subsequently writing the second sub data;

and correcting the second sub-data in the memory according to the recorded errors when the second sub-data is completely written.

7. The method of claim 1, wherein the method further comprises:

Determining a target size preset for the first sub-data;

and determining the number of the read threads according to the target size of the first sub data and the size of the data to be stored, and determining each read thread according to the number of the read threads.

8. A satellite data storage device for use with a satellite, comprising:

the preprocessing module is used for determining the data size of the data to be stored;

The first cutting module is used for dividing the data to be stored according to the number of the reading threads of the processor of the satellite to obtain first sub-data, and determining the corresponding relation between the first sub-data and the reading threads;

The reading module is used for writing the first sub-data into the cache of the processor through the reading thread corresponding to the first sub-data;

The second cutting module is used for responding to any completely written first sub-data in the cache, dividing the completely written first sub-data according to the number of the writing threads of the processor to obtain second sub-data, and determining the corresponding relation between the second sub-data and the writing threads;

and the writing module is used for writing the second sub-data into the memory of the satellite through the writing thread corresponding to the second sub-data.

9. A computer storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of any of the preceding claims 1-7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any of the preceding claims 1-7 when executing the program.