CN118471799B - Shielded gate field effect transistor and preparation method thereof, and electronic device - Google Patents
Shielded gate field effect transistor and preparation method thereof, and electronic device Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
- H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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Abstract
The invention provides a shielding grid field effect transistor and a preparation method thereof as well as an electronic device, wherein the preparation method comprises the steps of providing a substrate, forming a first groove extending from the surface of the substrate to the inside of the substrate, forming a shielding dielectric layer at the bottom and at least part of the side wall of the first groove, and forming a first shielding grid positioned on the shielding dielectric layer in the first groove, wherein the top surface of the first shielding grid is lower than the top surface of the shielding dielectric layer; etching the shielding dielectric layer above the first shielding grid, removing part of the shielding dielectric layer to form a second groove above the first shielding grid, forming a liner layer on the side wall of the second groove, forming a second shielding grid in the second groove, forming an inter-grid dielectric layer in the second groove to cover the second shielding grid, etching and removing part of the shielding dielectric layer, part of the liner layer and part of the inter-grid dielectric layer to form a third groove on the inter-grid dielectric layer, and forming a grid structure in the third groove.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor, a preparation method thereof and an electronic device.
Background
The advantages and disadvantages of the shielded gate trench (SHIELDED GATE TRENCH, SGT) are directly affected by the device performance in advanced logic circuit processes, such as the shielded gate trench is used in a metal oxide semiconductor field effect transistor (metal oxide semiconductor FIELD EFFECT MOSFET).
In the related art, when a shielded gate trench is applied to a metal oxide semiconductor field effect transistor, a trench extending from a surface of a substrate to an inside of the substrate is generally formed first, a shielding dielectric material layer is formed on a bottom, a sidewall and a surface of the substrate of the trench, a shielded gate with a partial depth is filled in the trench, and a part of the shielding dielectric material layer in the trench is removed by etching back to form the shielding dielectric layer. Because the critical dimension of the shielded gate trench applied to the low-voltage platform is smaller, the filling depth-to-width ratio of the deposition process of the inter-gate dielectric material layer is increased, and the requirement of the excessive filling depth-to-width ratio on the deposition process of high-density plasma (HIGH DENSITY PLASMA, HDP for short) is higher, the common HDP deposition process cannot meet the process requirement, namely the problem that the related preparation process has the limitation of the HDP deposition process.
In the related art, there is also a process of directly forming an inter-gate dielectric layer (for example, performing thermal oxidation on a part of the shielding gate), but since the sidewalls on both sides of the shielding gate trench are exposed, the sidewalls on both sides of the shielding gate trench are oxidized at the same time during the thermal oxidation, and if the oxide layer is subsequently removed, the Critical Dimension (CD) on both sides of the shielding gate trench is enlarged, so that the dimension of the gate structure formed on the shielding gate is enlarged, and the threshold voltage (Vth) is further affected.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems existing at present, the invention provides a preparation method of a shielded gate field effect transistor, which comprises the steps of providing a substrate, forming a first groove extending from the surface of the substrate to the inside of the substrate, forming a shielding dielectric layer at the bottom and at least part of the side wall of the first groove, forming a first shielded gate on the shielding dielectric layer in the first groove, wherein the top surface of the first shielded gate is lower than the top surface of the shielding dielectric layer, etching the shielding dielectric layer above the first shielded gate, removing part of the shielding dielectric layer to form a second groove above the first shielded gate, forming an opening in the side wall of the second groove, wherein the opening exposes at least part of the top surface of the first shielded gate, forming a second shielded gate in the second groove, wherein the top surface of the second shielded gate is lower than the surface of the substrate, and the second shielded gate is connected with the first shielded gate, forming a part of the shielding dielectric layer in the second groove, and forming a third dielectric layer in the second groove, and forming a part of the second shielded gate and a third dielectric layer in the second groove.
In one embodiment of the application, the forming a liner layer on the sidewalls of the second trench includes forming a liner material layer on the bottom and sidewalls of the second trench, and etching at least a portion of the liner material layer at the bottom of the second trench to form the liner layer including the opening.
In one embodiment of the application, forming an inter-gate dielectric layer in the second trench to cover the second shielding gate comprises oxidizing a portion of the second shielding gate to oxidize a portion of the second shielding gate to the inter-gate dielectric layer.
In one embodiment of the present application, after the step of etching to remove a portion of the shield dielectric layer, a portion of the liner layer, and a portion of the inter-gate dielectric layer to form a third trench on the inter-gate dielectric layer, top surfaces of the shield dielectric layer, the liner layer, and the inter-gate dielectric layer are flush.
In one embodiment of the application, forming a gate structure in the third trench comprises forming a gate dielectric layer on the side wall of the third trench, and forming a gate electrode layer filling the third trench and covering the gate dielectric layer to form the gate structure, wherein the gate structure comprises the gate dielectric layer and the gate electrode layer.
In one embodiment of the application, the material of the liner layer comprises at least one of silicon nitride, silicon carbide, silicon carbonitride, and/or the material of the first and second shield gates comprises polysilicon.
According to a second aspect of the application, a shielded gate field effect transistor is further provided, and comprises a substrate, a first groove, a shielded dielectric layer, a first shielded gate, a second groove, a liner layer, a second shielded gate, an inter-gate dielectric layer, a third groove and a gate structure, wherein the first groove extends from the surface of the substrate to the inside of the substrate, the shielded dielectric layer is formed on the bottom and part of the side wall of the first groove, the first shielded gate is formed in the first groove and is positioned on the shielded dielectric layer, the top surface of the first shielded gate is lower than the top surface of the shielded dielectric layer, the second groove is arranged on the first shielded gate and is surrounded by part of the shielded dielectric layer positioned above the first shielded gate, the liner layer is arranged on the side wall of the second groove, an opening is formed in the liner layer, at least part of the top surface of the first shielded gate is exposed, the second shielded gate is arranged in the second groove, the top surface of the second shielded gate is lower than the second groove, the top surface of the second shielded gate is positioned in the second groove and is connected with the top surface of the second groove, the top surface of the second shielded gate is positioned between the second groove and the third groove is connected with the medium layer.
In one embodiment of the application, the top surfaces of the shield dielectric layer, the liner layer and the inter-gate dielectric layer are flush.
In one embodiment of the present application, the gate structure includes a gate dielectric layer disposed on sidewalls of the third trench and a gate electrode layer filling the third trench and covering the gate dielectric layer.
According to a third aspect of the present application, there is also provided an electronic device comprising a shielded gate field effect transistor as described in any one of the above.
According to the shielding gate field effect transistor, the preparation method and the electronic device thereof, the shielding dielectric layer above the first shielding gate is etched, the shielding dielectric layer with partial thickness is removed, so that a second groove is formed above the first shielding gate, a liner layer is formed on the side wall of the second groove, the second shielding gate is formed in the second groove, and then the inter-gate dielectric layer is formed in the second groove to cover the second shielding gate.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention. In the accompanying drawings:
fig. 1 is a schematic cross-sectional view of a shield gate trench obtained by implementing a method for manufacturing a shield gate trench in the prior art;
fig. 2 is a flow chart of a method for manufacturing a shielded gate field effect transistor according to an embodiment of the present invention;
fig. 3A to 3G are schematic cross-sectional views of a shielded gate field effect transistor obtained by sequentially implementing a method for manufacturing a shielded gate field effect transistor according to an embodiment of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
In the related art, polysilicon formed in the trench of the shield gate is used as the shield gate, which may also be called Source polysilicon (Source Poly), which is a wine glass structure, and EPI (epitaxial layer) with smaller resistance can be used under the same Bv (breakdown voltage), so as to reduce Rdson (on-resistance). When the shielded gate trench is applied to a metal oxide semiconductor field effect transistor, a preparation process is generally adopted, wherein a trench 101 is formed in a substrate 100, a shielding dielectric material layer is formed on the side wall, the bottom and the surface of the substrate 100 of the trench 101, a shielded gate 103 is partially filled in the trench 101, and the shielded gate is in a shape similar to a wine glass, as shown in fig. 1. A portion of the shield dielectric material layer is removed by etching back to form the shield dielectric layer 102. The distance between the sidewalls of the trench 101 inside above the shield gate 103 is now W0, and the distance between the top surface of the shield gate 103 inside the trench 101 to the surface of the substrate 100 is L0. Subsequently, a layer of inter-gate dielectric material is deposited to fill the trench 101, for example, by a high density plasma (HIGH DENSITY PLASMA, HDP) deposition process to form the inter-gate dielectric material layer to fill the trench 101.
The inventor of the application discovers that the smaller critical dimension of the shielded gate trench applied to the low voltage platform can lead to the increase of the filling depth-to-width ratio of the deposition process of the inter-gate dielectric material layer, and the requirement of the oversized filling depth-to-width ratio on the deposition process of high density plasma (HIGH DENSITY PLASMA, HDP for short) is higher. If the common HDP deposition process is adopted to fill the inter-gate dielectric material layer, the filling window is insufficient when the inter-gate dielectric material layer is filled, so that cavities are easy to appear in the process of filling the inter-gate dielectric material layer, the electrical property of a product is further influenced, and the yield of the product is reduced, namely the common HDP deposition process is adopted to fill the inter-gate dielectric material layer, and the process requirement cannot be met. As shown in fig. 1, when the ratio of l0:w0 is greater than 2.5:1 (the ratio of L0/W0 is greater than 2.5), the conventional HDP deposition process cannot meet the requirements of the preparation process due to the limited filling capability, i.e., the related preparation process has the problem of limited HDP deposition process.
In the related art, there is also a process of directly forming an inter-gate dielectric layer (for example, performing thermal oxidation on a part of the shielding gate), but since the sidewalls on both sides of the shielding gate trench are exposed, the sidewalls on both sides of the shielding gate trench are oxidized at the same time during the thermal oxidation, and if the oxide layer is subsequently removed, the Critical Dimension (CD) on both sides of the shielding gate trench is enlarged, so that the dimension of the gate structure formed on the shielding gate is enlarged, and the threshold voltage (Vth) is further affected.
Therefore, in view of the foregoing technical problems, the present invention provides a method for preparing a shielded gate field effect transistor, as shown in fig. 2, which mainly includes the following steps:
Step S1, providing a substrate, forming a first groove extending from the surface of the substrate to the inside of the substrate, forming a shielding dielectric layer at the bottom and at least part of the side wall of the first groove, and forming a first shielding grid positioned on the shielding dielectric layer in the first groove, wherein the top surface of the first shielding grid is lower than the top surface of the shielding dielectric layer;
Step S2, etching the shielding dielectric layer above the first shielding grid, and removing part of the thickness of the shielding dielectric layer to form a second groove above the first shielding grid;
Step S3, forming a liner layer on the side wall of the second groove, wherein an opening is formed in the liner layer, and at least part of the top surface of the first shielding grid is exposed by the opening;
Step S4, forming a second shielding grid in the second groove, wherein the top surface of the second shielding grid is lower than the surface of the substrate, and the second shielding grid is connected with the first shielding grid;
s5, forming an inter-gate dielectric layer in the second groove to cover the second shielding gate;
Step S6, etching and removing part of the shielding dielectric layer, part of the liner layer and part of the inter-gate dielectric layer to form a third groove on the inter-gate dielectric layer;
step S7, forming a gate structure in the third groove.
In the scheme, the shielding dielectric layer above the first shielding grid is etched, part of the thickness of the shielding dielectric layer is removed, so that a second groove is formed above the first shielding grid, a liner layer is formed on the side wall of the second groove, the second shielding grid is formed in the second groove, and then an inter-grid dielectric layer is formed in the second groove to cover the second shielding grid. The depth-to-width ratio of the second groove can be reduced, so that the filling depth of the second groove is reduced, the filling depth-to-width ratio of the second groove is effectively reduced, the requirement on a high-density plasma deposition process is reduced, and the problem of limitation of the HDP deposition process is solved. And the filling window can be increased, the occurrence of filling holes is reduced, the filling effect is improved, and the electrical property and the yield of the device are improved. In the scheme of the application, the liner layer is formed on the side wall of the second groove, so that the effect of blocking the side wall of the second groove from being oxidized when the inter-gate dielectric layer is formed is achieved, and further, the expansion of Critical Dimensions (CD) on two sides of the second groove is avoided, the shape, the dimensions and the design of a grid structure are more consistent, the influence on threshold voltage (Vth) is avoided, and the stability and the reliability of a device are improved.
Examples 1
Next, a method for manufacturing a shielded gate field effect transistor according to the present invention will be described in detail with reference to fig. 2 to 3G, wherein fig. 2 shows a flowchart of a method for manufacturing a shielded gate field effect transistor according to an embodiment of the present invention, and fig. 3A to 3G show schematic cross-sectional views of the shielded gate field effect transistor obtained by sequentially implementing the method for manufacturing a shielded gate field effect transistor according to an embodiment of the present invention.
Illustratively, the method of fabricating a shielded gate field effect transistor of the present invention includes the steps of:
First, step S1 is performed, a substrate is provided, a first trench extending from a surface of the substrate to an inside of the substrate is formed, a shield dielectric layer is formed at a bottom and at least a portion of a sidewall of the first trench, and a first shield gate on the shield dielectric layer is formed in the first trench, and a top surface of the first shield gate is lower than a top surface of the shield dielectric layer.
In some embodiments, the substrate 300 may include a semiconductor base and an epitaxial layer formed on the semiconductor base, alternatively the semiconductor base and the epitaxial layer may have the same conductivity type, and in other embodiments, the substrate 300 may also include only the semiconductor base without forming the epitaxial layer.
Specifically, as shown in FIG. 3A, the substrate 300 includes a semiconductor base that may include at least one of Si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductors, or the semiconductor base may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which the semiconductor substrate may be formed are described herein, any material that may serve as a semiconductor substrate falls within the scope of the present invention. In addition, the substrate 300 may be divided into active regions, and/or a doping well (not shown) may be formed in the substrate 300, etc.
In one example, as shown in fig. 3A, a first trench 301 extending from a surface of a substrate 300 to an inside of the substrate 300 is formed, a shield dielectric layer 302 is formed at a bottom and at least a portion of a sidewall of the first trench 301, and a first shield gate 303 is formed in the first trench 301, and a top surface of the first shield gate 303 is lower than a top surface of the shield dielectric layer 302. At this time, the distance from the top surface of the first shielding gate 303 to the surface of the substrate 300 is a first depth L1, the distance between the sidewalls of the partial trench (also referred to herein as sub-trench) located above the first shielding gate 303 in the first trench 301 is a first width W1, the first depth L1 is substantially equal to the distance L0 shown in fig. 1, and the first width W1 is greater than the distance W0 shown in fig. 1, i.e., the width of the sub-trench of the first trench 301 is increased, then the aspect ratio of the sub-trench of the first trench 301 is reduced, so that the filling aspect ratio of the deposition process used for filling other materials in the sub-trench of the first trench 301 in the subsequent process of preparing the second shielding gate is reduced, thereby reducing the requirement on the high density plasma deposition process and solving the problem of the limitation of the HDP deposition process. And the filling window can be increased, so that the occurrence of voids in filling is reduced, the filling effect is improved, and the electrical property and the yield of the device are improved.
In one example, the shield dielectric layer 302 may include a silicon oxide layer, or a stack of a silicon oxide layer and a silicon nitride layer, or a stack of two silicon oxide layers with a silicon nitride layer sandwiched therebetween. I.e., shield dielectric layer 302 may be formed with one or more silicon oxide layers. Of course, in other embodiments, other materials may be used for the shield dielectric layer 302.
Illustratively, the material of the first shield gate 303 may include polysilicon or other suitable material. Illustratively, the polysilicon may be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon comprise that the reaction gas is silane (SiH 4), the flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150sccm, the temperature in the reaction chamber can be 700-750 ℃, the pressure in the reaction chamber can be 250-350 millimeters of mercury (mTorr), such as 300mTorr, the reaction gas can also comprise buffer gas, the buffer gas can be helium (He) or nitrogen, and the flow rates of the helium and the nitrogen can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15slm.
Next, step S2 is performed to etch the shield dielectric layer above the first shield gate, and remove a portion of the thickness of the shield dielectric layer to form a second trench above the first shield gate. It should be explained that, referring to fig. 3B, in this step, only the shield dielectric layer 302 over the first shield gate 303 is etched, thereby removing a part of the thickness of the shield dielectric layer 302 in the deposition thickness direction of the shield dielectric layer 302 to form the second trench 304.
Illustratively, a wet etch process may be employed to etch away the shield dielectric layer 302 over the first shield gate 303, removing a portion of the thickness of the shield dielectric layer 302 to form a second trench 304 over the first shield gate 303. In this embodiment, the wet etching process etches only the shield dielectric layer 302 and hardly etches the first shield gate 303 and the substrate 300. Illustratively, a selective etching process may be employed to etch away only the shield dielectric layer 302 over the first shield gate 303, and not the first shield gate 303.
In one example, as shown in fig. 3B, the shield dielectric layer 302 over the first shield gate 303 is etched, removing a portion of the thickness of the shield dielectric layer 302 to form a second trench 304 over the first shield gate 303. Such that the distance from the top surface of the first shield gate 303 to the surface of the substrate is a second depth L2, the second depth L2 being substantially equal to the first depth L1, and the distance W2 between the sidewalls of the second trench 304 located above the first shield gate 303 is greater than the first width W1, i.e. the width of the second trench 304 increases and the depth is unchanged, and thus the aspect ratio of the second trench 304 decreases. Thereby reducing the filling depth-to-width ratio of the deposition process in the process of filling other materials in the second trench 304, reducing the requirement on the high-density plasma deposition process, and solving the problem of the limitation of the HDP deposition process. And the filling window can be increased, so that the occurrence of voids in filling is reduced, the filling effect is improved, and the electrical property and the yield of the device are improved.
Subsequently, step S3 is performed to form a liner layer on the sidewall of the second trench, where an opening is further formed in the liner layer, and the opening exposes at least a portion of the top surface of the first shielding gate. Illustratively, referring to fig. 3C, a liner layer 306 is formed on the sidewalls of the second trench 304, the liner layer 306 being located only above the first shield gate 303, and an opening being formed in the liner layer 306 at a location at the bottom of the second trench 304, such that a top surface of the first shield gate 303 is at least partially exposed from the opening.
Illustratively, a method of forming a liner layer on the sidewalls of the second trench may include forming a liner material layer 305 on the bottom and sidewalls of the second trench 304, as shown in fig. 3B and 3C, and etching at least a portion of the liner material layer 305 at the bottom of the second trench 304 to form a liner layer 306 including an opening. For example, a liner material layer 305 is formed by deposition on the bottom and sidewalls of the second trench 304, and then at least a portion of the liner material layer at the bottom of the second trench is etched to form a liner layer 306 that includes an opening.
Illustratively, referring to fig. 3C, after forming the liner material layer on the bottom and sidewalls of the second trench, a photoresist 307 (PR) may be filled on the liner material layer 305 located inside the second trench 304, the photoresist 307 may be patterned using a photolithography template 308 (Mask), the photoresist 307 may be removed only from the bottom portion of the second trench 304, leaving the liner material layer at the bottom of the second trench 304 exposed, and then the liner material layer at the bottom of the second trench 304 may be etched using, for example, but not limited to, a wet etching process, forming an opening exposing at least a portion of the top surface of the first shielding gate. Then, the photoresist 307 is removed.
Illustratively, the material of the liner layer 306 may include at least one of silicon nitride, silicon carbide, silicon carbonitride. Specifically, the material of the liner layer 306 may be any one of silicon nitride, silicon carbide and silicon carbonitride, or the material of the liner layer 306 may be any two of silicon nitride, silicon carbide and silicon carbonitride, or the material of the liner layer 306 may be a combination of silicon nitride, silicon carbide and silicon carbonitride.
Subsequently, step S4 is performed to form a second shielding gate in the second trench, wherein a top surface of the second shielding gate is lower than a surface of the substrate, and the second shielding gate is connected to the first shielding gate. Illustratively, referring to fig. 3D, a second shield gate 309 may be formed in the second trench 304, and the second shield gate 309 does not fill the second trench 304, such that the top surface of the second shield gate 309 is lower than the surface of the substrate 300.
Illustratively, the material of the second shield gate 309 may include polysilicon or other suitable material. Illustratively, the polysilicon may be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon comprise that the reaction gas is silane (SiH 4), the flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150sccm, the temperature in the reaction chamber can be 700-750 ℃, the pressure in the reaction chamber can be 250-350 millimeters of mercury (mTorr), such as 300mTorr, the reaction gas can also comprise buffer gas, the buffer gas can be helium (He) or nitrogen, and the flow rates of the helium and the nitrogen can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15slm.
Alternatively, during the formation of the second shield gate in the second trench, the second trench 304 may be filled as the second shield gate and cover the surface of the substrate 300, or in some embodiments, the second shield gate may also partially fill the second trench 304, for example, cover the sidewalls of the second trench 304 and cover the first shield gate 303 and the shield dielectric layer 302.
Next, step S5 is performed, and an inter-gate dielectric layer is formed in the second trench to cover the second shield gate. Illustratively, referring to fig. 3E, an inter-gate dielectric layer 310 may continue to be formed within the second trench 304, with the inter-gate dielectric layer 310 overlying the second shield gate 309. Illustratively, the top surface of the inter-gate dielectric layer 310 may be made lower than the surface of the substrate 300.
The method for forming the inter-gate dielectric layer in the second trench to cover the second shielding gate can comprise oxidizing a portion of the second shielding gate to oxidize a portion of the second shielding gate to the inter-gate dielectric layer. Illustratively, referring to fig. 3E, a relatively thick second shield gate 309 material may be deposited, followed by an oxidation process of a portion of the thickness of the second shield gate 309 material to oxidize a portion of the second shield gate to an inter-gate dielectric layer 310. In the above embodiment, the inter-gate dielectric layer 310 is formed by oxidizing a portion of the second shielding gate 309, and during the oxidation process, the liner layer 306 covers the sidewall of the second trench 304, so as to block the sidewall of the second trench 304 from being oxidized, so that the critical dimension of the second trench 304 is not expanded, the morphology and design of the subsequently formed gate structure are more matched, and the influence on the threshold voltage (Vth) is prevented.
Next, step S6 is performed to etch and remove a portion of the shield dielectric layer, a portion of the liner layer, and a portion of the inter-gate dielectric layer to form a third trench on the inter-gate dielectric layer.
Illustratively, referring to fig. 3F, a portion of the shield dielectric layer 302, a portion of the liner layer 306, and a portion of the inter-gate dielectric layer 310 may be etched from top to bottom to form a third trench 311 over the remaining inter-gate dielectric layer 310.
Illustratively, referring to fig. 3F, after the step of etching away portions of shield dielectric layer 302, portions of liner layer 306, and portions of inter-gate dielectric layer 310 to form third trenches 311 overlying inter-gate dielectric layer 310, the top surfaces of shield dielectric layer 302, liner layer 306, and inter-gate dielectric layer 310 are level. It should be noted that the top surface is relatively flush, which may mean that the difference in height between the top of the shield dielectric layer 302, the top of the liner layer 306, and the top of the inter-gate dielectric layer 310 is less than a predetermined height, or that a portion is flush, a portion has a certain difference in height, due to an error in a process, etc.
In one example, as shown in fig. 3F, portions of the shield dielectric layer 302, portions of the liner layer 306, and portions of the inter-gate dielectric layer 310 are etched away to form a third trench 311 located over the inter-gate dielectric layer 310. So that the distance from the top surface of the shielding dielectric layer 302 to the surface of the substrate is the third depth L3, the third depth L3 is smaller than the second depth L2 due to the existence of the first shielding gate 303, the second shielding gate 309 and the remaining inter-gate dielectric layer 310, so that the filling depth of the subsequent deposition process is further reduced, and at this time, the distance W3 between the sidewalls of the third trench 311 located above the inter-gate dielectric layer 310 is greater than the second width W2, i.e. the width of the third trench 311 is increased and the depth is reduced, and thus the aspect ratio of the third trench is reduced. Therefore, the filling depth-to-width ratio of the subsequent gate electrode layer deposition process is reduced, the requirement on the high-density plasma deposition process is reduced, and the problem of limitation of the HDP deposition process is solved. And the filling window can be increased, so that the occurrence of voids in filling is reduced, the filling effect is improved, and the electrical property and the yield of the device are improved.
Finally, step S7 is performed to form a gate structure in the third trench. Illustratively, referring to fig. 3G, a gate structure 314 may be formed within the third trench 311 in any manner.
The method for forming the gate structure in the third trench may include forming a gate dielectric layer on a sidewall of the third trench, and forming a gate electrode layer filling the third trench and covering the gate dielectric layer to form the gate structure, wherein the gate structure includes the gate dielectric layer and the gate electrode layer. Illustratively, referring to fig. 3G, the gate structure 314 may include a gate dielectric layer 312 formed on sidewalls of the third trench 311, and a gate electrode layer 313 filled inside the third trench 311.
Illustratively, the gate dielectric layer 312 may be silicon oxide (SiO 2) or silicon oxynitride (SiON). The gate dielectric layer of silicon oxide may be formed by oxidation processes known to those skilled in the art, such as furnace oxidation, rapid thermal annealing oxidation (RTO), in situ steam oxidation (ISSG), and the like. The silicon oxide may be nitrided by performing a nitridation process on the silicon oxide, where the nitridation process may be high temperature furnace nitridation, rapid thermal annealing nitridation or plasma nitridation, although other nitridation processes may be used, and will not be described herein.
Illustratively, the material of the gate electrode layer 313 may include polysilicon or other suitable material, and the polysilicon may be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon comprise that the reaction gas is silane (SiH 4), the flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150sccm, the temperature in the reaction chamber can be 700-750 ℃, the pressure in the reaction chamber can be 250-350 millimeters of mercury (mTorr), such as 300mTorr, the reaction gas can also comprise buffer gas, the buffer gas can be helium (He) or nitrogen, and the flow rates of the helium and the nitrogen can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15slm.
In some embodiments, the material of the gate electrode layer 313 may also include a metallic material, such as tungsten (W) or other suitable metallic material.
The method for manufacturing the shielded gate field effect transistor of the present invention has been described so far, and the method for manufacturing the complete shielded gate field effect transistor may further include other steps, which are not described in detail herein, but it should be noted that the order of the steps may be adjusted on the premise of no conflict.
In summary, the preparation method of the embodiment of the invention comprises the steps of removing part of the thickness of the shielding dielectric layer by etching the shielding dielectric layer above the first shielding grid so as to form a second groove above the first shielding grid, forming a liner layer on the side wall of the second groove, forming a second shielding grid in the second groove, and then forming an inter-grid dielectric layer in the second groove to cover the second shielding grid. The depth-to-width ratio of the second groove can be reduced, so that the filling depth of the second groove is reduced, the filling depth-to-width ratio of the second groove is effectively reduced, the requirement on a high-density plasma deposition process is reduced, and the problem of limitation of the HDP deposition process is solved.
Specifically, a first trench extending from the surface of a substrate to the inside of the substrate is formed, a shielding dielectric layer is formed at the bottom and at least part of the side wall of the first trench, a first shielding gate positioned on the shielding dielectric layer is formed in the first trench, the shielding dielectric layer above the first shielding gate is etched, a part of the thickness of the shielding dielectric layer is removed to form a second trench above the first shielding gate, a liner layer is formed on the side wall of the second trench, a second shielding gate is formed in the second trench, an inter-gate dielectric layer is formed in the second trench to cover the second shielding gate, a part of the shielding dielectric layer, a part of the liner layer and a part of the inter-gate dielectric layer are etched and removed to form a third trench positioned on the inter-gate dielectric layer, and a gate structure is formed in the third trench. The preparation process comprises three etching steps and forms the first groove, the second groove and the third groove respectively, so that the depth-to-width ratio of the first groove, the second groove and the third groove can be reduced, the filling depth of the groove is reduced, the filling depth-to-width ratio of the groove is effectively reduced, the requirement on a high-density plasma deposition process is reduced, and the problem that the HDP deposition process is limited is solved. And the filling window can be increased, the occurrence of filling holes is reduced, the filling effect is improved, and the electrical property and the yield of the device are improved. The preparation method disclosed by the application can be suitable for supporting any HDP deposition process with a filling depth-to-width ratio, ensures that the selection of the filling process in the process of forming an inter-gate dielectric layer is not limited by the depth-to-width ratio of a groove, and solves the problem of limitation of the HDP deposition process.
In some embodiments, the shielding dielectric layer above the first shielding gate is etched to remove a part of the thickness of the shielding dielectric layer, so as to form a second trench above the first shielding gate, form a liner layer on the side wall of the second trench, and form the second shielding gate in the second trench; and then forming an inter-gate dielectric layer in the second trench to cover the second shielding gate, wherein in the scheme of the application, the liner layer is formed on the side wall of the second trench, so that the effect of blocking the oxidation of the side wall of the second trench can be realized when the inter-gate dielectric layer is formed, and further, the expansion of the Critical Dimension (CD) on two sides of the second trench is avoided, so that the form, the dimension and the design of the gate structure are more consistent, the influence on the threshold voltage (Vth) is avoided, and the stability and the reliability of the device are improved.
Examples 2
The application also provides a shielded gate field effect transistor which is prepared by the method in the first embodiment. The shielding gate field effect transistor comprises a substrate, a first groove, a shielding dielectric layer, a first shielding gate, a second groove, a liner layer, a second shielding gate, an inter-gate dielectric layer, a third groove and a gate structure, wherein the first groove extends from the surface of the substrate to the inside of the substrate, the shielding dielectric layer is formed on the bottom and part of the side wall of the first groove, the first shielding gate is formed in the first groove and is located on the shielding dielectric layer, the top surface of the first shielding gate is lower than the top surface of the shielding dielectric layer, the second groove is arranged on the first shielding gate and is surrounded by part of the shielding dielectric layer located above the first shielding gate, the liner layer is arranged on the side wall of the second groove, an opening is formed in the liner layer, the opening exposes at least part of the top surface of the first shielding gate, the second shielding gate is arranged in the second groove, the top surface of the second shielding gate is lower than the surface of the substrate, the second shielding gate is connected with the first shielding gate, the inter-gate dielectric layer is arranged in the second groove and covers the top surface of the second shielding gate, and the third groove extends from the surface of the substrate to the inside of the substrate to the surface of the first shielding gate, and is located between the third groove and the medium layer. Since the device of the present application is obtained by the aforementioned method, the same advantages as the aforementioned method are obtained.
Specifically, as shown in FIG. 3A, the substrate 300 includes a semiconductor base that may include at least one of Si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductors, or the semiconductor base may also include silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), or the like. Although a few examples of materials from which the semiconductor substrate may be formed are described herein, any material that may serve as a semiconductor substrate falls within the scope of the present invention. In addition, the substrate 300 may be divided into active regions, and/or a doping well (not shown) may be formed in the substrate 300, etc.
Illustratively, referring to fig. 3F, the top surfaces of the shield dielectric layer 302, liner layer 306, and inter-gate dielectric layer 310 are flush. It should be noted that the top surface is relatively flush, which may mean that the difference in height between the top of the shield dielectric layer 302, the top of the liner layer 306, and the top of the inter-gate dielectric layer 310 is less than a predetermined height, or that a portion is flush, a portion has a certain difference in height, due to an error in a process, etc.
Illustratively, referring to fig. 3G, the gate structure 314 may include a gate dielectric layer 312 and a gate electrode layer 313, the gate dielectric layer 312 being disposed on sidewalls of the third trench 311, the gate electrode layer 313 filling the third trench 311 and covering the gate dielectric layer 312.
The description of the structure of the shielded gate field effect transistor of the present invention is completed, and the complete device may further include other constituent structures, which are not described herein in detail.
Example (III)
The invention also provides an electronic device comprising any one of the shielded gate field effect transistors. The electronic device may be, for example, a chip such as, but not limited to, a processor, a memory, etc. containing a shielded gate field effect transistor. The electronic device may also be a terminal device such as a smart phone, a tablet computer, a desktop computer, or an intelligent wearable device, in which a part of the chips use the shielded gate field effect transistor.
Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Claims (10)
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| CN203325907U (en) * | 2012-07-16 | 2013-12-04 | 半导体元件工业有限责任公司 | Insulated gate semiconductor device structure |
| CN111681963A (en) * | 2020-08-11 | 2020-09-18 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
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| US8748976B1 (en) * | 2013-03-06 | 2014-06-10 | Texas Instruments Incorporated | Dual RESURF trench field plate in vertical MOSFET |
| US9299830B1 (en) * | 2015-05-07 | 2016-03-29 | Texas Instruments Incorporated | Multiple shielding trench gate fet |
| TWI696288B (en) * | 2019-07-16 | 2020-06-11 | 力晶積成電子製造股份有限公司 | Shield gate mosfet and method for fabricating the same |
| CN110676312A (en) * | 2019-11-07 | 2020-01-10 | 苏州凤凰芯电子科技有限公司 | Shielded gate MOS device terminal structure and fabrication method with stepped oxide layer |
| CN114420564A (en) * | 2022-03-28 | 2022-04-29 | 深圳市美浦森半导体有限公司 | MOS (Metal oxide semiconductor) device with separated gate groove and manufacturing method thereof |
| CN115148670B (en) * | 2022-07-05 | 2023-06-13 | 上海功成半导体科技有限公司 | A shielded gate trench MOSFET structure and its preparation method |
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| CN111681963A (en) * | 2020-08-11 | 2020-09-18 | 中芯集成电路制造(绍兴)有限公司 | Shielded gate field effect transistor and method of forming the same |
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