CN118471935B - Chip packaging structure and method for preparing chip packaging structure - Google Patents
Chip packaging structure and method for preparing chip packaging structure Download PDFInfo
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- CN118471935B CN118471935B CN202410911710.3A CN202410911710A CN118471935B CN 118471935 B CN118471935 B CN 118471935B CN 202410911710 A CN202410911710 A CN 202410911710A CN 118471935 B CN118471935 B CN 118471935B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 109
- 238000002360 preparation method Methods 0.000 claims abstract description 6
- 239000003292 glue Substances 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 36
- 238000003466 welding Methods 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 8
- 239000012790 adhesive layer Substances 0.000 description 25
- 238000005538 encapsulation Methods 0.000 description 16
- 239000010410 layer Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910000765 intermetallic Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 1
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000008093 supporting effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
技术领域Technical Field
本发明涉及芯片封装技术领域,具体而言,涉及一种芯片封装结构和芯片封装结构的制备方法。The present invention relates to the technical field of chip packaging, and in particular to a chip packaging structure and a method for preparing the chip packaging structure.
背景技术Background Art
在集成电路封装过程中,芯片通过各种封装方式进行I/O 引出,传统的I/O 端引出通过基板背面形成锡球结构实现与外部导通(外部器件:PCB 板/各种电子器件等),然而,在上板焊接过程中,锡球与PCB 板的焊盘之间在高温条件下会快速反应形成金属间化合物(IMC,intermetallic compound),从而导致PCB 板上的焊盘被快速消耗,出现锡球焊点断裂以及分层等问题。In the process of integrated circuit packaging, the chip is brought out through various packaging methods for I/O. The traditional I/O terminal is connected to the outside (external devices: PCB board/various electronic devices, etc.) by forming a solder ball structure on the back of the substrate. However, during the board soldering process, the solder ball and the pad of the PCB board will react quickly under high temperature conditions to form an intermetallic compound (IMC), which will cause the pad on the PCB board to be quickly consumed, resulting in problems such as solder ball solder joint breakage and delamination.
此外,锡球的导电率相对较差,且锡球焊接容易存在桥接以及锡球空洞的现象,影响其导电性能。并且,锡球在掉落测试中由于焊接强度不够容易导致焊接金属断裂失效。In addition, the conductivity of solder balls is relatively poor, and solder ball welding is prone to bridging and solder ball voids, which affect its conductivity. In addition, solder balls are prone to fracture and failure of solder metal during drop tests due to insufficient soldering strength.
发明内容Summary of the invention
本发明的目的包括,例如,提供了一种芯片封装结构和芯片封装结构的制备方法,其能够避免采用锡球焊接技术,避免了锡球焊接带来的一系列问题,保证了连接效果和连接强度,同时导电性能优异。The objectives of the present invention include, for example, providing a chip packaging structure and a method for preparing the chip packaging structure, which can avoid the use of solder ball welding technology, avoid a series of problems caused by solder ball welding, ensure the connection effect and connection strength, and have excellent conductive properties.
本发明的实施例可以这样实现:The embodiments of the present invention can be implemented as follows:
第一方面,本发明提供一种芯片封装结构,包括:In a first aspect, the present invention provides a chip packaging structure, comprising:
基板;Substrate;
第一芯片,所述第一芯片贴设在所述基板的一侧;A first chip, wherein the first chip is attached to one side of the substrate;
第一塑封体,所述第一塑封体设置在所述基板的一侧表面,并包覆在所述第一芯片外;A first plastic package, which is disposed on a side surface of the substrate and covers the first chip;
多个打线柱,多个所述打线柱设置在所述基板的另一侧表面,并朝向背离所述第一塑封体的方向凸起;A plurality of bonding posts, which are arranged on the other side surface of the substrate and protrude in a direction away from the first plastic package body;
第二塑封体,所述第二塑封体设置在所述基板的另一侧表面,并包覆在所述打线柱周围;A second plastic package body, the second plastic package body is arranged on the other side surface of the substrate and covers around the bonding post;
其中,每个所述打线柱与所述基板电连接,且每个所述打线柱至少部分外露于所述第二塑封体,用于与电路板电连接。Wherein, each of the bonding posts is electrically connected to the substrate, and each of the bonding posts is at least partially exposed outside the second plastic package body for being electrically connected to the circuit board.
在可选的实施方式中,所述芯片封装结构还包括第二芯片,所述第二芯片贴设在所述基板背离所述第一芯片的一侧表面,且所述第二芯片相对于所述基板的高度小于所述打线柱相对于所述基板的高度,所述第二塑封体围设在所述第二芯片的周围。In an optional embodiment, the chip packaging structure also includes a second chip, which is attached to a surface of the substrate on a side away from the first chip, and a height of the second chip relative to the substrate is less than a height of the bonding post relative to the substrate, and the second plastic package is disposed around the second chip.
在可选的实施方式中,所述第二芯片与所述基板之间还设置有填充胶层。In an optional implementation, a filling glue layer is further provided between the second chip and the substrate.
在可选的实施方式中,所述基板远离所述第一塑封体的一侧表面还设置有多个打线焊盘,多个所述打线柱一一对应地连接于多个所述打线焊盘。In an optional embodiment, a plurality of wire bonding pads are further disposed on a surface of the substrate at a side away from the first plastic packaging body, and the plurality of wire bonding posts are connected to the plurality of wire bonding pads in a one-to-one correspondence.
在可选的实施方式中,所述打线柱远离所述基板的一端伸出所述第二塑封体,并相对于所述第二塑封体远离所述基板的一侧表面凸起设置。In an optional embodiment, one end of the bonding post away from the substrate extends out of the second plastic packaging body and is arranged to be raised relative to a surface of one side of the second plastic packaging body away from the substrate.
在可选的实施方式中,所述打线柱嵌设在所述第二塑封体内,且所述第二塑封体的侧壁开设有第一沟槽,所述第一沟槽延伸至所述打线柱的侧壁。In an optional embodiment, the bonding post is embedded in the second plastic package body, and a first groove is formed in a side wall of the second plastic package body, and the first groove extends to the side wall of the bonding post.
在可选的实施方式中,所述第一沟槽远离所述基板的一侧内壁与所述打线柱的端面相平齐。In an optional embodiment, an inner wall of the first groove on a side away from the substrate is flush with an end surface of the bonding post.
在可选的实施方式中,所述第一沟槽的开口方向背离所述基板的中心。In an optional embodiment, an opening direction of the first groove is away from the center of the substrate.
在可选的实施方式中, 所述第二塑封体远离所述基板的一侧表面中部设置有第二沟槽,所述第二沟槽的宽度被配置为大于或等于所述电路板上的电连焊盘,以使所述电路板上的电连焊盘嵌设在所述第二沟槽内。In an optional embodiment, a second groove is provided in the middle of a surface of the second plastic package body away from the substrate, and a width of the second groove is configured to be greater than or equal to the electrical connection pad on the circuit board so that the electrical connection pad on the circuit board is embedded in the second groove.
在可选的实施方式中,所述第二沟槽的两端贯穿至所述第二塑封体的侧壁,以使所述电路板上的电连焊盘部分嵌设在所述第二沟槽内。In an optional embodiment, both ends of the second groove penetrate through the side wall of the second plastic package body, so that the electrical connection pad on the circuit board is partially embedded in the second groove.
在可选的实施方式中,所述第二沟槽的深度被配置为大于或等于所述电路板上的电连焊盘的高度。In an optional embodiment, the depth of the second groove is configured to be greater than or equal to the height of the electrical connection pad on the circuit board.
第二方面,本发明提供一种芯片封装结构的制备方法,用于制备如前述实施方式所述的芯片封装结构,所述制备方法包括:In a second aspect, the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure as described in the above embodiment, and the preparation method comprises:
在基板的一侧贴设第一芯片;A first chip is mounted on one side of the substrate;
在所述基板的一侧表面形成第一塑封体,所述第一塑封体包覆在所述第一芯片外;A first plastic package is formed on one side surface of the substrate, wherein the first plastic package covers the first chip;
在所述基板的另一侧表面打线形成多个打线柱,多个所述打线柱朝向背离所述第一塑封体的方向凸起;Bonding a plurality of bonding posts on the other side surface of the substrate, wherein the plurality of bonding posts protrude in a direction away from the first plastic package body;
在所述基板的另一侧表面形成第二塑封体,所述第二塑封体包覆在所述打线柱的周围;A second plastic package is formed on the other side surface of the substrate, wherein the second plastic package covers around the bonding post;
其中,每个所述打线柱与所述基板电连接,且每个所述打线柱至少部分外露于所述第二塑封体,用于与电路板电连接。Wherein, each of the bonding posts is electrically connected to the substrate, and each of the bonding posts is at least partially exposed outside the second plastic package body for being electrically connected to the circuit board.
本发明实施例的有益效果包括,例如:The beneficial effects of the embodiments of the present invention include, for example:
本发明实施例提供的芯片封装结构和芯片封装结构的制备方法,将第一芯片贴设在基板的一侧,同时在第一芯片外塑封形成第一塑封体,而在基板的另一侧表面打线形成多个打线柱,多个打线柱朝向背离第一塑封体的方向凸起,并且在基板的另一侧表面形成有第二塑封体,第二塑封体包覆在打线柱的周围,其中,每个打线柱与基板电连接,且每个打线柱至少部分外露于第二塑封体,用于与电路板电连接。相较于现有技术,本发明利用打线柱来替代锡球,避免了采用锡球焊接技术,进而避免了锡球焊接带来的一系列问题,同时利用第二塑封体来支撑保护打线柱,能够大幅提升结构强度,保证了连接效果和连接强度,同时打线柱不会出现桥接或空洞现象,导电性能优异。The chip packaging structure and the preparation method of the chip packaging structure provided by the embodiment of the present invention attach the first chip to one side of the substrate, and at the same time, plastic-encapsulate the first chip to form a first plastic encapsulation body, and wire the other side surface of the substrate to form a plurality of wire bonding posts, the plurality of wire bonding posts protrude in the direction away from the first plastic encapsulation body, and a second plastic encapsulation body is formed on the other side surface of the substrate, the second plastic encapsulation body is wrapped around the wire bonding posts, wherein each wire bonding post is electrically connected to the substrate, and each wire bonding post is at least partially exposed to the second plastic encapsulation body for electrical connection with the circuit board. Compared with the prior art, the present invention uses wire bonding posts to replace solder balls, avoids the use of solder ball welding technology, and thus avoids a series of problems caused by solder ball welding, and at the same time uses the second plastic encapsulation body to support and protect the wire bonding posts, which can greatly improve the structural strength, ensure the connection effect and connection strength, and at the same time, the wire bonding posts will not have bridging or void phenomena, and have excellent conductive properties.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本发明的某些实施例,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
图1为本发明实施例提供的第一种芯片封装结构的剖面示意图;FIG1 is a cross-sectional schematic diagram of a first chip packaging structure provided by an embodiment of the present invention;
图2为本发明实施例提供的第一种芯片封装结构的平面示意图;FIG2 is a schematic plan view of a first chip packaging structure provided by an embodiment of the present invention;
图3为本发明实施例提供的第一种芯片封装结构的上板结构示意图;3 is a schematic diagram of an upper plate structure of a first chip packaging structure provided by an embodiment of the present invention;
图4为本发明实施例提供的第二种芯片封装结构的剖面示意图;FIG4 is a cross-sectional schematic diagram of a second chip packaging structure provided by an embodiment of the present invention;
图5为本发明实施例提供的第二种芯片封装结构的平面示意图;FIG5 is a schematic plan view of a second chip packaging structure provided by an embodiment of the present invention;
图6为本发明实施例提供的第二种芯片封装结构的上板结构示意图;6 is a schematic diagram of an upper plate structure of a second chip packaging structure provided by an embodiment of the present invention;
图7为本发明实施例提供的第三种芯片封装结构的剖面示意图;7 is a cross-sectional schematic diagram of a third chip packaging structure provided by an embodiment of the present invention;
图8为本发明实施例提供的第三种芯片封装结构的上板结构示意图;8 is a schematic diagram of an upper plate structure of a third chip packaging structure provided by an embodiment of the present invention;
图9a为本发明实施例提供的第三种芯片封装结构的上板平面示意图;FIG9a is a schematic diagram of an upper plate plan view of a third chip packaging structure provided by an embodiment of the present invention;
图9b为图9a中A-A处的剖面结构示意图;Fig. 9b is a schematic diagram of the cross-sectional structure at A-A in Fig. 9a;
图10 为图8中Ⅹ的第一种局部放大示意图;FIG10 is a first partial enlarged schematic diagram of X in FIG8;
图11为图8中Ⅹ的第二种局部放大示意图;FIG11 is a second partial enlarged schematic diagram of X in FIG8;
图12至图16为本发明实施例提供的芯片封装结构的制备方法的工艺流程图。12 to 16 are process flow charts of a method for preparing a chip packaging structure provided in an embodiment of the present invention.
图标:100-芯片封装结构;110-基板;111-打线焊盘;120-第一芯片;130-第一塑封体;140-第二塑封体;141-第一沟槽;143-第二沟槽;150-打线柱;160-第二芯片;161-填充胶层;170-凹槽;200-电路板;210-电连焊盘;230-导电胶层。Icon: 100-chip packaging structure; 110-substrate; 111-wire bonding pad; 120-first chip; 130-first plastic package; 140-second plastic package; 141-first groove; 143-second groove; 150-wire bonding column; 160-second chip; 161-filling glue layer; 170-groove; 200-circuit board; 210-electrical connection pad; 230-conductive glue layer.
具体实施方式DETAILED DESCRIPTION
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围,而是仅仅表示本发明的选定实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
在本发明的描述中,需要说明的是,若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,或者是该发明产品使用时惯常摆放的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
此外,若出现术语“第一”、“第二”等仅用于区分描述,而不能理解为指示或暗示相对重要性。In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.
正如背景技术中所公开的,现有技术中的传统封装器件通常采用的是锡球焊接技术,即在基板的背面植球形成锡球后,利用锡球与外部器件(如电路板)焊接固定。然而,由于锡球的特性,在上板焊接过程中,锡球与电路板的焊盘之间在高温条件下会快速反应形成金属间化合物(IMC,intermetallic compound),从而导致PCB 板上的焊盘被快速消耗,出现锡球焊点断裂以及分层等问题。As disclosed in the background technology, conventional packaging devices in the prior art usually use solder ball welding technology, that is, after solder balls are planted on the back of the substrate to form solder balls, the solder balls are used to solder and fix with external devices (such as circuit boards). However, due to the characteristics of solder balls, during the soldering process on the upper board, the solder balls and the pads of the circuit board will react quickly under high temperature conditions to form intermetallic compounds (IMCs), which will cause the pads on the PCB to be quickly consumed, resulting in problems such as solder ball solder joints breaking and delamination.
此外,锡球的导电率相对较差,且锡球焊接容易存在桥接以及锡球空洞的现象,影响其导电性能。并且,锡球在掉落测试中由于焊接强度不够容易导致焊接金属断裂失效。In addition, the conductivity of solder balls is relatively poor, and solder ball welding is prone to bridging and solder ball voids, which affect its conductivity. In addition, solder balls are prone to fracture and failure of solder metal during drop tests due to insufficient soldering strength.
针对于此,现有技术中出现了管脚式结构,利用金属凸点或金属柱来实现上板焊接,然而,这种结构仍然需要高温焊接,同样容易出现焊接失效的问题,且金属凸点或金属柱与基板或芯片之间的连接结构强度较低,容易出现脱落的问题,同样影响其导电性能。In view of this, a pin-type structure has emerged in the prior art, which uses metal bumps or metal columns to achieve upper board welding. However, this structure still requires high-temperature welding and is also prone to welding failure problems. In addition, the connection structure strength between the metal bumps or metal columns and the substrate or chip is low and is prone to falling off, which also affects its conductive performance.
针对于此,本发明实施例提供了一种芯片封装结构和芯片封装结构的制备方法,需要说明的是,在不冲突的情况下,本发明的实施例中的特征可以相互结合。To this end, an embodiment of the present invention provides a chip packaging structure and a method for preparing the chip packaging structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.
请参考图1至图3,本发明实施例提供了一种芯片封装结构100,其能够避免采用锡球焊接技术,避免了锡球焊接带来的一系列问题,保证了连接效果和连接强度,同时导电性能优异。Please refer to Figures 1 to 3. An embodiment of the present invention provides a chip packaging structure 100, which can avoid the use of solder ball welding technology, avoid a series of problems caused by solder ball welding, ensure the connection effect and connection strength, and have excellent conductive performance.
本发明实施例提供的芯片封装结构100,包括基板110、第一芯片120、第一塑封体130、第二塑封体140和多个打线柱150,第一芯片120贴设在基板110的一侧,第一塑封体130设置在基板110的一侧表面,并包覆在第一芯片120外;多个打线柱150设置在基板110的另一侧表面,并朝向背离第一塑封体130的方向凸起;第二塑封体140设置在基板110的另一侧表面,并包覆在打线柱150周围;其中,每个打线柱150与基板110电连接,且每个打线柱150至少部分外露于第二塑封体140,用于与电路板200电连接。The chip packaging structure 100 provided in the embodiment of the present invention includes a substrate 110, a first chip 120, a first plastic package body 130, a second plastic package body 140 and a plurality of bonding posts 150. The first chip 120 is attached to one side of the substrate 110, the first plastic package body 130 is arranged on one side surface of the substrate 110 and covers the first chip 120; the plurality of bonding posts 150 are arranged on the other side surface of the substrate 110 and protrude in a direction away from the first plastic package body 130; the second plastic package body 140 is arranged on the other side surface of the substrate 110 and covers around the bonding posts 150; wherein each bonding post 150 is electrically connected to the substrate 110, and each bonding post 150 is at least partially exposed from the second plastic package body 140 for being electrically connected to the circuit board 200.
需要说明的是,本实施例中多个打线柱150间隔围设在基板110的边缘区域,每个打线柱150的周围均围设有第二塑封体140,第二塑封体140能够有效保护打线柱150。利用打线柱150来替代锡球,避免了采用锡球焊接技术,进而避免了锡球焊接带来的一系列问题,同时利用第二塑封体140来支撑保护打线柱150,能够大幅提升结构强度,保证了连接效果和连接强度,同时打线柱150不会出现桥接或空洞现象,导电性能优异。It should be noted that in this embodiment, a plurality of bonding posts 150 are arranged at intervals around the edge area of the substrate 110, and each bonding post 150 is surrounded by a second plastic package 140, which can effectively protect the bonding posts 150. Using the bonding posts 150 to replace the solder balls avoids the use of solder ball welding technology, thereby avoiding a series of problems caused by solder ball welding. At the same time, using the second plastic package 140 to support and protect the bonding posts 150 can greatly improve the structural strength, ensure the connection effect and connection strength, and at the same time, the bonding posts 150 will not have bridging or voids, and have excellent conductive properties.
进一步地,在一些实施例中,芯片封装结构100还包括第二芯片160,第二芯片160贴设在基板110背离第一芯片120的一侧表面,且第二芯片160相对于基板110的高度小于打线柱150相对于基板110的高度,第二塑封体140围设在第二芯片160的周围。具体地,第二芯片160倒装在基板110的底侧表面,第一芯片120倒装在基板110的顶侧表面,第一芯片120和第二芯片160对位且正面相对设置,第一芯片120和第二芯片160的贴装工艺可以参考常规的芯片贴装工艺。Furthermore, in some embodiments, the chip package structure 100 further includes a second chip 160, which is attached to a side surface of the substrate 110 away from the first chip 120, and the height of the second chip 160 relative to the substrate 110 is less than the height of the bonding pillar 150 relative to the substrate 110, and the second plastic package 140 is arranged around the second chip 160. Specifically, the second chip 160 is flip-mounted on the bottom side surface of the substrate 110, and the first chip 120 is flip-mounted on the top side surface of the substrate 110, and the first chip 120 and the second chip 160 are aligned and arranged opposite to each other on the front side, and the mounting process of the first chip 120 and the second chip 160 can refer to the conventional chip mounting process.
需要说明的是,第二芯片160贴设在基板110的中心区域,第二塑封体140可以呈围墙状围设在第二芯片160的周围,并同时包覆在多个打线柱150外。第二塑封体140可以通过特殊的塑封模具制备,也可以在平面塑封后通过激光开槽或刻蚀开槽的方式将中心区域去除,从而形成围墙结构。It should be noted that the second chip 160 is attached to the central area of the substrate 110, and the second plastic package 140 can be arranged around the second chip 160 in the shape of a wall, and at the same time cover the plurality of wire bonding posts 150. The second plastic package 140 can be prepared by a special plastic package mold, or the central area can be removed by laser grooving or etching grooving after plane plastic packaging, thereby forming a wall structure.
在一些实施例中,第二芯片160与基板110之间还设置有填充胶层161。具体地,填充胶层161可以将第二芯片160底部的凸点以及基板110上的焊盘包覆在内,从而起到保护作用。并且,第二塑封体140同样围设在填充胶层161的周围,填充胶层161相对于基板110的高度低于第二芯片160相对于基板110的高度。In some embodiments, a filling glue layer 161 is further provided between the second chip 160 and the substrate 110. Specifically, the filling glue layer 161 can cover the bumps at the bottom of the second chip 160 and the pads on the substrate 110, thereby playing a protective role. In addition, the second plastic package 140 is also arranged around the filling glue layer 161, and the height of the filling glue layer 161 relative to the substrate 110 is lower than the height of the second chip 160 relative to the substrate 110.
在一些实施例中,基板110远离第一塑封体130的一侧表面还设置有多个打线焊盘111,多个打线柱150一一对应地连接于多个打线焊盘111。具体地,通过多个打线焊盘111,能够实现打线柱150与基板110之间的电气连接,并且,多个打线焊盘111可以在制备基板110时一并形成,方便后续直接在打线焊盘111上进行打线制程。其中,多个打线焊盘111可以沿一矩形边框分布,并沿基板110的边缘区域分布,从而保证后续形成的多个打线柱150能够围设在第二芯片160的周围。In some embodiments, a plurality of wire bonding pads 111 are further provided on the surface of one side of the substrate 110 away from the first plastic package body 130, and a plurality of wire bonding posts 150 are connected to the plurality of wire bonding pads 111 in a one-to-one correspondence. Specifically, the electrical connection between the wire bonding posts 150 and the substrate 110 can be achieved through the plurality of wire bonding pads 111, and the plurality of wire bonding pads 111 can be formed together when preparing the substrate 110, so as to facilitate the subsequent wire bonding process directly on the wire bonding pads 111. Among them, the plurality of wire bonding pads 111 can be distributed along a rectangular frame and along the edge area of the substrate 110, so as to ensure that the plurality of wire bonding posts 150 formed subsequently can be arranged around the second chip 160.
在一些实施例中,打线柱150远离基板110的一端伸出第二塑封体140,并相对于第二塑封体140远离基板110的一侧表面凸起设置。具体地,第二塑封体140相对于基板110的高度低于打线柱150相对于基板110的高度,利用第二塑封体140能够保护打线柱150,提升其强度,并且打线柱150的端面和第二塑封体140远离基板110的一侧表面存在高度差,因此打线柱150远离基板110的一端能够形成凸点构造,方便上板时胶层的进入,从而能够大幅提升结合强度。In some embodiments, one end of the bonding post 150 away from the substrate 110 extends out of the second plastic package body 140, and is convexly arranged relative to the side surface of the second plastic package body 140 away from the substrate 110. Specifically, the height of the second plastic package body 140 relative to the substrate 110 is lower than the height of the bonding post 150 relative to the substrate 110. The second plastic package body 140 can protect the bonding post 150 and improve its strength. In addition, there is a height difference between the end face of the bonding post 150 and the side surface of the second plastic package body 140 away from the substrate 110. Therefore, a convex point structure can be formed at the end of the bonding post 150 away from the substrate 110, which facilitates the entry of the glue layer when the board is mounted, thereby greatly improving the bonding strength.
需要说明的是,在实际上板时,打线柱150的端面能够与电路板200上的电连焊盘210直接接触,即打线柱150与电连焊盘210连接,然后通过外部的胶层进行固定,此时的胶层优选可以是导电胶层230,当然也可以是绝缘胶。由于打线柱150的端面凸起于第二塑封体140,而打线柱150的端面直接与电路板200上的电连焊盘210接触,因此第二塑封体140与电路板200之间能够形成间隙,胶层可以进入到该间隙,从而提升胶层的覆盖面积,进而提升连接结合性,保证连接强度。It should be noted that, when actually mounting the board, the end face of the bonding post 150 can directly contact the electrical connection pad 210 on the circuit board 200, that is, the bonding post 150 is connected to the electrical connection pad 210, and then fixed by an external adhesive layer, at which time the adhesive layer can preferably be a conductive adhesive layer 230, and of course, it can also be an insulating adhesive. Since the end face of the bonding post 150 protrudes from the second plastic package 140, and the end face of the bonding post 150 directly contacts the electrical connection pad 210 on the circuit board 200, a gap can be formed between the second plastic package 140 and the circuit board 200, and the adhesive layer can enter the gap, thereby increasing the coverage area of the adhesive layer, thereby improving the connection bonding and ensuring the connection strength.
在一些实施例中,第二塑封体140远离所述基板110的端面上还设置有多个凹槽170,多个凹槽170间隔排布在第二塑封体140的端面上,在上板时,胶层能够填充至凹槽170中,从而大幅提升结合面积,进而提升其结合强度。In some embodiments, a plurality of grooves 170 are further provided on the end surface of the second plastic packaging body 140 away from the substrate 110. The plurality of grooves 170 are arranged at intervals on the end surface of the second plastic packaging body 140. When the board is mounted, the adhesive layer can be filled into the grooves 170, thereby greatly increasing the bonding area and further improving its bonding strength.
参见图4至图6,在一些较佳的实施例中,打线柱150嵌设在第二塑封体140内,且第二塑封体140的侧壁开设有第一沟槽141,第一沟槽141延伸至打线柱150的侧壁。具体地,第二塑封体140包覆在打线柱150外,第一沟槽141开设在第二塑封体140的侧壁处,并能够将打线柱150部分露出,方便胶层进入并与打线柱150接触,其中第一沟槽141一方面能够供导电胶层230进入,实现打线柱150与电连焊盘210之间的电连接,另一方面第一沟槽141还能够起到缓冲凹槽的作用,能够缓冲对于第二塑封体140的外部冲击,防止其隐裂或脱落,同时能够缓冲与电连焊盘210之间的冲击。Referring to FIG. 4 to FIG. 6 , in some preferred embodiments, the bonding post 150 is embedded in the second plastic package body 140, and the side wall of the second plastic package body 140 is provided with a first groove 141, and the first groove 141 extends to the side wall of the bonding post 150. Specifically, the second plastic package body 140 is covered on the outside of the bonding post 150, and the first groove 141 is provided at the side wall of the second plastic package body 140, and can partially expose the bonding post 150, so as to facilitate the entry of the adhesive layer and contact with the bonding post 150, wherein the first groove 141 can allow the conductive adhesive layer 230 to enter on the one hand, so as to realize the electrical connection between the bonding post 150 and the electrical connection pad 210, and on the other hand, the first groove 141 can also play the role of a buffer groove, which can buffer the external impact on the second plastic package body 140, prevent it from cracking or falling off, and can buffer the impact between the electrical connection pad 210.
需要说明的是,在实际上板时,由于打线柱150嵌设在第二塑封体140内部,因此打线柱150不与电路板200上的电连焊盘210直接接触,此时第二塑封体140远离基板110的一侧表面与电路板200上的电连焊盘210直接接触,且第二塑封体140与电路板200之间同样存在间隙。为了实现焊盘和打线柱150之间的电连接,此时可以采用导电胶层230作为结构胶层包覆在焊盘和打线柱150之间,在导电胶层230流动阶段,导电胶层230可以通过第一沟槽141流动至与打线柱150接触,并且可以流动至第二塑封体140与电路板200之间的间隙中与焊盘接触,因此打线柱150可以通过导电胶层230与焊盘电连接。It should be noted that, when the board is actually mounted, since the bonding post 150 is embedded in the second plastic package 140, the bonding post 150 does not directly contact the electrical connection pad 210 on the circuit board 200. At this time, the side surface of the second plastic package 140 away from the substrate 110 is in direct contact with the electrical connection pad 210 on the circuit board 200, and there is also a gap between the second plastic package 140 and the circuit board 200. In order to achieve electrical connection between the pad and the bonding post 150, a conductive adhesive layer 230 can be used as a structural adhesive layer to be coated between the pad and the bonding post 150. During the flow stage of the conductive adhesive layer 230, the conductive adhesive layer 230 can flow through the first groove 141 to contact the bonding post 150, and can flow to the gap between the second plastic package 140 and the circuit board 200 to contact the pad, so the bonding post 150 can be electrically connected to the pad through the conductive adhesive layer 230.
进一步地,第一沟槽141远离基板110的一侧内壁与打线柱150的端面相平齐。具体地,第一沟槽141位于第二塑封体140远离基板110的一端的端面附近,并且能够保持与打线柱150的端面相平齐,一方面能够保证上板时导电胶层230能够爬升至第二塑封体140的侧壁并进入第一沟槽141,另一方面也使得第一沟槽141尽可能第远离第一基板110,便于成型。Furthermore, the inner wall of the first groove 141 on one side away from the substrate 110 is flush with the end face of the bonding post 150. Specifically, the first groove 141 is located near the end face of the second plastic package body 140 away from the substrate 110, and can be kept flush with the end face of the bonding post 150. On the one hand, it can ensure that the conductive adhesive layer 230 can climb to the side wall of the second plastic package body 140 and enter the first groove 141 when the board is mounted, and on the other hand, it also makes the first groove 141 as far away from the first substrate 110 as possible to facilitate molding.
在一些实施例中,第一沟槽141的开口方向背离基板110的中心。具体地,每个第一沟槽141的开口方向均朝外,从而在点胶时可以尽可能地使得导电胶层230快速进入第一沟槽141。当然,在本发明其他较佳的实施例中,第一沟槽141的开口方向也可以朝内,或者倾斜/螺旋设置,对于第一沟槽141的开设方式,在此不作具体限定。In some embodiments, the opening direction of the first groove 141 is away from the center of the substrate 110. Specifically, the opening direction of each first groove 141 is outward, so that the conductive adhesive layer 230 can enter the first groove 141 as quickly as possible during dispensing. Of course, in other preferred embodiments of the present invention, the opening direction of the first groove 141 can also be inward, or inclined/spiral, and the opening method of the first groove 141 is not specifically limited here.
需要说明的是,此处第一沟槽141的制备可以通过特殊的塑封模具直接成型,也可以通过激光开槽工艺在第二塑封体140的侧壁开槽形成第一沟槽141。第一沟槽141设计在第二塑封体140的侧壁,利用第一沟槽141贯穿至打线柱150,从而能够形成缓冲结构,其上板时可以利用底部的导电胶层230通过毛细作用进入第一沟槽141以及第二塑封体140和电路板200之间的间隙,从而通过导电胶层230实现打线柱150和电路板200焊盘之间的电连接,而第一沟槽141和间隙的设置,能够使得导电胶层230的分布面积更大,大大提升了导电胶层230的结合力,使得整体连接效果和强度更好。It should be noted that the preparation of the first groove 141 here can be directly formed by a special plastic packaging mold, or the first groove 141 can be formed by slotting the side wall of the second plastic packaging body 140 through a laser slotting process. The first groove 141 is designed on the side wall of the second plastic packaging body 140, and the first groove 141 is used to penetrate to the wire post 150, so as to form a buffer structure. When the board is mounted, the conductive adhesive layer 230 at the bottom can enter the first groove 141 and the gap between the second plastic packaging body 140 and the circuit board 200 through capillary action, so as to realize the electrical connection between the wire post 150 and the pad of the circuit board 200 through the conductive adhesive layer 230. The setting of the first groove 141 and the gap can make the distribution area of the conductive adhesive layer 230 larger, greatly improve the bonding force of the conductive adhesive layer 230, and make the overall connection effect and strength better.
参见图7至图8,在一些实施例中,第二塑封体140远离基板110的一侧表面中部设置有第二沟槽143,第二沟槽143的宽度被配置为大于或等于电路板200上的电连焊盘210,以使电路板200上的电连焊盘210嵌设在第二沟槽143内。具体地,第二塑封体140的侧壁形成有第一沟槽141,同时在远离基板110的一侧表面形成有第二沟槽143,第二沟槽143的设置一方面可以提升底部胶层的结合力,另一方面能够将电路板200上的外接焊盘适配在内,从而提升定位精度。优选地,第二沟槽143的深度被配置为大于或等于电路板200上的电连焊盘210的高度,从而能够保证第二沟槽143能够容纳焊盘,并保证第二塑封体140与电路板200直接接触,起到支撑效果。Referring to FIG. 7 and FIG. 8 , in some embodiments, a second groove 143 is provided in the middle of the side surface of the second plastic package 140 away from the substrate 110, and the width of the second groove 143 is configured to be greater than or equal to the electrical connection pad 210 on the circuit board 200, so that the electrical connection pad 210 on the circuit board 200 is embedded in the second groove 143. Specifically, the side wall of the second plastic package 140 is formed with a first groove 141, and the second groove 143 is formed on the side surface away from the substrate 110. The second groove 143 can improve the bonding force of the bottom glue layer on the one hand, and can fit the external pad on the circuit board 200 inside, thereby improving the positioning accuracy. Preferably, the depth of the second groove 143 is configured to be greater than or equal to the height of the electrical connection pad 210 on the circuit board 200, so as to ensure that the second groove 143 can accommodate the pad, and ensure that the second plastic package 140 is in direct contact with the circuit board 200, so as to play a supporting effect.
值得注意的是,本实施例优选地,第二沟槽143被配置为与焊盘的形状相适配,即第二沟槽143的宽度基本与焊盘的宽度相同(有微小的安装间隙余量),第二沟槽143的深度基板110与焊盘的高度相同,从而能够进一步保证精准定位,如图10所示。当然,在其他较佳的实施例中,第二沟槽143也可以被配置为大于焊盘的尺寸,即第二沟槽143的宽度大于焊盘的宽度,第二沟槽143的侧壁与电连焊盘210之间能够形成间隙,同时第二沟槽143的深度大于电连焊盘210的高度,如图11所示,这种结构在保证定位贴装精度的同时,能够大幅提升底部导电胶层230的流动空间,提升其流动性,进而提升胶层的结合力。It is worth noting that, in this embodiment, the second groove 143 is preferably configured to match the shape of the pad, that is, the width of the second groove 143 is substantially the same as the width of the pad (with a slight installation gap margin), and the depth of the second groove 143 is the same as the height of the pad, so that accurate positioning can be further ensured, as shown in FIG10. Of course, in other preferred embodiments, the second groove 143 can also be configured to be larger than the size of the pad, that is, the width of the second groove 143 is greater than the width of the pad, and a gap can be formed between the sidewall of the second groove 143 and the electrical connection pad 210, and the depth of the second groove 143 is greater than the height of the electrical connection pad 210, as shown in FIG11. This structure can greatly increase the flow space of the bottom conductive adhesive layer 230, improve its fluidity, and thus improve the bonding force of the adhesive layer while ensuring the positioning and mounting accuracy.
进一步地,第二沟槽143的两端贯穿至第二塑封体140的侧壁,以使电路板200上的电连焊盘210部分嵌设在第二沟槽143内。具体地,第二沟槽143的两端均为贯穿结构,从而能够与外部空间连通,方便导电胶层230通过毛细作用进入到第二沟槽143,并与焊盘连接。Furthermore, both ends of the second groove 143 penetrate the side wall of the second plastic package 140, so that the electrical connection pad 210 on the circuit board 200 is partially embedded in the second groove 143. Specifically, both ends of the second groove 143 are through structures, so that they can be connected with the external space, which facilitates the conductive adhesive layer 230 to enter the second groove 143 through capillary action and connect with the pad.
请继续参见图9a和图9b,需要说明的是,此处电路板200上的电连焊盘210可以是条状焊盘,而第二沟槽143可以恰好扣合在条状焊盘上,大大提升了定位效果。其中第二沟槽143用于贴装固定在电连焊盘210的位置,从而能够提升定位精度,并提升底部导电胶层230的流动空间,从而提升底部焊盘的结合力。Please continue to refer to FIG. 9a and FIG. 9b. It should be noted that the electrical connection pad 210 on the circuit board 200 here can be a strip pad, and the second groove 143 can be just buckled on the strip pad, which greatly improves the positioning effect. The second groove 143 is used to be mounted and fixed on the position of the electrical connection pad 210, thereby improving the positioning accuracy and increasing the flow space of the bottom conductive adhesive layer 230, thereby improving the bonding force of the bottom pad.
进一步地,如图9a和图9b中所示,在实施例中,第二塑封体140可以是间断分布,即第二塑封体140仅仅分布在打线柱150的周围,此时,第一沟槽141可以开设在第二塑封体140任意方向的侧壁上,优选地,第一沟槽141的开口方向可以与条状的电连焊盘210的延伸方向相平行,通过这种设置,使得导电胶层230可以直接包覆在第二塑封体140的底部周围,并进入第一沟槽141,而相较于前述实施例,此处可以提升导电胶层230与电连焊盘210的接触面积,并且第一沟槽141和电连焊盘210之间距离减小,可以降低导电路径的距离,进而提升电连接性能。Further, as shown in Figures 9a and 9b, in an embodiment, the second plastic package body 140 can be intermittently distributed, that is, the second plastic package body 140 is only distributed around the wire bonding column 150. At this time, the first groove 141 can be opened on the side wall of the second plastic package body 140 in any direction. Preferably, the opening direction of the first groove 141 can be parallel to the extension direction of the strip-shaped electrical connection pad 210. Through this arrangement, the conductive adhesive layer 230 can be directly coated around the bottom of the second plastic package body 140 and enter the first groove 141. Compared with the aforementioned embodiment, the contact area between the conductive adhesive layer 230 and the electrical connection pad 210 can be increased here, and the distance between the first groove 141 and the electrical connection pad 210 is reduced, which can reduce the distance of the conductive path and thereby improve the electrical connection performance.
本发明实施例还提供了一种芯片封装结构100的制备方法,用于制备前述的芯片封装结构100,该制备方法包括以下步骤:The embodiment of the present invention further provides a method for preparing a chip packaging structure 100, which is used to prepare the aforementioned chip packaging structure 100. The method comprises the following steps:
S1:在基板110的一侧贴设第一芯片120。S1: placing a first chip 120 on one side of the substrate 110 .
参见图12,具体地,首先提供一基板110,该基板110上可以预先制备形成打线焊盘111,同时在芯片贴装区域也预先制备连接焊盘,然后通过常规的芯片贴装工艺,将第一芯片120倒装贴设在基板110一侧表面。当然,此处第一芯片120也可以采用正装芯片,并通过打线与基板110实现电连接。其中基板110可以是陶瓷板、引线框等结构。Referring to FIG. 12 , specifically, a substrate 110 is first provided, on which a wire bonding pad 111 may be pre-prepared, and a connection pad is also pre-prepared in the chip mounting area, and then a first chip 120 is flip-chip mounted on a surface of one side of the substrate 110 through a conventional chip mounting process. Of course, the first chip 120 may also be a face-up chip, and be electrically connected to the substrate 110 through wire bonding. The substrate 110 may be a ceramic board, a lead frame, or the like.
S2:在基板110的一侧表面形成第一塑封体130,第一塑封体130包覆在第一芯片120外。S2: forming a first plastic package 130 on one side surface of the substrate 110 , wherein the first plastic package 130 covers the first chip 120 .
参见图13,具体地,通过塑封工艺,在基板110的一侧表面形成第一塑封体130,其中第一塑封体130能够包覆在第一芯片120外,利用第一塑封体130保护贴装好的第一芯片120。13 , specifically, a first plastic package 130 is formed on one side surface of the substrate 110 through a plastic packaging process, wherein the first plastic package 130 can cover the first chip 120 , and the first plastic package 130 is used to protect the mounted first chip 120 .
S3:在基板110的另一侧表面打线形成多个打线柱150,多个打线柱150朝向背离第一塑封体130的方向凸起。S3: bonding the other surface of the substrate 110 to form a plurality of bonding posts 150 , wherein the plurality of bonding posts 150 protrude in a direction away from the first plastic package body 130 .
具体地,参见图14,在完成第一塑封体130后,可以翻转基板110,然后利用打线工艺,在基板110的背面的打线焊盘111上打垂直金属线,形成多个打线柱150。其中打线柱150可以是铜线、铝线或金线等材料。Specifically, referring to FIG. 14 , after the first plastic package 130 is completed, the substrate 110 can be turned over, and then a wire bonding process is used to bond vertical metal wires on the wire bonding pads 111 on the back of the substrate 110 to form a plurality of wire bonding posts 150. The wire bonding posts 150 can be made of materials such as copper wires, aluminum wires or gold wires.
S4:在基板110的另一侧表面形成第二塑封体140,第二塑封体140包覆在打线柱150的周围。S4 : forming a second plastic package body 140 on the other side surface of the substrate 110 , and the second plastic package body 140 covers around the bonding pillars 150 .
参见图15,具体地,可以利用塑封工艺,将打线结构进行塑封包裹,形成第二塑封体140,然后利用激光开槽方式,将打线柱150顶端的塑封料去除,从而露出打线柱150的端部,使得第二塑封体140的高度低于打线柱150的高度。其中,每个打线柱150与基板110电连接,且每个打线柱150至少部分外露于第二塑封体140,用于与电路板200电连接。Referring to FIG. 15 , specifically, the wire bonding structure can be encapsulated by a plastic encapsulation process to form a second plastic encapsulation body 140, and then the plastic encapsulation material at the top of the wire bonding post 150 can be removed by laser grooving to expose the end of the wire bonding post 150, so that the height of the second plastic encapsulation body 140 is lower than the height of the wire bonding post 150. Each wire bonding post 150 is electrically connected to the substrate 110, and each wire bonding post 150 is at least partially exposed outside the second plastic encapsulation body 140 for being electrically connected to the circuit board 200.
S5:在基板110的另一侧表面贴装第二芯片160。S5 : mounting the second chip 160 on the other surface of the substrate 110 .
参见图16,具体地,可以将第二芯片160倒装贴设在基板110的表面,并位于第二塑封体140的中心。第二芯片160通过填充胶层161固定和保护,无塑封胶层,能够提升其散热性能。最后利用切割工艺,沿切割道进行切割,从而分离为单颗产品。Referring to FIG. 16 , specifically, the second chip 160 can be flip-chip mounted on the surface of the substrate 110 and located at the center of the second plastic package 140. The second chip 160 is fixed and protected by a filling glue layer 161, and has no plastic sealing glue layer, which can improve its heat dissipation performance. Finally, a cutting process is used to cut along the cutting path to separate into individual products.
综上所述,本发明实施例提供的芯片封装结构100和芯片封装结构100的制备方法,将第一芯片120贴设在基板110的一侧,同时在第一芯片120外塑封形成第一塑封体130,而在基板110的另一侧表面打线形成多个打线柱150,多个打线柱150朝向背离第一塑封体130的方向凸起,并且在基板110的另一侧表面形成有第二塑封体140,第二塑封体140包覆在打线柱150的周围,其中,每个打线柱150与基板110电连接,且每个打线柱150至少部分外露于第二塑封体140,用于与电路板200电连接。相较于现有技术,本发明利用打线柱150来替代锡球,避免了采用锡球焊接技术,进而避免了锡球焊接带来的一系列问题,同时利用第二塑封体140来支撑保护打线柱150,能够大幅提升结构强度,保证了连接效果和连接强度,同时打线柱150不会出现桥接或空洞现象,导电性能优异。In summary, the chip packaging structure 100 and the preparation method of the chip packaging structure 100 provided in the embodiment of the present invention attach the first chip 120 to one side of the substrate 110, and at the same time, plastic-encapsulate the first chip 120 to form a first plastic encapsulation body 130, and wire-bond the other side surface of the substrate 110 to form a plurality of bonding posts 150, and the plurality of bonding posts 150 protrude in a direction away from the first plastic encapsulation body 130, and a second plastic encapsulation body 140 is formed on the other side surface of the substrate 110, and the second plastic encapsulation body 140 is wrapped around the bonding posts 150, wherein each bonding post 150 is electrically connected to the substrate 110, and each bonding post 150 is at least partially exposed from the second plastic encapsulation body 140 for being electrically connected to the circuit board 200. Compared with the prior art, the present invention utilizes a bonding post 150 to replace a tin ball, thereby avoiding the use of tin ball welding technology, thereby avoiding a series of problems caused by tin ball welding. At the same time, the second plastic package 140 is used to support and protect the bonding post 150, which can greatly improve the structural strength and ensure the connection effect and connection strength. At the same time, the bonding post 150 will not have bridging or void phenomena, and has excellent conductive performance.
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
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